JP5746199B2 - バイポーラトランジスタ - Google Patents

バイポーラトランジスタ Download PDF

Info

Publication number
JP5746199B2
JP5746199B2 JP2012537174A JP2012537174A JP5746199B2 JP 5746199 B2 JP5746199 B2 JP 5746199B2 JP 2012537174 A JP2012537174 A JP 2012537174A JP 2012537174 A JP2012537174 A JP 2012537174A JP 5746199 B2 JP5746199 B2 JP 5746199B2
Authority
JP
Japan
Prior art keywords
region
base
collector
transistor
bipolar transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2012537174A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013509730A5 (enExample
JP2013509730A (ja
Inventor
ウィリアム アレン レーン,
ウィリアム アレン レーン,
アンドゥルー デイビッド ベイン,
アンドゥルー デイビッド ベイン,
デレック フレデリック バウワーズ,
デレック フレデリック バウワーズ,
ポール マラキー デイリー,
ポール マラキー デイリー,
アン マリア デイニヤン,
アン マリア デイニヤン,
マイケル トーマス ダンバー,
マイケル トーマス ダンバー,
パトリック マーティン マゲネス,
パトリック マーティン マゲネス,
バーナード パトリック ステンソン,
バーナード パトリック ステンソン,
Original Assignee
アナログ デバイシス, インコーポレイテッド
アナログ デバイシス, インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by アナログ デバイシス, インコーポレイテッド, アナログ デバイシス, インコーポレイテッド filed Critical アナログ デバイシス, インコーポレイテッド
Publication of JP2013509730A publication Critical patent/JP2013509730A/ja
Publication of JP2013509730A5 publication Critical patent/JP2013509730A5/ja
Application granted granted Critical
Publication of JP5746199B2 publication Critical patent/JP5746199B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/40Vertical BJTs
    • H10D10/421Vertical BJTs having both emitter-base and base-collector junctions ending at the same surface of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283Lateral isolation by refilling of trenches with dielectric material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/01Manufacture or treatment
    • H10D10/051Manufacture or treatment of vertical BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/111Field plates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
JP2012537174A 2009-11-02 2010-11-01 バイポーラトランジスタ Expired - Fee Related JP5746199B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/611,074 2009-11-02
US12/611,074 US8350352B2 (en) 2009-11-02 2009-11-02 Bipolar transistor
PCT/US2010/055000 WO2011053927A1 (en) 2009-11-02 2010-11-01 Bipolar transistor

Publications (3)

Publication Number Publication Date
JP2013509730A JP2013509730A (ja) 2013-03-14
JP2013509730A5 JP2013509730A5 (enExample) 2013-10-24
JP5746199B2 true JP5746199B2 (ja) 2015-07-08

Family

ID=43618000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012537174A Expired - Fee Related JP5746199B2 (ja) 2009-11-02 2010-11-01 バイポーラトランジスタ

Country Status (5)

Country Link
US (2) US8350352B2 (enExample)
EP (1) EP2497113A1 (enExample)
JP (1) JP5746199B2 (enExample)
CN (1) CN102668087B (enExample)
WO (1) WO2011053927A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9653455B1 (en) * 2015-11-10 2017-05-16 Analog Devices Global FET—bipolar transistor combination
JP7386123B2 (ja) * 2020-04-28 2023-11-24 株式会社東海理化電機製作所 半導体装置

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1614749U (de) * 1949-12-05 1950-10-19 Patra Patent Treuhand Doppelfassung zur aufnahme von zwei parallel nebeneinander angeordneten rohrenden von leuchtroehren.
DE1614749A1 (de) 1967-01-07 1970-12-10 Telefunken Patent Integrierte Halbleiteranordnung
US3772577A (en) 1972-02-10 1973-11-13 Texas Instruments Inc Guard ring mesa construction for low and high voltage npn and pnp transistors and diodes and method of making same
JPS4991776A (enExample) * 1973-01-05 1974-09-02
JPS61278161A (ja) 1985-06-04 1986-12-09 Tdk Corp 高耐圧半導体装置
JPS61285764A (ja) * 1985-06-12 1986-12-16 Tdk Corp 高耐圧半導体装置
JP2979554B2 (ja) 1989-09-26 1999-11-15 株式会社デンソー 半導体装置の製造方法
DE58908843D1 (de) 1989-10-30 1995-02-09 Siemens Ag Eingangsschutzstruktur für integrierte Schaltungen.
JPH04506588A (ja) 1990-01-08 1992-11-12 ハリス コーポレーシヨン 薄い、絶縁分離したアイランドに納められた、低いコレクタ抵抗を持つ、トランジスタ構造
US5247201A (en) * 1990-02-15 1993-09-21 Siemens Aktiengesellschaft Input protection structure for integrated circuits
JP3798808B2 (ja) * 1991-09-27 2006-07-19 ハリス・コーポレーション 高いアーリー電壓,高周波性能及び高降伏電壓特性を具備した相補型バイポーラトランジスター及びその製造方法
US5274267A (en) 1992-01-31 1993-12-28 International Business Machines Corporation Bipolar transistor with low extrinsic base resistance and low noise
JP3110852B2 (ja) 1992-04-08 2000-11-20 株式会社ブリヂストン 空気入りタイヤ
JPH05291270A (ja) * 1992-04-13 1993-11-05 Sharp Corp 半導体装置
JP2812093B2 (ja) * 1992-09-17 1998-10-15 株式会社日立製作所 プレーナ接合を有する半導体装置
SE513512C2 (sv) * 1994-10-31 2000-09-25 Ericsson Telefon Ab L M Halvledaranordning med ett flytande kollektorområde
US5629552A (en) * 1995-01-17 1997-05-13 Ixys Corporation Stable high voltage semiconductor device structure
JPH10172980A (ja) * 1996-12-13 1998-06-26 Sanken Electric Co Ltd 半導体装置及びその製造方法
JP3906181B2 (ja) * 2003-05-26 2007-04-18 株式会社東芝 電力用半導体装置
US7737469B2 (en) 2006-05-16 2010-06-15 Kabushiki Kaisha Toshiba Semiconductor device having superjunction structure formed of p-type and n-type pillar regions
EP1936390A1 (en) * 2006-12-20 2008-06-25 Ecole Polytechnique Federale De Lausanne Epfl - Sti - Imm - Lmis3 Semiconductor device for measuring ultra small electrical currents and small voltages
US8008734B2 (en) * 2007-01-11 2011-08-30 Fuji Electric Co., Ltd. Power semiconductor device
JP5205856B2 (ja) * 2007-01-11 2013-06-05 富士電機株式会社 電力用半導体素子

Also Published As

Publication number Publication date
US8350352B2 (en) 2013-01-08
US8357985B2 (en) 2013-01-22
US20120112307A1 (en) 2012-05-10
WO2011053927A1 (en) 2011-05-05
EP2497113A1 (en) 2012-09-12
JP2013509730A (ja) 2013-03-14
US20110101486A1 (en) 2011-05-05
CN102668087B (zh) 2016-08-24
CN102668087A (zh) 2012-09-12

Similar Documents

Publication Publication Date Title
US10043792B2 (en) Electrostatic protection device
US10199482B2 (en) Apparatus for electrostatic discharge protection
US8503140B2 (en) Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures
JP5481562B2 (ja) 接合型電界効果トランジスタおよびその製造方法
CN110364523B (zh) Esd保护装置、包括esd保护装置的半导体装置和其制造方法
JP5746199B2 (ja) バイポーラトランジスタ
US8513713B2 (en) Junction field effect transistor with region of reduced doping
KR20080073313A (ko) 반도체 장치 및 그 제조 방법
CN100380676C (zh) 半导体结构及改善其esd与过负荷强度的方法
US8294218B2 (en) Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection
US20120028432A1 (en) Methods of forming a bipolar transistor
CN100390992C (zh) 具有静电放电保护装置的半导体结构
WO2007035416A2 (en) Integrated circuit with gate self-protection

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130905

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130905

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140912

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140917

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141112

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150420

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150507

R150 Certificate of patent or registration of utility model

Ref document number: 5746199

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: R3D04

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees