JP5732031B2 - Pipeline type A / D converter - Google Patents

Description

  The present invention relates to a pipeline type A / D converter, and more particularly to a pipeline type A / D converter capable of improving nonlinearity and operating at high speed.

  Electronic devices that need to convert analog signals into digital signals, such as various image sensors and image processing devices, are required to process a large amount of data at high speed. A pipe capable of performing a plurality of A / D conversion processes in one clock by configuring a plurality of A / D converters connected in cascade in multiple stages so that such a process can be performed. A line type A / D converter is known.

  In a pipelined A / D converter, each stage composed of a plurality of A / D converters constituting the pipelined A / D converter includes a switched capacitor circuit that samples an analog signal, an A / D converter circuit, and the like. The digital signal of a predetermined bit corresponding to the input analog signal is output. The pipeline type A / D converter generates digital signals of a plurality of bit strings corresponding to the input analog signals by synthesizing the digital signals output from the respective stages.

First, the configuration of the A / D converter unit 21 configuring each stage of the pipeline type A / D converter will be described with reference to FIG. The A / D converter unit 21 includes a general switched capacitor circuit 21a, an A / D converter circuit 21b, a D / A converter circuit 21c, and a reference voltage generation circuit 21d.
FIG. 8 is a circuit configuration diagram showing configurations of a general switched capacitor circuit 21a, an A / D converter circuit 21b, a D / A converter circuit 21c, and a reference voltage generation circuit 21d using an operational amplifier.

The switched capacitor circuit 21a shown in FIG. 8 includes analog signal input terminals Va and Vb, an analog signal output terminal Vc, an operational amplifier AM, sampling switching elements S1 to S5, and sampling capacitors C1 and C2. Yes.
The analog signal input terminal Va is a terminal for inputting the analog input signal Vin. The analog signal input terminal Vb is a terminal for inputting the output signal Van of the D / A converter circuit 21c. The analog signal output terminal Vc is a terminal for amplifying the analog input signal Vin input from the analog signal input terminal Va and then outputting it as an analog output signal Vout.

The sampling switching elements S1 to S5 are sampling switching for sampling (sampling and holding) the analog input signal Vin by switching the circuit connection state by control signals φ1 and φ2 output from a control unit (not shown), for example. It is an element. The sampling switching elements S1 to S5 alternately repeat the connected state and the disconnected state, whereby a continuous sampling operation is performed.
The sampling capacitors C1 and C2 are connected to the sampling switching elements S1 to S5, respectively, and store and hold charges corresponding to the analog input signal Vin by the sampling operation, so that the analog input input from the analog signal input terminal Va A sampling capacitor for sampling and holding a signal.

  The operational amplifier AM amplifies the analog input signal Vin sampled and held by the sampling capacitors C1 and C2 based on the amplification degree based on the gain A and the feedback amount based on the loop feedback coefficient β. When the switching element S3 is in the connected state, the sampling capacitors C1 and C2 are connected to the non-inverting input (+) terminal and the inverting input (−) terminal of the operational amplifier AM. When the sampling switching element S3 is disconnected, the sampling capacitors C1 and C2 are connected to the inverting input terminal of the operational amplifier AM, and the ground is connected to the non-inverting input terminal.

The A / D converter circuit 21b shown in FIG. 8 includes analog signal input terminals Vf and Ve, a digital signal output terminal Vd, a flash comparator CP, sampling switching elements S6 to S9, a sampling capacitor C3, and a memory ME.
The analog signal input terminal Vf is a terminal for inputting the analog input signal Vin. The analog signal input terminal Ve is a terminal for inputting the reference voltage 3. The digital signal output terminal Vd is a terminal for comparing the reference voltage 3 with the analog input signal Vin and binarizing the determination result and outputting the result as a digital signal Dout.

The flash comparator CP compares and determines the reference voltage 3 and the analog input signal Vin, and outputs a digital signal.
The sampling switching elements S6 to S9 are, for example, sampling switching elements for sampling the analog input signal Vin and the reference voltage 3 by switching the circuit connection state by control signals φ1 and φ2 output from a control unit (not shown). It is. The sampling switching elements S6 to S9 alternately repeat the connection state and the disconnection state, whereby continuous sampling and comparison operations are performed.

The memory ME holds the output result of the flash comparator CP and outputs a digital signal Dout.
The D / A converter circuit 21c shown in FIG. 8 includes a digital signal input terminal Vg, an analog signal output terminal Vh, and a D / A converter circuit DAC.
The D / A converter circuit DAC outputs an analog signal corresponding to the input digital signal Dout.

The reference voltage generating circuit 21d shown in FIG. 8 includes an analog signal output terminal Vi, reference voltages 1 to 3 and a reference voltage dividing resistor R.
The analog signal output terminal Vi is a terminal for outputting the reference voltage 3. A desired reference voltage 3 can be generated by connecting a plurality of reference voltage dividing resistors R between the reference voltages 1 and 2.

Next, the operation of the A / D converter unit 21 having the above configuration will be described.
In the A / D converter unit 21, the switching elements S1 to S3, S6, and S9 operate according to the control signal φ1, and the switching elements S4, S5, S7, and S8 operate according to the control signal φ2.
First, consider the case where, in the A / D converter circuit 21b, the sampling switching element S7 and the offset canceling switching element S8 are in the connected state, and the switching elements S6 and S9 are in the disconnected state.

In this case, the reference voltage 3 is supplied to one end of the sampling capacitor C3, and at the same time, the input terminal and the output terminal of the flash comparator CP are short-circuited, and the offset cancellation operation of the flash comparator CP is performed.
When switching from this state to the sampling operation phase in the switched capacitor circuit 21a, the sampling switching elements S1 to S3 are connected and the switching elements S4 and S5 are disconnected. Then, charges corresponding to the analog input signal Vin are stored in the two sampling capacitors C1 and C2, respectively, and the analog input signal Vin is sampled.

In the A / D converter circuit 21b, the sampling switching elements S6 and S9 are connected and the switching elements S7 and S8 are disconnected. Then, the analog input signal Vin is supplied to one end of the sampling capacitor C3, the flash comparator CP compares and determines the reference voltage 3 and the analog input signal Vin, the result is held in the memory ME, and the digital signal Dout Output as.
The D / A converter circuit 21c outputs an analog signal Van corresponding to the digital signal Dout.

  Subsequently, when the switched capacitor circuit 21a shifts to the hold phase, the sampling switching elements S1 to S3 are disconnected and the switching elements S4 and S5 are connected. Then, since the electric charge stored in each of the sampling capacitors C1 and C2 is held, the analog input signal Vin is amplified from the operational amplifier AM and an analog output signal Vout having an offset corresponding to the analog signal Van is output. The

  In this way, the switched capacitor circuit 21a, the A / D converter circuit 21b, the D / A converter circuit 21c, and the reference voltage generation circuit 21d perform the sampling operation while alternately repeating the sampling operation and the holding operation described above. A / D conversion processing is performed by the line type A / D converter.

  By the way, in the pipeline type A / D converter, since the output of the D / A converter circuit 21c changes before and after the threshold value of the A / D converter circuit 21b, the output of the switched capacitor circuit 21a becomes discontinuous. As a result, it is known that the nonlinearity of the pipeline type A / D converter increases around the threshold value of the A / D converter circuit 21b. In order to solve this problem, a technique for changing the threshold value of the A / D converter circuit using a dither as disclosed in Patent Document 1 has been proposed.

  Next, a pipeline type A / D converter that changes the threshold value of the A / D converter circuit using dither will be described with reference to FIG. The pipeline type A / D converter includes a plurality of stages of A / D converter units 31. The A / D converter unit 31 includes a switched capacitor circuit 31a, an A / D converter circuit 31b, and a D / A converter circuit. 31c and a reference voltage generation circuit 31d.

FIG. 9 illustrates an example of a switched capacitor circuit 31a, an A / D converter circuit 31b, a D / A converter circuit 31c, and a reference voltage generation circuit 31d of a pipeline type A / D converter that uses dither to change a threshold value. It is a circuit block diagram shown.
The switched capacitor circuit 31a, the A / D converter circuit 31b, and the D / A converter circuit 31c shown in FIG. 9 are the switched capacitor circuit 21a, the A / D converter circuit 21b, and the D / A of the A / D converter unit 21 shown in FIG. Since the configuration is the same as that of the converter circuit 21c, the same reference numerals are given to the same portions, and detailed descriptions thereof are omitted.
9 includes an analog signal output terminal Vi, a reference voltage 1 to a reference voltage 3, a reference voltage dividing resistor R, and switching elements S10 to S14.

  A plurality of reference voltage dividing resistors R are connected between the reference voltages 1 and 2, and switching elements S10 to S14 are connected to resistance ends of voltages to be generated. For example, only one of these switching elements S10 to S14 is connected and the remaining four are disconnected by a control signal output from a control unit (not shown), and one of the five reference voltages is selected. And output as a reference voltage 3. Of the five switching elements S10 to S14, which switching element is connected is switched using a control signal each time sampling is performed, and therefore the A / D converter circuit 31b has different reference voltages and analog input signals for each sampling. Comparison with Vin is performed. As a result, the non-linearity of the pipeline type A / D converter can be relaxed by dispersing the discontinuous points of the analog output voltage.

JP-A-11-330964

However, in the pipeline type A / D converter that changes the threshold value by using the above-described dither, the above-described advantages can be found, while a plurality of new reference voltage dividing resistors are added to the reference voltage generation circuit. Since the switching element group is added, the resistance and parasitic capacitance are increased, which may adversely affect high-speed operation.
The present invention has been made to achieve such an object. The object of the present invention is to change the threshold value of the comparator circuit to reduce non-linearity and to enable high-speed operation. The object is to provide an A / D converter.

One embodiment of the present invention is a pipeline-type A / D converter (for example, the pipeline-type A shown in FIG. 1) having A / D converter circuits (for example, the A / D converter circuit 11b shown in FIG. 1) connected in a plurality of stages. In the / D converter 10), at least one of the plurality of A / D converter circuits determines the threshold value of the A / D converter circuit according to a random clock signal (for example, the control signal φ2A shown in FIG. 2). A random clock generator (for example, the random clock generator 14c shown in FIG. 3) that generates the random clock signal that changes the threshold value of the A / D converter circuit by changing the pulse width . ) wherein the a / D converter circuit, have a switching element to switch to the state where no supply state for supplying a reference voltage The random clock signal is input only to the switching element, the length of the switching element is turned on according to the random clock signal, and the A / D converter circuit is connected via the switching element. A pipeline type A / D converter, wherein a voltage obtained by adjusting a reference voltage input by the switching element according to the random clock signal is operated as the threshold value .
Another aspect of the present invention is a pipeline type A / D converter (for example, the pipeline type shown in FIG. 1) having A / D converter circuits (for example, the A / D converter circuit 11b shown in FIG. 1) connected in a plurality of stages. In the A / D converter 10), at least one of the plurality of A / D converter circuits has a threshold value of the A / D converter circuit in accordance with a random clock signal (for example, the control signal φ2A shown in FIG. 2). A random clock generator (for example, a random clock generator shown in FIG. 3) that generates the random clock signal that changes the threshold value of the A / D converter circuit by changing the pulse width. 14c), the A / D converter circuit includes a comparator (for example, the flash comparator CP shown in FIG. 2) and the comparator. An offset canceling switching element (for example, offset canceling switching element S8 shown in FIG. 2) that is inserted in a path connecting the output end and the input end of the oscillator and samples the offset voltage of the A / D converter circuit; The random clock signal is input only to the offset canceling switching element, and the length of the period during which the offset canceling switching element is turned on changes according to the random clock signal. A pipeline type A / D converter.
Another aspect of the present invention is a pipeline type A / D converter (for example, the pipeline type shown in FIG. 1) having A / D converter circuits (for example, the A / D converter circuit 11b shown in FIG. 1) connected in a plurality of stages. In the A / D converter 10), at least one of the plurality of A / D converter circuits is configured such that a threshold value of the A / D converter circuit is determined according to a random clock signal, and a pulse A random clock generator (for example, the random clock generator illustrated in FIG. 3) that generates the random clock signal (for example, the control signal φ2A illustrated in FIG. 2) that changes the threshold value of the A / D converter circuit by changing the width. 14c), and the A / D converter circuit is configured to supply a reference voltage supply switch that switches between a reference voltage supply state and a non-supply state. Offset canceling device for sampling the offset voltage of the A / D converter circuit inserted in the path connecting the switching element, the comparator (for example, the flash comparator CP shown in FIG. 2), and the output terminal and the input terminal of the comparator. Switching element (for example, offset canceling switching element S8 shown in FIG. 2), and the random clock signal is input only to the reference voltage supplying switching element and the offset canceling switching element, and the reference voltage The switching element for supply and the switching element for offset cancellation change the length of the ON period according to the random clock signal, and the A / D converter circuit is a reference input via the switching element. The voltage is A pipeline A / D converter, wherein a voltage adjusted according to the random clock signal by an switching element operates as the threshold value.

The threshold value of the A / D converter circuit is determined according to the pulse width of the random clock signal, and the random clock signal may include at least two kinds of pulses having different pulse widths.
The random clock generation unit may generate one or a plurality of random clock signals and supply the plurality of random clock signals to different A / D converter circuits.

The random clock signal supplied to each of the plurality of A / D converter circuits may have the same pulse width change pattern.
The random clock signals supplied to each of the plurality of A / D converter circuits may have different pulse width change patterns .

  According to one embodiment of the present invention, each stage of the A / D converter circuit constituting the pipeline type A / D converter operates so that the threshold value changes every time the analog input signal is sampled. Discontinuous points of the analog output voltage can be dispersed to improve the nonlinearity of the pipelined A / D converter.

It is a block diagram which shows an example of a structure of the pipeline type A / D converter which concerns on this embodiment. It is an example of the block diagram which shows the structure of each part of the pipeline type A / D converter which concerns on this invention. It is a block diagram which shows an example of the control part of the pipeline type A / D converter which concerns on this invention. It is a timing chart which shows an example of the control signal in the pipeline type A / D converter concerning the present invention. It is a timing chart which shows an example of the control signal in the pipeline type A / D converter concerning the present invention. It is a graph which shows an example of the output characteristic of the reference voltage generation circuit connected to the sampling capacitor | condenser contained in the A / D converter circuit of the pipeline type A / D converter which concerns on this invention. It is a graph which shows the other example of the output characteristic of the reference voltage generation circuit connected to the sampling capacitor | condenser contained in the A / D converter circuit of the pipeline type A / D converter which concerns on this invention. It is a block diagram for demonstrating the conventional pipeline type A / D converter. It is a block diagram for demonstrating the pipeline type A / D converter comprised using a prior art.

  Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. In each drawing referred to in the following description, components equivalent to those in the other drawings are denoted by the same reference numerals.

(Circuit configuration of pipeline type A / D converter 10)
First, with reference to FIG. 1, the configuration of a pipeline type A / D converter 10 mounted inside an electronic device or the like will be described as an example of a device configured by applying a switched capacitor circuit according to the present invention. .
FIG. 1 is a block diagram showing a configuration of a pipeline type A / D converter 10 according to the present embodiment.

A pipeline type A / D converter 10 shown in FIG. 1 includes a plurality of A / D converter units 11-1 to 11-k (k is an integer) connected in cascade to each other, a storage unit 12, and an arithmetic processing unit 13. And a control unit 14.
Each of the A / D converter units 11-1 to 11-k includes a switched capacitor circuit 11a, an A / D converter circuit 11b, a D / A converter circuit 11c, and a reference voltage generation circuit 11d.

  The switched capacitor circuit 11a generates an analog output signal Vout from the analog input signal Vin input from the analog signal input terminal Va by the sample operation and the hold operation and the analog signal Van output from the D / A converter circuit 11c. The analog output signal Vout is output.

A / D converter circuit 11b, the sampling operation and the hold operation by inputting an analog input signal Vin and outputs into digital signals d ₁ to d _k.
D / A converter circuit 11c is configured to output into an analog signal Van to input digital signals _d 1 to d _k output from the A / D converter circuit 11b.
The reference voltage generation circuit 11d generates and outputs a reference voltage that becomes a threshold voltage of the A / D converter circuit 11b.

Storage unit 12 is configured to sequentially store the digital signal _d 1 to d _k output from the A / D converter unit 11-1 to 11-k.
The arithmetic processing unit 13 performs an operation for synthesizing each bit value of the digital signals d _{1 to} d _k stored in the storage unit 12 and outputs a digital signal Dout of a predetermined bit string corresponding to the analog input signal Vin It is.
The control unit 14 generates and outputs four control signals φ1, φ2, φ2A, and φ2B for switching the electrical connection states of the switching elements of the A / D converter units 11-1 to 11-k. .

The A / D converter units 11-1 to 11-k of each stage constituting the pipeline type A / D converter 10 according to the present embodiment receive the analog input signal Vin by the sampling operation of the internal switched capacitor circuit 11a. Input, convert to digital signals d _{1 to} d _k and output. At the same time, A / D converter unit 11-1 to 11-k of each stage, a subsequent stage the analog output signal Vout generated by the the digital signal _d 1 to d _k analog signal converted from Van and the analog input signal Vin Are output to the A / D converter unit 11-n (n is an integer of 2 to k) connected to.

  For example, the sampling operation of the switched capacitor circuit 11a is performed such that the analog output signal Vout is output from the A / D converter unit 11-1 to the A / D converter unit 11-2 at the subsequent stage. The analog output signal Vout output from the preceding A / D converter unit 11-1 is input to the A / D converter unit 11-2, and the subsequent A / D converter is output from the A / D converter unit 11-2. To the unit 11-3. The same applies to the A / D converter units 11-4 to 11-k.

(Circuit configuration of the switched capacitor circuit 11a)
Next, the details of the circuit configuration of the pipeline type A / D converter 10 according to the present embodiment will be described with reference to FIG. FIG. 2 is a circuit diagram showing a circuit configuration of the A / D converter units 11-1 to 11-k of the pipeline type A / D converter 10 according to the present embodiment.

  The switched capacitor circuit 11a, the A / D converter circuit 11b, the D / A converter circuit 11c, and the reference voltage generation circuit 11d shown in FIG. Although the circuit includes the same components as the converter circuit 21b, the D / A converter circuit 21c, and the reference voltage generation circuit 21d, in the present embodiment, the control terminals of the switching elements S7 and S8 of the A / D converter circuit 11b include The difference is that φ2A or φ2A ′, φ2B or φ2B ′ is connected in place of the control signal φ2. Except that the control signals are different, the same operation as that of each unit in the A / D converter unit 21 shown in FIG. 8 is performed, and thus detailed description thereof is omitted.

(Circuit structure of the control part 14)
Next, the circuit configuration of the control unit 14 of the pipeline type A / D converter 10 according to the present embodiment will be described with reference to FIGS. 3 to 5.
FIG. 3 is a block diagram showing a circuit configuration of the control unit 14 of the pipeline type A / D converter 10 according to the present embodiment. FIG. 4 is an example of a timing chart showing the output timing of the control signals φ1, φ2, φ2A, and φ2B generated by the control unit. FIG. 5 is another example of a timing chart showing the output timing of the control signals φ1, φ2, φ2A ′, and φ2B ′ generated by the control unit. 4 and 5, (a) represents the control signal φ1, (b) represents the control signal φ2, (c) represents the control signal φ2A or φ2A ′, and (d) represents the control signal φ2B or φ2B ′.

The control unit 14 illustrated in FIG. 3 includes a master clock generation unit 14a, a sampling operation control signal generation unit 14b, and a random clock generation unit 14c.
The master clock generation unit 14a generates a master clock signal φ at a master clock frequency set therein.
The sampling operation control signal generator 14b controls the control signal φ1 for switching the electrical connection state of the sampling switching elements S1 to S3, S6, and S9 for sampling the analog input signal Vin in accordance with the master clock signal φ. And a circuit for generating a control signal φ2 for switching the electrical connection state of the sampling switching elements S4 and S5.

As shown in FIGS. 4 and 5, when the control signal φ1 is at the high level, the control signal φ2 is at the low level. When the control signal φ1 is at the low level, the control signal φ2 is at the high level, but they are in a non-overlapping relationship.
The random clock generator 14c controls the control signals φ2A and φ2A ′ for switching the electrical connection state of the sampling switching element S7 for sampling the reference voltage 3 and the offset of the flash comparator CP in accordance with the master clock signal φ. This is a circuit for generating control signals φ2B and φ2B ′ for switching the electrical connection state of the switching element S8 for performing the cancel operation.

In the control signals φ2A, φ2A ′, φ2B, and φ2B ′, the period of the high level is not constant, and the clock edge is randomly selected so that the period of the high level changes every cycle.
That is, the control signals φ2A and φ2B are made up of signals having five different pulse widths, as shown in FIGS. Then, one of the five pulse widths is selected as the control signals φ2A and φ2B. The control signals φ2A and φ2B are configured to realize five pulse widths by changing the timing of switching from the High level to the Low level.

  Any number of pulse width options may be used as long as it is two or more. The pulse width may be selected by either φ2A or φ2B or either one. Further, the change in pulse width may or may not change equally in all the pulses. Further, the pulse width may be changed for each pulse, or may be changed every one or a plurality of pulses.

As shown in FIG. 4, when the control signal φ1 is at a high level, the control signals φ2A and φ2B are at a low level. When the control signal φ1 is at the low level, the control signals φ2A and φ2B are at the high level, but are in a non-overlapping relationship.
Similarly, the control signals φ2A ′ and φ2B ′ are composed of signals having five different pulse widths, as shown in FIGS. Then, one of the five pulse widths is selected as the control signals φ2A ′ and φ2B ′. The control signals φ2A ′ and φ2B ′ are configured to realize five pulse widths by changing the timing of switching from the Low level to the High level.

  Also in this case, any number of pulse width options may be used as long as it is two or more. The pulse width may be selected by either φ2A ′ or φ2B ′ or either one. Further, the change in pulse width may or may not change equally in all the pulses. Further, the pulse width may be changed for each pulse, or may be changed every one or a plurality of pulses.

  As shown in FIG. 5, when the control signal φ1 is at a high level, the control signals φ2A ′ and φ2B ′ are at a low level. When the control signal φ1 is at the low level, the control signals φ2A ′ and φ2B ′ are at the high level, but are in a non-overlapping relationship.

(Voltage characteristics of node N1 of A / D converter circuit 11b)
Next, the manner in which the threshold value of the A / D converter circuit 11b changes with each sampling will be described with reference to FIGS.
FIG. 6 is a graph showing the voltage characteristics of the control signal φ2A and the voltage characteristics of the node N1 at one end on the switches S6 and S7 side of the sampling capacitor C3 of the A / D converter circuit 11b. Similarly, FIG. 7 is a graph showing the voltage characteristic of the control signal φ2A ′ and a graph showing the voltage characteristic of the node N1 at one end on the switches S6 and S7 side of the sampling capacitor C3 of the A / D converter circuit 11b.

The horizontal axis of the graphs shown in FIGS. 6 and 7 indicates time t. The vertical axis indicates the voltages at φ2A and φ2A ′ and the voltage at the node N1.
In the conventional A / D converter circuit shown in FIGS. 8 and 9, the voltage at the node N1 at one end of the sampling capacitor C3 is converged to the reference voltage 3 when the control signal φ2 is at a high level. The threshold value of the A / D converter circuit is always at a constant level.

  However, in the A / D converter circuit 11b of this embodiment, as shown in FIGS. 4 and 5, the high level times of the control signals φ2A and φ2A ′ are different for each sampling. The voltage at the node N1 at one end of the sampling capacitor C3 may converge to the reference voltage 3, or φ2A and φ2A ′ may be switched to a low level before convergence, and the sampling period may end.

As a result, the threshold value of the A / D converter circuit 11b always changes, and the discontinuous points of the analog output signal Vout of the switched capacitor circuit 11a are dispersed, thereby improving the nonlinearity of the pipeline type A / D converter. Can do.
Furthermore, in the present embodiment, there is no additional switching element or the like when sampling the reference voltage 3 to the sampling capacitor C3, so that there is no increase in resistance or parasitic capacitance. Therefore, high speed operation is also possible.

Next, the influence when the high level time of the control signals φ2B and φ2B ′ changes will be considered.
The control signals φ2B and φ2B ′ are connected to the control terminal of the switching element S8 for short-circuiting the input terminal and the output terminal of the flash comparator CP. Accordingly, when the high level time of the control signals φ2B and φ2B ′ changes, the time of the offset cancel operation changes. Therefore, one end of the sampling capacitor C3 may converge to the offset voltage, or the control signals φ2B and φ2B ′ may be switched to the low level before convergence, and the sampling period may end. As a result, as in the case of the control signals φ2A and φ2A ′, the threshold value of the A / D converter circuit 11b always fluctuates, the discontinuous points of the analog output signal Vout of the switched capacitor circuit 11a are dispersed, and the pipeline type The non-linearity of the A / D converter can be improved.

Also in this case, since there is no additional switching element in sampling the offset voltage of the flash comparator CP to the sampling capacitor C3, there is no increase in resistance or parasitic capacitance. Therefore, high speed operation is also possible.
Note that it is not necessary to use the control signals φ2A or φ2B, φ2A ′, or φ2B ′ whose pulse width changes in all the A / D converter circuits 11b configuring each stage of the pipeline type A / D converter 10. For example, in any one or a plurality of A / D converter circuits 11b, a control signal φ2A or φ2B, φ2A ′ or φ2B ′ whose pulse width changes may be used, and among the plurality of A / D converter circuits 11b, Some of the switching elements may be controlled using a control signal φ2A or φ2A ′ whose pulse width changes, and the rest are controlled using a control signal φ2B or φ2B ′ whose pulse width changes.

  In particular, it can be used as a switched capacitor circuit and a pipelined A / D converter for electronic devices such as video cameras and audio devices that require conversion from analog signals to digital signals.

DESCRIPTION OF SYMBOLS 10 Pipeline type A / D converter 11-1 to 11-k, 21, 31 A / D converter part 12 Memory | storage part 13 Arithmetic processing part 14 Control part 11a, 21a, 31a Switched capacitor circuit 11b, 21b, 31b A / D Converter circuit 11c, 21c, 31c D / A converter circuit AM Amplifying calculator S1 to S9 Switching element for sampling S10 to S14 Switching element for selecting reference voltage C1, C2, C3 Capacitor for sampling CP Flash comparator for A / D converter circuit ME Memory for A / D converter circuit DAC D / A converter circuit R Reference voltage generating resistor

Claims (7)

In a pipeline type A / D converter having A / D converter circuits connected to a plurality of stages,
At least one of the plurality of A / D converter circuits is configured such that a threshold value of the A / D converter circuit is determined according to a random clock signal,
A random clock generation unit that generates the random clock signal that changes a threshold value of the A / D converter circuit by changing a pulse width ;
The A / D converter circuit includes a switching element that switches between a state in which a reference voltage is supplied and a state in which a reference voltage is not supplied.
The random clock signal is input only to the switching element,
The switching element has a length of a period in which the switching element is turned on according to the random clock signal.
The A / D converter circuit operates using, as the threshold value, a voltage obtained by adjusting a reference voltage input via the switching element according to the random clock signal by the switching element. Pipeline type A / D converter. In a pipeline type A / D converter having A / D converter circuits connected to a plurality of stages,
At least one of the plurality of A / D converter circuits is configured such that a threshold value of the A / D converter circuit is determined according to a random clock signal,
A random clock generation unit that generates the random clock signal that changes a threshold value of the A / D converter circuit by changing a pulse width ;
The A / D converter circuit is:
A comparator,
An offset canceling switching element that is inserted in a path connecting the output terminal and the input terminal of the comparator and samples the offset voltage of the A / D converter circuit,
The random clock signal is input only to the offset canceling switching element,
The pipeline A / D converter is characterized in that the offset canceling switching element is turned on in accordance with the random clock signal . In a pipeline type A / D converter having A / D converter circuits connected to a plurality of stages,
At least one of the plurality of A / D converter circuits is configured such that a threshold value of the A / D converter circuit is determined according to a random clock signal,
A random clock generation unit that generates the random clock signal that changes a threshold value of the A / D converter circuit by changing a pulse width ;
The A / D converter circuit is:
A switching element for supplying a reference voltage that switches between supplying a reference voltage and not supplying a reference voltage;
A comparator,
An offset canceling switching element that is inserted in a path connecting the output terminal and the input terminal of the comparator and samples the offset voltage of the A / D converter circuit,
The random clock signal is input only to the switching element for supplying the reference voltage and the switching element for offset cancellation,
The reference voltage supply switching element and the offset canceling switching element are turned on according to the random clock signal.
The A / D converter circuit operates using, as the threshold value, a voltage obtained by adjusting a reference voltage input via the switching element according to the random clock signal by the switching element. Pipeline type A / D converter. The threshold value of the A / D converter circuit is determined according to the pulse width of the random clock signal,
The pipeline type A / D converter according to any one of claims 1 to 3, wherein the random clock signal includes at least two kinds of pulses having different pulse widths. The random clock generation unit generates one or a plurality of the random clock signals, and supplies the plurality of random clock signals to the different A / D converter circuits, respectively . The pipeline type A / D converter according to any one of the above. 6. The random clock signal supplied to each of the plurality of A / D converter circuits has the same pulse width change pattern, according to claim 1 . Pipeline type A / D converter. 6. The pipe according to claim 1 , wherein the random clock signal supplied to each of the plurality of A / D converter circuits has a different change pattern of the pulse width. 7. Line type A / D converter.

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