JP2009124447A - Sampling device and analog/digital conversion device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To average sampling errors due to the jitters of a clock section. <P>SOLUTION: A sampling device includes first and second sampling sections for sampling input signals; first and second charge retaining sections for retaining charges, sampled by the first and second sampling sections; first and second discharging sections for discharging the charges retained by the first and second charge retaining sections; a first clock section for supplying a first clock signal to the first sampling section; and a second clock section for supplying a second clock signal to the second sampling section. The output of the first discharging section and the output of the second discharging section are connected. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a sampling device that performs sampling of an analog signal and an analog-digital conversion device.

  An analog-to-digital converter is a device that converts a continuously changing signal, that is, an analog signal into a digital signal. When converting an analog signal into a digital signal, the analog signal is usually sampled by a sample hold circuit or the like. Sampling is performed in synchronization with a clock signal output from a clock unit such as a PLL, but the clock signal includes jitter.

  Jitter is a temporal fluctuation of a signal waveform. This changes the sampling timing. Therefore, when high sampling accuracy is required, the requirement for jitter becomes severe. The more demanding jitter is, the more difficult circuit design becomes.

  As a known document, Patent Document 1 is known.

Patent Document 1 includes an averaging circuit that takes an average of a plurality of consecutive digital sample values as a countermeasure against jitter in the clock unit.
JP 2002-118463 A

  An object of the present invention is to provide a sampling device and an analog-digital conversion device that reduce the influence of jitter of a clock section in sampling of an analog signal.

  In order to solve the above problems, the sampling device includes first and second sampling units that sample an input signal, and first and second charges that are sampled by the first and second sampling units, respectively. A second charge holding unit; first and second discharge units for discharging the charges held by the first and second charge holding units; and a first clock signal supplied to the first sampling unit. A clock unit; and a second clock unit that supplies a second clock signal to the second sampling unit, wherein the output of the first discharge unit and the output of the second discharge unit are connected to each other. To do.

  According to the embodiment, by connecting a plurality of sample-and-hold circuits in parallel, the sampling error of the sample-and-hold circuit due to jitter in the clock unit can be averaged.

  Examples of the present invention will be described below. The present invention is not limited to the following examples.

  FIG. 1 is an analog-digital conversion apparatus diagram for explaining one embodiment. In FIG. 1A, an input analog signal 103, which is an input signal to the analog-to-digital converter, is input to n sample and hold circuits 100 (n) connected in parallel. n is a natural number of 2 or more. The outputs from the sample and hold circuits 100 (n) are connected to one and input to the conversion unit 104. The conversion unit 104 converts an input analog signal into a digital signal 105 and outputs the digital signal 105, and is generally referred to as an ADC (Analog to Digital Converter).

  Each sample and hold circuit 100 (n) has a clock unit 101 (n) individually. The clock unit 101 (n) is a PLL (Phase Locked Loop) circuit or the like designed to output a clock signal in the same phase and in the same cycle based on the same clock source 106. The clock source 106 supplies a clock signal φ0 to each clock unit 101 (n). The clock unit 101 (n) supplies a clock signal φn to each corresponding sample and hold circuit 100 (n). The clock signal φn controls the sample and hold operation of each sample and hold circuit 100 (n).

  The clock signal φh is supplied from one clock unit 102 to each sample and hold circuit 100 (n). The clock signal φh controls the timing of outputting the signal stored in each sample and hold circuit 100 (n). The clock units 102 and 101 (1) have a non-overlapping circuit 600 described later. Further, the clock units 101 (2) to 101 (n) have a delay circuit 620 described later. As a result, it is possible to avoid overlapping of φn and φh.

  Each sample and hold circuit 100 (n) has a sampling unit, a charge holding unit, and a discharge unit. The sampling unit samples the charge of the input signal at the timing of the clock signal φn. The charge holding unit holds the signal charge sampled at the timing of the clock signal φn. The charge holding unit is realized by a capacitive element, for example. The discharge unit discharges the signal charge held in the charge holding unit from the sample hold circuit 100 (n) at the timing of φh. Since the output of each sample and hold circuit is made common, the charge held in the capacitive element which is the charge holding unit of each sample and hold circuit is redistributed. As a result, the charge amount of each capacitive element becomes an average value of the charge amount charged in each capacitive element before output. As a result, even if there is a variation in the voltage value sampled for each sample-and-hold circuit, the influence can be minimized by connecting a plurality of sample-and-hold circuits so that the output units are common. .

  FIG. 1B is a schematic diagram when a clock is supplied from one clock unit to a plurality of sampling units in the area 110 of FIG. 1A. The clock unit 101 (1) supplies the clock signal φ1 to the sample hold circuits 100 (1) and 100 (2). Even if the sample-and-hold circuit and the clock unit are not 1: 1, if there are a plurality of clock units in the entire apparatus, the effect of the present invention of averaging the jitter of the clock unit can be achieved.

  FIG. 2 is a configuration diagram of a PLL circuit which is an example of the clock unit 101 (n). The reference clock signal 204 input to the PLL is input to the phase detector 200. The phase detector 200 compares the phase difference between the two input signals and outputs a voltage proportional to the phase difference. The output voltage is smoothed by the loop filter 201 and input to a VCO (Voltage Controlled Oscillator) 202. The loop filter 201 is realized by a resistance element, a capacitance element, or the like. The VCO 202 outputs a clock signal 205 having a frequency corresponding to the input voltage. The clock signal 205 is frequency-divided by the frequency divider 203 and input to the phase detector 200.

  The VCO 202 is realized by a multivibrator or the like. When the signal purity of the VCO 202 is low, that is, there is a lot of phase noise, the jitter of the clock signal output from the PLL becomes large.

  FIG. 3 is a waveform diagram of a clock signal that controls a specific example of the sample hold circuit and the switches of each sample hold circuit.

  FIG. 3A shows the sample hold circuit 100 (1) of FIG. 1 embodied by switches 300 (n) and 301 (n) and a capacitive element 302 (n). The switches 300 (n) and 301 (n) are realized by MOS transistors or the like. The switch 300 (n) is a sampling unit and is controlled by a clock signal φn that is an output of a clock unit 101 (n) (not shown). The switch 301 (n) is a discharge unit, and is controlled by a clock signal φh that is an output of the clock unit 102 (not shown). The capacitor 302 (n) is a charge holding portion.

  By turning on the switch 300 (n) and turning off the switch 301 (n), the analog input signal input to the wiring 303 is sampled and charges the capacitor 302 (n). When the switch 300 (n) is turned off, the voltage value of the analog input signal at the moment when the switch 300 (n) is turned off is held in each capacitor 302 (n). When the clock signal φn has different jitters, the moment when the switch 300 (n) is turned off is different, so that the voltage value held in each capacitor 302 (n) is also different.

  When the clock signal φn has no jitter, the voltage value of the analog input signal at the moment when the switch 300 (n) is turned off is Vin. The voltage value of the analog input signal at the moment when the switch 300 (n) is turned off when the clock signal φn has jitter is (Vin + Vn). Vn is a sampling error caused by jitter, and n is a natural number of 2 or more. In the present invention, jitter is generated randomly. The voltage value of the analog output 304 when the switch 301 (n) is turned on is Vout, and the capacitance value of the capacitor 302 (n) is C.

When the input / output units of the two sample and hold circuits are connected in common, that is, when n = 2,
2 × C × Vout = C × (Vin + V1) + C × (Vin + V2)
Holds. Organizing the equation for Vout,
Vout = Vin + (V1 + V2) / 2
It becomes. That is, by connecting the sample and hold circuits in parallel, the error generated in the output voltage is an average value of the sampling errors due to jitter in the individual sample and hold circuits.

  FIG. 3B is a signal waveform diagram of the clock signals φn and φh input to the switches 300 (n) and 301 (n). A waveform 310 (n) represents a waveform of φn, and a waveform 311 represents a waveform of φh. Waveform 312 is an example of input signal 303 in FIG. 3A. The hatched portions of T1 and T2 indicate the jitter generation range of each clock signal φn. Each clock signal waveform 310 (n) changes from “1” to “0” somewhere in the jitter generation range T1. The same operation is performed for the jitter generation range T2. It can be seen that the sampling timing of the waveform 312 changes due to the influence of jitter and a sampling error occurs.

  The clock signal waveform 311 of the clock signal φh is designed so that the timing when it becomes “1” does not overlap with the signal waveform 310 (n) of the clock signal φn.

  FIG. 4 is a waveform diagram of another specific example of the sample and hold circuit and a clock signal for controlling the switch of each sample and hold circuit.

  FIG. 4A shows the sample hold circuit 100 (1) of FIG. 1 embodied with switches 400 (n) and 401 (n) and a capacitive element 402 (n). The switches 400 (n) and 401 (n) are each realized by two MOS transistors or the like. On / off of each MOS transistor is controlled by a separate clock signal.

  In the switch 400 (n), the timing for connecting the wiring 404 and the capacitor 402 (n) is controlled by the clock signal φh, and the timing for connecting the wiring 403 and the capacitor 402 (n) is controlled by the clock signal φnd. The clock signal φnd is a signal obtained by delaying the clock signal φn for a certain time. For the switch 401 (n), the timing for connecting the wiring 405 and the capacitor 402 (n) is controlled by the clock signal φh, and the timing for connecting the wiring 407 and the capacitor 402 (n) is controlled by the clock signal φn. Each of the switches 400 (n) and 401 (n) may be one switch that selects connection with one of the wirings, or is connected using one switch for connection with each wiring. It may be a thing.

  The operation of the sample and hold circuit of FIG. 4A will be described. The capacitor 402 (n) and the wiring 407 are connected by the clock signal φn, and the wiring 403 and the capacitor 402 (n) are connected by the clock signal φnd after a predetermined time has elapsed. The capacitor 402 (n) is charged by an analog input signal input to the wiring 403. The voltage value of the analog input signal at the moment when the clock signal φn becomes “0” is held in the capacitor 402 (n), and the clock signal φnd becomes “0” after a predetermined time has elapsed.

  After that, the clock signal φh is input to the switches 400 (n) and 401 (n), and the wiring 404 and the capacitor 402 (n), and the capacitor 402 (n) and the wiring 405 are connected. As a result, the charge stored in the capacitor 402 (n) is averaged as in FIG. 3, and the average value of the voltage value held in each capacitor 402 (n) is output from the operational amplifier 408. Since the operational amplifier 408 separates the input side and output side circuits with high impedance, even if a capacitive element having a charge is connected to the output of the operational amplifier, the charge charged in the sample hold circuit is not affected. Thereby, the sampling accuracy of the analog input signal can be improved.

  FIG. 4B is a signal waveform diagram of clock signals φn, φnd, and φh input to the switches 400 (n) and 401 (n). Waveform 420 (n) shows the waveform of φn, waveform 421 (n) shows the waveform of φnd, and waveform 422 shows the waveform of φh. The hatched portions of the waveforms 421 (n) and 422 (n) indicate the jitter generation ranges of the clock signals φn and φnd. The clock signal waveforms 420 (n) and 421 (n) change from “1” to “0” somewhere in the jitter generation range.

  The waveform 421 (n) of the clock signal φnd is obtained by delaying the waveform 420 (n) of the clock signal φn by a certain time described later. Further, the clock signal waveform 422 of the clock signal φh is designed so that the timing when it becomes “1” does not overlap with the waveforms 420 (n) and 421 (n) of the clock signals φn and φnd.

  FIG. 5 is a diagram for explaining the reason why the clock signal φnd is delayed for a predetermined time with respect to the clock signal φn.

  FIG. 5A shows the connection between the capacitor 402 (n), the wiring 403, and the wiring 407 with n-type MOS transistors for the switches 400 (n) and 401 (n) in FIG. V1 is applied to the gate of the transistor 501, and V2 is applied to the drain. When the transistor 501 is on, a channel is formed between the drain and source of the transistor 501. The magnitude of the charge forming the channel is proportional to (V1-V2).

  When the voltage value V1 becomes low, the transistor 501 is turned off, and the channel charge forming the channel moves to the drain and source of the transistor. If a current path exists in the circuit when the transistor is turned off, this charge is added to the capacitor 402 (n), thereby causing a sampling error.

  FIG. 5B is a diagram for explaining the operation when the switch 401 (n) is turned off before the switch 400 (n). The switch is realized by an n-type MOS transistor, and the gate voltage V1 is applied when the transistor is turned on. The same members as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

  The channel charge of the switch 401 (n) is proportional to the difference between the gate voltage V1 of the transistor and the ground voltage Vs. Since Vs is 0 V, the channel charge Q1 that moves to the capacitor 402 (n) when the switch 401 (n) is turned off is always constant.

  FIG. 5C is a diagram illustrating an operation when the switch 400 (n) is turned off before the switch 401 (n). The switch is realized by an n-type MOS transistor, and the gate voltage V1 is applied when the transistor is on. The same members as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

  The channel charge Q2 of the switch 400 (n) is proportional to the difference between the gate voltage V1 and the drain voltage Vin of the transistor. Since Vin is an analog signal to be sampled, a different channel charge Q2 moves to the capacitive element 402 (n) at each sampling timing. This is added to the charge of the capacitive element 402 (n), resulting in a sampling error.

  As described above, the sampling error due to the channel charge of the transistor can be reduced by turning off the switch 401 (n) before the switch 400 (n). It is desirable that the switching delay time between the switch 400 (n) and the switch 401 (n) be longer than the time required for the channel charge of the switch 401 (n) to move to the capacitor 402 (n).

  FIG. 6 is a circuit diagram for preventing the logic of the clock signal φn and the clock signal φh from overlapping.

  FIG. 6A shows an example of a non-overlapping circuit 600 that generates the clock signal φ1 and the clock signal φh. A clock signal 601 and a delay signal 611 are input to the NAND circuit 603. The output of the NAND circuit 603 becomes a delay signal 612 delayed by T3 time by the delay unit 605. The delay unit 605 is configured by, for example, connecting a plurality of NOT circuits in series. The delay time can be changed by changing the number of NOT circuits connected in series. The delay signal 612 is inverted by a NOT circuit 607 to become a signal 609. The signal 609 is the clock signal φ1.

  A clock signal 602 obtained by logically inverting the clock signal 601 and a delay signal 612 are input to the NAND circuit 604. The output of the NAND circuit 604 is delayed by T4 time by the delay unit 606 to become a delay signal 611. The delay signal 611 is inverted by the NOT circuit 608 to become a signal 610. Signal 610 is a clock signal φh. When the clock signals φn and φh are simultaneously “1”, the switch for controlling the sampling timing of the sample hold circuit and the switch for outputting the sampled voltage are simultaneously turned on. Since this causes a sampling error, the delay unit is designed so that the delay time T3 is longer than the delay time T4.

  FIG. 6B is an example of a delay circuit for delaying clock signals φ2 to φn for T3 time. The delay circuit 620 includes a NAND circuit 622 (n), a delay unit 623 (n), and a NOT circuit 624 (n). n is a natural number starting from 2. A signal “1” and the clock signal 621 (n) are input to the NAND circuit 622 (n). The output of the NAND circuit 622 (n) is delayed by T3 time by the delay unit 623 (n) and inverted by the NOT circuit 624 (n) to become a signal 625 (n). The signal 625 (n) is a clock signal φn, and n is a natural number starting from 2.

  FIG. 7 is a waveform diagram for explaining the operation of FIG. A waveform 701 represents the clock signal 601 in FIG. 6A, and a waveform 702 represents the clock signal 602. A waveform 702 is obtained by inverting the logic of the waveform 701. Waveform 703 represents signal 609 in FIG. 6A and waveform 704 represents signal 610. Waveform 705 represents signal 625 of FIG. 6B.

  The waveform 703 falls from the waveform 701 with a delay of T3 time. The waveform 704 rises after a delay of T4 time from the fall of the waveform 703. The waveform 704 falls with a delay of T4 from the fall of the waveform 702, and the waveform 703 rises with a delay of T3 time from the fall of the waveform 704. Thereby, the waveform 703 and the waveform 704 do not become the same signal level at the same time. Further, by making the delay time of T3 and T4 larger than the jitter generated in the clock signal φn or φh, it is possible to prevent the waveform 703 and the waveform 704 from having the same signal level simultaneously due to the influence of the jitter. Thereby, the voltage sampled by the sample hold circuit can be output with high accuracy.

  Comparing the waveform 703 and the waveform 705, the rising timing is different, but the falling timing is the same. The sampling voltage value of the analog signal is determined by the falling timing of the sampling clock signal. Therefore, analog signals with the same timing can be sampled if the falling times are the same.

  FIG. 8 is obtained by adding a drive control circuit 801 to the analog-digital conversion apparatus of FIG. The drive control circuit 801 controls the number of drives of the sample hold circuit 100 (n) and the clock unit 101 (n).

  The analog-digital conversion apparatus in FIG. 8 includes a sample and hold circuit 100 (n), clock units 101 (n) and 102, and a conversion unit 104, similar to that in FIG. The same members as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. The drive control circuit 801 receives a signal for determining the number of parallel operations of the sample and hold circuit corresponding to the allowable value of jitter, and controls the sample and hold circuit 100 (n) and the clock unit 101 (n) to stop or drive each. Send a signal. Here, the allowable value of jitter is the fluctuation width in the time direction allowed for the clock signal, and is determined by the accuracy required for the analog-digital converter.

  A clock unit such as a PLL and a conversion unit such as an ADC generally have a power saving mode for stopping circuit operation. Therefore, the drive control circuit 801 is set so as to send a control signal by designating a clock unit to be set in the power saving mode according to the jitter tolerance. Further, the operation of the sample and hold circuit is prevented from becoming unstable by setting the clock unit to the power saving mode. For example, when the clock unit 101 (1) is set to the power saving mode, a switch that operates in response to the clock signal φ1 of the clock unit 101 (1), for example, the switch 300 (1) in FIG. 3A is always turned on. The signal of φ1 is fixed to. Further, the switch 301 (1) is always turned off. That is, the sample hold circuit corresponding to the clock unit set to the power saving mode is fixed to the sample state.

  In the analog-to-digital converter of the present invention, the effect of error due to jitter becomes smaller as the number of parallel sample / hold circuits 100 (n) is increased. On the other hand, when the number of sample and hold circuits 100 (n) and clock units 101 (n) increases, the power consumption increases. Therefore, it is possible to realize low power consumption by mounting a multi-stage sample hold circuit in advance and reducing the number of operations of the sample hold circuit when the allowable value of jitter is large. In addition, the redesign time of the analog-digital converter according to the allowable value of jitter can be shortened.

  FIG. 9 is a diagram illustrating a specific circuit configuration of the drive control circuit 801.

  FIG. 9A is an example of a drive control circuit that can output four control signals. The drive control circuit 801 includes an AND circuit 920 and an OR circuit 921. The drive control circuit 801 receives signals 900 and 901 and outputs signals 911, 912, 913, and 914. The output of the signal 911 is connected to the ground and is always “0”. The signal 912 is a logical product of the signals 900 and 901 input to the AND circuit. Signal 913 is equal to signal 901. The signal 914 is a logical sum of the signals 900 and 901.

  FIG. 9B is a truth table of the drive control circuit 801 shown in FIG. 9A. By using the signals 911, 912, 913, and 914 as control signals, the operation mode of one to four sample and hold circuits can be controlled. For example, when the control signal is “0”, it is defined that the clock unit 101 (n) or the like maintains the operation, and when the control signal is “1”, the operation of the clock unit 101 (n) or the like is stopped. When the signal 900 is “0” and the signal 901 is “1”, only the control signal 914 is “1”, and the other control signals 911 to 913 are “0”. Then, three of the four clock units 101 (n) are in an operating state and one is in a stopped state. In this manner, each drive of the clock unit 101 (n) and the like can be controlled by an input signal to the drive control unit 801.

  FIG. 10 is a diagram for explaining another embodiment of the analog-digital converter. The analog-digital conversion apparatus in FIG. 10 includes a sample and hold circuit 100 (n), clock units 101 (n) and 102, a conversion unit 1000 (n), and a digital average processing unit 1001. 10, the same members as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  A major feature of the analog-digital converter of FIG. 10 is that a conversion unit 1000 (n) is provided at each output of the sample and hold circuit 100 (n). n is a natural number of 2 or more. The analog signals held in the sample hold circuit 100 (n) are encoded into digital signals by the conversion unit 1000 (n), respectively. The encoded digital signal is averaged by a digital average processing unit 1001 and output as a digital signal 1004.

  The digital average processing unit 1001 includes an adding unit 1002 and a dividing unit 1003. Adder 1002 adds the digital signals output from converter 1000 (n). The division unit 1003 divides the added digital signal by 1 / n to calculate an average value. Thereby, in the analog-digital conversion apparatus according to this embodiment, the sampling error due to jitter can be reduced as in the circuit of FIG.

  FIG. 11 is a circuit diagram in which a drive control circuit 801 is added to the analog-digital conversion apparatus of FIG. The analog-digital conversion apparatus in FIG. 11 includes a sample hold circuit 100 (n), clock units 101 (n) and 102, a conversion unit 1000 (n), a digital average processing unit 1101, and a drive control circuit 801. n is a natural number of 2 or more. The same parts constituting FIG. 11 are denoted by the same reference numerals, and the description thereof is omitted. The digital average processing unit 1101 has an adding unit 1102 and a dividing unit 1103. The division unit 1103 changes the value of the division value n according to the control signal of the drive control circuit 801.

  Similar to FIG. 8, the drive control circuit 801 controls the sample hold circuit 100 (n) and the clock unit 101 (n). Further, the drive control unit 801 controls each drive of the conversion unit 1000 (n). In the analog-to-digital converter of the present invention, the effect of error due to jitter becomes smaller as the number of parallel sample / hold circuits 100 (n) is increased. On the other hand, when the number of operations of the sample hold circuit 100 (n), the clock unit 101 (n), and the conversion unit 1000 (n) increases, the power consumption increases. Therefore, by implementing a multi-stage sample and hold circuit in advance and reducing the number of sample and hold circuit operations according to the required jitter value, the design time of the analog-digital converter is shortened while realizing low power consumption. I can do it.

As the number of operations of the sample and hold circuit 100 (n) is decreased, the division value n of the division unit 1103 needs to be changed. The division unit 1103 has a plurality of division circuits having different division values. In accordance with the control signal 1105 transmitted from the drive control circuit 801, a division circuit having a division value n corresponding to the number of operations of the sample hold circuit 100 (n) is selected. Thereby, even if the number of operations of the sample hold circuit 100 (n) changes, the average value can be calculated accurately.
The features of the present invention are described below.
(Appendix 1)
First and second sampling units for sampling an input signal;
First and second charge holding units respectively holding charges sampled by the first and second sampling units;
First and second discharge parts for discharging the charges held by the first and second charge holding parts, respectively;
A first clock unit for supplying a first clock signal to the first sampling unit;
A second clock unit for supplying a second clock signal to the second sampling unit;
Have
The sampling apparatus, wherein the output of the first discharge unit and the output of the second discharge unit are connected.
(Appendix 2)
The sampling apparatus according to claim 1, further comprising a third clock unit that supplies a third clock signal to the first and second discharge units.
(Appendix 3)
The sampling apparatus according to appendix 1, wherein the first clock signal and the second clock signal are delayed by a first time after the third clock signal becomes low level and become high level.
(Appendix 4)
The sampling apparatus according to appendix 1, wherein the first clock signal and the second clock signal are at a low level earlier than a second time from a time when the third clock signal is at a high level.
(Appendix 5)
The sampling apparatus according to appendix 4, wherein the first time is longer than the second time.
(Appendix 6)
The first sampling unit includes a first switch that is turned on / off by the first clock signal;
The second sampling unit includes a second switch that is turned on / off by the second clock signal,
The first charge holding unit includes a first capacitive element connected between the first switch and a ground,
The second charge holding unit includes a second capacitive element connected between the second switch and the ground,
The first discharge unit includes a third switch that is turned on / off by the third clock signal,
The sampling apparatus according to appendix 2, wherein the second discharge unit includes a fourth switch that is turned on / off by the third clock signal.
(Appendix 7)
Further having an operational amplifier,
The first charge holding unit includes a first capacitor element,
The second charge holding unit includes a second capacitive element,
The first sampling unit is connected between one electrode of the first capacitor element and turned on / off by the first clock signal, and is connected between the other electrode of the first capacitor element and the ground. A second switch that is turned on and off by a four clock signal;
The second sampling unit is connected between one electrode of the second capacitive element and turned on / off by the second clock signal, and connected between the other electrode of the second capacitive element and the ground. A fourth switch that is turned on and off by a 5-clock signal;
The first discharge unit is connected between the one electrode of the first capacitive element and the output of the operational amplifier, and is turned on / off by the third clock signal, and the other electrode of the first capacitive element And a sixth switch connected between the operational amplifier and the input of the operational amplifier, and turned on and off by the third clock signal. The second discharge part is between the one electrode of the second capacitive element and the output of the operational amplifier. And a seventh switch that is turned on / off by the third clock signal and an eighth switch that is connected between the other electrode of the second capacitor and the input of the operational amplifier and is turned on / off by the third clock signal. The sampling apparatus according to Supplementary Note 2, wherein
(Appendix 8)
The fourth clock signal is delayed with respect to the first clock signal by a time longer than the time when the channel charge of the first switch is discharged,
The sampling apparatus according to claim 7, wherein the fifth clock signal is delayed with respect to the second clock signal by a time at which the channel charge of the third switch is discharged.
(Appendix 9)
The sampling apparatus according to any one of appendices 1 to 8, further comprising a drive control unit that controls driving of each of the first clock unit and the second clock unit.
(Appendix 10)
First and second sampling units for sampling an input signal;
First and second charge holding units respectively holding charges sampled by the first and second sampling units;
First and second discharge units for discharging the charges held by the first and second charge holding units, respectively;
A first clock unit for supplying a first clock signal to the first sampling unit;
A second clock unit for supplying a second clock signal to the second sampling unit;
A first converter that converts the electric charge discharged by the first discharge unit into a first digital signal;
A second conversion unit that converts the electric charge discharged by the second discharge unit into a second digital signal;
An analog-to-digital conversion device comprising: a digital average processing unit that outputs an average value of the first and second digital signals output from the first and second conversion units.
(Appendix 11)
The analog-digital conversion apparatus according to appendix 10, further comprising a third clock unit that supplies a third clock to the first and second discharge units.
(Appendix 12)
The digital averaging processor is
An adder for adding the first and second digital signals output from the first and second converters;
The analog-digital conversion apparatus according to appendix 10, further comprising: a division unit that divides the addition result by the number of the conversion units.
(Appendix 13)
First and second sampling units for sampling an input signal;
First and second charge holding units respectively holding charges sampled by the first and second sampling units;
First and second discharge units for discharging the charges held by the first and second charge holding units, respectively;
A first clock unit for supplying a first clock signal to the first sampling unit;
A second clock unit for supplying a second clock signal to the second sampling unit;
An analog-digital conversion device comprising: a digital conversion unit commonly connected to the first discharge unit and the second discharge unit.
(Appendix 14)
14. The analog-digital conversion apparatus according to appendix 13, further comprising a third clock unit that supplies a third clock to the first and second discharge units.

Diagram of analog-digital conversion apparatus of embodiment 1 PLL circuit diagram Sample hold circuit diagram Sample hold circuit diagram Diagram of analog-digital conversion apparatus of embodiment 1 Non-overlapping circuit diagram Clock signal waveform diagram Analog-digital converter diagram Drive control circuit diagram Analog-digital converter diagram of embodiment 2 Analog-digital converter diagram of embodiment 2

Explanation of symbols

100 (n) Sample hold circuit 101 (n) Clock unit 102 Clock unit 103 Analog signal 104 Conversion unit 105 Digital signal 106 Clock source 200 Phase detector 201 Loop filter 202 VCO
203 Divider 204 Reference clock 205 Output clock signal 300 (n) Switch 301 (n) Switch 302 (n) Capacitor 310 (n), 311 Clock signal waveform 312 Input signal waveform 408 Operational amplifier 400 (n) Switch 401 (n ) Switch 402 (n) Capacitance element 420 (n) Clock signal waveform 421 (n), 422 Clock signal waveform 501 MOS transistor 600 Non-overlapping circuit 605, 606 Delay unit 620 (n) Delay circuit 701-705 Clock signal waveform 801 Drive control unit 920 AND circuit 921 OR circuit 1000 (n) ADC
1001, 1101 Digital average processor 1002, 1102 Adder 1003, 1103 Dividers 1004, 1104 Digital signal 1105 Control signal

Claims (10)

First and second sampling units for sampling an input signal;
First and second charge holding units respectively holding charges sampled by the first and second sampling units;
First and second discharge parts for discharging the charges held by the first and second charge holding parts, respectively;
A first clock unit for supplying a first clock signal to the first sampling unit;
A second clock unit for supplying a second clock signal to the second sampling unit;
Have
The sampling apparatus, wherein the output of the first discharge unit and the output of the second discharge unit are connected.   The sampling apparatus according to claim 1, further comprising a third clock unit that supplies a third clock signal to the first and second discharge units. The first sampling unit includes a first switch that is turned on / off by the first clock signal;
The second sampling unit includes a second switch that is turned on / off by the second clock signal,
The first charge holding unit includes a first capacitive element connected between the first switch and a ground,
The second charge holding unit includes a second capacitive element connected between the second switch and the ground,
The first discharge unit includes a third switch that is turned on / off by the third clock signal,
The sampling apparatus according to claim 2, wherein the second discharge unit includes a fourth switch that is turned on / off by the third clock signal. Further having an operational amplifier,
The first charge holding unit includes a first capacitor element,
The second charge holding unit includes a second capacitive element,
The first sampling unit is connected between one electrode of the first capacitor element and turned on / off by the first clock signal, and is connected between the other electrode of the first capacitor element and the ground. A second switch that is turned on and off by a four clock signal;
The second sampling unit is connected between one electrode of the second capacitive element and turned on / off by the second clock signal, and connected between the other electrode of the second capacitive element and the ground. A fourth switch that is turned on and off by a 5-clock signal;
The first discharge unit is connected between the one electrode of the first capacitive element and the output of the operational amplifier, and is turned on / off by the third clock signal, and the other electrode of the first capacitive element And a sixth switch connected between the operational amplifier and the input of the operational amplifier, and turned on and off by the third clock signal. The second discharge part is between the one electrode of the second capacitive element and the output of the operational amplifier. And a seventh switch that is turned on / off by the third clock signal and an eighth switch that is connected between the other electrode of the second capacitor and the input of the operational amplifier and is turned on / off by the third clock signal. The sampling device according to claim 2, wherein: The fourth clock signal is delayed with respect to the first clock signal by a time longer than the time when the channel charge of the first switch is discharged,
5. The sampling apparatus according to claim 4, wherein the fifth clock signal is delayed with respect to the second clock signal by at least a time during which the channel charge of the third switch is discharged.   6. The sampling apparatus according to claim 1, further comprising a drive control unit that controls driving of each of the first clock unit and the second clock unit. First and second sampling units for sampling an input signal;
First and second charge holding units respectively holding charges sampled by the first and second sampling units;
First and second discharge units for discharging the charges held by the first and second charge holding units, respectively;
A first clock unit for supplying a first clock signal to the first sampling unit;
A second clock unit for supplying a second clock signal to the second sampling unit;
A first converter that converts the electric charge discharged by the first discharge unit into a first digital signal;
A second conversion unit that converts the electric charge discharged by the second discharge unit into a second digital signal;
An analog-to-digital conversion device comprising: a digital average processing unit that outputs an average value of the first and second digital signals output from the first and second conversion units. The digital averaging processor is
An adder for adding the first and second digital signals output from the first and second converters;
The analog-digital conversion apparatus according to claim 7, further comprising: a division unit that divides the addition result by the number of the conversion units. First and second sampling units for sampling an input signal;
First and second charge holding units respectively holding charges sampled by the first and second sampling units;
First and second discharge units for discharging the charges held by the first and second charge holding units, respectively;
A first clock unit for supplying a first clock signal to the first sampling unit;
A second clock unit for supplying a second clock signal to the second sampling unit;
An analog-digital conversion device comprising: a digital conversion unit commonly connected to the first discharge unit and the second discharge unit. The analog-digital converter according to claim 9, further comprising a third clock unit that supplies a third clock to the first and second discharge units.