JP5724206B2 - Master slice memory cell - Google Patents

Description

  The technology disclosed in the present application relates to a master slice type memory cell.

  The master slice method is one of the technologies related to the formation of a semiconductor integrated circuit. A base (in the following description, referred to as a bulk) is prepared in advance, in which basic cells composed of a predetermined combination of transistors are arranged in a lower layer such as a diffusion layer other than metal wiring or a polysilicon layer. By forming a metal wiring layer according to the circuit configuration, a necessary circuit configuration is realized. A semiconductor integrated circuit corresponding to various circuit configurations is realized by replacing a pattern mask for forming a metal wiring layer which is the final stage of the semiconductor process. This technology contributes to shortening the development and manufacturing period.

  As for the master slice type semiconductor integrated circuit, proposals for various problems have been made. For example, a proposal has been made regarding a method of clipping one gate of a basic cell to a desired potential (for example, Patent Document 1). In addition, in a memory-mounted gate array LSI device, a proposal has been made that a memory block is provided in addition to a logic block having a plurality of basic cells and is used as a dedicated area for realizing a memory circuit (Patent Document 2, etc.). In addition, regarding gate array LSIs, proposals have been made that include a matrix test type test circuit that can read out the signal state at an internal gate (Patent Document 3, etc.). In addition, in order to achieve both the gate speed and the memory density for the master slice type LSI, proposals have been made regarding the configuration of the basic cell transistor (Patent Documents 4, 6, 7, etc.). In addition, a proposal has been made to improve the utilization rate of the basic cells by configuring the memory cells with the basic cells (Patent Document 5, etc.).

Japanese Patent Publication No. 8-28482 Japanese Patent Publication No. 6-95569 JP-A-5-63046 JP-A-6-69475 JP-A-6-84390 JP-A-6-310688 Japanese Patent No. 3277339

  The background art discloses various problems related to the master slice method. However, a basic cell that can handle a plurality of types of circuit configurations with respect to the memory cell by the master slice method is not disclosed. Moreover, it is impossible to realize a basic cell dedicated to a memory cell that can handle this.

  In this regard, Patent Document 2 and the like disclose that a memory block is provided. However, the memory block in this disclosure is a so-called memory cell array including a plurality of memory cells. The disclosure is not related to a basic cell dedicated to a memory cell that can handle a plurality of types of memory cells by the master slice method.

  Further, Patent Documents 4, 6, and 7 disclose that a memory cell can be configured by a basic cell. However, in this disclosure, the basic cell is a configuration for disposing memory cells in high density and disposing transistors constituting a high-speed logic gate. Further, the memory cells to be arranged are only the memory cells having the basic configuration, and are not related to a technique that enables a plurality of types of memory cells to be handled by the master slice method.

  The technology disclosed in the present application has been proposed in view of the above-described problems, and an object thereof is to provide a master slice type memory cell dedicated to a memory cell capable of handling a plurality of types of circuit configurations by the master slice type. .

A master slice type memory cell according to a technique disclosed in the present application includes an N-type first diffusion layer that extends in a column direction and forms a source or drain of the first or second N-type transistor, juxtaposed adjacent to the diffusion layer, and a second diffusion layer of the P-type conductivity type to form a source or drain of the first or second P-type transistor, is juxtaposed adjacent to second diffusion layer, the third or A third diffusion layer of N-type conductivity that forms the source or drain of the fourth N-type transistor, and extends in the row direction, and is disposed above the first diffusion layer and the second diffusion layer, and the first N-type A first gate layer forming a gate electrode of the transistor and the first P-type transistor, and a second gate extending in the row direction and disposed on the first diffusion layer and forming a gate electrode of the second N-type transistor A gate layer and a first Is extended in the row direction on the extension of the over coat layer is disposed on the upper layer of the third diffusion layer, a third gate layer to form a gate electrode of the third N-type transistor, the row on the extended line of the second gate layer A fourth gate layer extending in the direction and disposed on the second diffusion layer and the third diffusion layer and forming gate electrodes of the fourth N-type transistor and the second P-type transistor; The first region of the first diffusion layer between the second gate layer and the second region of the second diffusion layer between the first gate layer and the fourth gate layer with reference to the first gate layer. The first storage node connected to the region at the position by the third metal layer, the third region of the third diffusion layer between the third gate layer and the fourth gate layer, and the fourth gate layer as a reference A second storage node connected to the region opposite to the second region by a third metal layer; 1 region, a region facing the first region with respect to the first gate layer, a region facing the first region with respect to the second gate layer, a second region, and the first gate layer as a reference A region facing the second region, a region facing the second region with reference to the fourth gate layer, a third region, a region facing the third region with reference to the third gate layer, And a plurality of regions connected to any one of the first metal layer, the second metal layer, and the third metal layer above the third metal layer. A plurality of second contact layers disposed in the first contact layer, the first to fourth gate layers, and connected to any of the first to third metal layers, and adjacent to each other among the plurality of first contact layers. Between first contact layers or among a plurality of second contact layers A first metal wiring region in which either the second or third metal layer can be wired along the row direction, at least one of the second contact layers adjacent to each other, a first diffusion layer, A memory unit having a second metal wiring region between which the third metal layer can be wired along the column direction between the second diffusion layer and between the second diffusion layer and the third diffusion layer , Arranged adjacent to each other in mirror symmetry along the column direction, and arranged adjacent to each other along the row direction, arranged in two rows and two columns, and in the first metal layer in the column direction, a power line, a ground line, A pair of bit lines are wired. In each row in which the memory units are juxtaposed, the first and second word lines connected to each of the memory units are wired in the second metal layer below the first metal layer in the row direction . The first to third diffusion layers of the memory unit are disposed between the first and second word lines, and one of the plurality of first contact layers and the plurality of second contact layers of the memory unit is selected. , A power line, a ground line, a pair of bit lines, a first word line, and a second word line.

  According to the master slice type memory cell according to the technique disclosed in the present application, memory units each having one storage node are arranged in two rows and two columns in the row and column directions. In each memory unit, a first metal wiring region is secured along the row direction, and a second metal wiring region is secured along the column direction. Either the second metal layer or the third metal layer can be wired in the first metal wiring region, and the third metal layer can be wired in the second metal wiring region. Selection of a unit used as a memory cell among four memory units arranged in 2 rows and 2 columns, and wiring of the second or third metal layer to the first and second metal wiring regions of each memory unit Depending on the presence or absence, a plurality of types of memory cells having different circuit configurations and driving capabilities can be realized.

It is a layout diagram of a basic memory cell of an embodiment. It is a circuit diagram of a basic memory cell (1 port memory cell). It is the figure which laid out the basic memory cell in the 2-port memory cell. It is a circuit diagram of a 2-port memory cell. FIG. 3 is a diagram in which basic memory cells are laid out in a 1-port high-drive capability memory cell. FIG. 6 is a circuit diagram of a 1-port high drive capability memory cell. FIG. 3 is a diagram in which basic memory cells are laid out in a two-port high drive capability memory cell. FIG. 5 is a circuit diagram of a two-port high drive capability memory cell. It is the figure which laid out the basic memory cell of other embodiments in the high drive capability memory cell of 1 port. FIG. 6 is a circuit diagram of a 1-port high drive capability memory cell using basic memory cells of another embodiment. It is a figure which shows the number of the various memory cells per basic memory cell. It is a figure which shows the area ratio of the basic memory cell of an embodiment, and a dedicated memory cell.

  FIG. 1 shows a basic memory cell 1 constituting the master slice type memory cell of the embodiment. This is the base layout for the master slice method. Four memory units 11A, 11B, 12A, and 12B are arranged in two rows and two columns. In the row direction (X1-X2), the memory unit 11A and the memory unit 11B, and the memory unit 12A and the memory unit 12B are juxtaposed and arranged adjacent to each other. In the column direction (Y1-Y2), the memory unit 11A and the memory unit 12A, and the memory unit 11B and the memory unit 12B are adjacently arranged in mirror symmetry.

  The configuration of the memory unit will be described. The memory units 11A, 11B, 12A, and 12B all have the same configuration. Hereinafter, the memory unit 11A will be described as a representative. The first to third diffusion layers 21 to 23 have a long rectangular shape in the column direction (Y1-Y2) and are juxtaposed in the row direction (X1-X2). In each diffusion layer 21 to 23, two gate layers intersect in the row direction (X1-X2). In this configuration, transistors are connected in parallel. Among these, in the first diffusion layer 21 and the second diffusion layer 22, the gate layer on the column direction (Y2) side is directly connected. The second diffusion layer 22 and the third diffusion layer 23 are directly connected to the gate layer on the column direction (Y1) side.

  Outside the first to third diffusion layers 21 to 23 on the column direction (Y2) side and the (Y1) side, the basic memory cell 1 is penetrated in the row direction (X1-X2), and the first metal layer is formed by the middle metal layer. A word line WLA1 and a second word line WLB1 are wired. The first word line WLA1 is connected to the gate layer that intersects the column direction (Y1) side of the first diffusion layer 21 and the gate layer that intersects the column direction (Y2) side of the third diffusion layer 213. They are connected via a contact layer. The first word line WLA1 to the second contact layer are wired with an upper metal layer. The second word line WLB1 is connected to the corresponding gate layer of the memory unit 11B juxtaposed in the row direction (X2) side via the upper metal layer and the second contact layer.

  The first to third diffusion layers 21 to 23 are formed in an upper metal layer and a middle metal layer in each of the outer region on the column direction (Y1) side and the (Y2) side from each gate layer and the region sandwiched between the gate layers. A first contact layer connected to either the first layer or the lower metal layer.

  A first contact layer in a region sandwiched between gate layers intersecting the first diffusion layer 21, a first contact layer in an outer region on the column direction (Y2) side from the gate layer intersecting the second diffusion layer 22, The second contact layer in the gate layer passing through the second diffusion layer 22 and the third diffusion layer 23 is connected by the lower metal layer to form the storage node N1. Also, a first contact layer in a region sandwiched between gate layers intersecting the third diffusion layer 23, and a first contact in an outer region on the column direction (Y1) side from the gate layer intersecting the second diffusion layer 22 The second contact layer in the gate layer passing through the first diffusion layer 21 and the second diffusion layer 22 is connected by the lower metal layer to form the complementary storage node / N1. These lower metal layers constitute a pair of storage nodes.

  Bit line BLA wired in the upper metal layer in the column direction (Y1-Y2) to the first contact layer (B) in the outer region on the column direction (Y1) side from the gate layer intersecting the first diffusion layer 21 Is connected. The first contact layer (G) in the outer region on the column direction (Y2) side from the gate layer intersecting the first diffusion layer 21 is grounded by the upper metal layer in the column direction (Y1-Y2). Is connected.

  A power line VDD wired by an upper metal layer in the column direction (Y1-Y2) is connected to the first contact layer (V) in the region sandwiched between the gate layers intersecting the second diffusion layer 22.

  A ground line GND wired in the upper metal layer in the column direction (Y1-Y2) to the first contact layer (G) in the outer region on the column direction (Y1) side from the gate layer intersecting the third diffusion layer 23 Is connected. Complementary bit lines wired in the upper metal layer in the column direction (Y1-Y2) to the first contact layer (B) in the outer region on the column direction (Y2) side from the gate layer intersecting the third diffusion layer 23 / BLA is connected.

  From the above connection, the memory unit 11A has the configuration shown in FIG. That is, the inverter gate I1 is configured by the transistors (T2) and (T3) configured by the gate layer penetrating the first diffusion layer 21 and the second diffusion layer 22. The inverter gate I2 is configured by the transistors (T4) and (T5) configured by the gate layer penetrating the third diffusion layer 23 and the second diffusion layer 22. A memory core storing one bit is configured by the inverter gates I1 and I2. The transistor (T1) constituted by the gate layer on the column direction (Y1) side among the gate layers intersecting the first diffusion layer 21 is a transfer interposed between the storage node N1 of the memory core and the bit line BLA. The transistor (T6) that is configured by the gate layer on the column direction (Y2) side of the gate layer that forms the gate and intersects the third diffusion layer 23 includes the complementary storage node / N1 of the memory core and the complementary bit line / BLA. A transfer gate interposed between the two is configured.

  Here, the bit line BLA, the complementary bit line / BLA, the ground line GND, and the power supply line VDD are wired through the memory units 11A and 12A in the column direction (Y1-Y2) by the upper metal layer.

  The basic memory cell 1 has a first contact between the first contact layers disposed in the first to third diffusion layers 21 to 23 through the memory units juxtaposed in the row direction (X1-X2). A first metal wiring region is secured between the layer and the second contact layer. The first metal wiring areas 11-1 and 11-2 are secured through the memory units 11A and 11B, and the first metal wiring areas 12-1 and 12-2 penetrate through the memory units 12A and 12B. Secured. In the first metal wiring regions 11-1, 11-2, 12-1, and 12-2, an intermediate metal layer and a lower metal layer are wired according to the type of the memory cell.

  In addition, the basic memory cell 1 passes through memory units arranged in mirror symmetry in the column direction (Y1-Y2), and extends between the first to third diffusion layers 21 to 23 in the column direction (Y1-Y2). In addition, a second metal wiring region is secured. The second metal wiring regions 2A-1, 2A-2 are secured through the memory units 11A, 12A, and the second metal wiring regions 2B-1, 2B-2 are penetrated through the memory units 11B, 12B. Secured. In the second metal wiring regions 2A-1, 2A-2, 2B-1, and 2B-2, lower metal layers are wired according to the type of the memory cell. Here, the second metal wiring regions 2A-1, 2A-2, 2B-1, and 2B-2 are wired while avoiding interference with the second contact layer as necessary.

  Further, in the memory units 12A and 12B juxtaposed in the row direction (X1-X2), the basic memory cell 1 is placed in the row direction (X1-X2) outside the first to third diffusion layers 21-23. The first word line WLA2 and the second word line WLB2 are wired through the middle metal layer. The first word line WLA2 is connected to the memory unit 12A disposed on the row direction (X1) side via the second contact layer. The first word line WLA2 to the second contact layer are wired with an upper metal layer. The second word line WLB2 is connected to the memory unit 12B disposed on the row direction (X2) side via the second contact layer. The second word line WLB2 to the second contact layer are wired with an upper metal layer.

  FIG. 2 is a circuit diagram of the basic memory cell 1. It is a circuit diagram implement | achieved by the layout (FIG. 1) used as the base of a master slice system. Each of the memory units 11A, 11B, 12A, and 12B includes a 1-bit memory core. Each of the memory units 11A, 11B, 12A, and 12B is selectively controlled by the word lines WLA1, WLB1, WLA2, and WLB2. With this configuration, a 1-port memory cell is configured.

  FIG. 3 is a layout obtained by changing the glass mask for forming the middle metal layer and the lower metal layer for the basic memory cell 1 serving as the base of the master slice method. This is a metal connection for obtaining a 2-port memory cell from the basic memory cell 1. Intermediate metal layers 24, 25, 28, and 29 are wired in the first metal wiring regions 11-1, 11-2, 12-1, and 12-2. The middle metal layer 24 connects the corresponding storage nodes of the memory units 11A and 11B juxtaposed in the row direction (X1-X2). The storage node N1 of the memory unit 11A is connected to the corresponding storage node of the memory unit 11B. The middle metal layer 25 connects corresponding complementary storage nodes of the memory units 11A and 11B juxtaposed in the row direction (X1-X2). The complementary storage node / N1 of the memory unit 11A is connected to the corresponding complementary storage node of the memory unit 11B. The same applies to the middle metal layers 28 and 29. Corresponding storage nodes and complementary storage nodes of the memory units 12A and 12B juxtaposed in the row direction (X1-X2) are connected to each other.

  Further, the branch metal layers 26, 27, 30, 31 are deleted from the memory units 11B, 12B arranged in mirror symmetry in the column direction. Here, the branch metal layer is a part of the lower metal layer constituting the storage node and the complementary storage node. The branched metal layers 26 and 30 are wirings that connect the first contact layer of the first diffusion layer and the first contact layer of the second diffusion layer. The branched metal layers 27 and 31 are wirings that connect the first contact layer of the third diffusion layer and the first contact layer of the second diffusion layer. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move.

  FIG. 4 is a circuit diagram for a 2-port memory cell. FIG. 4 is a circuit diagram of a memory cell obtained by a layout (FIG. 3) in which a glass mask for forming an intermediate metal layer and a lower metal layer is changed with respect to the basic memory cell 1 (FIG. 1).

  In memory unit 11A and memory unit 11B, and in memory unit 12A and memory unit 12B, nodes corresponding to each other in a pair of storage nodes are connected by intermediate metal layers 24, 26, and 28, 29, respectively. Further, in the memory units 11B and 12B, the signal path from the power line VDD of the inverter gate constituting the memory core is divided by deleting the branch metal layers 26, 27 and 30, 31.

  As a result, the memory core of the memory unit 11A is accessed through two ports, the port selected by the first word line WLA1 and the port selected by the second word line WLB1. The memory core of the memory unit 12A is accessed through two ports, a port selected by the first word line WLA2 and a port selected by the second word line WLB2.

  FIG. 5 shows a layout obtained by changing the glass mask for forming the lower metal layer for the basic memory cell 1 serving as the base of the master slice method. This is a metal connection for obtaining a one-port high drive capability memory cell from the basic memory cell 1. Lower metal layers 32, 33, 34, and 35 are wired in the second metal wiring regions 2A-1, 2A-2, 2B-1, and 2B-2. The lower metal layer 32 connects the corresponding storage nodes of the memory units 11A and 12A arranged in the column direction (Y1-Y2). The storage node N1 of the memory unit 11A is connected to the corresponding storage node of the memory unit 12A. The lower metal layer 33 connects the corresponding complementary storage nodes of the memory units 11A and 12A arranged in the column direction (Y1-Y2). The complementary storage node / N1 of the memory unit 11A is connected to the corresponding complementary storage node of the memory unit 12A. The same applies to the lower metal layers 34 and 35. Corresponding storage nodes and complementary storage nodes of the memory units 11B and 12B arranged in the column direction (Y1-Y2) are connected to each other.

  FIG. 6 is a circuit diagram for a 1-port high drive capability memory cell. FIG. 6 is a circuit diagram of a memory cell obtained by a layout (FIG. 5) in which a glass mask for forming a lower metal layer is changed with respect to the basic memory cell 1 (FIG. 1).

  In memory unit 11A and memory unit 12A, and in memory unit 11B and memory unit 12B, nodes corresponding to each other in a pair of storage nodes are connected by lower metal layers 32, 33, and 34, 35, respectively. When accessing the memory core, the first word lines WLA1 and WLA2 and the second word lines WLB1 and WLB2 are each short-circuited by a metal wiring (not shown) or operated synchronously as a circuit operation.

  Thus, the memory units 11A and 12A constitute one memory core, and the memory units 11B and 12B constitute one memory core. Each of them is accessed in parallel after being connected in parallel. While the driving capability of the memory core is doubled, the on-resistance during conduction is halved by connecting two transistors in parallel to the transfer gate. By doubling the driving capability and halving the resistance of the signal path, a memory cell with high driving capability can be obtained.

  FIG. 7 shows a layout obtained by changing the glass mask for forming the middle metal layer and the lower metal layer for the basic memory cell 1 serving as the base of the master slice method. This is a metal connection for obtaining a 2-port high drive capability memory cell from the basic memory cell 1. Intermediate metal layers 24, 25, 28, and 29 are wired in the first metal wiring regions 11-1, 11-2, 12-1, and 12-2. The middle metal layer 24 connects the corresponding storage nodes of the memory units 11A and 11B juxtaposed in the row direction (X1-X2). The storage node N1 of the memory unit 11A is connected to the corresponding storage node of the memory unit 11B. The middle metal layer 25 connects corresponding complementary storage nodes of the memory units 11A and 11B juxtaposed in the row direction (X1-X2). The complementary storage node / N1 of the memory unit 11A is connected to the corresponding complementary storage node of the memory unit 11B. The same applies to the middle metal layers 28 and 29. Corresponding storage nodes and complementary storage nodes of the memory units 12A and 12B juxtaposed in the row direction (X1-X2) are connected to each other.

  Further, the branch metal layers 26, 27, 30, and 31 are deleted from the memory units 11B and 12B that are arranged mirror-symmetrically in the column direction. Here, the branch metal layer is a part of the lower metal layer constituting the storage node and the complementary storage node. The branched metal layers 26 and 30 are wirings that connect the first contact layer of the first diffusion layer and the first contact layer of the second diffusion layer. The branched metal layers 27 and 31 are wirings that connect the first contact layer of the third diffusion layer and the first contact layer of the second diffusion layer. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move.

  The metal wiring described above is the same as the layout (FIG. 3) when a 2-port memory cell is configured.

  Further, lower metal layers 32 and 33 are wired in the second metal wiring regions 2A-1 and 2A-2. The lower metal layer 32 connects the corresponding storage nodes of the memory units 11A and 12A arranged in the column direction (Y1-Y2). The storage node N1 of the memory unit 11A is connected to the corresponding storage node of the memory unit 12A. The lower metal layer 33 connects the corresponding complementary storage nodes of the memory units 11A and 12A arranged in the column direction (Y1-Y2). The complementary storage node / N1 of the memory unit 11A is connected to the corresponding complementary storage node of the memory unit 12A.

  The above metal wiring is the same as that of the lower metal layers 32 and 33 in the layout (FIG. 5) when a 1-port high drive capability memory cell is configured.

  FIG. 8 is a circuit diagram in the case of a 2-port high drive capability memory cell. FIG. 8 is a circuit diagram of a memory cell obtained by a layout (FIG. 7) in which a glass mask for forming an intermediate layer and a lower metal layer is changed with respect to the basic memory cell 1 (FIG. 1).

  In the circuit diagram of the 2-port memory cell illustrated in FIG. 4, the nodes corresponding to each other among the pair of storage nodes of the memory unit 11 </ b> A and the memory unit 12 </ b> A are connected by the lower metal layers 32 and 33. . When accessing the memory core, the first word lines WLA1 and WLA2 and the second word lines WLB1 and WLB2 are each short-circuited by a metal wiring (not shown) or operated synchronously as a circuit operation.

  As a result, the memory units 11A, 12A, 11B, and 12B constitute one memory core. Here, the memory cores in the memory units 11B and 12B are not used. The memory cores of the memory units 11A and 12A are accessed in synchronization after being connected in parallel. While the driving capability of the memory core is doubled, the on-resistance during conduction is halved by connecting two transistors in parallel to the transfer gate. The access has a two-port configuration that is performed from each of the first word lines WLA1 and WLA2 or the second word lines WLB1 and WLB2. By doubling the driving capability and halving the resistance of the signal path, a two-port memory cell that can be a memory cell with high driving capability is configured.

  FIG. 9 shows the basic configuration of another embodiment in which the first metal wiring regions 11-3, 11-4, 12-3, and 12-4 are secured for the basic memory cell 1 serving as the base of the master slice system. It is based on a memory cell. It is a layout obtained by changing the glass mask which forms a lower metal layer. This is another metal connection for obtaining a 1-port high drive capability memory cell from the basic memory cell. Lower metal layers 34 and 35 are wired in the first metal wiring regions 11-3 and 11-4. In the memory unit 11A, the first contact layer of the third diffusion layer to which the complementary bit line / BLA is connected is removed. Instead, a first contact layer for connecting the lower metal layer 34 is disposed in the third diffusion layer of the memory unit 11A. Lower metal layer 34 is connected to complementary bit line / BLB. Similarly, in the memory unit 11B, the first contact layer of the first diffusion layer to which the bit line BLB is connected is removed. Instead, a first contact layer for connecting the lower metal layer 35 is disposed in the first diffusion layer of the memory unit 11B. The lower metal layer 35 is connected to the bit line BLA.

  The same applies to the lower metal layers 36 and 37. In the memory unit 12A, the first contact layer of the third diffusion layer to which the complementary bit line / BLA is connected is removed. Instead, a first contact layer for connecting the lower metal layer 36 is disposed in the third diffusion layer of the memory unit 12A. Lower metal layer 36 is connected to complementary bit line / BLB. Similarly, in the memory unit 12B, the first contact layer of the first diffusion layer to which the bit line BLB is connected is removed. Instead, a first contact layer for connecting the lower metal layer 37 is disposed in the first diffusion layer of the memory unit 12B. The lower metal layer 37 is connected to the bit line BLA.

  FIG. 10 is a circuit diagram in the case of a 1-port high drive capability memory cell realized by another embodiment. FIG. 10 is a circuit diagram realized by the layout of FIG. 9.

  The memory cores of the memory units 11A, 11B, 12A, and 12B are connected in parallel between the bit line BLA and the complementary bit line / BLB. When accessing the memory core, the first word line WLA1 and the second word line WLB1, and the first word line WLA2 and the second word line WLB2 are each short-circuited by a metal wiring (not shown) or synchronously operated as a circuit operation. Is done.

  Thus, the memory units 11A and 11B constitute one memory core, and the memory units 12A and 12B constitute one memory core. The memory core has a configuration in which the memory cores of the memory units 11A and 11B and the memory cores of the memory units 12A and 12B are connected in parallel. Access is performed in synchronization with two word lines. While the driving capability of the memory core is doubled, the on-resistance during conduction is halved by connecting two transistors in parallel to the transfer gate. By doubling the driving capability and halving the resistance of the signal path, a memory cell with high driving capability can be obtained. The access has two ports.

  From the basic memory cell 1 described with reference to FIGS. 1 to 8 or the basic memory cell described with reference to FIGS. 9 and 10, the types of memory cells configured by changing the metal layer by the master slice method and the number per basic memory cell As shown in FIG.

  Memory cells composed of basic memory cells are 1-port memory cells (FIGS. 1 and 2), 2-port memory cells (FIGS. 3 and 4), and 1-port high drive capability memory cells (FIGS. 5, 6, and 9). 10) and two-port high-capacity memory cells (FIGS. 7 and 8).

  The number of memory cells per basic memory cell of each memory cell is 4 for a 1-port memory cell (FIGS. 1 and 2), 2 for a 2-port memory cell (FIGS. 3 and 4), and 1 port In the case of the high drive capability memory cell (FIGS. 5, 6, 9, and 10), there are two, and there is one 2-port high drive capability memory cell (FIGS. 7 and 8).

  By changing the metal layer for the basic memory cell 1 (FIG. 1) or the basic memory cell (in the case of another embodiment of FIG. 9), four types of memory cells can be obtained based on the bulk configuration of the basic memory cell. Thus, the area can be configured efficiently.

  FIG. 12 is a diagram comparing the exclusive area of the master slice type memory cell of the embodiment with the case where the dedicated memory cell is used. FIG. 11 illustrates a case where area comparison is performed between a 1-port memory cell (denoted as 1RW) and a 2-port memory cell (denoted as 2RW).

  In the layout in which the basic memory cells of the embodiment are arranged in a matrix of 2 rows and 6 columns, when only 1 port memory cells are configured (A), when 1 port / 2 ports are mixed (B), 2 ports Consider the three cases (C) in which only memory cells are configured.

  In the basic memory cell of 2 rows and 6 columns, the type (A) is a 24-port 1-port memory cell, the type (B) is a 12-cell 1-port memory cell and a 6-cell 2-port memory cell, and the type (C) is 12 The 2-port memory cell of the cell can be handled by changing the metal layer by the master slice method.

  When the same memory cell configuration is realized by dedicated memory cells of 1 port / 2 ports, it is necessary to provide a 1-port memory cell array of 4 rows and 6 columns and a 2-port memory cell array of 2 rows and 6 columns. Two times as many famous sites as the area ratio are required.

  According to the embodiment, a master slice type memory cell is provided, and a plurality of types of memory cells can be configured in accordance with the change of the metal layer, and the area efficiency in the layout can be improved.

  Here, in the embodiment, the upper metal layer is an example of the first metal layer, the middle metal layer is an example of the second metal layer, and the lower metal layer is an example of the third metal layer.

  As described above in detail, the basic memory cell 1 in which the memory units 11A, 11B, 12A, and 12B are arranged in 2 rows and 2 columns, or the basic memory cell in another embodiment, is changed by the master slice method that changes the metal layer. By configuring, it is possible to configure four types of memory cells: 1-port memory cell, 2-port memory cell, 1-port high drive capability memory cell, and 2-port high drive capability memory cell simply by changing the metal layer. can do. Compared with the case where a dedicated memory cell is prepared for each type, the area efficiency in the layout can be improved. A plurality of types of memory cells can be configured in a limited layout region, and a plurality of types of memory cells can be mixed.

Needless to say, the present configuration is not limited to the illustrated embodiment, and various modifications and changes can be made without departing from the spirit of the present object.
For example, the case where memory units are arranged in two rows and two columns as basic memory cells is illustrated, but the present invention is not limited to this. A configuration in which memory units are arranged in three or more rows or / and three or more columns can be used as a basic memory cell. This makes it possible to configure further types of memory cells by the master slice method. For example, a configuration in which the number of ports is a multi-port with three or more ports, a configuration in which the driving capability is set in multiple stages such as double, triple, and quadruple are possible.

1 Basic memory cells 11A, 11B, 12A, 12B Memory units 21-23 First to third diffusion layers 24, 25, 28, 29 Middle metal layers 26, 27, 30, 31 Branch metal layers 32, 33, 34, 35 , 36, 37 Lower metal layers 11-1, 11-2, 11-3, 11-4, 12-1, 12-2, 12-3, 12-4 First metal wiring regions 2A-1, 2A- 2, 2B-1, 2B-2 Second metal wiring area BLA, BLB Bit line / BLA, / BLB Complementary bit line GND Ground line I1, I2 Inverter gate N1 Storage node / N1 Complementary storage node T1 to T6 Transistor VDD Power supply Lines WLA1, WLA2 First word lines WLB1, WLB2 Second word lines Y1-Y2 Column direction

Claims (4)

An N-type conductivity type first diffusion layer extending in the column direction and forming the source or drain of the first or second N-type transistor;
A P-type conductivity type second diffusion layer juxtaposed adjacent to the first diffusion layer and forming a source or drain of the first or second P-type transistor;
A third diffusion layer of N type conductivity type juxtaposed adjacent to the second diffusion layer and forming a source or drain of a third or fourth N type transistor;
Is extended in the row direction, and the first is located in the upper layer of the diffusion layer and said second diffusion layer, a first gate layer to form the first N-type transistor and the gate electrode of the first P-type transistor,
A second gate layer extending in the row direction and disposed on an upper layer of the first diffusion layer and forming a gate electrode of the second N-type transistor;
A third gate layer extending in the row direction on an extension line of the first gate layer and disposed on an upper layer of the third diffusion layer, and forming a gate electrode of the third N-type transistor;
The gates of the fourth N-type transistor and the second P-type transistor are extended in the row direction on the extension line of the second gate layer, and are disposed on the second diffusion layer and the third diffusion layer. A fourth gate layer forming an electrode;
A first region of the first diffusion layer between the first gate layer and the second gate layer, and between the first gate layer and the fourth gate layer with reference to the first gate layer; A first storage node connected by a third metal layer to a region facing the second region of the second diffusion layer;
A third region of the third diffusion layer between the third gate layer and the fourth gate layer and a region at a position facing the second region with respect to the fourth gate layer are a third region . A second storage node connected by a metal layer;
The first region, the region facing the first region with respect to the first gate layer, the region facing the first region with respect to the second gate layer, the second region, A region facing the second region with respect to the first gate layer; a region facing the second region with respect to the fourth gate layer; the third region; and the third gate layer. The first metal layer and the first metal layer above the third metal layer are disposed in a region facing the third region with respect to the reference and a region facing the third region with respect to the fourth gate layer, respectively. a plurality of first contact layer connected to either of the second metal layer and third metal layer,
A plurality of second contact layers disposed on the first to fourth gate layers and connected to any of the first to third metal layers;
At least one of the first contact layers adjacent to each other among the plurality of first contact layers or between the second contact layers adjacent to each other among the plurality of second contact layers, A first metal wiring region in which either the second or third metal layer can be wired along the row direction;
A second metal wiring region in which the third metal layer can be wired along the column direction between the first diffusion layer and the second diffusion layer and between the second diffusion layer and the third diffusion layer;
Are arranged adjacent to each other in mirror symmetry along the column direction, and arranged side by side along the row direction, and arranged in 2 rows and 2 columns,
Power line, ground line, and a first metal layer you wire a pair of bit lines to said column direction,
Wherein for each row of the memory units are juxtaposed, the row direction are wired by the second metal layer of the lower layer than the first metal layer, and first and second word line connected to each of said memory units,
The first to third diffusion layers of the memory unit are disposed between the first and second word lines;
One of the plurality of first contact layers and the plurality of second contact layers of the memory unit is selected, and the power line, the ground line, the pair of bit lines, the first word line, and A master slice type memory cell connected to any one of the second word lines. About two rows of the memory units arranged adjacent to each other in mirror symmetry along the column direction,
The second metal interconnection region, the first storage node of one of said memory unit, and a third metal layer that connects to the first storage node of the other of said memory unit, said of said one memory unit a second storage node, and a third metal layer that connects to the second storage node of the other memory unit,
2. The master slice type memory cell according to claim 1, wherein the two rows of memory units are configured as one-port high drive capability memory cells by the synchronous operation of the first or second word lines. Regarding the two memory units juxtaposed adjacently along the row direction,
One bit line of the pair of bit lines connected to one of the memory units is connected to the first metal wiring region with respect to the second gate layer of the other memory unit . a third metal layer that connects to the region opposed to the first region of the memory unit, the other bit line of the pair of bit lines, wherein connected to one of the memory units, of the other memory unit and a third metal layer on the basis of the third gate layer to connect to the third region of the other memory unit,
2. The master slice type memory cell according to claim 1, wherein the two rows of memory units are configured as one-port high drive capability memory cells. A cell region disposed on a semiconductor substrate;
First to fourth memory cell regions arranged in a matrix in the cell region, each having a quarter area of the cell region;
A first word line disposed on the first memory cell region and the second memory cell region adjacent to the first memory cell region in the row direction and extending in the row direction;
A second word disposed on the first memory cell region and the second memory cell region, extending in the row direction, and spaced apart in the column direction with respect to the first word line Lines and,
Arranged on the third memory cell region adjacent to the first memory cell region in the column direction and on the fourth memory cell region adjacent to the third memory cell region in the row direction; A third word line extending in the direction;
The fourth memory cell region is disposed on the third memory cell region and the fourth memory cell region, extends in the row direction, and is spaced apart from the third word line in the column direction. A word line,
A first memory unit connected to the first word line and disposed in the first memory cell region;
A second memory unit connected to the second word line, disposed in the second memory cell region, and having the same structure as the first memory unit;
Connected to the third word line, disposed in the third memory cell region, and at the boundary between the first memory cell region and the third memory cell region with respect to the first memory unit A third memory unit having a mirror-symmetric structure;
A fourth memory unit connected to the fourth word line, disposed in the fourth memory cell region, and having the same structure as the third memory unit;
Have
The first memory unit is
First to third diffusion regions having a rectangular shape extending in the column direction and spaced apart in the row direction in the first memory cell region;
A first gate line disposed on the first and second diffusion regions in the first memory cell region and extending in the row direction;
A second gate wiring disposed on the first diffusion region, extending in the row direction, and spaced apart in the column direction with respect to the first gate wiring;
A third gate line extending on an extension of the first gate line and disposed on the third diffusion region in the first memory cell region;
A fourth gate line extending on an extension of the second gate line and disposed on the second and third diffusion regions in the first memory cell region;
A first metal wiring region provided between the first gate wiring and the fourth gate wiring and provided in the row direction on the first to third diffusion regions;
A second metal wiring region provided in the column direction between the first diffusion region and the second diffusion region and between the second diffusion region and the third diffusion region;
A first region of the first diffusion region between the first gate wiring and the second gate wiring; and the first gate wiring and the fourth gate on the basis of the first gate wiring. A first storage node connected by a third metal layer to a region facing the second region of the second diffusion region between the gate wiring and the second wiring region;
A third region of the third diffusion region between the third gate wiring and the fourth gate wiring and a region facing the second region with respect to the fourth gate wiring A second storage node connected by a third metal layer;
Have
The third memory unit is
First to third diffusion regions having a rectangular shape extending in the column direction and spaced apart in the row direction in the third memory cell region;
A first gate line disposed on the first and second diffusion regions in the third memory cell region and extending in the row direction;
A second gate wiring disposed on the first diffusion region, extending in the row direction, and spaced apart in the column direction with respect to the first gate wiring;
A third gate line extending on an extension of the first gate line and disposed on the third diffusion region in the third memory cell region;
A fourth gate line extending on an extension of the second gate line and disposed on the second and third diffusion regions in the third memory cell region;
A first metal wiring region provided between the first gate wiring and the fourth gate wiring and provided in the row direction on the first to third diffusion regions;
A second metal wiring region provided in the column direction between the first diffusion region and the second diffusion region and between the second diffusion region and the third diffusion region;
A first region of the first diffusion region between the first gate wiring and the second gate wiring; and the first gate wiring and the fourth gate on the basis of the first gate wiring. A first storage node connected by a third metal layer to a region facing the second region of the second diffusion region between the gate wiring and the second wiring region;
A third region of the third diffusion region between the third gate wiring and the fourth gate wiring and a region facing the second region with respect to the fourth gate wiring A second storage node connected by a third metal layer;
Have
The first storage node of the first memory unit is connected to the first storage node of the third memory unit in the second metal wiring region of each of the first and third memory units. A third metal layer, and a third metal layer connecting the second storage node of the first memory unit to the second storage node of the third memory unit;
A master slice type memory cell characterized in that the first and third memory units are configured as one-port high drive capability memory cells by the synchronous operation of the first and third word lines .

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