JP5699817B2 - Memory cell - Google Patents

Description

  The technology disclosed in the present application relates to a memory cell. In particular, the present invention relates to a memory cell in which a bulk layer such as a diffusion layer or a polysilicon layer is fixed and at least one of a metal layer and a contact layer can be changed to support a plurality of circuit specifications.

  The master slice method is one of the technologies related to the formation of a semiconductor integrated circuit. A base (in the following description, referred to as a bulk) is prepared in advance, in which basic cells composed of a predetermined combination of transistors are arranged in a lower layer such as a diffusion layer other than metal wiring or a polysilicon layer. By forming a metal wiring layer according to the circuit configuration, a necessary circuit configuration is realized. A semiconductor integrated circuit corresponding to various circuit configurations is realized by replacing a pattern mask for forming a metal wiring layer which is the final stage of the semiconductor process. This technology contributes to shortening the development and manufacturing period.

  As for the master slice type semiconductor integrated circuit, proposals for various problems have been made. For example, a proposal has been made regarding a method of clipping one gate of a basic cell to a desired potential (for example, Patent Document 1). In addition, in a memory-mounted gate array LSI device, a proposal has been made that a memory block is provided in addition to a logic block having a plurality of basic cells and is used as a dedicated area for realizing a memory circuit (Patent Document 2, etc.). In addition, regarding gate array LSIs, proposals have been made that include a matrix test type test circuit that can read out the signal state at an internal gate (Patent Document 3, etc.). In addition, in order to achieve both the gate speed and the memory density for the master slice type LSI, proposals have been made regarding the configuration of the basic cell transistor (Patent Documents 4, 6, 7, etc.). In addition, a proposal has been made to improve the utilization rate of the basic cells by configuring the memory cells with the basic cells (Patent Document 5, etc.).

Japanese Patent Publication No. 8-28482 Japanese Patent Publication No. 6-95569 JP-A-5-63046 JP-A-6-69475 JP-A-6-84390 JP-A-6-310688 Japanese Patent No. 3277339

  The background art discloses various problems related to the master slice method. However, a basic cell that can handle a plurality of types of circuit configurations with respect to the memory cell by the master slice method is not disclosed. Moreover, it is impossible to realize a basic cell dedicated to a memory cell that can handle this.

  In this regard, Patent Document 2 and the like disclose that a memory block is provided. However, the memory block in this disclosure is a so-called memory cell array including a plurality of memory cells. The disclosure is not related to a basic cell dedicated to a memory cell that can handle a plurality of types of memory cells by the master slice method.

  Further, Patent Documents 4, 6, and 7 disclose that a memory cell can be configured by a basic cell. However, in this disclosure, the basic cell is a configuration for disposing memory cells in high density and disposing transistors constituting a high-speed logic gate. Further, the memory cells to be arranged are only the memory cells having the basic configuration, and are not related to a technique that enables a plurality of types of memory cells to be handled by the master slice method.

  The technology disclosed in the present application has been proposed in view of the above-mentioned problems, and a plurality of types of circuit configurations are fixed in a bulk layer such as a diffusion layer or a polysilicon layer, and a metal layer and a contact layer An object of the present invention is to provide a memory cell that can be handled by changing at least one of the layers.

A memory cell according to the technology disclosed in the present application includes a memory unit that is arranged in mirror symmetry along the column direction and juxtaposed along the row direction and arranged in two rows and two columns, In each row in which the memory units are juxtaposed, first and second word lines connected to each of the memory units are wired with a first metal layer. A power supply line, a ground line, and a bit line are wired in the column direction in the second metal layer.
The memory unit includes first and second diffusion layers juxtaposed along the row direction and extended in the column direction, and a diffusion provided between the first diffusion layer and the second diffusion layer and extended in the column direction for use in the transistor A first diffusion layer extending between the first diffusion layer and the third diffusion layer, the gate layer extending from one side of the gate layer intersecting the first diffusion layer, and extending in the column direction. A diffusion layer provided for the transistor, and a fourth diffusion layer extending from the gate layer on the other side that intersects the second diffusion layer, and is connected in parallel by each diffusion layer A transistor is configured. Between the region of the first diffusion layer sandwiched between the gate layer of the transistor and the region of the third diffusion layer on the same side as the region of the first diffusion layer with respect to the gate layer on one side, and sandwiched between the gate layer of the transistor A pair of second diffusion layers connected to each other by a third metal layer between the second diffusion layer region and the fourth diffusion layer region on the same side as the second diffusion layer region with respect to the other gate layer. Configure storage nodes. Two first metal wiring regions are secured between the first word line and the second word line. A first metal layer can be wired in the first metal wiring region. Among the memory units arranged in 2 rows and 2 columns, it is a boundary region between memory units arranged adjacent to each other in the column direction, along the column direction at a position in the column direction where the third and fourth diffusion layers are arranged. A second metal wiring region is secured. A second metal wiring region is secured along the column direction between the first diffusion layer and the second diffusion layer and between the second diffusion layer and the third diffusion layer. A second metal layer can be wired in the second metal wiring region.
The memory cell according to the technology disclosed in the present application is configured by arranging memory units in two rows and two columns in the row direction and the column direction. In this case, they are arranged adjacent to each other in mirror symmetry along the column direction and the row direction.
The memory unit includes first and second diffusion layers juxtaposed along the row direction and extended in the column direction, and a diffusion provided between the first diffusion layer and the second diffusion layer and extended in the column direction for use in the transistor A first diffusion layer extending between the first diffusion layer and the third diffusion layer, the gate layer extending from one side of the gate layer intersecting the first diffusion layer, and extending in the column direction. A diffusion layer provided for the transistor, and a fourth diffusion layer extending from the gate layer on the other side that intersects the second diffusion layer, and is connected in parallel by each diffusion layer A transistor is configured. Between the region of the first diffusion layer sandwiched between the gate layer of the transistor and the region of the third diffusion layer on the same side as the region of the first diffusion layer with respect to the gate layer on one side, and sandwiched between the gate layer of the transistor A pair of second diffusion layers connected to each other by a third metal layer between the second diffusion layer region and the fourth diffusion layer region on the same side as the second diffusion layer region with respect to the other gate layer. Configure storage nodes. A 1-1 metal wiring region is secured along the row direction between the first word line and the second word line. The first metal layer can be wired in the 1-1 metal wiring region. One of a pair of storage nodes in a memory unit arranged adjacent to one of a pair of storage nodes in a boundary region of memory units arranged adjacent to each other in the row direction among memory units arranged in two rows and two columns The first metal wiring region 1-2 that can be wired with the third metal layer provided for connection to the memory region and the boundary region between the memory units arranged adjacent to each other in the column direction among the memory units arranged in two rows and two columns Thus, a 2-1 metal wiring region in which the third metal layer can be wired along the column direction is secured at a position in the column direction where the third diffusion layer is disposed. Among the memory units arranged in 2 rows and 2 columns, in the boundary region of the memory units adjacently arranged in the column direction and adjacent to the memory units adjacently arranged in the row direction, the second 2-2 along the column direction The metal wiring area is secured. The second metal layer or the third metal layer can be wired in the 2-2 metal wiring region.

According to the memory cell according to the technique disclosed in the present application, memory units each having one storage node are arranged in two rows and two columns in the row and column directions. In each memory unit, a first metal wiring region is secured along the row direction, and a second metal wiring region is secured along the column direction. A first metal layer can be wired in the first metal wiring region, and a second metal layer can be wired in the second metal wiring region.
Further, according to the memory cell according to the technique disclosed in the present application, one memory unit having a storage node is arranged in two rows and two columns in the row and column directions. In each memory unit, 1-1 and 1-2 metal wiring regions are secured in the row direction in the individual memory units, and 2-1 and second in the column direction. -2 metal wiring area is secured. A first metal layer can be wired in the 1-1 metal wiring region, and a third metal layer can be wired in the 1-2 metal wiring region. The third metal layer can be wired in the 2-1 metal wiring region, and the second or third metal layer can be wired in the 2-2 metal wiring region.
According to these, depending on whether or not the selection of the unit used as a memory cell among the four memory units arranged in 2 rows and 2 columns, and the wiring of each metal layer to each metal wiring region of each memory unit, A plurality of types of memory cells having different circuit configurations and driving capabilities can be realized.

FIG. 3 is a layout diagram of a basic memory cell according to the first embodiment. It is a circuit diagram of a basic memory cell (1 port memory cell). FIG. 3 is a diagram in which the basic memory cell of the first embodiment is laid out in a 2-port memory cell. It is a circuit diagram of a 2-port memory cell. FIG. 3 is a diagram in which the basic memory cell according to the first embodiment is laid out in a 1-port high drive capability memory cell. FIG. 6 is a circuit diagram of a 1-port high drive capability memory cell. FIG. 3 is a diagram in which the basic memory cell according to the first embodiment is laid out in a 2-port high drive capability memory cell. FIG. 5 is a circuit diagram of a two-port high drive capability memory cell. FIG. 3 is a diagram in which the basic memory cell according to the first embodiment is laid out in a 1-port low-voltage memory cell. 1 is a circuit diagram of a 1-port low-voltage memory cell. FIG. FIG. 3 is a diagram in which the basic memory cell according to the first embodiment is laid out in a two-port low voltage type memory cell. It is a circuit diagram of a low voltage memory cell of 2 ports. FIG. 6 is a diagram (another example) in which the basic memory cell according to the first embodiment is laid out in a 1-port high drive capability memory cell. FIG. 6 is a circuit diagram (another example) of a 1-port high drive capability memory cell. FIG. 6 is a layout diagram of a basic memory cell according to a second embodiment. It is the figure which laid out the basic memory cell of 2nd Embodiment in the 2 port memory cell. FIG. 10 is a diagram in which the basic memory cell of the second embodiment is laid out in a 1-port high drive capability memory cell. FIG. 10 is a diagram in which the basic memory cell according to the second embodiment is laid out in a 2-port high drive capability memory cell. FIG. 10 is a diagram in which the basic memory cell according to the second embodiment is laid out in a 1-port low-voltage memory cell. FIG. 10 is a diagram in which the basic memory cell according to the second embodiment is laid out in a two-port low-voltage memory cell. FIG. 11 is a diagram (another example) in which the basic memory cell according to the second embodiment is laid out in a 1-port high drive capability memory cell. It is a figure which shows the number of the various memory cells per basic memory cell. It is a figure which shows the area ratio of the basic memory cell of each embodiment, and a dedicated memory cell.

  FIG. 1 shows a basic memory cell 1a in which a bulk layer such as a diffusion layer or a polysilicon layer of the first embodiment forms a fixed memory cell. This is a layout serving as a base of a memory cell that can accommodate various circuit specifications by changing at least one of the metal layer and the contact layer. Four memory units 11Aa, 11Ba, 12Aa, 12Ba are arranged in 2 rows and 2 columns. In the row direction (X1-X2), the memory unit 11Aa and the memory unit 11Ba, and the memory unit 12Aa and the memory unit 12Ba are juxtaposed and arranged adjacent to each other. In the column direction (Y1-Y2), the memory unit 11Aa and the memory unit 12Aa, and the memory unit 11Ba and the memory unit 12Ba are adjacently arranged in mirror symmetry. The third contact described in FIG. 1 is a so-called via contact that connects metal wirings.

  The configuration of the memory unit will be described. The memory units 11Aa, 11Ba, 12Aa, and 12Ba all have the same configuration. Hereinafter, the memory unit 11Aa will be described as a representative. The first diffusion layer 21a, the second diffusion layer 23a, the third diffusion layer 22-1a, and the fourth diffusion layer 22-2a have a long rectangular shape in the column direction (Y1-Y2) and have a row direction (X1- X2). Two gate layers intersect with each of the first diffusion layer 21a and the second diffusion layer 23a in the row direction (X1-X2). In this configuration, transistors are connected in parallel. A gate layer on the column direction (Y2) side that intersects the first diffusion layer 21a is directly connected to the third diffusion layer 22-1a. The fourth diffusion layer 22-2a is directly connected to the gate layer on the column direction (Y1) side that intersects the second diffusion layer 23a. The region limit to the memory unit 12Aa on the column direction (Y1) side of the third diffusion layer 22-1a and the fourth diffusion layer 22-2a is the second metal wiring region 2A-1a.

  Out of the first diffusion layer 21a and the second diffusion layer 23a on the column direction (Y2) side and the (Y1) side, the basic memory cell 1a is penetrated in the row direction (X1-X2), and the first metal layer is formed by the upper metal layer. One word line WLA1 and second word line WLB1 are wired. The first word line WLA1 is connected to the gate layer intersecting the column direction (Y1) side of the first diffusion layer 21a and the gate layer intersecting the column direction (Y2) side of the second diffusion layer 23a. They are connected via a contact layer. The first word line WLA1 to the second contact layer are wired with an intermediate metal layer. The second word line WLB1 is connected to a corresponding gate layer of the memory units 11Ba arranged adjacent to each other in the row direction (X2) side through an intermediate metal layer and a second contact layer.

  The first diffusion layer 21a and the second diffusion layer 23a are formed in an upper metal layer, an intermediate layer in each of the outer region on the column direction (Y1) side and the (Y2) side from each gate layer, and the region sandwiched between the gate layers. A first contact layer connected to either the metal layer or the lower metal layer is provided.

  A first contact layer in a region sandwiched between gate layers intersecting with the first diffusion layer 21a, and a first contact in an outer region on the column direction (Y1) side from the gate layer intersecting with the third diffusion layer 22-1a The first contact layer in the gate layer passing through the layer and the fourth diffusion layer 22-2a and the second diffusion layer 23a is connected by the lower metal layer to form the storage node N1. Further, the first contact layer in the region sandwiched between the gate layers intersecting the second diffusion layer 23a and the first layer in the outer region on the column direction (Y2) side from the gate layer intersecting the fourth diffusion layer 22-2a. The first contact layer and the first contact layer in the gate layer passing through the first diffusion layer 21a and the third diffusion layer 22-1a are connected by the lower metal layer to form the complementary storage node / N1. These lower metal layers constitute a pair of storage nodes.

  A bit line BLA wired in the middle metal layer in the column direction (Y1-Y2) is connected to the first contact layer (B) at the boundary between the memory unit 11Aa and the memory unit 12Aa of the first diffusion layer 21a. The first contact layer (G) at the boundary of the memory unit 11Aa in the outer region on the column direction (Y2) side from the gate layer intersecting the first diffusion layer 21a is an intermediate metal layer in the column direction (Y1-Y2). A ground line GND to be wired is connected.

  The first contact layer (V) at the boundary of the memory unit 11Aa in the outer region on the column direction (Y2) side from the gate layer intersecting the third diffusion layer 22-1a, and the memory unit of the fourth diffusion layer 22-2a The first contact layer (V) at the boundary between 11Aa and the memory unit 12Aa is connected to the power supply line VDD wired in the middle metal layer in the column direction (Y1-Y2).

  The first contact layer (G) at the boundary between the memory unit 11Aa and the memory unit 12Aa of the second diffusion layer 23a is connected to the ground line GND wired in the middle metal layer in the column direction (Y1-Y2). The first contact layer (B) at the boundary of the memory unit 11Aa in the outer region on the column direction (Y2) side from the gate layer intersecting with the second diffusion layer 23a is an intermediate metal layer in the column direction (Y1-Y2). A complementary bit line / BLA to be wired is connected.

  From the above connection, the memory unit 11Aa has the configuration shown in FIG. That is, the inverter gate I2 is configured by the transistors (T2) and (T3) configured by the gate layer penetrating the first diffusion layer 21a and the third diffusion layer 22-1a. The inverter gate I1 is configured by the transistors (T4) and (T5) including a gate layer penetrating the second diffusion layer 23a and the fourth diffusion layer 22-2a. A memory core storing one bit is configured by the inverter gates I1 and I2. The transistor (T1) constituted by the gate layer on the column direction (Y1) side among the gate layers intersecting the first diffusion layer 21a is a transfer interposed between the storage node N1 of the memory core and the bit line BLA. The transistor (T6) that is configured by the gate layer on the column direction (Y2) side among the gate layers that form the gate and intersect the second diffusion layer 23a includes the complementary storage node / N1 of the memory core and the complementary bit line / BLA. A transfer gate interposed between the two is configured.

  Here, the bit line BLA, the complementary bit line / BLA, the ground line GND, and the power supply line VDD are wired through the memory units 11Aa and 12Aa in the column direction (Y1-Y2) by the middle metal layer.

  In the basic memory cell 1a, first metal wiring regions 11-1a, 11-2a, 12-1a, and 12-2a are secured through the memory units juxtaposed in the row direction (X1-X2). The first metal wiring regions 11-1a, 11-2a, and 12-1a, 12-2a are respectively between the first word line WLA1 and the second word line WLB1, and between the first word line WLA2 and the second word line. Secured between WLB2. Two first metal wiring regions 11-1a and 11-2a are arranged at equal intervals between the first word line WLA1 and the second word line WLB1, and are secured through the memory units 11Aa and 11Ba. . Two first metal wiring regions 12-1a and 12-2a are arranged at equal intervals between the first word line WLA2 and the second word line WLB2, and are secured through the memory units 12Aa and 12Ba. . In the first metal wiring regions 11-1a, 11-2a, 12-1a, and 12-2a, an upper metal layer is wired according to the type of the memory cell. As a result, the wiring pitch between the first word line WLA1, the second word line WLB1, and the first metal wiring regions 11-1a and 11-2a can be set to the minimum pitch of the upper metal layer.

  The basic memory cell 1a includes second metal wiring regions 2A-1a, 2A-2a, 2B-1a, and 2B-2a that pass through the memory units that are mirror-symmetrically arranged in the column direction (Y1-Y2). Secured. The second metal wiring regions 2A-1a and 2A-2a are secured through the memory units 11Aa and 12Aa, and the second metal wiring regions 2B-1a and 2B-2a penetrate through the memory units 11Ba and 12Ba. Secured. Each second metal wiring region 2A-1a, 2A-2a, 2B-1a, 2B-2a is arranged between the bit line BLA and the power supply line VDD in the second metal wiring region 2A-1a. In second metal interconnection region 2A-2a, it is arranged between power supply line VDD and complementary bit line / BLA. Similarly, the second metal wiring region 2B-1a is disposed between the bit line BLB and the power supply line VDD. In second metal interconnection region 2B-2a, it is arranged between power supply line VDD and complementary bit line / BLB. An intermediate metal layer is wired in the second metal wiring regions 2A-1a, 2A-2a, 2B-1a, and 2B-2a. The middle metal layer that penetrates each of the memory units 11Aa, 12Aa, 11Ba, and 12Ba includes a ground line GND, a bit line BLA or BLB, a power supply line VDD, a complementary bit line / BLA or / BLB, a ground line GND, and a second metal. There are a total of seven wiring regions 2A-1a, 2A-2a, or 2B-1a, 2B-2a.

  Further, the memory units 12Aa and 12Ba juxtaposed in the row direction (X1-X2) include the first diffusion layer 21a, the second diffusion layer 23a, the third diffusion layer 22-1a, and the fourth diffusion layer 22-2a. The first word line WLA2 and the second word line WLB2 are wired outwardly through the basic memory cell 1a in the row direction (X1-X2) by an upper metal layer. The first word line WLA2 is connected to the memory unit 12Aa arranged on the row direction (X1) side via the second contact layer. The first word line WLA2 to the second contact layer are wired with an intermediate metal layer. The second word line WLB2 is connected to the memory unit 12Ba arranged on the row direction (X2) side via the second contact layer. The second word line WLB2 to the second contact layer are wired with an intermediate metal layer.

  FIG. 2 is a circuit diagram of the basic memory cell 1. FIG. 2 is a circuit diagram realized by a layout (FIG. 1) serving as a base to which a bulk layer such as a diffusion layer or a polysilicon layer is fixed. Each of the memory units 11Aa, 11Ba, 12Aa, and 12Ba includes a 1-bit memory core. Each of the memory units 11Aa, 11Ba, 12Aa, and 12Ba is selectively controlled by the word lines WLA1, WLB1, WLA2, and WLB2. With this configuration, a 1-port memory cell is configured.

  FIG. 3 is a layout obtained by changing the glass mask for forming the upper metal layer, the middle metal layer, and the contact layer in the basic memory cell 1a of the first embodiment. This is a metal connection for obtaining a 2-port memory cell from the basic memory cell 1a. Upper metal layers 24a, 25a, 28a, and 29a are wired in the first metal wiring regions 11-1a, 11-2a, 12-1a, and 12-2a. The upper metal layer 24a connects the corresponding storage nodes of the memory units 11Aa and 11Ba juxtaposed in the row direction (X1-X2). The storage node N1 of the memory unit 11Aa is connected to the corresponding storage node of the memory unit 11Ba through the upper metal layer 24a, the third contact layer, the middle metal layer, the second contact layer, and the lower metal layer. The upper metal layer 25a connects the corresponding complementary storage nodes of the memory units 11Aa and 11Ba juxtaposed in the row direction (X1-X2). The complementary storage node / N1 of the memory unit 11Aa is connected to the corresponding complementary storage node of the memory unit 11Ba through the upper metal layer 25a, the third contact layer, the middle metal layer, the second contact layer, and the lower metal layer. The same applies to the upper metal layers 28a and 29a. Corresponding storage nodes and complementary storage nodes of the memory units 12Aa and 12Ba juxtaposed in the row direction (X1-X2) are connected to each other.

  Further, the branch contact layers 26a, 27a, 30a, and 31a are deleted from the memory units 11Ba and 12Ba that are arranged mirror-symmetrically in the column direction. Here, the branch contact layer is a part of the first contact layer that connects the lower metal layer constituting the storage node and the complementary storage node and the diffusion layer. The branch contact layers 26a and 30a are contact layers that connect the complementary storage node N1 of the memory units 11Ba and 12Ba and the third diffusion layer 22-1a of the memory units 11Ba and 12Ba. The branch contact layers 27a and 31a are contact layers that connect the complementary storage node / N1 of the memory units 11Ba and 12Ba and the fourth diffusion layer 22-2a of the memory units 11Ba and 12Ba. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move.

  FIG. 4 is a circuit diagram for a 2-port memory cell. FIG. 4 is a circuit diagram of a memory cell obtained by a layout (FIG. 3) obtained by changing a glass mask for forming an upper metal layer and a contact layer with respect to a basic memory cell 1a (FIG. 1).

  In the memory unit 11Aa and the memory unit 11Ba, and in the memory unit 12Aa and the memory unit 12Ba, nodes corresponding to each other among the pair of storage nodes are connected by the upper metal layers 24a and 25a, and 28a and 29a. Further, in the memory units 11Ba and 12Ba, the signal path from the power supply line VDD of the inverter gate constituting the memory core is divided by deleting the branch contact layers 26a, 27a, 30a, and 31a.

  As a result, the memory core of the memory unit 11Aa is accessed through two ports, the port selected by the first word line WLA1 and the port selected by the second word line WLB1. The memory core of the memory unit 12Aa is accessed through two ports, a port selected by the first word line WLA2 and a port selected by the second word line WLB2.

  FIG. 5 is a layout obtained by changing the glass mask for forming the middle metal layer, the lower metal layer, and the contact layer for the basic memory cell 1a of the first embodiment. This is a metal connection for obtaining a one-port high drive capability memory cell from the basic memory cell 1a. Intermediate metal layers 32a, 33a, 34a, and 35a are wired in the second metal wiring regions 2A-1a, 2A-2a, 2B-1a, and 2B-2a. The middle metal layer 32a connects the corresponding storage nodes of the memory units 11Aa and 12Aa arranged in the column direction (Y1-Y2). The storage node N1 of the memory unit 11Aa is connected to the corresponding storage node of the memory unit 12Aa through the intermediate metal layer 32a, the second contact layer, and the lower metal layer. The middle metal layer 33a connects the corresponding complementary storage nodes of the memory units 11Aa and 12Aa arranged in the column direction (Y1-Y2). The complementary storage node / N1 of the memory unit 11Aa is connected to the corresponding complementary storage node of the memory unit 12Aa via the intermediate metal layer 33a, the second contact layer, and the lower metal layer. The same applies to the middle metal layers 34a and 35a. Corresponding storage nodes and complementary storage nodes of the memory units 11Ba and 12Ba arranged in the column direction (Y1-Y2) are respectively connected.

  Connection between the first contact layer (V) of the fourth diffusion layer 22-2a at the boundary between the memory units 11Aa and 12Aa and the boundary between the memory units 11Ba and 12Aa and the power supply line VDD, and intermediate metal layers 33a and 35a Is connected to the contact layer (V) of the fourth diffusion layer 22-2a through a lower metal layer (not shown).

  FIG. 6 is a circuit diagram for a 1-port high drive capability memory cell. 6 is a circuit diagram of a memory cell obtained by a layout (FIG. 5) in which a glass mask for forming an intermediate metal layer, a lower metal layer, and a contact layer is changed with respect to the basic memory cell 1a (FIG. 1).

  In the memory unit 11Aa and the memory unit 12Aa, and in the memory unit 11Ba and the memory unit 12Ba, nodes corresponding to each other among the pair of storage nodes are connected by the middle metal layers 32a, 33a, and 34a, 35a. When accessing the memory core, the first word lines WLA1 and WLA2 and the second word lines WLB1 and WLB2 are each short-circuited by a metal wiring (not shown) or operated synchronously as a circuit operation.

  Thereby, the memory units 11Aa and 12Aa constitute one memory core, and the memory units 11Ba and 12Ba constitute one memory core. Each of them is accessed in parallel after being connected in parallel. While the driving capability of the memory core is doubled, the on-resistance during conduction is halved by connecting two transistors in parallel to the transfer gate. By doubling the driving capability and halving the resistance of the signal path, a memory cell with high driving capability can be obtained.

  FIG. 7 is a layout obtained by changing the glass mask for forming the upper metal layer, the middle metal layer, the lower metal layer, and the contact layer for the basic memory cell 1a of the first embodiment. This is a metal connection for obtaining a 2-port high drive capability memory cell from the basic memory cell 1a. Upper metal layers 24a, 25a, 28a, and 29a are wired in the first metal wiring regions 11-1a, 11-2a, 12-1a, and 12-2a. The upper metal layer 24a connects the corresponding storage nodes of the memory units 11Aa and 11Ba juxtaposed in the row direction (X1-X2). The storage node N1 of the memory unit 11Aa is connected to the corresponding storage node of the memory unit 11Ba through the upper metal layer 24a, the third contact layer, the middle metal layer, the second contact layer, and the lower metal layer. The upper metal layer 25a connects the corresponding complementary storage nodes of the memory units 11Aa and 11Ba juxtaposed in the row direction (X1-X2). The complementary storage node / N1 of the memory unit 11Aa is connected to the corresponding complementary storage node of the memory unit 11Ba through the upper metal layer 25a, the third contact layer, the middle metal layer, the second contact layer, and the lower metal layer. The same applies to the upper metal layers 28a and 29a. Corresponding storage nodes and complementary storage nodes of the memory units 12Aa and 12Ba juxtaposed in the row direction (X1-X2) are respectively connected.

  Further, the branch contact layers 26a, 27a, 30a, and 31a are deleted from the memory units 11Ba and 12Ba that are arranged mirror-symmetrically in the column direction. The branch contact layers 26a and 30a connect the lower metal layer connected to the first contact layer of the first diffusion layer 21a and the third diffusion layer 22-1a. The branch contact layers 27a and 31a connect the lower metal layer connected to the first contact layer of the second diffusion layer 23a and the fourth diffusion layer 22-2a. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move.

  The metal wiring described above is the same as the layout (FIG. 3) when a 2-port memory cell is configured.

  Further, intermediate metal layers 32a and 33a are wired in the second metal wiring regions 2A-1a and 2A-2a. The middle metal layer 32a connects the corresponding storage nodes of the memory units 11Aa and 12Aa arranged in the column direction (Y1-Y2). The storage node N1 of the memory unit 11Aa is connected to the corresponding storage node of the memory unit 12Aa through the intermediate metal layer 32a, the second contact layer, and the lower metal layer. The middle metal layer 33a connects the corresponding complementary storage nodes of the memory units 11Aa and 12Aa arranged in the column direction (Y1-Y2). The complementary storage node / N1 of the memory unit 11Aa is connected to the corresponding complementary storage node of the memory unit 12Aa via the intermediate metal layer 33a, the second contact layer, and the lower metal layer.

  The metal wiring described above is the same as that of the middle metal layers 32a and 33a in the layout (FIG. 5) for forming a one-port high drive capability memory cell.

  In order to prevent the connection between the first contact layer (V) of the fourth diffusion layer 22-2a at the boundary between the memory units 11Aa and 12Aa and the power supply line VDD and the interference with the intermediate metal layer 33a, the power supply line VDD is It connects to the contact layer (V) of the third diffusion layer 22-1a through a lower metal layer (not shown).

  FIG. 8 is a circuit diagram in the case of a 2-port high drive capability memory cell. FIG. 8 is a circuit diagram of a memory cell obtained by a layout (FIG. 7) in which a glass mask for forming an upper metal layer, a middle metal layer, a lower metal layer, and a contact layer is changed with respect to the basic memory cell 1a (FIG. 1).

  In the circuit diagram of the 2-port memory cell illustrated in FIG. 4, the nodes corresponding to each other among the pair of storage nodes of the memory unit 11Aa and the memory unit 12Aa are connected by the middle metal layers 32a and 33a. . When accessing the memory core, the first word lines WLA1 and WLA2 and the second word lines WLB1 and WLB2 are each short-circuited by a metal wiring (not shown) or operated synchronously as a circuit operation.

  Thereby, the memory units 11Aa, 12Aa, 11Ba, and 12Ba constitute one memory core. Here, the memory cores in the memory units 11Ba and 12Ba are not used. The memory cores of the memory units 11Aa and 12Aa are accessed in synchronization after being connected in parallel. While the driving capability of the memory core is doubled, the on-resistance during conduction is halved by connecting two transistors in parallel to the transfer gate. The access has a two-port configuration that is performed from each of the first word lines WLA1 and WLA2 or the second word lines WLB1 and WLB2. By doubling the driving capability and halving the resistance of the signal path, a two-port memory cell that can be a memory cell with high driving capability is configured.

  FIG. 9 is a layout obtained by changing the glass mask for forming the middle metal layer, the lower metal layer, and the contact layer for the basic memory cell 1a of the first embodiment. This is a metal connection for obtaining a one-port low-voltage memory cell from the basic memory cell 1a.

  Similar to the layout diagram of the one-port high drive capability memory cell shown in FIG. 5, the middle metal layers 32a, 33a, and the second metal wiring regions 2A-1a, 2A-2a, 2B-1a, 2B-2a 34a and 35a are wired. The middle metal layer 32a connects the corresponding storage nodes of the memory units 11Aa and 12Aa arranged in the column direction (Y1-Y2). The storage node N1 of the memory unit 11Aa is connected to the corresponding storage node of the memory unit 12Aa. The middle metal layer 33a connects the corresponding complementary storage nodes of the memory units 11Aa and 12Aa arranged in the column direction (Y1-Y2). The complementary storage node / N1 of the memory unit 11Aa is connected to the corresponding complementary storage node of the memory unit 12Aa. The same applies to the middle metal layers 34a and 35a. Corresponding storage nodes and complementary storage nodes of the memory units 11Ba and 12Ba arranged in the column direction (Y1-Y2) are respectively connected.

  Further, the branch contact layers 39a, 40a, 30a, and 31a are deleted from the memory units 12Aa and 12Ba that are juxtaposed in the row direction. The branch contact layers 39a and 30a connect the lower metal layer connected to the first contact layer of the first diffusion layer 21a and the third diffusion layer 22-1a. The branch contact layers 40a and 31a connect the lower metal layer connected to the first contact layer of the second diffusion layer 23a and the fourth diffusion layer 22-2a. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move.

  Further, the branch contact layers 38a, 41a, 42a, 43a are deleted from the memory units 12Aa, 12Ba. The branch contact layers 41a and 43a are first contact layers in a gate layer that penetrates the first diffusion layer 21a and the third diffusion layer 22-1a. The lower metal layer connected to the first contact layer of the second diffusion layer 23a and the gate layer penetrating the first diffusion layer 21a and the third diffusion layer 22-1a are connected. The branch contact layers 38a and 42a are first contact layers in a gate layer that penetrates the second diffusion layer 23a and the fourth diffusion layer 22-2a. The lower metal layer connected to the first contact layer of the first diffusion layer 21a and the gate layer penetrating the second diffusion layer 23a and the fourth diffusion layer 22-2a are connected.

  The gate layer that penetrates the first diffusion layer 21a and the third diffusion layer 22-1a penetrates from the ground line GND wired in the middle metal layer in the column direction (Y1-Y2) in the first diffusion layer 21a. The gate layer is connected to the ground line GND through the first contact layer (G), the lower metal layer, and the first contact layer in the outer region on the column direction (Y1) side. Further, the gate layer that penetrates the second diffusion layer 23a and the fourth diffusion layer 22-2a penetrates from the ground line GND wired by the middle metal layer in the column direction (Y1-Y2) in the second diffusion layer 23a. The gate layer is connected to the ground line GND through the first contact layer (G), the lower metal layer, and the first contact layer in the outer region on the column direction (Y2) side. In a pair of inverter gates constituting the memory core, the input of each inverter gate is a ground line GND, thereby opening a signal path interposed between the storage node or complementary storage node as an output node and the ground line GND. To do. As a result, the memory core can be brought into a non-operating state.

  Connection between the first contact layer (V) of the fourth diffusion layer 22-2a at the boundary between the memory units 11Aa and 12Aa and the boundary between the memory units 11Ba and 12Ba and the power supply line VDD, and intermediate metal layers 33a and 35a In order to prevent the interference, the power supply line VDD is connected to the contact layer (V) of the fourth diffusion layer 22-2a through a lower metal layer (not shown).

  FIG. 10 is a circuit diagram in the case of a 1-port low-voltage memory cell. FIG. 10 is a circuit diagram of a memory cell obtained by a layout (FIG. 9) in which a glass mask for forming an intermediate metal layer, a lower metal layer, and a contact layer is changed with respect to the basic memory cell 1a (FIG. 1).

  The circuit diagram of the one-port high drive capability memory cell illustrated in FIG. 6 is different in the following two points. The first point is as follows. In the memory units 12Aa and 12Ba, the signal path from the power supply line VDD of the inverter gate configuring the memory core is divided by deleting the branch contact layers 39a, 40a, 30a, and 31a. Further, the branch contact layers 38a, 41a, 42a, 43a are deleted, the first contact layer in the gate layer passing through the first diffusion layer 21a and the third diffusion layer 22-1a is connected to the ground line GND, and the second By connecting the first contact layer in the gate layer passing through the diffusion layer 23a and the fourth diffusion layer 22-2a to the ground line GND, the signal path from the ground line GND of the inverter gate constituting the memory core is divided. ing.

  The second point is as follows. Unlike the case of FIG. 6, the conduction methods of the first word line WLA2 and the second word line WLB2 are different. When accessing the memory core, the output signal of the AND circuit is input to the first word line WLA2. The AND circuit receives the first word line WLA1 and the write enable signal WEA. The write enable signal WEA is at a high level during write access. Similarly, the output signal of the AND circuit is input to the second word line WLB2. The AND circuit receives the second word line WLB1 and the write enable signal WEB. At the time of write access, the write enable signals WEA and WEB are at a high level, and the first word line WLA2 and the second word line WLB2 are also at a high level according to the selection of the first word line WLA1 and the second word line WLB1. The two sets of transfer gates constituting the memory cell are turned on together (for example, transfer gates T1, T6, T7, T12 connected to the bit lines BLA, / BLA). On the other hand, at the time of read access, the write enable signals WEA and WEB are at a low level. As a result, the first word line WLA2 and the second word line WLB2 are maintained at a low level. Depending on the selection of the first word line WLA1 and the second word line WLB1, one transfer gate (for example, transfer gate T1, connected to the bit lines BLA, / BLA) of the two sets of transfer gates constituting the memory cell. T6) conducts.

  Thereby, the memory units 11Aa and 12Aa constitute one memory core, and the memory units 11Ba and 12Ba constitute one memory core. Each memory core includes two sets of transfer gates. Therefore, in write access, the path between the memory core and the bit line is connected with a low resistance and flows to the transfer gate as compared with the basic memory cell 1a. The current can be increased. On the other hand, one set conducts during read access. Therefore, the current flowing through the transfer gate can be reduced as compared with the write access. With the recent reduction in power supply voltage, memory cells are designed as low voltage memory cells with improved data retention characteristics. With the configuration shown in FIGS. 9 and 10, the two sets of transfer gates are made conductive at the time of write access to reduce the resistance of the signal path. As a result, the ability to write to the low voltage type memory cell can be enhanced, and data can be written to the low voltage type memory cell having a high data holding ability. On the other hand, at the time of read access, one transfer gate is made conductive to ensure a resistance value on the signal path. The inside and outside of the low voltage memory cell can be electrically separated to some extent across the transfer gate, and the stored data can be prevented from being inverted due to external influences. In the low voltage memory cell, a memory cell with improved write characteristics can be obtained.

  FIG. 11 is a layout obtained by changing the glass mask for forming the lower metal layer, the middle metal layer, the upper metal layer, and the contact layer in the basic memory cell 1a of the first embodiment. This is a metal connection for obtaining a 2-port low voltage memory cell from the basic memory cell 1a.

  Similar to the layout diagram of the two-port high drive capability memory cell shown in FIG. 7, the upper metal layers 24a, 25a, and the first metal wiring regions 11-1a, 11-2a, 12-1a, 12-2a 28a and 29a are wired. The upper metal layer 24a connects the corresponding storage nodes of the memory units 11Aa and 11Ba juxtaposed in the row direction (X1-X2). The storage node N1 of the memory unit 11Aa is connected to the corresponding storage node of the memory unit 11Ba through the upper metal layer 24a, the third contact layer, the middle metal layer, the second contact layer, and the lower metal layer. The upper metal layer 25a connects the corresponding complementary storage nodes of the memory units 11Aa and 11Ba juxtaposed in the row direction (X1-X2). The complementary storage node / N1 of the memory unit 11Aa is connected to the corresponding complementary storage node of the memory unit 11Ba through the upper metal layer 25a, the third contact layer, the middle metal layer, the second contact layer, and the lower metal layer. The same applies to the upper metal layers 28a and 29a. Corresponding storage nodes and complementary storage nodes of the memory units 12Aa and 12Ba juxtaposed in the row direction (X1-X2) are respectively connected.

  Further, the branch contact layers 26a, 27a, 30a, and 31a are deleted from the memory units 11Ba and 12Ba that are arranged mirror-symmetrically in the column direction. The branch contact layers 26a and 30a connect the lower metal layer connected to the first contact layer of the first diffusion layer 21a and the third diffusion layer 22-1a. The branch contact layers 27a and 31a connect the lower metal layer connected to the first contact layer of the second diffusion layer 23a and the fourth diffusion layer 22-2a. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move.

  Further, intermediate metal layers 32a and 33a are wired in the second metal wiring regions 2A-1a and 2A-2a. The middle metal layer 32a connects the corresponding storage nodes of the memory units 11Aa and 12Aa arranged in the column direction (Y1-Y2). The storage node N1 of the memory unit 11Aa is connected to the corresponding storage node of the memory unit 12Aa through the intermediate metal layer 32a, the second contact layer, and the lower metal layer. The middle metal layer 33a connects the corresponding complementary storage nodes of the memory units 11Aa and 12Aa arranged in the column direction (Y1-Y2). The complementary storage node / N1 of the memory unit 11Aa is connected to the corresponding complementary storage node of the memory unit 12Aa via the intermediate metal layer 33a, the second contact layer, and the lower metal layer.

  Further, the branch contact layers 39a and 40a are deleted from the memory unit 12Aa. The branch contact layer 39a connects the lower metal layer connected to the first contact layer of the first diffusion layer 21a and the third diffusion layer 22-1a. The branch contact layer 40a connects the lower metal layer connected to the first contact layer of the second diffusion layer 23a and the fourth diffusion layer 22-2a. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move.

  Further, the branch contact layers 38a, 41a, 42a, 43a are deleted from the memory units 12Aa, 12Ba. The gate layer that penetrates the first diffusion layer 21a and the third diffusion layer 22-1a penetrates from the ground line GND wired in the middle metal layer in the column direction (Y1-Y2) in the first diffusion layer 21a. The gate layer is connected to the ground line GND through the first contact layer (G), the lower metal layer, and the first contact layer in the outer region on the column direction (Y1) side. Further, the gate layer that penetrates the second diffusion layer 23a and the fourth diffusion layer 22-2a penetrates from the ground line GND wired by the middle metal layer in the column direction (Y1-Y2) in the second diffusion layer 23a. The gate layer is connected to the ground line GND through the first contact layer (G), the lower metal layer, and the first contact layer in the outer region on the column direction (Y2) side. In a pair of inverter gates constituting the memory core, the input of each inverter gate is a ground line GND, thereby opening a signal path interposed between the storage node or complementary storage node as an output node and the ground line GND. To do. As a result, the memory core can be brought into a non-operating state.

  FIG. 12 is a circuit diagram in the case of the 2-port low voltage memory cell of the first embodiment. 12 is a circuit diagram of a memory cell obtained by a layout (FIG. 11) in which a glass mask for forming an upper metal layer, a middle metal layer, a lower metal layer, and a contact layer is changed with respect to the basic memory cell 1a (FIG. 1).

  The circuit diagram of the two-port low-voltage memory cell illustrated in FIG. 12 is different from the one-port illustrated in FIG. 10 in the following points. First, in FIG. 10, the middle metal layers 34a and 35a connecting the memory unit 11Ba and the memory unit 12Ba are not wired. Second, the branch contact layers 26a and 27a arranged in the memory unit 11Ba of FIG. 10 are deleted. Third, the memory unit 11Aa and the memory unit 11Ba, and the memory unit 12Aa and the memory unit 12Ba are connected to each other among the pair of storage nodes by the upper metal layers 24a, 25a, and 28a, 29a. Is done. The control of the word line when accessing the memory core is the same as in the case of FIG.

  The memory units 11Aa, 12Aa, 11Ba, and 12Ba constitute one memory core and are provided with two sets of transfer gates. Two sets of transfer gates are turned on during write access, whereas one set of two sets of transfer gates is turned on during read access. The path between the memory core and the bit line is connected with low resistance in the write access with respect to the read access. Therefore, like the one-port low-voltage memory cell shown in FIGS. 9 and 10, the low-voltage memory cell can be a memory cell with improved write characteristics. In addition, a 2-port memory cell that can be a 2-port low-voltage memory cell that can prevent inversion of the memory cell due to a current flowing from the bit line during read access is configured.

  FIG. 13 is a layout obtained by changing the glass mask for forming the upper metal layer, the middle metal layer, the lower metal layer, and the contact layer for the basic memory cell 1a, and is another example of FIG. This is another example of metal connection for obtaining a one-port high drive capability memory cell from the basic memory cell 1a. Upper metal layers 44a and 45a are wired in the first metal wiring regions 11-1a and 11-2a, respectively. The upper metal layer 44a is provided in the first diffusion layer 21a common to the memory units 11Ba and 12Ba from the bit line BLA via the third contact layer, the middle metal layer, the second contact layer, and the lower metal layer. Connected to the contact layer (B). The upper metal layer 45a is a first contact layer in the second diffusion layer 23a of the memory unit 11Ba from the complementary bit line / BLA via the third contact layer, the middle metal layer, the second contact layer, and the lower metal layer. Connected to (B). The first contact layer (B) in the second diffusion layer 23a of the memory unit 12Ba has an upper metal layer 45a disposed in another basic memory cell 1a adjacent to the Y1 side in the column direction (Y1-Y2). Connected by.

    14 is a circuit diagram of another example of FIG. 6 in the case of a 1-port high drive capability memory cell realized by the layout of FIG.

  Memory cores of the memory units 11Aa, 11Ba, 12Aa, and 12Ba are connected in parallel between the bit line BLA and the complementary bit line / BLA. When accessing the memory core, the first word line WLA1 and the second word line WLB1, and the first word line WLA2 and the second word line WLB2 are each short-circuited by a metal wiring (not shown) or synchronously operated as a circuit operation. Is done.

  Thus, the memory units 11Aa and 11Ba constitute one memory core, and the memory units 12Aa and 12Ba constitute one memory core. The memory core has a configuration in which the memory cores of the memory units 11Aa and 11Ba and the memory cores of the memory units 12Aa and 12Ba are connected in parallel. Access is performed in synchronization with two word lines. While the driving capability of the memory core is doubled, the on-resistance during conduction is halved by connecting two transistors in parallel to the transfer gate. By doubling the driving capability and halving the resistance of the signal path, a memory cell with high driving capability can be obtained.

  FIG. 15 shows a basic memory cell 1b in which a bulk layer such as a diffusion layer or a polysilicon layer of the second embodiment constitutes a fixed memory cell. This is a layout serving as a base of a memory cell that can correspond to a plurality of circuit specifications by changing at least one of a metal layer and a contact layer. Four memory units 11Ab, 11Bb, 12Ab, and 12Bb are arranged in two rows and two columns. In the row direction (X1-X2), the memory unit 11Ab and the memory unit 11Bb, and the memory unit 12Ab and the memory unit 12Bb are arranged adjacent to each other in mirror symmetry. In the column direction (Y1-Y2), the memory unit 11Ab and the memory unit 12Ab, and the memory unit 11Bb and the memory unit 12Bb are adjacently arranged in mirror symmetry.

  The configuration of the memory unit will be described. The memory units 11Ab, 11Bb, 12Ab, and 12Bb all have the same configuration. Hereinafter, the memory unit 11Ab will be described as a representative. The first diffusion layer 21b, the second diffusion layer 23b, the third diffusion layer 22-1b, and the fourth diffusion layer 22-2b have a long rectangular shape in the column direction (Y1-Y2) and have a row direction (X1- X2). Two gate layers intersect the first and second diffusion layers 21b and 23b in the row direction (X1-X2). In this configuration, transistors are connected in parallel. The gate layer that intersects the third diffusion layer 22-1b is directly connected to the gate layer on the column direction (Y2) side that intersects the first diffusion layer 21b. The gate layer that intersects the fourth diffusion layer 22-2b is directly connected to the gate layer on the column direction (Y1) side that intersects the second diffusion layer 23b. The region limit to the memory unit 12Ab on the column direction (Y1) side of the third diffusion layer 22-1b is the second metal wiring region 2A-1b.

  Outside the first diffusion layer 21b and the second diffusion layer 23b on the column direction (Y2) side and (Y1) side, the basic memory cell 1b is penetrated in the row direction (X1-X2), and the first metal layer is formed by the upper metal layer. One word line WLA1 and second word line WLB1 are wired. The first word line WLA1 is connected to the gate layer intersecting the column direction (Y1) side of the first diffusion layer 21b and the gate layer intersecting the column direction (Y2) side of the second diffusion layer 23b. They are connected via a contact layer. The first word line WLA1 to the second contact layer are wired with an intermediate metal layer through a third contact layer. The second word line WLB1 is connected to the corresponding gate layer of the memory unit 11Bb juxtaposed adjacently in the row direction (X2) side via the third contact layer, the middle metal layer, and the second contact layer. Yes.

  The first diffusion layer 21b and the second diffusion layer 23b are formed in an upper metal layer, an intermediate layer in each of the outer region on the column direction (Y1) side and the (Y2) side from each gate layer, and the region sandwiched between the gate layers. A first contact layer connected to either the metal layer or the lower metal layer is provided.

  A first contact layer in a region sandwiched between gate layers intersecting with the first diffusion layer 21b, and a first contact in an outer region on the column direction (Y1) side from the gate layer intersecting with the third diffusion layer 22-1b The first contact layer in the gate layer passing through the layer and the fourth diffusion layer 22-2b and the second diffusion layer 23b is connected by the lower metal layer to constitute the storage node N1. Further, the first contact layer in the region sandwiched between the gate layers intersecting the second diffusion layer 23b and the first layer in the outer region on the column direction (Y2) side from the gate layer intersecting the fourth diffusion layer 22-2b. The first contact layer and the first contact layer in the gate layer passing through the first diffusion layer 21b and the third diffusion layer 22-1b are connected by the lower metal layer to form the complementary storage node / N1. These lower metal layers constitute a pair of storage nodes.

  A bit line BLA wired in the middle metal layer in the column direction (Y1-Y2) is connected to the first contact layer (B) at the boundary between the memory unit 11Ab and the memory unit 12Ab in the first diffusion layer 21b. The first contact layer (G) at the boundary of the memory unit 11Ab in the outer region on the column direction (Y2) side from the gate layer intersecting the first diffusion layer 21b is an intermediate metal layer in the column direction (Y1-Y2). A ground line GND to be wired is connected.

  The first contact layer (V) at the boundary of the memory unit 11Ab in the outer region on the column direction (Y2) side from the gate layer intersecting the third diffusion layer 22-1b, and the memory unit of the fourth diffusion layer 22-2b The first contact layer (V) at the boundary between 11Ab and the memory unit 12Ab is connected with the power supply line VDD wired in the middle metal layer in the column direction (Y1-Y2).

  The first contact layer (G) at the boundary between the memory unit 11Ab and the memory unit 12Ab in the second diffusion layer 23b is connected to the ground line GND wired in the middle metal layer in the column direction (Y1-Y2). The first contact layer (B) at the boundary of the memory unit 11Ab in the outer region on the column direction (Y2) side from the gate layer intersecting the second diffusion layer 23b is an intermediate metal layer in the column direction (Y1-Y2). A complementary bit line / BLA to be wired is connected.

  From the above connection, the memory unit 11Ab has the same configuration as that shown in FIG. That is, the inverter gate I2 is configured by the transistors (T2) and (T3) configured by the gate layer penetrating the first diffusion layer 21b and the third diffusion layer 22-1b. An inverter gate I1 is configured by the transistors (T4) and (T5) including a gate layer penetrating the second diffusion layer 23b and the fourth diffusion layer 22-2b. A memory core storing one bit is configured by the inverter gates I1 and I2. The transistor (T1) constituted by the gate layer on the column direction (Y1) side among the gate layers intersecting the first diffusion layer 21b is a transfer interposed between the storage node N1 of the memory core and the bit line BLA. The transistor (T6) that is configured by the gate layer on the column direction (Y2) side among the gate layers that form the gate and intersect the second diffusion layer 23b includes the complementary storage node / N1 of the memory core and the complementary bit line / BLA. A transfer gate interposed between the two is configured.

  Here, the bit line BLA, the complementary bit line / BLA, the ground line GND, and the power supply line VDD are wired through the memory units 11Ab and 12Ab in the column direction (Y1-Y2) by the middle metal layer.

  In the basic memory cell 1b, 1-1 metal wiring regions 11-1b and 12-1b are secured through memory units arranged in mirror symmetry in the row direction (X1-X2). Also, the 1-2 metal wiring regions 11-3b and 12-3b are secured in the boundary region. The 1-1 metal wiring region 11-1b is disposed between the first word line WLA1 and the second word line WLB1, and is secured through the memory units 11Ab and 11Bb. The 1-1 metal wiring region 12-1b is disposed between the first word line WLA2 and the second word line WLB2, and is secured through the memory units 12Ab and 12Bb. In the 1-1 metal wiring regions 11-1b and 12-1b, an upper metal layer is wired according to the type of the memory cell. The 1-2 metal wiring regions 11-3b and 12-3b are respectively between the first word line WLA1 and the second word line WLB1 and between the first word line WLA2 and the second word line WLB2. Arranged and secured in each boundary region of the memory units 11Ab and 11Bb and the memory units 12Ab and 12Bb. A lower metal layer is wired in the 1-2 metal wiring regions 11-3b and 12-3b. In the case of the first embodiment, two first metal wiring areas are secured, whereas one 1-1 metal wiring area is secured. Since the area for one line is reduced, the length in the column direction (Y1-Y2) can be reduced.

  In addition, the basic memory cell 1b includes the 2-1 metal wiring regions 2A-1b, 2B-1b, and the 2-2 through the memory units arranged in mirror symmetry in the column direction (Y1-Y2). Metal wiring regions 2A-2b and 2B-2b are secured. The 2-1 and 2-2 metal wiring regions 2A-1b and 2A-2b are secured in the boundary region between the memory units 11Ab and 12Ab, and the 2-1 and 2-2 metal wiring regions 2B. -1b and 2B-2b are secured in the boundary area between the memory units 11Bb and 12Bb. In the 2-1 metal wiring regions 2A-1b and 2B-1b, a lower metal layer is wired and arranged along the column direction at a position in the column direction where the third diffusion layer 22-1b is arranged. The 2-2 metal wiring areas 2A-2b and 2B-2b are the boundary areas of the memory units 11Ab and 12Ab and the memory units 11Bb and 12Bb, respectively, and are arranged in a mirror symmetry in the row direction. 11Ab, 11Bb, and 12Ab, 12Bb are arranged in the vicinity of the boundary region. An intermediate metal layer is wired in the 2-2 metal wiring regions 2A-2b and 2B-2b. The intermediate metal layers that penetrate each of the memory units 11Ab, 12Ab, 11Bb, and 12Bb in the column direction (Y1-Y2) are the ground line GND, the bit line BLA or BLB, the power supply line VDD, the complementary bit line / BLA or / BLB, the ground There are five lines GND. In addition, in the column direction (Y1-Y2), there are two wiring areas, a 2-1 metal wiring area 2A-1b or 2B-1b and a 2-2 metal wiring area 2A-2b or 2B-2b. Is secured.

  Thereby, the circuit configuration realized by the layout (FIG. 15) according to the basic memory cell 1b of the second embodiment is the same as the circuit configuration (FIG. 2) of the basic memory cell 1a (1-port memory cell) of the first embodiment. It is the same. Each of the memory units 11Ab, 11Bb, 12Ab, and 12Bb includes a 1-bit memory core. Each of the memory units 11Ab, 11Bb, 12Ab, and 12Bb is selectively controlled by the word lines WLA1, WLB1, WLA2, and WLB2. Therefore, similarly to the layout according to FIG. 1 of the first embodiment, a 1-port memory cell is configured from the layout according to FIG. 15 of the second embodiment.

  FIG. 16 is a layout obtained by changing the glass mask for forming the upper metal layer, the middle metal layer, the lower metal layer, and the contact layer in the basic memory cell 1b of the second embodiment. This is a metal connection for obtaining a 2-port memory cell from the basic memory cell 1b. The lower metal layers 25b and 29b are wired to the upper metal layers 24b and 28b and the first metal wiring regions 11-3b and 12-3b to the first metal wiring regions 11-1b and 12-1b, respectively. To do. The upper metal layer 24b connects the corresponding storage nodes of the memory units 11Ab and 11Bb arranged in mirror symmetry in the row direction (X1-X2). The storage node N1 of the memory unit 11Ab is connected to the corresponding storage node of the memory unit 11Bb via the upper metal layer 24b, the third contact layer, the middle metal layer, and the second contact layer. The lower metal layer 25b connects the corresponding complementary storage nodes of the memory units 11Ab and 11Bb arranged in mirror symmetry in the row direction (X1-X2). The complementary storage node / N1 of the memory unit 11Ab is connected to the corresponding complementary storage node of the memory unit 11Bb. The same applies to the upper metal layer 28b and the lower metal layer 29b. The corresponding storage nodes and complementary storage nodes of the memory units 12Ab and 12Bb juxtaposed in the row direction (X1-X2) are connected to each other.

  Further, the branch contact layers 26b, 27b, 30b, and 31b are deleted from the memory units 11Bb and 12Bb that are arranged mirror-symmetrically in the column direction. Here, the branch contact layer is a part of the first contact layer that connects the lower metal layer constituting the storage node and the complementary storage node and the diffusion layer. The branch contact layers 26b and 30b are contact layers that connect the storage node N1 of the memory units 11Bb and 12Bb and the third diffusion layer 22-1b of the memory units 11Bb and 12Bb. The branch contact layers 27b and 31b are contact layers that connect the complementary storage node / N1 of the memory units 11Bb and 12Bb and the fourth diffusion layer 22-2b of the memory units 11Bb and 12Bb. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move.

  With respect to basic memory cell 1b (FIG. 15), memory unit 11Ab and memory unit 11Bb, and memory unit 12Ab and memory unit 12Bb each have a node corresponding to each other in a pair of storage nodes, upper metal layer 24b, 28b and lower metal layers 25b and 29b. Further, in the memory units 11Bb and 12Bb, the signal path from the power supply line VDD of the inverter gate constituting the memory core is divided by deleting the branch contact layers 26b, 27b, 30b, and 31b.

  Accordingly, the circuit configuration according to the layout of FIG. 16 is the same as the circuit configuration of the 2-port memory cell (FIG. 4). Therefore, the memory core of the memory unit 11Ab is accessed through two ports, a port selected by the first word line WLA1 and a port selected by the second word line WLB1. The memory core of the memory unit 12Ab is accessed through two ports, a port selected by the first word line WLA2 and a port selected by the second word line WLB2.

  FIG. 17 is a layout obtained by changing the glass mask for forming the middle metal layer, the lower metal layer, and the contact layer for the basic memory cell 1b of the second embodiment. This is a metal connection for obtaining a one-port high drive capability memory cell from the basic memory cell 1b. Lower metal layers 32b and 34b are wired to the 2-1 metal wiring regions 2A-1b and 2B-1b, and intermediate metal layers 33b and 35b are wired to the 2-2 metal wiring regions 2A-2b and 2B-2b. To do. The lower metal layer 32b connects the corresponding storage nodes of the memory units 11Ab and 12Ab arranged in the column direction (Y1-Y2). The storage node N1 of the memory unit 11Ab is connected to the corresponding storage node of the memory unit 12Ab. The middle metal layer 33b connects the corresponding complementary storage nodes of the memory units 11Ab and 12Ab arranged in the column direction (Y1-Y2). The complementary storage node / N1 of the memory unit 11Ab is connected to the corresponding complementary storage node of the memory unit 12Ab through the intermediate metal layer 33b, the second contact layer, and the lower metal layer. The same applies to the lower metal layer 34b and the middle metal layer 35b. Corresponding storage nodes and complementary storage nodes of the memory units 11Bb and 12Bb arranged in the column direction (Y1-Y2) are respectively connected.

  Accordingly, the circuit configuration according to the layout of FIG. 17 is the same as the circuit configuration of the one-port high drive capability memory cell (FIG. 6). Therefore, the memory unit 11Ab and the memory unit 12Ab, and the memory unit 11Bb and the memory unit 12Bb are connected to each other among the pair of storage nodes by the lower metal layers 32b and 34b and the middle metal layers 33b and 35b. Has been. When accessing the memory core, the first word lines WLA1 and WLA2 and the second word lines WLB1 and WLB2 are each short-circuited by a metal wiring (not shown) or operated synchronously as a circuit operation.

  Thus, the memory units 11Ab and 12Ab constitute one memory core, and the memory units 11Bb and 12Bb constitute one memory core. Each of them is accessed in parallel after being connected in parallel. While the driving capability of the memory core is doubled, the on-resistance during conduction is halved by connecting two transistors in parallel to the transfer gate. By doubling the driving capability and halving the resistance of the signal path, a memory cell with high driving capability can be obtained.

  FIG. 18 is a layout obtained by changing the glass mask for forming the upper metal layer, middle metal layer, lower metal layer, and contact layer in the basic memory cell 1b of the second embodiment. This is a metal connection for obtaining a 2-port high drive capability memory cell from the basic memory cell 1b. The lower metal layers 25b and 29b are wired to the upper metal layers 24b and 28b and the first metal wiring regions 11-3b and 12-3b to the first metal wiring regions 11-1b and 12-1b, respectively. To do. The upper metal layer 24b connects the corresponding storage nodes of the memory units 11Ab and 11Bb arranged in mirror symmetry in the row direction (X1-X2). The storage node N1 of the memory unit 11Ab is connected to the corresponding storage node of the memory unit 11Bb via the upper metal layer 24b, the third contact layer, the middle metal layer, and the second contact layer. The lower metal layer 25b connects the corresponding complementary storage nodes of the memory units 11Ab and 11Bb juxtaposed in the row direction (X1-X2). The complementary storage node / N1 of the memory unit 11Ab is connected to the corresponding complementary storage node of the memory unit 11Bb. The same applies to the upper metal layer 28b and the lower metal layer 29b. Corresponding storage nodes and complementary storage nodes of the memory units 12Ab and 12Bb juxtaposed in the row direction (X1-X2) are respectively connected.

  Further, the branch contact layers 26b, 27b, 30b, and 31b are deleted from the memory units 11Bb and 12Bb that are arranged mirror-symmetrically in the column direction. The branch contact layers 26b and 30b connect the lower metal layer connected to the first contact layer of the first diffusion layer 21b and the third diffusion layer 22-1b. The branch contact layers 27b and 31b connect the lower metal layer connected to the first contact layer of the second diffusion layer 23b and the fourth diffusion layer 22-2b. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move.

  The metal wiring described above is the same as the layout (FIG. 16) when a 2-port memory cell is configured.

  Further, the lower metal layer 32b is wired to the 2-1 metal wiring region 2A-1b, and the middle metal layer 33b is wired to the 2-2 metal wiring region 2A-2b. The lower metal layer 32b connects the corresponding storage nodes of the memory units 11Ab and 12Ab arranged in the column direction (Y1-Y2). The storage node N1 of the memory unit 11Ab is connected to the corresponding storage node of the memory unit 12Ab. The middle metal layer 33b connects the corresponding complementary storage nodes of the memory units 11Ab and 12Ab arranged in the column direction (Y1-Y2). The complementary storage node / N1 of the memory unit 11Ab is connected to the corresponding complementary storage node of the memory unit 12Ab through the intermediate metal layer 33b, the second contact layer, and the lower metal layer.

  The metal wiring described above is the same as that of the lower metal layer 32b and the middle metal layer 33b in the layout (FIG. 17) when configuring a one-port high drive capability memory cell.

  Accordingly, the circuit configuration according to the layout of FIG. 18 is the same as the circuit configuration of the two-port high drive capability memory cell (FIG. 8). Therefore, the nodes corresponding to each other among the pair of storage nodes of the memory unit 11Ab and the memory unit 12Ab are connected by the lower metal layer 32b and the intermediate metal layer 33b. When accessing the memory core, the first word lines WLA1 and WLA2 and the second word lines WLB1 and WLB2 are each short-circuited by a metal wiring (not shown) or operated synchronously as a circuit operation.

  Thereby, the memory units 11Ab, 12Ab, 11Bb, and 12Bb constitute one memory core. Here, the memory cores in the memory units 11Bb and 12Bb are not used. The memory cores of the memory units 11Ab and 12Ab are connected in parallel and accessed in synchronization. While the driving capability of the memory core is doubled, the on-resistance during conduction is halved by connecting two transistors in parallel to the transfer gate. The access has a two-port configuration that is performed from each of the first word lines WLA1 and WLA2 or the second word lines WLB1 and WLB2. By doubling the driving capability and halving the resistance of the signal path, a two-port memory cell that can be a memory cell with high driving capability is configured.

  FIG. 19 shows a layout obtained by changing the glass mask for forming the middle metal layer, the lower metal layer, and the contact layer for the basic memory cell 1b of the second embodiment. This is a metal connection for obtaining a one-port low-voltage memory cell from the basic memory cell 1b.

  Similar to the layout diagram of the one-port high-drive capability memory cell shown in FIG. 17, the lower metal layers 32b and 34b and the second-second metal wiring are formed in the second-first metal wiring regions 2A-1b and 2B-1b. Intermediate metal layers 33b and 35b are wired in regions 2A-2b and 2b-2b. The lower metal layer 32b connects the corresponding storage nodes of the memory units 11Ab and 12Ab arranged in the column direction (Y1-Y2). The storage node N1 of the memory unit 11Ab is connected to the corresponding storage node of the memory unit 12Ab. The middle metal layer 33b connects the corresponding complementary storage nodes of the memory units 11Ab and 12Ab arranged in the column direction (Y1-Y2). The complementary storage node / N1 of the memory unit 11Ab is connected to the corresponding complementary storage node of the memory unit 12Ab through the intermediate metal layer 33b, the second contact layer, and the lower metal layer. The same applies to the lower metal layer 34b and the middle metal layer 35b. Corresponding storage nodes and complementary storage nodes of the memory units 11Bb and 12Bb arranged in the column direction (Y1-Y2) are respectively connected.

  Further, the branch contact layers 39b, 40b, 30b, and 31b are deleted from the memory units 12Ab and 12Bb that are juxtaposed in the row direction. The branch contact layers 39b and 30b connect the lower metal layer connected to the first contact layer of the first diffusion layer 21b and the third diffusion layer 22-1b. The branch contact layers 40b and 31b connect the lower metal layer connected to the first contact layer of the second diffusion layer 23b and the fourth diffusion layer 22-2b. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move.

  Further, the branch contact layers 38b, 41b, 42b, and 43b are deleted from the memory units 12Ab and 12Bb. The branch contact layers 41b and 43b are first contact layers in a gate layer that penetrates the first diffusion layer 21b and the third diffusion layer 22-1b. The lower metal layer connected to the first contact layer of the second diffusion layer 23b and the gate layer penetrating the first diffusion layer 21b and the third diffusion layer 22-1b are connected. The branch contact layers 38b and 42b are first contact layers in the gate layer that penetrate the second diffusion layer 23b and the fourth diffusion layer 22-2b. The lower metal layer connected to the first contact layer of the first diffusion layer 21b and the gate layer penetrating the second diffusion layer 23b and the fourth diffusion layer 22-2b are connected.

  In the memory unit 12Ab, the gate layer penetrating the first diffusion layer 21b and the third diffusion layer 22-1b is connected to the first diffusion layer 21b from the ground line GND wired in the middle metal layer in the column direction (Y1-Y2). Are connected to the ground line GND through the first contact layer (G), the lower metal layer, and the first contact layer in the outer region on the column direction (Y1) side from the penetrating gate layer. Further, the gate layer that penetrates the second diffusion layer 23b and the fourth diffusion layer 22-2b penetrates from the ground line GND wired in the middle metal layer in the column direction (Y1-Y2) in the second diffusion layer 23b. The gate layer is connected to the ground line GND through the first contact layer (G), the lower metal layer, and the first contact layer in the outer region on the column direction (Y2) side. Similarly, in the memory unit 12Bb, the gate layer that penetrates the first diffusion layer 21b and the third diffusion layer 22-1b extends from the gate layer that penetrates the first diffusion layer 21b to the outer region on the column direction (Y1) side. It is connected to the ground line GND through a certain first contact layer (G), a lower metal layer, and a first contact layer. The gate layer that penetrates the second diffusion layer 23b and the fourth diffusion layer 22-2b is a first contact layer (in the outer region on the column direction (Y2) side from the gate layer that penetrates the second diffusion layer 23b). G), connected to the ground line GND through the lower metal layer and the first contact layer. In a pair of inverter gates constituting the memory core, the input of each inverter gate is a ground line GND, thereby opening a signal path interposed between the storage node or complementary storage node as an output node and the ground line GND. To do. As a result, the memory core can be brought into a non-operating state.

  Accordingly, the circuit configuration according to the layout of FIG. 19 is the same as the circuit configuration of the one-port low-voltage memory cell (FIG. 10). Therefore, the memory units 11Ab and 12Ab constitute one memory core, and the memory units 11Bb and 12Bb constitute one memory core. Each memory core includes two sets of transfer gates, one of which is turned on during read access, while two sets of transfer gates are turned on during write access. The path between the memory core and the bit line is connected with low resistance in the write access with respect to the read access. Therefore, as in the case of the layout of the first embodiment (FIG. 9), the low voltage memory cell can be a memory cell with improved write characteristics. Further, it is possible to provide a one-port low-voltage memory cell that can prevent inversion of the memory cell due to a current flowing from the bit line during read access.

  FIG. 20 is a layout obtained by changing the glass mask for forming the upper metal layer, middle metal layer, lower metal layer, and contact layer for the basic memory cell 1b of the second embodiment. This is a metal connection for obtaining a 2-port low voltage memory cell from the basic memory cell 1b.

  Similar to the layout diagram of the two-port high drive capability memory cell shown in FIG. 18, the upper metal layers 24b and 28b and the first and second metal layers are formed in the first and second metal wiring regions 11-1b and 12-1b. Lower metal layers 25b and 29b are wired in the wiring regions 11-3b and 12-3b. The upper metal layer 24b connects the corresponding storage nodes of the memory units 11Ab and 11Bb juxtaposed in the row direction (X1-X2). The storage node N1 of the memory unit 11Ab is connected to the corresponding storage node of the memory unit 11Bb via the upper metal layer 24b, the third contact layer, the middle metal layer, and the second contact layer. The lower metal layer 25b connects the corresponding complementary storage nodes of the memory units 11Ab and 11Bb juxtaposed in the row direction (X1-X2). The complementary storage node / N1 of the memory unit 11Ab is connected to the corresponding complementary storage node of the memory unit 11Bb. The same applies to the upper metal layer 28b and the lower metal layer 29b. Corresponding storage nodes and complementary storage nodes of the memory units 12Ab and 12Bb juxtaposed in the row direction (X1-X2) are respectively connected.

  Further, the branch contact layers 26b, 27b, 30b, and 31b are deleted from the memory units 11Bb and 12Bb that are arranged mirror-symmetrically in the column direction. The branch contact layers 26b and 30b connect the lower metal layer connected to the first contact layer of the first diffusion layer 21b and the third diffusion layer 22-1b. The branch contact layers 27b and 31b connect the lower metal layer connected to the first contact layer of the second diffusion layer 23b and the fourth diffusion layer 22-2b. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move. The metal wiring described above is the same as the layout (FIG. 16) when a 2-port memory cell is configured.

  Further, the lower metal layer 32b is wired to the 2-1 metal wiring region 2A-1b, and the middle metal layer 33b is wired to the 2-2 metal wiring region 2A-2b. The lower metal layer 32b connects the corresponding storage nodes of the memory units 11Ab and 12Ab arranged in the column direction (Y1-Y2). The storage node N1 of the memory unit 11Ab is connected to the corresponding storage node of the memory unit 12Ab. The middle metal layer 33b connects the corresponding complementary storage nodes of the memory units 11Ab and 12Ab arranged in the column direction (Y1-Y2). The complementary storage node / N1 of the memory unit 11Ab is connected to the corresponding complementary storage node of the memory unit 12Ab through the intermediate metal layer 33b, the second contact layer, and the lower metal layer. The metal wiring described above is the same as that of the lower metal layer 32b and the middle metal layer 33b in the layout (FIG. 18) when configuring a one-port high drive capability memory cell.

  Further, the branch contact layers 39b and 40b are deleted from the memory unit 12Ab. The branch contact layer 39b connects the lower metal layer connected to the first contact layer of the first diffusion layer 21b and the third diffusion layer 22-1b. The branch contact layer 40b connects the lower metal layer connected to the first contact layer of the second diffusion layer 23b and the fourth diffusion layer 22-2b. In a pair of inverter gates constituting the memory core, a signal path interposed between a storage node or complementary storage node as an output node and the power supply line VDD is opened. Thereby, a memory core can be made into the state which does not operate | move.

  Further, the branch contact layers 38b, 41b, 42b, and 43b are deleted from the memory units 12Ab and 12Bb. The gate layer that penetrates the first diffusion layer 21b and the third diffusion layer 22-1b penetrates the first diffusion layer 21b from the ground line GND wired in the middle metal layer in the column direction (Y1-Y2). The gate layer is connected to the ground line GND through the first contact layer (G), the lower metal layer, and the first contact layer in the outer region on the column direction (Y1) side. Further, the gate layer that penetrates the second diffusion layer 23b and the fourth diffusion layer 22-2b penetrates from the ground line GND wired in the middle metal layer in the column direction (Y1-Y2) in the second diffusion layer 23b. The gate layer is connected to the ground line GND through the first contact layer (G), the lower metal layer, and the first contact layer in the outer region on the column direction (Y2) side. In a pair of inverter gates constituting the memory core, the input of each inverter gate is a ground line GND, thereby opening a signal path interposed between the storage node or complementary storage node as an output node and the ground line GND. To do. As a result, the memory core can be brought into a non-operating state.

  The circuit diagram of the two-port low-voltage memory cell illustrated in FIG. 20 is different from the one-port illustrated in FIG. 19 in the following points. First, in FIG. 19, the lower metal layer 34b and the middle metal layer 35b that connect the memory unit 11Bb and the memory unit 12Bb are not wired. Second, the branch contact layers 26b and 27b arranged in the memory unit 11Bb of FIG. 19 are deleted. Third, the memory unit 11Ab and the memory unit 11Bb, and the memory unit 12Ab and the memory unit 12Bb are respectively configured such that the nodes corresponding to each other among the pair of storage nodes are the upper metal layer 24b, the lower metal layer 25b, and the upper metal. The layers 28b and the lower metal layer 29b are connected. The control of the word line when accessing the memory core is the same as in the case of FIG.

  Thus, the circuit configuration according to the layout of FIG. 20 is the same as the circuit configuration of the 2-port low-voltage memory cell (FIG. 12). Accordingly, the memory units 11Ab, 12Ab, 11Bb, and 12Bb constitute one memory core and are provided with two sets of transfer gates. At the time of read access, one set of the two sets of transfer gates is turned on, whereas at the time of write access, the two sets of transfer gates are turned on. The path between the memory core and the bit line is connected with low resistance in the write access with respect to the read access. Therefore, similarly to the layout of the first embodiment (FIG. 11), the low-voltage memory cell can be a memory cell with improved write characteristics compared to the memory cell. In addition, a 2-port memory cell that can be a 2-port low-voltage memory cell that can prevent inversion of the memory cell due to a current flowing from the bit line during read access is configured.

  FIG. 21 shows a layout obtained by changing the glass mask for forming the upper metal layer, the middle metal layer, the lower metal layer, and the contact layer for the basic memory cell 1b, which is another example of FIG. This is another example of metal connection for obtaining a one-port high drive capability memory cell from the basic memory cell 1b. Upper metal layers 45b and 36b are wired in the first-first metal wiring regions 11-1b and 12-1b, respectively. The upper metal layer 45b is located in the second diffusion layer 23b of the memory unit 11Bb from the complementary bit line / BLA via the upper metal layer, the third contact layer, the middle metal layer, the second contact layer, and the lower metal layer. Connected to the first contact layer (B). The upper metal layer 36b is in the first diffusion layer 21b common to the memory units 11Bb and 12Bb from the bit line BLA via the third contact layer, the middle metal layer, the second contact layer, and the lower metal layer. Connected to the first contact layer (B). The first contact layer (B) in the second diffusion layer 23b of the memory unit 12Bb has an upper metal layer 45b disposed in another basic memory cell 1b adjacent to the Y1 side in the column direction (Y1-Y2). Connected by

  Thus, the circuit configuration according to the layout of FIG. 21 is the same as the circuit configuration (FIG. 14) which is another example of the one-port high drive capability memory cell. The memory units 11Ab and 11Bb constitute one memory core, and the memory units 12Ab and 12Bb constitute one memory core. The memory core has a configuration in which the memory cores of the memory units 11Ab and 11Bb and the memory cores of the memory units 12Ab and 12Bb are connected in parallel. Access is performed in synchronization with two word lines. While the driving capability of the memory core is doubled, the on-resistance during conduction is halved by connecting two transistors in parallel to the transfer gate. By doubling the driving capability and halving the resistance of the signal path, a memory cell with high driving capability can be obtained.

  From the basic memory cells 1a and 1b of the first and second embodiments described with reference to FIGS. 1 to 21, a bulk layer such as a diffusion layer or a polysilicon layer is fixed, and is configured by changing a metal layer or a contact layer. FIG. 22 shows the types of memory cells to be performed and the number per basic memory cell.

  The memory cells composed of the basic memory cells 1a and 1b of the first to second embodiments are a 1-port memory cell (FIGS. 1, 2, and 15), a 2-port memory cell (FIGS. 3, 4, and 16), 1 port high drive capability memory cell (FIGS. 5, 6, 13, 14, 17, 21), 2 port high drive capability memory cell (FIGS. 7, 8, 18), 1 port low voltage type memory cell (FIG. 9, 10, 19), and two-port low-voltage memory cells (FIGS. 11, 12, and 20).

  The number of memory cells per basic memory cell of each memory cell is 4 for a 1-port memory cell (FIGS. 1, 2, and 15) and 2 for a 2-port memory cell (FIGS. 3, 4, and 16). 2 for 1 port high drive capability memory cells (FIGS. 5, 6, 13, 14, 17, 21) and 1 for 2 port high drive capability memory cells (FIGS. 7, 8, 18). There are two in the case of one-port, low-voltage memory cells (FIGS. 9, 10, and 19), and one in the case of two-port low-voltage memory cells (FIGS. 11, 12, and 20).

  By changing at least one of the metal layer and the contact layer with respect to the basic memory cells 1a and 1b (FIGS. 1 and 15), six types of memory cells can be formed on the basis of the bulk configuration of the basic memory cells. It can be configured efficiently.

  FIG. 23 is a diagram comparing the occupied area of the memory cells of the first and second embodiments with the case where a dedicated memory cell is used. FIG. 22 illustrates a case where area comparison is performed between a 1-port memory cell (denoted as 1 RW) and a 2-port memory cell (denoted as 2 RW).

  In the layout in which the basic memory cells of the first to second embodiments are arranged in a matrix of 2 rows and 6 columns, when only one port memory cell is configured (A), when 1 port / 2 ports are mixed (B ) Consider the three cases (C) in the case where only two-port memory cells are configured.

  In the basic memory cell of 2 rows and 6 columns, the type (A) is a 24-port 1-port memory cell, the type (B) is a 12-cell 1-port memory cell and a 6-cell 2-port memory cell, and the type (C) is 12 The two-port memory cell of the cell can be handled by changing at least one of the metal layer and the contact layer.

  When the same memory cell configuration is realized by dedicated memory cells of 1 port / 2 ports, it is necessary to provide a 1-port memory cell array of 4 rows and 6 columns and a 2-port memory cell array of 2 rows and 6 columns. The area ratio is twice as large.

  According to the first and second embodiments, a memory cell is provided, and a plurality of types of memory cells can be configured in accordance with a change in at least one of the metal layer and the contact layer, thereby improving the area efficiency on the layout. It becomes possible to plan.

  In the first and second embodiments, the upper metal layer is an example of the first metal layer, the middle metal layer is an example of the second metal layer, and the lower metal layer is an example of the third metal layer.

  As described above in detail, the basic memory cell 1a in which the memory units 11Aa, 11Ba, 12Aa, and 12Ba are arranged in two rows and two columns, and the basic that the memory units 11Ab, 11Bb, 12Ab, and 12Bb are arranged in two rows and two columns By changing at least one of the metal layer and the contact layer of the memory cell 1b, only by changing the metal layer and the contact layer, the memory cell of 1 port, the memory cell of 2 ports, the memory of 1 port Six types of memory cells can be configured: a high drive capability memory cell, a 2-port high drive capability memory cell, a 1-port low-voltage memory cell, and a 2-port low-voltage memory cell. Compared with the case where a dedicated memory cell is prepared for each type, the area efficiency in the layout can be improved. A plurality of types of memory cells can be configured in a limited layout region, and a plurality of types of memory cells can be mixed.

Needless to say, the present configuration is not limited to the illustrated embodiment, and various modifications and changes can be made without departing from the spirit of the present object.
For example, the case where memory units are arranged in two rows and two columns as basic memory cells is illustrated, but the present invention is not limited to this. A configuration in which memory units are arranged in three or more rows or / and three or more columns can be used as a basic memory cell. This makes it possible to configure further types of memory cells. For example, a configuration in which the number of ports is a multi-port with three or more ports, a configuration in which the driving capability is set in multiple stages such as double, triple, and quadruple are possible.

  In the configuration of the memory unit of each embodiment, the upper metal layer and the middle metal layer can be interchanged.

  In the second embodiment, a lower metal layer may be wired in the 2-2 metal wiring regions 2A-2b and 2B-2b.

1a Basic memory cells 11Aa, 11Ba, 12Aa, 12Ba Memory units 21a, 22-1a, 22-2a, 23a First to fourth diffusion layers 24a, 25a, 28a, 29a, 36a, 37a Upper metal layers 32a, 33a, 34a 35a Middle metal layer 26a, 27a, 30a, 31a, 38a, 39a, 40a, 42a, 42a
Branch contact layers 11-1a, 11-2a, 12-1a, 12-2a First metal wiring regions 2A-1a, 2A-2a, 2B-1a, 2B-2a Second metal wiring regions BLA, BLB Bit lines / BLA, / BLB Complementary bit line GND Ground line I1, I2 Inverter gate N1 Storage node / N1 Complementary storage nodes T1-T6 Transistor VDD Power supply line WLA1, WLA2 First word line WLB1, WLB2 Second word line Y1-Y2 Column direction

Claims (14)

A memory unit that is arranged in mirror symmetry along the column direction and is juxtaposed along the row direction and arranged in two rows and two columns;
First and second word lines wired by a first metal layer for each row in which the memory units are juxtaposed and connected to each of the memory units;
A second metal layer for wiring a power line, a ground line, and a bit line in the column direction,
The memory unit is
A diffusion layer provided in a transistor extending in the column direction and connected in parallel, the first and second diffusion layers juxtaposed along the row direction;
A diffusion layer between the first diffusion layer and the second diffusion layer and extending in the column direction and provided to the transistor, the gate extending from a gate layer on one side intersecting the first diffusion layer A third diffusion layer where the layers intersect;
A diffusion layer between the first diffusion layer and the second diffusion layer and extending in the column direction to be used for a transistor, the gate extending from the gate layer on the other side intersecting the second diffusion layer A fourth diffusion layer where the layers intersect;
Between the region of the first diffusion layer sandwiched between the gate layers of the transistor and the region of the third diffusion layer on the same side as the region of the first diffusion layer with respect to the gate layer on one side; and A third metal is interposed between the region of the second diffusion layer sandwiched between the gate layers and the region of the fourth diffusion layer on the same side as the region of the second diffusion layer with respect to the gate layer on the other side. A pair of storage nodes connected by layers;
Two first metal wiring regions in which a first metal layer can be wired along the row direction between the first word line and the second word line;
Of the memory units arranged in the two rows and two columns, the column is located at a position in the column direction where the third and fourth diffusion layers are arranged, which is a boundary region of memory units arranged adjacent to each other in the column direction. And a second metal wiring region in which the second metal layer can be wired along the direction. Regarding two columns of memory units juxtaposed adjacently along the row direction,
Deactivating a memory cell of one memory unit and deactivating a pair of storage nodes connected to the memory cell;
In the first metal wiring region, a first metal layer that connects one storage node of the one memory unit to one storage node of the other memory unit, and the other storage node of the one memory unit A first metal layer connected to the other storage node of the other memory unit,
2. The memory cell according to claim 1, wherein the two rows of memory units are configured as a two-port memory cell. For two rows of memory units arranged adjacent to each other in mirror symmetry along the column direction,
A second metal layer connecting one storage node of one memory unit to one storage node of the other memory unit in the second metal wiring region; and the other storage node of the one memory unit as the other storage node. A second metal layer connected to the other storage node of the memory unit,
2. The memory cell according to claim 1, wherein the two rows of memory units are configured as one-port high-drive capacity memory cells by a synchronous operation of the first or second word line. For memory units arranged in the 2 rows and 2 columns,
For each of two columns of memory units juxtaposed in parallel along the row direction, the memory cell of one memory unit is deactivated and a pair of storage nodes connected to the memory cell is deactivated,
In the first metal wiring region, a first metal layer that connects one storage node of the one memory unit to one storage node of the other memory unit, and the other storage node of the one memory unit A first metal layer connected to the other storage node of the other memory unit,
Of the two rows of memory units arranged adjacent to each other in mirror symmetry along the column direction, the unit that does not deactivate the memory cell,
A second metal layer connecting one storage node of one memory unit to one storage node of the other memory unit in the second metal wiring region; and the other storage node of the one memory unit as the other storage node. A second metal layer connected to the other storage node of the memory unit,
2. The memory cell according to claim 1, wherein the memory cell is configured as a two-port high drive capability memory cell. For two rows of memory units arranged adjacent to each other in mirror symmetry along the column direction,
Deactivating a memory cell of one memory unit and deactivating a pair of storage nodes connected to the memory cell;
A second metal layer connecting one storage node of one memory unit to one storage node of the other memory unit in the second metal wiring region; and the other storage node of the one memory unit as the other storage node. A second metal layer connected to the other storage node of the memory unit,
By driving either the first or second word line during a read operation and driving both the first and second word lines during a write operation, the two rows of memory units are connected to a low power operation memory cell of one port. The memory cell according to claim 1, wherein the memory cell is configured as follows. Out of the memory units arranged in the 2 rows and 2 columns, the memory cells of three memory units are deactivated, and a pair of storage nodes connected to the memory cells are deactivated,
For each two columns of memory units juxtaposed adjacently along the row direction,
In the first metal wiring region, a first metal layer that connects one storage node of the one memory unit to one storage node of the other memory unit, and the other storage node of the one memory unit A first metal layer connected to the other storage node of the other memory unit,
Among the memory units arranged in the two rows and two columns, the memory units of two rows including the remaining memory units and arranged adjacent to each other in mirror symmetry along the column direction.
A second metal layer connecting one storage node of one memory unit to one storage node of the other memory unit in the second metal wiring region; and the other storage node of the one memory unit as the other storage node. A second metal layer connected to the other storage node of the memory unit,
By driving either the first word line or the second word line during a read operation and driving both the first and second word lines during a write operation, the memory unit of 2 rows and 2 columns operates at a low power of 2 ports. The memory cell according to claim 1, wherein the memory cell is configured as a memory cell. Regarding two columns of memory units juxtaposed adjacently along the row direction,
The first metal wiring region has a first metal layer connecting a path between one bit line in one memory unit and one storage node of the other memory unit, and the one memory unit has A first metal layer connecting a path between the other bit line and the other storage node of the other memory unit;
2. The memory cell according to claim 1, wherein the two rows of memory units are configured as one-port high drive capability memory cells. A memory unit arranged adjacent to each other in mirror symmetry along each of the column direction and the row direction, and arranged in 2 rows and 2 columns;
First and second word lines wired in the row direction by a first metal layer for each row and connected to each of the memory units;
A second metal layer for wiring a power line, a ground line, and a bit line in the column direction,
The memory unit is
A diffusion layer provided in a transistor extending in the column direction and connected in parallel, the first and second diffusion layers juxtaposed along the row direction;
A diffusion layer between the first diffusion layer and the second diffusion layer and extending in the column direction and provided to the transistor, the gate extending from a gate layer on one side intersecting the first diffusion layer A third diffusion layer where the layers intersect;
A diffusion layer between the first diffusion layer and the second diffusion layer and extending in the column direction to be used for a transistor, the gate extending from the gate layer on the other side intersecting the second diffusion layer A fourth diffusion layer where the layers intersect;
Between the region of the first diffusion layer sandwiched between the gate layers of the transistor and the region of the third diffusion layer on the same side as the region of the first diffusion layer with respect to the gate layer on one side; and A third metal is interposed between the region of the second diffusion layer sandwiched between the gate layers and the region of the fourth diffusion layer on the same side as the region of the second diffusion layer with respect to the gate layer on the other side. A pair of storage nodes connected by layers;
A 1-1 metal wiring region in which a first metal layer can be routed along the row direction between the first word line and the second word line;
A pair of memory units arranged adjacent to each other in the row direction among the memory units arranged in the two rows and two columns in the memory unit arranged adjacent to one of the pair of storage nodes. A 1-2 metal wiring region in which the third metal layer provided for connection with one of the storage nodes can be wired;
Of the memory units arranged in the two rows and two columns, in the boundary region of the memory units arranged adjacent to each other in the column direction, along the column direction at a position in the column direction where the third diffusion layer is arranged 2-1 metal wiring region in which the third metal layer can be wired;
Of the memory units arranged in the two rows and two columns, in the boundary region of the memory units adjacently arranged in the column direction and adjacent to the memory units arranged adjacent in the row direction, along the column direction A memory cell comprising: a 2-2 metal wiring region in which the second metal layer or the third metal layer can be wired. For two columns of memory units arranged in mirror symmetry along the row direction,
Deactivating a memory cell of one memory unit and deactivating a pair of storage nodes connected to the memory cell;
A first metal layer connecting one storage node of the one memory unit to one storage node of the other memory unit in the 1-1 metal wiring region;
A third metal layer connecting the other storage node of the one memory unit to the other storage node of the other memory unit in the 1-2 metal wiring region;
9. The memory cell according to claim 8, wherein the two columns of memory units are configured as two-port memory cells. For two rows of memory units arranged adjacent to each other in mirror symmetry along the column direction,
A third metal layer connecting one storage node of one memory unit to one storage node of the other memory unit in the 2-1 metal wiring region;
A second metal layer connecting the other storage node of the one memory unit to the other storage node of the other memory unit in the 2-2 metal wiring region;
9. The memory cell according to claim 8, wherein the two rows of memory units are configured as one-port high drive capability memory cells by a synchronous operation of the first or second word line. For memory units arranged in the 2 rows and 2 columns,
For each two columns of memory units arranged adjacent to each other in mirror symmetry along the row direction, the memory cell of one memory unit is deactivated and a pair of storage nodes connected to the memory cell is deactivated. ,
A first metal layer connecting one storage node of the one memory unit to one storage node of the other memory unit in the 1-1 metal wiring region;
A third metal layer connecting the other storage node of the one memory unit to the other storage node of the other memory unit in the 1-2 metal wiring region;
Of the two rows of memory units arranged adjacent to each other in mirror symmetry along the column direction, the unit that does not deactivate the memory cell,
A third metal layer connecting one storage node of one memory unit to one storage node of the other memory unit in the 2-1 metal wiring region;
A second metal layer connecting the other storage node of the one memory unit to the other storage node of the other memory unit in the 2-2 metal wiring region;
9. The memory cell according to claim 8, wherein the memory cell is configured as a two-port high drive capability memory cell. For two rows of memory units arranged adjacent to each other in mirror symmetry along the column direction,
Deactivating a memory cell of one memory unit and deactivating a pair of storage nodes connected to the memory cell;
A third metal layer connecting one storage node of one memory unit to one storage node of the other memory unit in the 2-1 metal wiring region;
A second metal layer connecting the other storage node of the one memory unit to the other storage node of the other memory unit in the 2-2 metal wiring region;
By driving either the first or second word line during a read operation and driving both the first and second word lines during a write operation, the two rows of memory units are connected to a low power operation memory cell of one port. The memory cell according to claim 8, wherein the memory cell is configured as follows. Out of the memory units arranged in the 2 rows and 2 columns, the memory cells of three memory units are deactivated, and a pair of storage nodes connected to the memory cells are deactivated,
For each of two columns of memory units arranged adjacent to each other in mirror symmetry along the row direction,
A first metal layer connecting one storage node of the one memory unit to one storage node of the other memory unit in the 1-1 metal wiring region;
A third metal layer connecting the other storage node of the one memory unit to the other storage node of the other memory unit in the 1-2 metal wiring region;
Among the memory units arranged in the two rows and two columns, the memory units of two rows including the remaining memory units and arranged adjacent to each other in mirror symmetry along the column direction.
A third metal layer connecting one storage node of one memory unit to one storage node of the other memory unit in the 2-1 metal wiring region;
A second metal layer connecting the other storage node of the one memory unit to the other storage node of the other memory unit in the 2-2 metal wiring region;
By driving either the first word line or the second word line during a read operation and driving both the first and second word lines during a write operation, the memory unit of 2 rows and 2 columns operates at a low power of 2 ports. 9. The memory cell according to claim 8, wherein the memory cell is configured as a memory cell. For memory units arranged in the 2 rows and 2 columns,
One bit line in each memory unit arranged in one column and one storage node of each memory unit arranged in the other column in the 1-1 metal wiring region in one row A first metal layer connecting the path between
In the 1-1 metal wiring region in the other row, the other bit line in each memory unit arranged in one column and the other storage node of each memory unit arranged in the other column A first metal layer connecting the path between
9. The memory cell according to claim 8, wherein two columns of memory units arranged adjacent to each other in mirror symmetry along the row direction are configured as one-port high drive capability memory cells.

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