CN104700888B - Three-dimensional three port bit locations and its assemble method - Google Patents
Three-dimensional three port bit locations and its assemble method Download PDFInfo
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- CN104700888B CN104700888B CN201410743598.3A CN201410743598A CN104700888B CN 104700888 B CN104700888 B CN 104700888B CN 201410743598 A CN201410743598 A CN 201410743598A CN 104700888 B CN104700888 B CN 104700888B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/416—Read-write [R-W] circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
A kind of three port three-dimensional bit locations, generally include the reading part of unit being arranged in the first level.Reading part includes multiple read port elements.What three port bit locations also included being disposed relative to unit in the second level of the first level vertical stacking writes part.First level and the second level are coupled using at least one through hole.Writing part includes multiple write port elements.Present invention also offers the assemble method of three-dimensional three port bit locations.
Description
The intersection application of related application
The present invention is entitled " the THREE DIMENSIONAL DUAL-PORT BIT submitted on December 6th, 2013
The part of CELL AND METHOD OF ASSEMBING SAME " U.S. Patent Application No. 14/098,567 is continued, and its is complete
Portion's content is hereby expressly incorporated by reference.
Technical field
The system and method for the present invention are related to static RAM (" SRAM ") array, more particularly, to
Three port bit location workable for SRAM array.
Background technology
Multiple units that static RAM (" SRAM ") or semiconductor memory include being arranged to row and column with
Form array.Sram cell includes multiple transistors coupled to bit line and wordline, and its neutrality line and wordline are used for from memory
Unit reads data and to memory cell write data.Single-port SRAM can write individual data position in special time
Bit location or from bit location read data bit.On the contrary, multi-port SRAM can carry out more readings or more write-ins simultaneously substantially.Tradition
Multi-port SRAM structure include different metal line in wordline (" WL "), due to user's SRAM signal routings different metal grow
Spend and cause different capacitive loads.Compared with single-port SRAM structure, multi-port SRAM structure it is larger on WL directions and compared with
It is wide.Due to multi-port SRAM on WL directions it is larger and wider, so weight WL load during can influence SRAM array in length and breadth
Than being designed particularly with wide input/output (" I/O ").When compared with single-port SRAM, the peripheral logic electricity of multi-port SRAM
Road doubles.In this way, multi-port SRAM can take larger area, and signal routing complexity can be produced.
The content of the invention
The defects of in order to solve in the presence of prior art, according to an aspect of the present invention, there is provided a kind of three ends of three-dimensional
Mouth bit location, including：Part is write, is arranged in the first level, the part of writing includes multiple write port elements；And reading portion
Point, it is arranged in the second level, second level is relative to the first level vertical stacking and uses at least one through hole
Coupled to first level, second level includes multiple read port elements.
In the port bit location of three-dimensional three, the part of writing also includes a plurality of write bit line, and every write bit line is described
Extend along a first direction in first conductive layer of the first level, and the reading part also includes a plurality of sense bit line, every reading
Bit line extends in the first conductive layer of second level along the first direction.
In the port bit location of three-dimensional three, the part of writing also includes at least one write word line, and the write word line is in institute
State along the second direction extension different from the first direction in the second conductive layer of the first level, and the reading part is also
Including at least one readout word line, the readout word line prolongs in the second conductive layer of second level along the second direction
Stretch.
In the port bit location of three-dimensional three, the multiple read port element includes multiple read port grids.
In the port bit location of three-dimensional three, the part of reading also includes being arranged in second level and being coupled to institute
State at least one latch inverters of multiple read port grids.
It is the multiple to write subelement and include multiple write port grids in the port bit location of three-dimensional three.
In the port bit location of three-dimensional three, three port bit location includes ten transistor units, the read port
Element includes four transistor arrangements and the write port element includes six transistor arrangements.
It is each in the multiple read port grid and the multiple write port grid in the port bit location of three-dimensional three
Individual is one kind in nmos device and PMOS device.
The port bit location of three-dimensional three also includes：Write control circuit, it is arranged in first level；And read control electricity
Road, it is arranged in second level.
In the port bit location of three-dimensional three, the reading control circuit includes read port control circuit and readout word line decodes
Device, and the write control circuit includes write port control circuit and write word line decoder.
According to another aspect of the present invention, there is provided a kind of semiconductor memory, including：First level, including first end
Mouth array portion；Second level, using at least one through hole relative to the first level vertical stacking, the second level bag
Include second port array portion；And at least one three-dimensional three port bit location, including：Part I, it is arranged on described first
On array of ports part, the Part I includes multiple write port elements；And Part II, it is arranged on the second port battle array
Arrange on part, the Part II includes multiple read port elements.
In the semiconductor memory, the Part I also includes a plurality of write bit line, and each write bit line is described
Extend along a first direction in first conductive layer of the first level, and the Part II also includes a plurality of sense bit line, it is each
Bar sense bit line extends in the first conductive layer of second level along the first direction.
In the semiconductor memory, the Part I also includes at least one write word line, and each write word line exists
Extend in second conductive layer of first level along the second direction different from the first direction, and described second
Dividing also includes at least one readout word line, and each readout word line is along described second in the second conductive layer of second level
Direction extends.
In the semiconductor memory, the multiple read port element includes multiple read port grids.
In the semiconductor memory, the Part II also includes at least one coupled to the multiple read port grid
Individual latch inverters.
The semiconductor memory also includes：The write port control circuit that is arranged in first level and it is arranged on described
Read port control circuit in second level.
The semiconductor memory also includes：The write driver and write word line decoder that are arranged in first level and
Read input/output (I/O) circuit and the readout word line decoder being arranged in second level.
According to another aspect of the invention, there is provided a kind of method, including：Three-dimensional three port positions are set in the first level
Unit writes part, and the part of writing includes multiple write port elements；Relative to the second of the first level vertical stacking
The reading part of the three-dimensional three port bit location is set in level, and the reading part includes multiple read port elements；And use
First level is coupled to second level by least one through hole.
This method also includes：It is that the multiple write port element transmits first group of signal in first level；And
It is that the multiple read port element transmits second group of signal in second level.
This method also includes：At least one latch inverters are set in second level；And at least one by described in
Individual latch inverters are coupled to the multiple read port element.
Brief description of the drawings
When read in conjunction with the accompanying drawings, various aspects of the invention are more fully understood according to detailed description below.Pay attention to,
According to the standard practices of industry, all parts are not necessarily to scale.In fact, it is clear for discussion, can arbitrarily it increase
Add deduct the sizes of small all parts.
Fig. 1 is the stereogram according to an example of the 3 D semiconductor integrated circuit of some embodiments.
Fig. 2 is that the three-dimensional static that the 3 D semiconductor integrated circuit according to Fig. 1 of some embodiments uses is deposited at random
The circuit diagram of one example of access to memory (SRAM) array.
Fig. 3 is a reality of the three-dimensional dual-port bit location that the SRAM array according to Fig. 2 of some embodiments uses
The circuit diagram of example.
Fig. 4 is the block diagram of the three-dimensional dual-port bit location shown in Fig. 3.
Fig. 5 is the flow chart of an example of the method for the three-dimensional dual-port bit location shown in assembling figure 3.
Fig. 6 is the D S array ram that the 3 D semiconductor integrated circuit according to Fig. 1 of some embodiments uses
The circuit diagram of one example.
Fig. 7 is that the NMOS that includes that the SRAM array according to Fig. 6 of some embodiments uses transmits grid (pass-
Gate) the circuit diagram of an example of the port bit location of three-dimensional three of structure.
Fig. 8 is the block diagram of the port bit location of three-dimensional three shown in Fig. 7.
Fig. 9 is include PMOS transmission grid structures three that the SRAM array according to Fig. 6 of some embodiments uses
Tie up the circuit diagram of an example of three port bit locations.
Figure 10 is the block diagram of the port bit location of three-dimensional three shown in Fig. 9.
Figure 11 is to include being arranged on the port of three-dimensional three for reading multiple latch inverters (latch invertor) on part
The circuit diagram of one example of bit location.
Embodiment
Understand the description of exemplary embodiment with reference to the accompanying drawing for the part for being considered as entire disclosure.
The following disclosure provides many different embodiments or example that are used to implement the different characteristic of present subject matter.With
Lower description part or the instantiation of configuration are of the invention to simplify.Certainly, these are only example rather than limitation.For example,
In the following description, first component and second component can be included by shape by forming first component in second component above and over
As the embodiment directly contacted, and can also make including additional component can be formed between first component and second component
Obtain the embodiment that first component and second component do not contact directly.In addition, the present invention can repeated reference in various embodiments
Label and/or letter.These repeat be in order to simplify and clear, itself be not offered as each embodiment for being discussed and/or
Relation between structure.
In addition, for ease of description, can use space relative terms (such as " in ... lower section ", " under ", " bottom ",
" on ", " top " etc.) to describe the relation of an element shown in figure or part and another element or part.Except institute in figure
Outside the orientation shown, space relative terms also include equipment being differently directed in use or operating process.Device can be with it
His mode is oriented and (is rotated by 90 ° or in other orientations), therefore the relative description in space used herein can carry out similar solution
Release.
Some embodiments of three-dimensional bit location described herein have the structure and design for being beneficial to reduce footprints, simultaneously
Improve overall unit performance and suppress wherein to use the corresponding semiconductor memory or static RAM of unit
The signal routing complexity of (" SRAM ") array.For example, in certain embodiments, configure three-dimensional bit location so that latch
One group of port element of a part be arranged on that one layer of three-dimensional (" 3D ") semiconductor integrated circuit (" IC ") upper and latch it is another
Another group of port element of a part be arranged on IC with above-mentioned layer vertically adjacent to different layers on.Have on IC different layers
Two groups of different port elements are beneficial to the reduction of footprints, and also reduce wordline (" WL ") dead resistance and electric capacity.Cause
This, substantially increases the overall performance of unit.
Fig. 1 shows an example of 3D semiconducter ICs 10.3D IC 10 include multilayer 12-1,12-2,12-3,12-n
(" layer 12 "), they are stacked with a z-direction.In certain embodiments, layer 12 is to utilize at least one substrate through vias
Each pipe that through hole (" ILD ") (being not shown in Fig. 1) is electrically coupled to one another between (" TSV ") or inter-level vias (" ILV ") or device
Core.It should be noted that as it is used herein, " coupling " is not limited between part directly machinery, heat, communication and/or electrical connection,
But indirect machinery, heat, communication and/or electrical connection between multiple parts can also be included.
In certain embodiments, 3D IC 10 each layer 12 is corresponding " level ", and each level includes pair
(it can include multiple conductive layers (such as M1, M2 etc.) for the active device layer answered and corresponding interconnection structure.Such as art technology
What personnel were understood, interlayer dielectric (" ILD ") layer (not shown) can be arranged between the level of direct neighbor.
Fig. 2 shows semiconductor memory or an example of SRAM array 100.In certain embodiments, SRAM array
100 are included in 3D IC 10 (as shown in Figure 1).For example, SRAM array 100 can be across two layers or level (such as bottom 12-
1 and upper strata 12-2) it is configured, they arranged perpendicular and for example (are being schemed by one or more ILV 102 relative to each other
One is only shown in 2) it is coupled.
In certain embodiments, bottom 12-1 includes a port (such as A ports), and upper strata 12-2 includes another
Port (such as B ports).In this way, in certain embodiments, input/output (" I/O ") circuit for A ports and B ports is set
Put on two independent conductive layers.For example, in certain embodiments, bottom 12-1 includes A port elements, such as A ports battle array
Arrange part 106 and A ports wordline (" WL ") decoder and driver portion 108.In certain embodiments, A array of ports portion
Divide 106 by being coupled to A ports I/ positioned at the paratope line (" BL ") (such as BL_A and the BLB_A being complementary to) between them
O circuit 110.In certain embodiments, A ports I/O circuits 110 are configured as receiving input signal and pass data output signal
The defeated outside to SRAM 100.
As it is used herein, term " circuit " typically refers to any programmable system, including system and microcontroller,
Reduced instruction set circuits (" RISC "), application specific integrated circuit (" ASIC "), PLD (" PLC ") and are able to carry out
Any other circuit of function specifically described herein.What examples detailed above was merely exemplary, therefore do not limit art in any way
The definition of language " circuit " and/or implication.
In certain embodiments, A ports WL decoders and driver portion 108 are coupled to A port control circuits 112.A ends
Mouth control circuit 112 can be configured as receiving the clock signal of A ports and write enable signal (negative enabled).A port controllings electricity
Road 112 can be additionally configured to receive address signal.
Top layer 12-2 includes B array of ports part 116 and B ports WL decoders and driver portion 118.In some realities
Apply in example, B array of ports part 116 passes through positioned at complementary BL (such as BL_B and the BLB_B being complementary to) coupling between them
It is bonded to B ports I/O circuits 120.In certain embodiments, B ports I/O circuits 120 are configured as receiving data input signal simultaneously
Data output signal is transferred to outside array 100.In certain embodiments, B ports WL decoders and the coupling of driver portion 118
B port control circuits 122 are bonded to, the B port control circuits 122 can be configured as receiving the clock signal of B ports and write enabled
Signal (negative enabled).B port control circuits 122 can be additionally configured to receive address signal.
SRAM array 100 includes at least one three-dimensional dual-port bit location 150, and it includes being arranged on first layer (such as bottom
Layer 12-1) on Part I 152.For example, Part I 152 is arranged at least a portion of A array of ports part 106.
Dual-port bit location 150 also includes the Part II 154 for setting (for example, upper strata 12-2 of SRAM array 100) on the second layer,
Wherein the second layer is vertically arranged relative to first layer.For example, Part II 154 is included at least the one of B array of ports part 116
In part.As being explained in detail hereinafter with reference to Fig. 3 and Fig. 4, dual-port bit location 150, which has, to be beneficial to reduce footprints
Improve overall cell performance simultaneously and suppress the structure and design of the signal routing complexity of SRAM array 100.
In certain embodiments, A array of ports part 106 and A ports WL decoders and driver portion 108 are arranged on
On bottom 12-1 so that A array of ports part 106 and A ports WL decoders and driver portion 108 respectively with B ports battle array
Arrange part 116 and B ports WL decoders and driver portion 118 is symmetrical.Similarly, A ports I/O circuits 110 and A ports
Control circuit 112 is arranged on bottom 12-1 so that A ports I/O circuits 110 and A port control circuits 112 respectively with B ends
Mouth I/O circuits 120 and B port control circuits 122 are symmetrical.
Fig. 3 is the circuit diagram according to an example of the dual-port bit location 150 of some embodiments.Fig. 4 is dual-port position
The layout of unit 150.Reference picture 3, in certain embodiments, dual-port bit location 150 are high density dual-port bit locations, and
And as described above, the Part I 152 of unit 150 is arranged on SRAM array 100 (Fig. 2) first layer, such as bottom 12-1
(as depicted in figs. 1 and 2).For example, Part I 152 is arranged at least one of A array of ports part 106 (as shown in Figure 2)
On point.Therefore, Part I 152 includes A port elements.The Part II 154 of bit location 150 is arranged on the (figure of SRAM array 100
2) on the second layer, such as upper strata 12-2 (as depicted in figs. 1 and 2), it is vertically arranged relative to first layer.For example, second
154 are divided to be arranged at least a portion of B array of ports part 116 (as shown in Figure 2), therefore Part II 154 includes B ports
Element.
Reference picture 3 and Fig. 4, in certain embodiments, each part 152 and 154 include being provided with BL's and WL
Multiple wires or layer (for example, M1, M2, M3 etc.) (" ML ") so that BL is in the upper and lower or level 12-2 (such as Fig. 1 and Fig. 2 institutes
Show) and level 12-1 (as depicted in figs. 1 and 2) at least one conductive layer (such as M1, M2, M3) of each in along first
Direction extend, and wordline WL at least one second conductive layer (such as M1, M2, M3) of the upper and lower or level 12 along
Second direction extends, and wherein first direction is different from second direction.For example, Part I 152 includes at least one WL, it is such as horizontal
Across bottom 12-1 (as depicted in figs. 1 and 2) horizontal-extending (i.e. along x directions) WL_A.Part I 152 also includes the bottom of across
Layer 12-1 extends vertically at least one pair of paratope line BL of (i.e. along y directions).For example, Part I 152 may include at least one
To complementary BL, BL_A and BLB_A shown in such as Fig. 3 and Fig. 4.As shown in figure 4, bit line BL_A and BLB_A are extended parallel to each other,
Power line (such as VSS) arranges value extends between them and parallel to bit line BL_A and BLB_A.Second source line (such as VDD)
Be also disposed at BL_A, BLB_A and VSS identical conductive layer (such as M1, M2, M3) in.Line for VDD be arranged to
BLB_A is adjacent and extends parallel to bit line BL_A and BLB_A and VSS.In certain embodiments, Part I 152 also includes A
Port element, it includes at least two transmission grid (PG) transistor devices (such as PGA0 and PGA1), they coupled to WL and
BL.In certain embodiments, PG transistor devices are NMOS or PMOS device.In certain embodiments, additional interconnection structure
290 are used to connect the active device of Part I 152 and the active device (such as transistor) of Part II 154.
In certain embodiments, Part I 152 also includes at least one phase inverter 302, wherein each phase inverter 302 is equal
At least one pull-up (PU) transistor device (such as PU_A, Fig. 4) and at least one drop-down (PD) transistor device can be included
(such as PD_A, Fig. 4).In certain embodiments, PU transistor devices and PD transistor devices are NMOS or PMOS device.First
Part 152 can have any amount of PG, PU and PD transistor device.
Similar to Part I 152, Part II 154 can also include at least one WL, such as across upper strata 12-2 water
WL_B of the flat extension (i.e. along x directions).Part II 154 also includes extending vertically (i.e. along y directions) across upper strata 12-2
At least one pair of paratope line BL.For example, Part II 154 may include at least one pair of complementary BL, such as BL_B and BLB_B.
In some embodiments, Part II 154 also includes B port elements, it include at least two PG transistor devices (such as PGB0 and
PGB1), they are coupled to WL and BL.In certain embodiments, PG transistor devices are NMOS or PMOS device.
In certain embodiments, Part II 154 also includes at least one phase inverter 304, and wherein phase inverter 304 can wrap
Include at least one PU transistor devices (such as PU_B) and at least one PD transistor devices (such as PD_B).In some embodiments
In, PU transistor devices and PD transistor devices are NMOS or PMOS device.Part II 154 can have any amount of PG,
PU and PD transistor devices.
As shown in figure 4, each transistor device PGA0, PGA1, PD_A, PU_A, PGB0, PGB1, PD_B, PU_B include
Grid 310, its can include polysilicon (" poly ")/silicon oxynitride (" SION ") structure, high k/ metal gate structures or they
Combination.The example of Semiconductor substrate includes but is not limited to body silicon, silicon phosphorus (" SiP "), SiGe (" SiGe "), carborundum
(" SiC "), germanium (" Ge "), silicon-on-insulator-silicon (" SOI-Si "), silicon-on-insulator-germanium (" SOI-Ge ") or combinations thereof.
In certain embodiments, various technologies can be used to form one or more active regions in Semiconductor substrate for grid 310
Above (" OD ").For example, grid 310 is formed as block planar metal oxide field-effect transistor (" MOSFET "), had
The block FinFET of one or more fins or finger piece, semiconductor-on-insulator (" SOI ") planar MOSFET, there is one or more
The SOI FinFET or combinations thereof of individual fin or finger piece.
In certain embodiments, PGA0, PGA1, PD_A and PU_A transistor device are arranged on bottom 12-1 so that
PGA0, PGA1, PD_A and PU_A transistor device are symmetrical with PGB0, PGB1, PD_B and PU_B respectively.For example, in some implementations
In example, such as A ports and the port of B ports (as shown in Figure 2) are substantially parallel to one another so that PGA0 and PGA1 transistor device phases
It is parallel for PD_A with the PU_A transistor devices on same layer 12-1.Similarly, PGB0 and PGB1 transistor devices relative to
PD_B with PU_B transistor devices on same layer 12-2 are parallel.
In certain embodiments, various through holes are used in each layer of 12-1 and 12-2 or between layer 12-1 and 12-2
Connection.For example, as shown in figure 4, in certain embodiments, an ILV 102 is used to the through hole 312 in layer 12-2 being connected to layer
Through hole 336 in 12-1.Similarly, another ILV 102 is used to the through hole 324 in layer 12-2 being connected to leading in layer 12-1
Hole 347.PU_B transistor devices are connected to transistor PGA0 and power line VDD by through hole 314 and 316 respectively.Through hole 317 will
PGB1 transistor devices are connected to BLB_B.PD_B transistor devices are connected to power line VSS by through hole 318,325 and 328.It is logical
PGB0 transistor devices are connected to PD_B transistor devices by hole 320 and 322 and cross tie part 290.Through hole 319 is by PGB0 crystal
Tube device is connected to BL_B, and PGB0 transistor devices are connected to through hole 324 by through hole 326 and cross tie part 290.Through hole 321
PGB0 transistor devices are connected to WL_B.
In certain embodiments, PGA0 transistor devices are connected to WL_A by through hole 330.Through hole 334 is by PGA0 transistors
Device is connected to BL_A.PD_A transistor devices and PGA0 are connected to ILV 102 by through hole 337 and cross tie part 290.Through hole 336
PGA0 transistor devices are connected to PD_A transistor devices with 338 and cross tie part 290.Through hole 339,342 and 344 and mutually
Even PD_A transistor devices are connected to power line VSS by part 290.PGA1 transistor devices are connected to BLB_A by through hole 340.It is logical
PU_A transistor devices are connected to ILV 290 by hole 346 and 347 and cross tie part 290.Through hole 345 connects transistor PU_A
To power line VDD.
When using the said structure of dual-port bit location 150, one group of port element (such as A ports) is arranged on SRAM battle arrays
On the bottom 12-1 of row 100, and another group of port element (such as B ports) is arranged on the upper strata 12-2 of SRAM array 100.
This design and structure are beneficial to the reduction of unit footprints and the reduction of integral unit area.Due to dual-port bit location
150 structure has two groups of port elements on independent layer, so reducing WL dead resistances and electric capacity.In this way, change significantly
The overall performance of dual port cell 150 is entered.In addition, by having two groups of port elements, A ports and B ends on independent layer
The power-supply wiring of each and signal routing in mouthful are dispersed among two layers.For example, in certain embodiments, for A ports
Power supply can be connected up in the bottom 12-1 for PU_A or PD_A transistor devices, and be used for first group of signal of A ports
(WL_A, BL_A and BLB_A) can be connected up in the bottom 12-1 for PGA0 and PGA1 transistor devices.Similarly, for B
The power supply of port can connect up in the upper strata 12-2 for PU_B or PD_B transistor devices, and be used for second group of B ports
Signal (WL_B, BL_B and BLB_B) can connect up in the upper strata 12-2 for PGB0 and PGB1 transistor devices.
Fig. 5 is the flow chart of an example of method 500, and this method is used to assemble semiconductor memory or SRAM array
Three-dimensional dual-port bit location (such as unit 150 (such as Fig. 2, Fig. 3 and Fig. 4 that (such as SRAM array 100 (as shown in Figure 2)) uses
It is shown)).In step 502, the Part I of latch is set on the first layer.For example, Part I 152 (such as Fig. 2, figure
Shown in 3 and Fig. 4) it is arranged on the A array of ports portion on 3D IC 10 (as shown in Figure 1) bottom 12-1 (as depicted in figs. 1 and 2)
Divide at least a portion of 106 (as shown in Figure 2).In certain embodiments, the active device of Part I 152 uses semiconductor
Treatment technology is formed in Semiconductor substrate (not shown).A ports WL decoders and driver portion 108 (as shown in Figure 2), A
Port I/O circuits 110 (as shown in Figure 2) and A port control circuits 112 (as shown in Figure 2) are also formed in bottom 12-1 and neutralize bottom
On layer 12-1.
In step 504, the Part II of latch is arranged on the second layer adjacent with first layer.For example, second
Divide the 154 upper strata 12-2 (as depicted in figs. 1 and 2) for being arranged on 3D IC 10 (as shown in Figure 2, Figure 3 and Figure 4) B array portions
In at least a portion of 116 (as shown in Figure 2).B ports WL decoders and driver portion 118 (as shown in Figure 2), B ports I/O
Circuit 120 (as shown in Figure 2) and B port control circuits 122 (as shown in Figure 2) are also formed in the 12-2 of upper strata and upper strata 12-2
On.
In step 506, first layer and the second layer are coupled together using at least one through hole so that the second layer relative to
First layer vertical stacking.For example, if layer 12-1 and 12-2 are independent semiconductor chips, layer 12-1 and 12-2 are mutually perpendicular to
Stack, align and be joined together.In certain embodiments, such as layer 12-1 and 12-2 is that layer is mutual in the embodiment of level
Stack and stack complementary metal oxide semiconductor CMOS IC to create 3D.It should be appreciated by those skilled in the art that in some implementations
In example, one or more layers can be arranged on layer between 12-1 and 12-2.In certain embodiments, formed in layer 12-1 and/or
On circuit using at least one through hole (such as ILV 102 (as shown in Figure 2, Figure 3 and Figure 4)) coupled to formed in layer 12-2
Circuit on and/or.For example, in certain embodiments, as shown in figure 4, an ILV 102 is used for the through hole in layer 12-2
312 are connected to the through hole 336 in layer 12-1.Similarly, as shown in figure 4, another ILV 102 is used for the through hole in layer 12-2
324 are connected to the through hole 347 in layer 12-1.In addition, the as shown in figure 4, company that various through holes are used in each layer 12-1 and 12-2
Connect.
Fig. 6 shows semiconductor memory or an example of SRAM array 600.In certain embodiments, SRAM array
600 are included in 3D IC 10 (as shown in Figure 1).For example, SRAM array 600 can be across two (or multiple) layers or level (example
Such as bottom 12-1 and upper strata 12-2 (as shown in Figure 1)) set, these layers stack and for example pass through one or more vertically
ILV 602a, 602b are coupled.
In certain embodiments, SRAM array 600 includes writing layer 604a and read layer 604b.Writing layer 604a includes write port member
Part, such as write port array portion 606 and write port wordline decoder 608.In certain embodiments, write port array portion
606 are coupled to write port driver 610 by paratope line 614 (for example, WBL and its complement line WBLB).In some embodiments
In, write port driver 610 is configured as receiving the input signal for SRAM 600.Write port control circuit 612 can couple
To write port wordline decoder 608.Write port control circuit 612 is configured as receiving the clock signal of write port and writes enabled letter
Number (such as negative enable signal).Write port control circuit 612 can be additionally configured to receive address signal.
In certain embodiments, SRAM 600 includes read layer 604b.Read layer 604b includes read port element, such as read port
Array portion 616 and read port wordline decoder and driver 618.In certain embodiments, read port array portion 616 passes through
Paratope line 624 (such as RBL and its complement line RBLB) is coupled to read port I/O circuits 620.In certain embodiments, end is read
Mouth I/O circuits 620 are configured as receiving data input signal and/or data output signal are transferred to outside SRAM 600.
In some embodiments, read port wordline decoder 608 is coupled to read port control circuit 622.Read port control circuit 622 may be used also
To be configured as receiving the clock signal of read port and read enable signal.Read port control circuit 622 can be additionally configured to connect
Receive address signal.
SRAM array 600 includes at least one three-dimensional three port bit location 650, and it includes setting first on the first layer
Part 652 (such as write port array portion 606) and (such as the read port array part of Part II 654 on the second layer is set
Divide 616) (referring to Fig. 7).As explained in more detail below, three port bit locations 650 have beneficial to smaller unit footprints,
The structure and design of faster speed and adjustable and flexible WL decoders layout, it is simple and wiring is friendly.
In certain embodiments, write port array portion 606 and write port WL decoders 608 are arranged on and write on layer 604a,
So that write port array portion 606 and write port WL decoders 608 respectively with read port array portion 616 and read port WL
Decoder and driver portion 618 are symmetrical.Similarly, write port driver 610 and write port controller 612 can respectively with reading
Port I/O circuits 620 and read port controller 622 are symmetrical.
Fig. 7 is the circuit diagram according to an example of the port bit location 650 of three-dimensional three of some embodiments.Fig. 8 is three ends
The layout of mouth bit location 650.Reference picture 7, in certain embodiments, it is single that three port bit locations 650 include the port of high density three
Member, it includes writing part 652 and reads part 654.Write part 652 and be arranged on SRAM array 600 the of three port bit locations 650
In at least a portion of one layer (such as writing a layer 604a).The reading part 654 of three port bit locations 650 is arranged on SRAM array 600
The second layer (such as read layer 604b) at least a portion on.
In certain embodiments, each part 652,654 of three port bit locations 650 includes being provided with bit line
(BL) and wordline (WL) multiple wires or layer so that bit line extends along a first direction at least one conductive layer, and word
Line extends at least one second conductive layer along second direction, and wherein first direction is different from second direction.For example, scheming
In embodiment shown in 7, writing part 652 includes one group of paratope line WBL and WBLB.Bit line, which is arranged on, writes the first of part 652
In conductive layer.Writing part 652 also includes write word line WWL.WWL is arranged in the second conductive layer for writing part 652.WBL and WBLB
(such as vertical direction) extends along a first direction, and WWL extends along second direction (such as horizontal direction).Read part 654
Including one group of bit line RBL_1 and RBL_2 being arranged in the first conductive layer for reading part 654.One group of bit line RBL_1 and RBL_2
It may include paratope line RBL and RBLB.Read part 654 also includes being arranged in the second conductive layer for reading part 654 at least one
Bar readout word line.In an illustrated embodiment, reading part 654 includes the first readout word line and the second readout word line, respectively RWL_1 with
RWL_2.(such as vertical direction) extends RBL_1 and RBL_2 along a first direction, and RWL_1 and RWL_2 is along second direction
(such as horizontal direction) extends.In certain embodiments, RWL_1 and RWL_2 may include wall scroll readout word line.
In certain embodiments, writing part 652 and/or reading part 654 includes multiple transmission grid (PG) transistor devices,
Such as it is arranged on and writes WPG1 in part 652 and WPG2 and be arranged on the RPG1 and RPG2 read in part 654.WPG1 and WPG2
WBL and WBLB are coupled respectively to, and is all coupled to WWL.RPG1 is coupled to RBL_1 (or RBL) and RWL_1, and RPG2 couplings
It is bonded to RBL_2 (or RBLB) and RWL_2.PG transistor devices may include PMOS or nmos pass transistor device.For example, Fig. 7 and Fig. 8
Show one embodiment of the bit location 650 including NMOS transmission grid structures.As another example, Fig. 9 and Figure 10 show
One embodiment of bit location 750 is gone out, wherein transmission grid WPG1 and WPG2 include PMOS transmission grid structures.
In certain embodiments, writing part 652 and/or reading part 654 may include one or more additional transistor tube devices.
For example, in certain embodiments, writing part 652 includes multiple latch 656a, 656b.Multiple latch 656a, 656b include
Self-reinforcing configures.Multiple latch 656a, 656b are coupled to the WPG1 and WPG2 for writing part 652.In certain embodiments, reading portion
654 are divided to include being coupled to RPG1 and RPG2 multiple grid 658a, 658b.In certain embodiments, read layer 654 includes multiple locks
Deposit phase inverter (referring to Figure 11).
As shown in figure 8, in certain embodiments, be arranged on multiple latch 656a, the 656b write on layer 652 include it is multiple
Pull up (PU) transistor device and multiple drop-down (PD) transistor devices.In various embodiments, PU transistor devices and PD are brilliant
Body tube device includes NMOS and/or PMOS device.In an illustrated embodiment, each latch include PU transistor devices and
PD transistor devices.
In certain embodiments, multiple through holes are formed so that each layer 652,654 is interior and writes layer 652 and read layer 654
Between connection, one or more inter-level vias (ILV) allow to write the connection between layer 652 and read layer 654.For example, at one
In embodiment, the first ILV 602a are configured as the through hole 614 being electrically coupled to the through hole 628 write in layer 652 in read layer 654,
And the 2nd ILV 602b be configured as the through hole 621 that is electrically coupled to the through hole 637 write in layer 652 in read layer 654.Through hole
626 and 635 are configured as PG transistor devices (such as WPG1 and WPG2) being coupled to WWL.Through hole 631,632,639 and 640
Power vd D is coupled to each latch 656a, 656b PU transistor devices.Power supply VSS is coupled to by through hole 629 and 638
Each latch 656a, 656b PD transistor devices.
In certain embodiments, read layer 654 includes multiple through holes, and they are configured as the connection being beneficial in read layer 654.It is logical
RPG1 is coupled to RWL_1 by hole 612 and 613.RPG2 is coupled to RWL_2 by through hole 619 and 620.Through hole 615 and 622 is by power supply
VSS is coupled to pull-down transistor 658a, 658b, is shown respectively as RPD1 and RPD2.RBL_1 is coupled to by through hole 624 and 625
RBL_2 is coupled to RPG2 by RPG1, and through hole 617 and 618.It will be appreciated by persons skilled in the art that layer 652 can write
And/or read layer 654 includes more or less through holes.
In certain embodiments, three port bit locations 650 include three-dimensional three port ten transistor (3D10T) bit location.3D
10T bit locations are arranged to SRAM storage organizations.3D 10T bit locations include being arranged on the different layers of SRAM array 600
Write part 652 and read part 654, such as respectively write port array portion 606 and read port array portion 616.In some realities
Apply in example, writing part 652 includes six transistors (6T) NMOS SRAM structures, and reading part 654 includes four transistor arrangements.
In certain embodiments, writing part 652 includes 6T PMOS transmission grid (PPG) SRAM structures.Write part 652 and read part 654
Coupled by multiple ILV 602a, 602b.3D10T bit locations are advantageous to smaller footprints, and eliminate the front end of free time
The waste (wasted empty front-end area) in region, so as to produce 3D 10T bit locations simple and that wiring is friendly
Periphery.
In various embodiments, three port bit locations 650 may include three ports or two-port operation.In three port operations
In, first port RPG1 and second port RPG2 are independent.For example, as shown in fig. 7, RPG1 is coupled to the first readout word line RWL_
1, and RPG2 is coupled to the first readout word line RWL_2.RPG1 and RPG2 read port operation may include single-ended reading, keep simultaneously
The value of (" maintenance ") unit.RPG1 and RPG2 is coupled in two-port operation, such as by wall scroll readout word line (not shown).Both ends
Mouth read port operation may include voltage difference sense amplifier scheme.
The said structure of three port bit locations 650 is beneficial to the reduction of unit footprints and subtracting for overall cell area
It is small.For example, in one embodiment, above-mentioned 3D 10T bit locations can almost reduce macroscopic view relative to traditional 3D 10T bit locations
The 50% of area.Further, since three port bit locations 650 have the write port 652 and read port 654 set on the different layers,
So WL dead resistances and electric capacity are reduced, so as to improve the overall performance of three port bit locations 650.By on the different layers
With write port 652 and read port 654, for writing part and reading the power-supply wiring and signal routing of each part in part
It can disperse between the two layers, so as to realize simply and connect up the periphery having had.
Fig. 9 and Figure 10 shows one embodiment of three-dimensional three port bit locations 750, wherein, writing layer 752 includes first
PMOS transmits grid structure WPG1 and the 2nd PMOS transmission grid structures WPG2.Three-dimensional three port bit locations 750, which are similar to, to be combined
The bit location 650 of Fig. 7 and Fig. 8 descriptions.Figure 10 shows the block diagram of the port bit location 750 of three-dimensional three shown in Fig. 9.Bit location
750 include multiple through holes in favor of the connection between layer 752,754 and in every layer 752,754.Through hole 729,730,738 and 739
Latch 656a, 656b PU transistors are coupled to power vd D.Through hole 731,732,740 and 741 by latch 656a,
656b PD transistors are coupled to power supply VSS.Figure 10 block diagram is similar to the block diagram shown in Fig. 8.
Figure 11 shows the bit location 850 that multiple latch inverters 856a and 856b on part 854 are read including being arranged on
One embodiment.Multiple latch inverters 856a and 856b may include multiple NMOS and/or PMOS device.In some embodiments
In, transistor device WPG1, WPG2 and latch 856a and 856b are arranged on and write on layer 852 so that they are relative to reading part
854 transistor RPG1, RPG2 and anti-phase latch 856a and 856b are symmetrical arranged.
The embodiment of three-dimensional dual-port bit location described herein, which has, to be beneficial to reduce footprints while improves overall list
First performance simultaneously suppresses to correspond to the signal routing complexity of static RAM (" SRAM ") array used in unit
Structure and design.For example, in certain embodiments, configure 3D dual port cells so that one group of port of a part for latch
Element is arranged on one layer of 3D semiconducter ICs, and another part of latch another group of port element be arranged on IC with
Above-mentioned layer vertically adjacent to different layers on.On IC different layers there are two groups of different port elements to be beneficial to subtracting for footprints
It is small, and also reduce WL dead resistances and electric capacity.Therefore, the overall performance of unit is substantially increased.
In certain embodiments, three-dimensional dual-port bit location includes be arranged on latch in the first level first
Point, wherein, Part I includes multiple first port elements.The Part II of latch, which is arranged on, uses at least one through hole phase
For in the second level of the first level vertical stacking, wherein the second level includes multiple second port elements.
In certain embodiments, semiconductor memory includes the first level, and it includes first port array portion.Semiconductor
Second level of the memory also including the use of at least one through hole relative to the first level vertical stacking, wherein the second level includes
Second port array portion.Semiconductor memory also includes at least one three-dimensional dual port cell, and it includes being arranged on first end
The Part I of latch on mouth array portion, wherein Part I include multiple first port elements.Dual-port bit location
Also include the Part II of latch being arranged on the second array portion, wherein Part II includes multiple second ports member
Part.
In certain embodiments, included using the method for three-dimensional dual-port bit location：Set in the first level three-dimensional double
The Part I of the latch of port bit location, Part I include multiple first port elements.This method also includes：Using
At least one through hole sets the latch of three-dimensional dual-port bit location in the second level relative to the first level vertical stacking
Part II, Part II include multiple second port elements.
The embodiment of three-dimensional three port bit location described herein, which has, to be beneficial to reduce footprints while improves overall list
First performance simultaneously suppresses to correspond to the signal routing complexity of static RAM (" SRAM ") array used in unit
Structure and design.For example, in certain embodiments, configure the port units of 3D tri- so that write port element group is arranged on 3D and partly led
On body IC first layer, and read port element group be arranged on IC with above-mentioned first layer vertically adjacent to the second layer on.In IC
Different layers on there is the reduction that two groups of different port elements are beneficial to footprints, and also reduce WL dead resistances and electricity
Hold.Therefore, the overall performance of unit is substantially increased.
In certain embodiments, three-dimensional three port bit locations include the reading part being arranged in the first level.Part is read to wrap
Include multiple read port elements.The three ports bit location also includes being disposed relative in the second level of the first level vertical stacking
Write part.First and second levels are coupled using at least one through hole.Writing part includes multiple write port elements.
In certain embodiments, semiconductor memory includes the first level, and it includes first port array portion.Semiconductor
Memory also includes the second level relative to the first level vertical stacking.First and second levels use at least one through hole coupling
Close.Second level includes second port array portion.Semiconductor memory also includes at least one three-dimensional three port unit.This three
Tieing up three port bit locations includes being arranged on the first port array portion of the first level writing part.Writing part includes multiple write
Port element.Three-dimensional three port bit locations also include the reading part being arranged on the second port array portion of the second level.Read
Part includes multiple read port elements.
In certain embodiments, the method to form three-dimensional three port bit locations is disclosed.In the first step, in semiconductor
The reading part of three-dimensional three port bit locations is set in the first level of structure.The reading part of three-dimensional three port bit locations includes multiple
Read port element.In the second step, bit location is set in the second level of semiconductor structure writes part.Writing part includes
Multiple write port elements.First level and the second level vertical stacking and coupled by least one through hole.
The feature of multiple embodiments is discussed above so that those skilled in the art better understood when that the present invention's is each
Individual aspect.It should be appreciated by those skilled in the art that they easily can design or change use using based on the present invention
In other techniques and structure for performing with embodiment identical purpose as described herein and/or realizing same advantage.This area skill
Art personnel should also be appreciated that these equivalent structures without departing substantially from the spirit and scope of the present invention, and can be without departing substantially from this hair
Make a variety of changes, replace and change in the case of bright spirit and scope.
Claims (17)
1. a kind of three port bit locations of three-dimensional, including：
Part is write, is arranged in the first level, the part of writing includes multiple write port elements；And
Part is read, is arranged in the second level, second level is relative to the first level vertical stacking and using at least
One through hole is coupled to first level, and second level includes multiple read port elements, wherein, the reading part is also wrapped
Include and be arranged in second level and coupled at least one latch inverters of the multiple read port element.
2. three-dimensional three port bit location according to claim 1, wherein, the part of writing also includes a plurality of write bit line, often
Bar write bit line extends along a first direction in the first conductive layer of first level, and the reading part is also including more
Bar sense bit line, every sense bit line extend in the first conductive layer of second level along the first direction.
3. three-dimensional three port bit location according to claim 2, wherein, the part of writing also is write including at least one
Line, the write word line prolong in the second conductive layer of first level along the second direction different from the first direction
Stretch, and the reading part also includes at least one readout word line, and the readout word line is in the second conductive layer of second level
Extend along the second direction.
4. three-dimensional three port bit location according to claim 1, wherein, the multiple read port element includes multiple reading ends
Mouth grid.
5. three-dimensional three port bit location according to claim 3, wherein, it is the multiple to write subelement and include multiple writing end
Mouth grid.
6. three-dimensional three port bit location according to claim 5, wherein, three port bit location includes ten transistors
Unit, the read port element includes four transistor arrangements and the write port element includes six transistor arrangements.
7. three-dimensional three port bit location according to claim 5, wherein, the multiple read port grid and the multiple write
Each in the grid of port is one kind in nmos device and PMOS device.
8. three-dimensional three port bit location according to claim 1, in addition to：
Write control circuit, it is arranged in first level；And
Control circuit is read, is arranged in second level.
9. three-dimensional three port bit location according to claim 8, wherein, the reading control circuit includes read port control electricity
Road and readout word line decoder, and the write control circuit includes write port control circuit and write word line decoder.
10. a kind of semiconductor memory, including：
First level, including first port array portion；
Second level, include second relative to the first level vertical stacking, second level using at least one through hole
Array of ports part；And
At least one three-dimensional three port bit location, including：
Part I, it is arranged on the first port array portion, the Part I includes multiple write port elements；With
Part II, it is arranged on the second port array portion, the Part II includes multiple read port elements, described
Part II also includes at least one latch inverters coupled to the multiple read port element.
11. semiconductor memory according to claim 10, wherein, the Part I also includes a plurality of write bit line, often
One write bit line extends along a first direction in the first conductive layer of first level, and the Part II also wraps
A plurality of sense bit line is included, each sense bit line extends in the first conductive layer of second level along the first direction.
12. semiconductor memory according to claim 11, wherein, the Part I also writes including at least one
Line, each write word line is along the second direction different from the first direction in the second conductive layer of first level
Extension, and the Part II also includes at least one readout word line, and each readout word line is the second of second level
Extend in conductive layer along the second direction.
13. semiconductor memory according to claim 10, wherein, the multiple read port element includes multiple read ports
Grid.
14. semiconductor memory according to claim 10, in addition to：The write port control being arranged in first level
Circuit processed and the read port control circuit being arranged in second level.
15. semiconductor memory according to claim 10, in addition to：The write driver being arranged in first level
With write word line decoder and read input/output (I/O) circuit and readout word line decoder that are arranged in second level.
16. a kind of method for assembling semiconductor memory, including：
The part of writing of three-dimensional three port bit locations is set in the first level, and the part of writing includes multiple write port elements；
The reading part of the three-dimensional three port bit location is set on the second level relative to the first level vertical stacking,
The reading part includes multiple read port elements and at least one latch inverters, wherein, at least one latch is anti-phase
Device is coupled to the multiple read port element；And
First level is coupled to second level using at least one through hole.
17. the method according to claim 16 for assembling semiconductor memory, in addition to：
It is that the multiple write port element transmits first group of signal in first level；And
It is that the multiple read port element transmits second group of signal in second level.
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| US14/098,567 | 2013-12-06 | ||
| US14/098,567 US9208854B2 (en) | 2013-12-06 | 2013-12-06 | Three dimensional dual-port bit cell and method of assembling same |
| US14/334,935 | 2014-07-18 | ||
| US14/334,935 US10083739B2 (en) | 2013-12-06 | 2014-07-18 | Three-dimensional three-port bit cell and method of assembling same |
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| CN101131858A (en) * | 2007-09-28 | 2008-02-27 | 山东大学 | Three-dimensional multi-port memory and control method thereof |
| CN101308839A (en) * | 2007-05-18 | 2008-11-19 | 国际商业机器公司 | Compact multi-port cam cell implemented in 3d vertical integration |
| CN101312199A (en) * | 2007-05-21 | 2008-11-26 | 国际商业机器公司 | Multiple port register file cell and manufacturing method thereof |
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|---|---|---|---|---|
| CN101308839A (en) * | 2007-05-18 | 2008-11-19 | 国际商业机器公司 | Compact multi-port cam cell implemented in 3d vertical integration |
| CN101312199A (en) * | 2007-05-21 | 2008-11-26 | 国际商业机器公司 | Multiple port register file cell and manufacturing method thereof |
| CN101131858A (en) * | 2007-09-28 | 2008-02-27 | 山东大学 | Three-dimensional multi-port memory and control method thereof |
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