JP5721444B2 - Source driver and liquid crystal display device using the same - Google Patents

Description

  The present invention relates to a driving technique for a liquid crystal panel, and more particularly to a source driver that inverts and drives a data line.

  The liquid crystal panel includes a plurality of data lines, a plurality of scanning lines arranged orthogonal to the data lines, and a plurality of TFTs (Thin Film Transistors) arranged in a matrix at intersections of the data lines and the scanning lines. . In order to drive the liquid crystal panel, a gate driver circuit that sequentially selects a plurality of scanning lines and a source driver that applies a voltage corresponding to the luminance to each data line are provided.

  When a DC voltage is continuously applied to the data line, there is a problem that the liquid crystal panel deteriorates. In order to solve this problem, in recent years, a method (inversion drive method) in which voltages having different polarities are alternately applied to each data line in an alternating manner has become mainstream.

JP-A-8-320684 JP 2009-109881 A

  The source driver includes, for each data line, a D / A converter that converts luminance data indicating a drive voltage to be applied to the data line into an analog voltage, and an amplifier that applies the analog voltage to the data line. Since the number of data lines is as large as several hundred, the circuit area of the source driver becomes large.

  The present invention has been made in view of such a situation, and one of the exemplary purposes of an aspect thereof is to reduce the circuit area of the source driver.

  One embodiment of the present invention relates to a source driver that inverts and drives a plurality of data lines of a liquid crystal panel. This source driver has an upper power supply terminal for receiving a first upper power supply voltage and a lower power supply terminal for receiving a lower power supply voltage lower than the first upper power supply voltage, and a drive voltage to be applied to each of the plurality of data lines. A logic circuit that outputs luminance data to be instructed and a drive circuit provided for each of two adjacent data lines, receiving luminance data from the logic circuit, and having a first polarity of the first polarity corresponding to the luminance data An inverting drive circuit that generates a drive voltage and a second drive voltage having a second polarity opposite to the first polarity, and alternately applies the first drive voltage and the second drive voltage to the two data lines in a predetermined cycle; . Each inversion driving circuit includes an upper power supply terminal to which a second upper power supply voltage higher than the first upper power supply voltage is supplied, and a lower side to which a predetermined intermediate voltage between the second upper power supply voltage and the lower power supply voltage is supplied. A high-side amplifier that generates a first drive voltage corresponding to the first analog voltage, an upper power supply terminal to which an intermediate voltage is supplied, and a lower power supply terminal to which a lower power supply voltage is supplied A low-side amplifier that generates a second drive voltage corresponding to the second analog voltage, and the first and second drive voltages generated by the high-side amplifier and the low-side amplifier are applied to two data lines with a predetermined value. An output switch that switches the output at a cycle, a first share switch provided between one of the two data lines and the lower power supply terminal of the high side amplifier, the other of the two data lines, and the low side amplifier With the upper power supply terminal The high-level voltage of the first luminance data indicating the first drive voltage is level-shifted to the second upper power supply voltage, and the low-level voltage of the first luminance data is set to the intermediate voltage. A first level shift circuit for shifting, a second level shift circuit for level-shifting a high level voltage of the second luminance data indicating the second drive voltage to an intermediate voltage, and an upper power supply terminal to which a second upper power supply voltage is supplied A first power supply terminal to which an intermediate voltage is supplied, a first D / A converter that converts the first luminance data output from the first level shift circuit into a first analog voltage, and the intermediate voltage is supplied. A second D / A that converts the second luminance data output from the second level shift circuit into a second analog voltage, and an upper power supply terminal that is supplied with a lower power supply voltage. It includes a converter, a.

According to this aspect, the second upper power supply voltage AVDD and the intermediate voltage Vc are supplied to the power supply terminal of the high side amplifier, and a voltage between the second upper power supply voltage AVDD and the intermediate voltage Vc is also input to the input terminal. The first drive voltage that is the output also changes between the second upper power supply voltage AVDD and the intermediate voltage Vc. The same applies to the first D / A converter. That is, the high-side amplifier and the first D / A converter may be configured with a breakdown voltage of about (AVDD−Vc).
Further, the intermediate voltage Vc and the lower power supply voltage VSS are supplied to the power supply terminal of the low side amplifier, the intermediate voltage Vc and the lower power supply voltage VSS are also supplied to the input terminals, and the second drive voltage as the output is also supplied. , And varies between the intermediate voltage Vc and the lower power supply voltage VSS. The same applies to the second D / A converter. In other words, the low-side amplifier and the second D / A converter may be configured with a breakdown voltage of about (Vc−VSS).
Therefore, the circuit area can be reduced as compared with the conventional circuit in which the high-side amplifier, the low-side amplifier, and the first and second D / A converters need to be configured with a breakdown voltage of about (AVDD-VSS).

Each inverting drive circuit includes a first diode provided between the output terminal of the high-side amplifier and the lower power supply terminal of the high-side amplifier so that the cathode faces the output terminal, and the upper power supply terminal of the low-side amplifier. There may be further provided a second diode provided between the output terminals of the low-side amplifier in such a direction that the anode is on the output terminal side.
By providing the first diode and the second diode, it is possible to prevent an overvoltage from being applied during polarity reversal.

  The source driver according to an aspect may further include a voltage source that is provided in common to the plurality of inverting drive circuits and generates an intermediate voltage.

The intermediate voltage may be a midpoint voltage between the second upper power supply voltage and the lower power supply voltage.
In this case, the breakdown voltage required for the pair of the high side amplifier and the first D / A converter and the breakdown voltage required for the pair of the low side amplifier and the second D / A converter can be made uniform.

The first share switch and the second share switch may be turned on every time the polarity is inverted.
Thereby, it is possible to prevent an overvoltage from being applied during polarity reversal.

The first luminance data and the second luminance data may be set to values at which the first and second drive voltages become substantially intermediate voltages every time the polarity is inverted.
Thereby, it is possible to prevent an overvoltage from being applied during the polarity reversal.

  The polarity inversion is performed for each image frame, and the first share switch and the second share switch may be turned on during a blank period of the image frame.

  Another embodiment of the present invention is a liquid crystal display device. The liquid crystal display device includes a liquid crystal panel, the source driver according to any one of the above-described modes for driving a plurality of data lines of the liquid crystal panel, and a gate driver circuit for driving the plurality of scanning lines of the liquid crystal panel.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, the circuit area of the source driver can be reduced.

It is a circuit diagram which shows the structure of the liquid crystal display provided with the source driver which concerns on embodiment. 2A to 2D are circuit diagrams illustrating state transitions of the source driver of FIG. FIG. 2 is an operation waveform diagram of the source driver of FIG. 1. It is a figure which shows the modification of a liquid crystal panel. It is an operation waveform diagram in the case of polarity inversion for each image frame.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 1 is a circuit diagram illustrating a configuration of a liquid crystal display 200 including a source driver 100 according to an embodiment. The liquid crystal display 200 includes a source driver 100, a gate driver 110, a liquid crystal panel 120, and a timing controller 130.

  The liquid crystal panel 120 includes m data lines LD1 to LDm and n scanning lines LS1 to LSn, and pixel circuits arranged in a matrix are provided at intersections of the data lines LD and the scanning lines LS. FIG. 1 shows only the TFT for each pixel. The gate of the TFTij in the i-th row and the j-th column is connected to the scanning line LSj in the j-th column, and its source is connected to the data line LDi in the i-th row.

The gate driver 110 receives data from the timing controller 130, sequentially applies voltages to the plurality of scanning lines LS1 to LSn, and selects them cyclically. The source driver 100 receives the luminance data S1 from the timing controller 130, a plurality of data lines LD1～LDm, supplies a driving voltage _V DRV1 _{~V DRVm} in accordance with luminance data S1. The source driver 100 performs inversion driving in which a drive voltage having a first polarity higher than a predetermined reference voltage Vc and a drive voltage having a second polarity lower than the reference voltage Vc are alternately applied to each data line LD.

  The source driver 100 is a functional IC integrated on a single semiconductor substrate. The output terminals P1 to Pm of the source driver 100 are connected to the data lines LD1 to LDm, respectively. Further, luminance data S <b> 1 indicating the luminance for each pixel is input to the data input terminal 102 of the source driver 100. The capacitor terminal 104 is connected with a charge share capacitor C1 for holding charges, which will be described later.

  Two adjacent data lines LD form a pair. That is, the data lines LD1 and LD2 form a first pair, and the data lines LD3 and LD4 form a second pair. When generalized, the data lines LD (2i-1) and LD (2i) form the i-th pair.

  The source driver 100 includes a digital power supply voltage (first upper power supply voltage) DVDD, an analog power supply voltage (second upper power supply voltage) AVDD higher than the first upper power supply voltage DVDD, and a ground voltage (lower power supply voltage) VSS. A fixed voltage is supplied. For example, the first upper power supply voltage DVDD = 3.3V, the second upper power supply voltage AVDD = 12V, and the lower power supply voltage VSS = 0V.

  The source driver 100 includes a logic circuit 10, an inverting drive circuit 12, and a regulator 20.

  The regulator 20 stabilizes one end 104 of the charge share capacitor C1 to an intermediate voltage Vc between the second upper power supply voltage AVDD and the lower power supply voltage VSS. The regulator 20 and the charge share capacitor C1 can be understood as voltage sources that generate the intermediate voltage Vc. Preferably, the intermediate voltage Vc is the midpoint voltage Vc = (AVDD + VSS) / 2 between the second upper power supply voltage AVDD and the lower power supply voltage VSS. The intermediate voltage Vc is not limited to the midpoint voltage, and may be set to any value as long as the high side amplifier HAMP and the low side amplifier LAMP can generate the drive voltage to be supplied to the data line over the entire range. From another point of view, it is desirable to make the intermediate voltage Vc coincide with a reference voltage that is a boundary between the first polarity and the second polarity of the drive voltage.

Logic circuit 10 receives a first upper power supply voltage DVDD on its upper side power supply terminal _{P H,} receives the lower supply voltage VSS to the lower power supply terminal _{P L.} The logic circuit 10 includes an interface circuit that receives the luminance data S1 from the timing controller 130. The logic circuit 10 divides the luminance data S1 received from the timing controller 130 into luminance data S2 for each pixel, that is, for each data line. 12 is output. The luminance data S2 is n-bit (n is a natural number) parallel data, and the high level of each bit is the first upper power supply voltage DVDD, and the low level is the lower power supply voltage VSS.

  The inversion drive circuit 12 is provided for every two data lines forming a pair. That is, the inversion drive circuit 12_1 is provided for the pair of data lines LD1 and LD2, and the inversion drive circuit 12_m / 2 is provided for the pair of the data lines LDm-1 and LDm.

Each inversion drive circuit 12 receives the luminance data S2 _P, S2 _N from the logic circuit 10, a first driving voltage V _P of the first polarity corresponding to each luminance data, the second polarity opposite to the first polarity second generates a second driving voltage V _N, it is applied a first driving voltage V _P and the second driving voltage V _N, alternately to the data line LD of the two in a predetermined cycle.

  The inverting drive circuit 12 includes a high side amplifier HAMP, a low side amplifier LAMP, an output switch SW, a first share switch SWC1, a second share switch SWC2, a first level shift circuit LVS1, a second level shift circuit LVS2, and a first D / A, respectively. It includes a converter DAC1, a second D / A converter DAC2, a first diode D1, and a second diode D2.

The upper power supply terminal P _H of the high-side amplifier HAMP is supplied second upper power supply voltage AVDD, the intermediate voltage Vc is supplied to the lower power supply terminal P _L. The high-side amplifier HAMP generates the first driving voltage _{V P} corresponding to the first analog voltage Va _P is the input. The high side amplifier HAMP and the low side amplifier LAMP may be configured as a voltage follower circuit using an operational amplifier.

The low-side amplifier LAMP upper power supply terminal P _H, the intermediate voltage Vc is supplied, the lower supply voltage VSS is supplied to the lower power supply terminal P _L. The low side amplifier LAMP generates a second drive voltage V _N corresponding to the second analog voltage Va _N.

The output switch SW switches the first drive voltage V _P and the second drive voltage V _N generated by the high side amplifier HAMP and the low side amplifier LAMP to the two data lines LDi and LDi + 1 at a predetermined cycle and outputs them. That is, depending on the state of the output switch SW, the first driving voltage V _P of the first polarity is applied to the data line LDi, the first state φ1 to the second driving voltage V _N of the second polarity is applied to the data line LDi + 1 When the first driving voltage _{V P} is applied to the data line LDi + 1, the second state φ2 to the second driving voltage _{V N} is applied to the data line LDi is switched alternately.

First Share switches SWC1 is provided between the one LDi of two data lines, and the lower power supply terminal _{P L} of the high-side amplifier HAMP. The second share switch SW2, the other LDi + 1 of two data lines are provided between the upper power supply terminal _{P H} of the low-side amplifier LAMP.
The first share switch SWC1 and the second share switch SWC2 are turned on every time the polarity is inverted. Thereby, the potential of the data lines LDi and LDi + 1 becomes equal to the intermediate voltage Vc for every inversion of polarity. In the present embodiment, the polarity is inverted every time the scanning line LS is switched.

The first level shift circuit LVS1 is a high-level voltage of the first luminance data S2 _P for instructing a first driving voltage _{V P} (DVDD), level-shifted to the second upper power supply voltage AVDD, the first luminance data S2 _P The low level voltage (VSS) is level shifted to the intermediate voltage Vc.
The second level shift circuit LVS2 is level-shifted high-level voltage of the second luminance data S2 _N instructing second driving voltage _{V N} a (DVDD) to the intermediate voltage Vc.

The upper power supply terminal _{P H} of the 1D / A converter DAC1 is supplied second upper power supply voltage AVDD, the intermediate voltage Vc is supplied to the lower power supply terminal _{P L.} The 1D / A converter DAC1 converts the first luminance data S2 _P 'output from the first level shift circuit LVS1 the first analog voltage Va _P.

The upper power supply terminal _{P H} of the 2D / A converter DAC2 intermediate voltage Vc is supplied, the lower supply voltage VSS is supplied to the lower power supply terminal _{P L.} The second D / A converter DAC2 converts the second luminance data S2 _N ′ output from the second level shift circuit LVS2 into the second analog voltage Va _N.

The first diode D1, between the lower power supply terminal P _L of the output terminal of the high-side amplifier HAMP and the high-side amplifier HAMP, are disposed in a direction where the cathode is an output terminal side. The second diode D2 is provided between the output terminal of the low-side amplifier LAMP upper power supply terminal P _H and the low-side amplifier LAMP, it is disposed in a direction in which the anode is an output terminal side.

  The above is the configuration of the source driver 100. Next, the operation of the source driver 100 will be described. 2A to 2D are circuit diagrams illustrating state transitions of the source driver 100 of FIG. FIG. 3 is an operation waveform diagram of the source driver 100 of FIG.

  2A to 2D show only the peripheral circuits of the inverting drive circuit 12 that drives the two data lines LD1 and LD2 that make a pair. Each of the high side amplifier HAMP and the low side amplifier LAMP includes a push-pull type output stage. The high side amplifier HAMP includes, as an output stage, a P-channel MOSFET (hereinafter referred to as a first transistor M1) and an N-channel MOSFET (hereinafter referred to as a second transistor M2) connected in series between a power supply voltage AVDD and an intermediate voltage Vc. Prepare. Further, the low-side amplifier LAMP includes an P-channel MOSFET (hereinafter referred to as a third transistor M3) and an N-channel MOSFET (hereinafter referred to as a fourth transistor M4) connected in series between the intermediate voltage Vc and the ground voltage VSS as an output stage. including. The input differential stage and the amplification stage of the high side amplifier HAMP and the low side amplifier LAMP are omitted.

  The source driver 100 repeats the states of φ1, φ12, φ2, and φ21 described below in synchronization with the selection operation of the scanning line LS of the gate driver 110.

φ1. When the gate driver 110 selects the j-th scanning line LSj, the source driver 100, the data lines LD1 in the first polarity of the driving voltage _{V P,} and drives the data line LD2 in the second polarity of the driving voltage _{V N.} This state is referred to as a first state φ1. In the first state φ1, the output switch SW is set so that one data line LD1 is driven by the high side amplifier HAMP and the other data line LD2 is driven by the low side amplifier LAMP. At this time, the share switches SWC1 and SWC2 are all set to OFF. FIG. 2A shows an equivalent circuit of the first state φ1.

φ2. When the gate driver 110 selects j + 1 th scan line LSj + 1, the source driver 100, the data lines LD1 in the second polarity of the driving voltage _{V N,} and drives the data line LD2 in the first polarity of the driving voltage _{V P.} This state is referred to as a second state φ2. In the second state φ2, the output switch SW is set so that the other data line LD2 is driven by the high side amplifier HAMP and the other data line LD1 is driven by the low side amplifier LAMP. At this time, the share switches SWC1 and SWC2 are all set to OFF. FIG. 2C shows an equivalent circuit in the second state φ2.

  The source driver 100 alternately repeats the first state φ1 and the second state φ2 in synchronization with the driving timing of the scanning line LS by the gate driver 110. The following states are inserted in the transition period from the first state φ1 to the second state φ2 and the transition period from the second state φ2 to the first state φ1.

  φ12. At the timing of transition from the first state φ1 to the second state φ2, the source driver 100 is set to the first transition state φ12. In the first transition state φ12, the output switch SW is turned off, and the high side amplifier HAMP and the low side amplifier LAMP are disconnected from the data lines LD1 and LD2. At this time, the share switches SWC1 and SWC2 are all turned on. FIG. 2B shows an equivalent circuit of the first transition state φ12.

  φ21. At the timing of transition from the second state φ2 to the first state φ1, the source driver 100 is set to the second transition state φ21. In the second transition state φ21, the output switch SW is turned off, and the high side amplifier HAMP and the low side amplifier LAMP are disconnected from the data lines LD1 and LD2. At this time, the share switches SWC1 and SWC2 are all turned on. FIG. 2D shows an equivalent circuit of the second transition state φ21. The circuit states of the first transition state φ12 and the second transition state φ21 are the same.

  Thereafter, the state transits to the first state φ1, and the j + 2th scanning line LSj + 2 is driven.

  That is, the source driver 100 sequentially repeats the first state φ1, the first transition state φ12, the second state φ2, and the second transition state φ21 in synchronization with the driving timing of the scanning line LS.

Reference is made to the time chart of FIG. In the first state φ1, the potential V _DRV1 of the data line LD1 rises with time and is set to the target voltage having the first polarity corresponding to the luminance. Further, the potential V _DRV2 of the data line LD2 decreases with time and is set to a target voltage having the second polarity according to the luminance.

In the subsequent first transition state φ12, the share switches SWC1 and SWC2 are turned on, and the data lines LD1 and LD2 are connected to the charge share capacitor C1. As a result, the potentials V _DRV1 and V _DRV2 of the data lines LD1 and LD2 coincide with the intermediate voltage Vc.

In the subsequent second state φ2, the potential V _DRV1 of the data line LD1 decreases with time and is set to a target voltage of the second polarity corresponding to the luminance. Further, the potential V _DRV2 of the data line LD2 rises with time and is set to a target voltage having the first polarity according to the luminance.

In the subsequent second transition state φ21, the share switches SWC1 and SWC2 are turned on, and the data lines LD1 and LD2 are connected to the charge share capacitor C1. As a result, the potentials V _DRV1 and V _DRV2 of the data lines LD1 and LD2 coincide with the intermediate voltage Vc.

  According to the source driver 100 according to the embodiment, the sink current (sink current) of the high side amplifier HAMP flows into the charge share capacitor C1 via the second transistor M2. The source current (discharge current) of the low-side amplifier LAMP is supplied from the charge share capacitor C1 to the data line via the third transistor M3. In other words, the charge supplied to the data line by the high side amplifier HAMP can be collected in the charge share capacitor C1, and the charge can be used as a power source for the low side amplifier LAMP.

  As a result, the current thrown away to the ground each time the polarity of the driving voltage of each data line is switched as in the conventional case can be reduced. The source driver 100 according to the embodiment can reduce power consumption by nearly 50% compared to the conventional one. As power consumption is reduced, circuit heat generation can be greatly reduced.

  In the embodiment, the high side amplifier HAMP operates by receiving the power supply voltage AVDD and the intermediate voltage Vc, and the low side amplifier HAMP operates by receiving the intermediate voltage Vc and the ground voltage VSS. When Vc = AVDD / 2 is set, the operating voltage range of each amplifier is AVDD / 2.

  On the other hand, in the conventional source driver, both the high-side amplifier and the low-side amplifier are operated by applying the power supply voltage AVDD and the ground voltage VSS without providing the charge share capacitor C1. That is, conventionally, the operating voltage range of each amplifier is AVDD. That is, according to the source driver 100 according to the present embodiment, the voltage applied to each amplifier is reduced as compared with the conventional source driver, so that power consumption can be reduced. Further, since the high-side amplifier HAMP and the low-side amplifier LAMP can use a low breakdown voltage process, the circuit area can be reduced.

  Further, by providing the regulator 20 that stabilizes the intermediate voltage Vc, the operations of the high-side amplifier HAMP and the low-side amplifier LAMP can be stabilized.

  Furthermore, by providing the share switch SWC, the potential of the data line LD can be set to the target value of the regulator 20 before transitioning to the voltage corresponding to the luminance. It is desirable that the target value of the regulator 20 matches the voltage corresponding to 0 in luminance.

In addition embodiments, the first 1D / A converter DAC1 is operated at the same voltage range as the high-side amplifier HAMP, the input voltage level thereto, i.e. the amplitude of the luminance data S2 _P, and optimized by the first level shift circuit LVS1 Yes. As a result, the power consumption of the first D / A converter DAC1 can be reduced as compared with the conventional one, and a low withstand voltage process can be used, so that the circuit area can be reduced. The same applies to the second D / A converter DAC2.

  Further, by providing the first diode D1, the potential of the output terminal of the high side amplifier HAMP can be limited to (Vc + Vz) or less. Vz is a Zener voltage of the first diode D1. Similarly, by providing the second diode D2, the potential of the output terminal of the low-side amplifier LAMP can be limited to (Vc−Vz) or more. As a result, at the timing of polarity inversion, the transfer gate constituting the output switch SW, the transistors M1 to M4 in the output stage of the high side amplifier HAMP, the low side amplifier LAMP, the first share switch SWC1, the second share switch SWC2, etc. It is possible to prevent an overvoltage exceeding the breakdown voltage from being applied.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

(First modification)
In the embodiment, the case where the polarity is inverted every time the scanning line LS is switched has been described, but the present invention is not limited to this. FIG. 4 is a diagram illustrating a modification of the liquid crystal panel. The liquid crystal panel of FIG. 4 is a so-called triple gate panel. When such a panel is used, the polarity inversion may be performed for each image frame. Specifically, the first share switch SWC1 and the second share switch SWC2 may be turned on in the blank period τ _BLK . FIG. 5 is an operation waveform diagram when the polarity is inverted for each image frame.
Even when a panel other than the triple gate panel is driven, the polarity may be reversed for each image frame.

  Alternatively, polarity inversion may be performed for each of a plurality of scanning lines.

(Second modification)
In the embodiment, a case has been described in which the potential of the data lines LDi and LDi + 1 is returned to the intermediate voltage Vc by turning on the first share switch SWC1 and the second share switch SWC2. However, the present invention is not limited to this.
For example, instead of controlling the first share switch SWC1 and the second share switch SWC2, the logic circuit 10 determines the values of the luminance data S2 _P and S2 _N as the luminance data S1 from the timing controller 130 for each inversion of polarity. Regardless, the drive voltages V _P and V _N may be set so as to be at or near the intermediate voltage Vc. In this case, the first share switch SWC1 and the second share switch SWC2 can be omitted. Alternatively, in addition to the control of the first share switch SWC1 and the second share switch SWC2, the values of the luminance data S2 _P and S2 _N may be set.

  The second modification is effective even when polarity inversion is performed for each scanning line, but in this case, the processing load increases. From the viewpoint of processing load, the second modification is particularly effective when polarity inversion is performed for each image frame as in the first modification.

  In the embodiment, the case where the common charge share capacitor C1 is provided for the plurality of inverting drive circuits 12 has been described. However, the driver amplifier may be segmented and the charge share capacitor C1 may be provided for each segment. By segmenting, the capacity per charge share capacitor C1 can be reduced and the CR time constant can be reduced, so that the circuit operation can be speeded up.

  A segment may be a unit of several adjacent driver amplifiers. Since the luminance of adjacent pixels is often approximated probabilistically, high speed operation can be expected by segmenting these. Furthermore, this case is advantageous from the viewpoint of circuit layout. Alternatively, the segment may be a unit of pixel color.

  In the embodiment, the case where the charge share capacitor C1 is externally attached to the outside of the source driver 100 has been described, but this may be incorporated in the source driver 100.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments are defined in the claims. Needless to say, many modifications and changes in arrangement are allowed without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10 ... Logic circuit, 12 ... Inversion drive circuit, HAMP ... High side amplifier, LAMP ... Low side amplifier, SW ... Output switch, SWC1 ... 1st share switch, SWC2 ... 2nd share switch, LVS1 ... 1st level shift circuit, LVS2 2nd level shift circuit, DAC1 1st D / A converter, DAC2 2nd D / A converter, D1 1st diode, D2 2nd diode, 20 Regulator, C1 Charge share capacitor, 100 Source driver, DESCRIPTION OF SYMBOLS 102 ... Data input terminal, 104 ... Capacitor terminal, 110 ... Gate driver, 120 ... Liquid crystal panel, 130 ... Timing controller, 200 ... Liquid crystal display, DVDD ... First upper power supply voltage, AVDD ... Second upper power supply voltage, VSS ... Lower Side supply voltage.

Claims (7)

A source driver that inverts and drives a plurality of data lines of a liquid crystal panel,
A first upper power supply line to which a first upper power supply voltage is supplied;
A ground line to which a ground voltage is supplied;
A second power supply line to which a second upper power supply voltage higher than the first upper power supply voltage is supplied;
An intermediate voltage line to which a predetermined intermediate voltage between the second upper power supply voltage and the ground voltage is supplied;
A charge share capacitor connected to the intermediate voltage line;
An upper power supply terminal connected to the first upper power supply line and a lower power supply terminal connected to the ground line, and outputs brightness data indicating a drive voltage to be applied to each of the plurality of data lines. Logic circuit;
A driving circuit provided for each of two adjacent data lines, which receives the luminance data from the logic circuit, and has a first driving voltage having a first polarity corresponding to the luminance data, and the first polarity An inverting drive circuit that generates a second drive voltage of opposite second polarity, and alternately applies the first drive voltage and the second drive voltage to the two data lines at a predetermined period;
With
Each inversion drive circuit
An upper power supply terminal connected to the second power supply line and a lower power supply terminal connected to the intermediate voltage line, and the first drive voltage corresponding to the first analog voltage is output from the output terminal High-side amplifier to
A low-side amplifier having an upper power supply terminal connected to the intermediate voltage line and a lower power supply terminal connected to the ground line, and outputting the second drive voltage according to a second analog voltage from its output terminal When,
An output switch that outputs the first and second drive voltages generated by the high-side amplifier and the low-side amplifier by switching to the two data lines at a predetermined cycle;
A first share switch provided on the data line side from the output switch and between one of the two data lines and the intermediate voltage line;
A second share switch provided on the data line side of the output switch and between the other of the two data lines and the intermediate voltage line;
A first level shift circuit for level-shifting the high-level voltage of the first luminance data indicating the first driving voltage to the second upper power supply voltage and level-shifting the low-level voltage of the first luminance data to the intermediate voltage When,
A second level shift circuit for level-shifting a high level voltage of second luminance data indicating the second drive voltage to the intermediate voltage;
An upper power supply terminal connected to the second power supply line and a lower power supply terminal connected to the intermediate voltage line, and the first luminance data output from the first level shift circuit is the first power data. A first D / A converter for converting to an analog voltage;
An upper power supply terminal connected to the intermediate voltage line and a lower power supply terminal connected to the ground line, and the second luminance data output from the second level shift circuit is used as the second analog voltage. A second D / A converter for converting to
A cathode connected to a connection point between the output terminal of the high-side amplifier and the output switch; a first diode connected to the intermediate voltage line;
A second diode having a cathode connected to the intermediate voltage line and an anode connected to a connection point between the output terminal of the low-side amplifier and the output switch;
A source driver characterized by including: The source driver according to claim 1 , further comprising a voltage source that is provided in common to a plurality of inversion driving circuits and generates the intermediate voltage. The intermediate voltage source driver according to claim 1 or 2, characterized in that the midpoint voltage of the second upper power supply voltage and the ground voltage.   4. The source driver according to claim 1, wherein the first share switch and the second share switch are turned on every inversion of polarity. 5. Said first luminance data and the second luminance data for each polarity reversal, the first, any of claims 1 to 3 in which the second driving voltage, characterized in that it is set to a value to be the intermediate voltage Source driver described in Inversion of the polarity is performed for each image frame, the first share switch and the second share switch according to any one of claims 1 to 5, characterized in that on the blank period of the image frame Source driver. LCD panel,
A source driver according to any of claims 1 to 6 for driving a plurality of data lines of the liquid crystal panel,
A gate driver circuit for driving a plurality of scanning lines of the liquid crystal panel;
A liquid crystal display device comprising:

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