JP5720356B2 - Audio demultiplexer and audio demultiplexing method - Google Patents

Description

  The present invention relates to an audio demultiplexer, an audio demultiplexing method, an audio multiplexer, and an audio multiplexing method. It relates to the plex method.

  Prior to standardization of HDTV, audio multiplexing using the scanning line 525 line method did not use audio clock phase information data. Even in HDTV, there is a reception method that does not use audio clock phase information data. Non-Patent Document 1 describes audio clock phase information data. In the following description, the audio clock phase information data may be referred to as AUCK.

  By attaching the audio clock phase information data to the signal, there is an advantage that the audio asynchronous to the video can be received as it is. Also, the delay time can be made constant by design, and the recovery after a temporary error can be accelerated.

"Audio Data Format of Bit-serial Digital Interface for 1125/60 HDTV Systems BTA S-006C 1.0 Version", [online], July 2009 Association of Radio Industries and Businesses, Internet <URL: http://www.arib.or.jp/english/html/overview/doc/2-BTA_S-006_C1_0.pdf>

  However, a signal with incorrect audio clock phase information data may occur. Non-Patent Document 1 does not assume a signal that violates the standard, so no countermeasure is taken for a signal with incorrect audio clock phase information data. Non-Patent Document 1 does not specify the definition of the jitter of the audio clock phase information data or the alarm detection method for the audio clock phase information data.

  FIG. 10 is a block diagram illustrating an example of a general demultiplexer that performs reading using a clock generated from a video clock. The AUD detection unit 2002 detects an ancillary data flag (ADF) and DID (data ID) from a 10-bit parallel video signal supplied to the input terminal 2001. The AUD detection unit 2002 converts the multiplexed audio data or the like into parallel data, sends the audio data to the memory 2003, and outputs a write pulse to the memory 2003. As a result, the audio data with the reduced and expanded time axis sent in the horizontal blanking is written in the memory 2003.

  A 48 KHz GEN (48 KHz clock generator: 48 KHz clock generation unit) 2005 generates a 48 KHz clock from the video clock. Audio having a relationship where the number of samples of 48 KHz audio in the 5-frame period of the video is 8008 is referred to as audio synchronized with the video. If the number of audio samples to be written and the number of samples to be read are the same in the 5-frame period of the video and read at a timing slightly delayed from the timing of writing, the audio signal is restored to a 48 KHz rate audio signal with the same time axis. . The number of audio samples multiplexed every 1H (one horizontal period) is about 1.4 samples on average, and one or two samples of audio data are multiplexed in the horizontal blanking period. The audio data sent from the memory 2003 to the output terminal 2004 is data having a regular interval of 48 KHz and no jitter. However, since the readout clock of the memory 2003 is generated from the video clock, when the so-called asynchronous audio is multiplexed with the video, the same data is repeated or one sample is missing at the output of the memory 2003.

  Next, a description will be given with reference to FIG. FIG. 11 is an explanatory diagram illustrating an example of a change in the number of samples for each frame. Here, a case where the frequency of one frame of video is 30 / 1.001 = 29.97 Hz will be described. The number of audio samples in a 5-frame period of video is 8008. Accordingly, the number of audio samples for each frame is, for example, 1602, 1601, 1602, 1601, 1602. However, since the reference signal (black burst) supplied to the device does not include information of a 5-frame period, five types of phases can be considered. (Furthermore, if there is a phase of video frame and audio of 48 KHz and jitter of 48 KHz, such a regular arrangement does not necessarily occur.) With regard to the number of samples, when a signal that does not match the phase of such a 5-frame period is switched. The number of buffer samples remaining in the memory 2003 shown in FIG.

  The row numbers shown in FIG. 11 correspond to frame numbers. In the frame numbers 1 to 5, the number of writing and the number of reading are the same, and the state of the 4-sample buffer is not changed. However, the number of buffer samples decreases by switching at frame number 6, frame number 8, frame number 10, and frame number 11, and switching at frame number 14 causes the buffer to be negative at frame number 16. The failure of the buffer occurred later, not just after switching. Immediately after switching, the sound is muted silently, but noise may be generated after returning from mute. It is necessary to detect the switching by some method and manage the buffer every time switching is performed.

  Also, the audio is grouped as 1 group 4ch audio and 8ch audio is sent using 2 groups, but there is no clear information to match the memory phase between groups. Further, it is not obliged that the number of multiplexed samples in all lines is the same in groups 1 and 2. However, in order to transmit surround sound using two groups, it is necessary that the phase between the groups match. Regarding the maintenance of the audio phase between groups, it is described in the item of “2.2 Deliberation progress at the time of revision of version A standard (1996) (3)” on page 27 of Non-Patent Document 1. Seems to remain.

  If the audio clock phase information data can be used, for example, if the two groups are read again at a delay of about 10 microseconds in a half cycle from the 48 KHz in which the audio clock phase information data of group 1 is restored, there is a deviation of about 4 microseconds, for example. Can be aligned at the same timing without causing an error.

  FIG. 12 is a block diagram illustrating an example of a general demultiplexer that uses audio clock phase information data. The same elements as those in FIG. 10 are denoted by the same reference numerals as those in FIG. The H counter 2007 counts a value from 0 to 2199 and outputs the value to an AUCKDET (AUCK Detector). AUCKDET 2006 receives audio clock phase information data in which user data words are 0 (UDW0) and 1 (UDW1) in audio packets sent during the horizontal blanking period of the parallel data of the chroma series of video. The AUCKDET 2006 receives the count value output from the H counter 2007. Although the jitter for one clock of the video is increased, the 48 KHz clock on the multiplex side is faithfully restored. The memory 1003 performs reading with a 48 KHz signal output from the AUCKDET 1006. With this operation, it is possible to handle audio that is asynchronous to the video. That is, 48 KHz and audio data on the multiplexer side that is the transmission side can be faithfully restored on the reception side.

  The demultiplexer using audio clock phase information data described in Non-Patent Document 1 can solve the problem of inter-group phase matching and the problem of handling asynchronous audio. However, when a signal with wrong audio clock phase information data is generated, noise may be generated in the demultiplexer for returning to the AES (Audio Engineering Society) audio. Since the video and audio are asynchronous, noise may occur in the audio. However, noise may occur in the audio because the wrong audio clock phase information data is added to the signal.

  Therefore, an object of the present invention is to provide an audio demultiplexer and an audio demultiplexing method capable of preventing the generation of audio noise even when wrong audio clock phase information data is attached to a signal.

  It is another object of the present invention to provide an audio multiplexer and an audio multiplexing method that prevent the generation of such erroneous audio clock phase information data.

The audio demultiplexer according to the present invention is an audio demultiplexer applied to a receiving system in HDTV, and two samples of audio data multiplexed on a horizontal line of video are multiplexed on the same horizontal line of the video. The audio clock phase information data attached to the second sample is larger than the audio clock phase information data attached to the first sample and is multiplexed one horizontal period before the horizontal line. Determination means for determining whether or not a condition that the audio clock phase information data attached to the first sample in the horizontal line is smaller than the audio clock phase information data of the last sample that has been satisfied, An alarm output means for outputting an alarm when it is determined that the condition is not satisfied; And a clock output means for outputting an audio clock generated from the video when the video is detected.

In addition, the audio demultiplexing method according to the present invention is an audio demultiplexing method applied to a receiving method in HDTV, and a sample which is a unit of audio data multiplexed on a horizontal line of video is the same in the video. When two are multiplexed on the horizontal line, the audio clock phase information data attached to the second sample is larger than the audio clock phase information data attached to the first sample, and 1 of the horizontal line Whether or not the condition that the audio clock phase information data attached to the first sample in the horizontal line is smaller than the audio clock phase information data of the last sample multiplexed before the horizontal period is satisfied. When an alarm is output and an alarm is detected when it is determined that the condition is not met And outputting an audio clock made from the video.

The audio multiplexer according to the present invention is an audio multiplexer applied to a transmission method in HDTV, and audio clock phase information data is added to a sample which is a unit of audio data multiplexed on a horizontal line of video , If the audio clock phase information data of the next sample has increased with respect to the audio clock phase information data of the first sample, the next sample becomes the second sample and is the same as the first sample. If the audio clock phase information data of the next sample is reduced with respect to the audio clock phase information data of the first sample after multiplexing on the horizontal line , the next sample is multiplexed with the first sample. And a multiplexing means for multiplexing the horizontal line next to the horizontal line.

The audio multiplexing method according to the present invention is an audio multiplexing method applied to a transmission system in HDTV, and adds audio clock phase information data to a sample which is a unit of audio data multiplexed on a horizontal line of video. If the audio clock phase information data of the next sample is increased with respect to the audio clock phase information data of the first sample, the next sample is set as the second sample . multiplexed to sample the same horizontal line, with respect to first samples of the audio clock phase information data, if the audio clock phase information data of the next sample is reduced, the next sample, first The sample is multiplexed on the horizontal line next to the multiplexed horizontal line.

  According to the audio demultiplexer and the audio demultiplexing method of the present invention, it is possible to prevent the generation of audio noise even if wrong audio clock phase information data is attached to the signal.

  Further, according to the audio multiplexer and the audio multiplexing method of the present invention, it is possible to prevent the audio clock phase information data from being attached to the signal in error.

It is a block diagram which shows the example of the audio | voice demultiplexer of this invention. It is explanatory drawing which shows the detailed structural example of the audio | voice demultiplexer of this invention. It is explanatory drawing which shows the detailed structural example of the audio | voice demultiplexer of this invention. It is explanatory drawing which shows the detailed structural example of the audio | voice demultiplexer of this invention. FIG. 4 is a signal timing chart of each part of the audio demultiplexer (particularly the part shown in FIGS. 2 and 3). It is a timing chart of a signal when a mistake is mixed. It is a timing chart of the signal of each part of an audio | voice demultiplexer. It is a block diagram which shows the example of the minimum structure of the audio | voice demultiplexer of this invention. It is a block diagram which shows the example of the minimum structure of the audio | voice multiplexer of this invention. It is a block diagram which shows the example of the general demultiplexer which reads with the clock produced from the clock of the image | video. It is explanatory drawing which shows the example of a change of the sample number for every flame | frame. It is a block diagram which shows the example of the general demultiplexer which uses audio | voice clock phase information data.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The present invention is applied to HDTV (High Definition Television). In the present embodiment, the number of clocks in one horizontal period (denoted as 1H) of video is 2200, and audio data of about 1.4 samples per 1H is multiplexed on average from the relationship with the audio sampling frequency of 48 kHz. It will be. Therefore, there are a time when 1 sample is multiplexed per 1 H and a time when 2 samples are multiplexed. In the present invention, the audio clock phase information data when the second sample is multiplexed is increased with respect to the audio clock phase information data of the first sample, and the audio clock phase information is exceeded when one horizontal period is crossed. Does not output an alarm when it detects that data is decreasing.

That is, when two samples are multiplexed on the same line, the audio clock phase information data attached to the second sample is larger than the audio clock phase information data attached to the first sample, and The condition that the audio clock phase information data of the first sample multiplexed on the line of interest is smaller than the audio clock phase information data of the last sample multiplexed 1H before the line of interest When it is detected that is not satisfied, an alarm for audio clock phase information data is output.

  Furthermore, the present invention includes a circuit (selector 303 in FIG. 4 described later) that outputs an alternative audio clock when an output alarm is detected.

  The number of clocks in one horizontal period (1H) of the video is 2200, and one cycle of 48 KHz corresponds to the 1545 clock period of the video. Therefore, when crossing 1H, the data is reduced by about 655. However, in Jpn. Pat. Appln. KOKAI Publication No. 2004-0897, the jitter standard is not specified, so it is not appropriate to use the exact jitter value for the judgment of the alarm output. Therefore, in the present invention, whether to output an alarm is determined by paying attention to the increase / decrease in the audio clock phase information data.

  FIG. 1 is a block diagram showing an example of an audio demultiplexer according to the present invention. An audio demultiplexer according to the present invention includes an input terminal 1001, an AUD detection unit 1002, a memory 1003, an output terminal 1004, a 48KHz GEN (48KHz clock generator: 48KHz clock generation unit) 1005, and an AUCKDET (AUCK Detector: AUCK detection unit). ) 1006, H counter 1007, AUCKALM (AUCK Alarm output unit: AUCK alarm output unit) 1008, SEL (Selector) 1009, and alarm output terminal 1010.

  The input terminal 1001, AUD detection unit 1002, memory 1003, and output terminal 1004 are the same as the input terminal 2001, AUD detection unit 2002, memory 2003, and output terminal 2004 shown in FIGS. The 48 KHz GEN 1005 is the same as the 48 KHz GEN 2005 shown in FIG. Further, the AUCKDET 1006 and the H counter 1007 are the same as the AUCKDET 2006 and the H counter 2007 shown in FIG.

The AUCKALM 1008 is a circuit that detects the presence or absence of an error in the audio clock phase information data, and outputs an alarm to the alarm output terminal 1010 and the selector 1009 when an error is detected. That is, the AUCCALM 1008 monitors whether or not the above condition is satisfied, and outputs an alarm to the alarm output terminal 1010 and the selector 1009 when detecting that the condition is not satisfied.

  The selector 1009 selects either the 48 KHz clock generated based on the AUCK (audio clock phase information data) from the AUCKDET 1006 or the clock received from the 48 KHz GEN 1005 that generates a 48 KHz clock from the video clock by the control from the AUCKALM 1008. Output to the memory 1003. When there is an error in the audio clock phase information data (that is, when an alarm is detected), the selector 1009 switches to 48 KHz created from the video and outputs it.

  2, 3 and 4 are explanatory diagrams showing detailed configuration examples of the audio demultiplexer according to the present invention. The wirings denoted by reference signs A to H in FIG. 2 correspond to the wirings denoted by reference signs A to H in FIG. Similarly, the wirings denoted by reference signs I to R in FIG. 3 correspond to the wirings denoted by reference signs I to R in FIG.

  A video signal (10 bits of a series of color signal components) is supplied from the input terminal 1 to the shift register including the latches 10 to 28 illustrated in FIG. This shift register operates with a clock of about 74.176 MHz (74.25 MHz / 1.001).

  The audio demultiplexer is provided with a clock input terminal 2.

  The decoder 35 detects the ancillary data flag (ADF) and the data ID (DID), and when the user data words 0 to 17 (UDW0 to 17) of the voice packet are prepared, the timing pulse sending latch 29 (hereinafter simply latched). 29.)

  In the example shown in FIG. 2, latches 31 to 34 are provided on the input terminal 1 side of the decoder 35. Further, a parallel latch pulse generator 36 is provided between the decoder 35 and the latch 29. A latch 45 and a counter 42 are provided on the output side of the parallel latch pulse generator 36 (see FIG. 2).

  From the latch 29, 4ch of audio data, V, U, C, P, and Z bits defined in Non-Patent Document 1 and audio clock phase information data (total 13 bits) are output at the same timing. Is done. Audio data and the like are sent to the memory 41. In the example shown in FIG. 2, a latch 103 is provided between the memory 41 and the output terminal 3.

  The counter 42 counts memory write addresses. The output of the counter 42 changes as illustrated in FIG.

  The TRS decoder 55 (see FIG. 3) receives the signals of the latches 51 to 54, and outputs an EAV timing pulse and an SAV timing pulse indicating the end of the video and the start of the video. In the following description, the EAV timing pulse may be simply referred to as EAV, and the SAV timing pulse may be simply referred to as SAV. The counter 61 is reset at the EAV timing and counts how many samples (0, 1, 2) the voice packet is until the SAV. The counter 61 outputs an additional pulse to the latches 71 and 72 twice at the SAV timing when the voice packet is 0 sample and once when it is 1 sample. The counter 61 adds 4095, which is an invalid value as audio clock phase data (corresponding to CK0 to CK11), to the second sample when the audio packet has only one sample. CK is defined in Non-Patent Document 1.

  A decoder 62 is provided on the output side of the counter 61 (see FIG. 3). The decoder 62 receives the output of the counter 61, decodes it, and outputs a signal. Specifically, the decoder 62 outputs a logic “1” when “0” is input, and outputs a logic “1” when “1” is input. An OR gate 63 is provided on the output side of the decoder 62. Further, latches 67 and 68 are provided on the output side of the TRS decoder 55. Further, AND gates 64 and 65 and an OR gate 66 are provided on the output side of the OR gate 63 and the TRS decoder 55, as shown in FIG.

  A selector 70 is provided on the output side of the OR gate 66. The selector 70 is a 2-bit selector. When S is “0”, the input A0 is output to Y0, and the input A1 is output to Y1. When S is “1”, the input B0 is output to Y0, and the input B1 is output to Y1.

  The OR gate 69 outputs two pulses per 1H. Here, for the sake of simplicity, it is assumed that the latches 217 and 218 are not provided, and the input side and the output side of the latch 217 shown in FIG. 3 are simply connected. It is assumed that the side is simply connected. The latches 73 and 74 serve as simultaneous timing information for two samples. The output of the latch 73 is sent first, and is rearranged as the second information in the latch 74. Further, in addition to the audio clock phase information data (CK0 to CK11 and CK12), the address information obtained by subtracting 1 (0 is 7) from the address written in the memory 41 passes through the latches 73 and 74 as a pair. The address written in the memory 41 is associated with the audio clock phase information data at that time. By using this write address as a read address, the memory 41 is operated like a simple latch. The audio demultiplexer shown in FIGS. 2 to 4 is configured to realize two types of operations: a mode using audio clock phase information data and a mode of reading at 48 KHz generated from a video clock.

  Further, there is a method in which data such as sound from the latch 29 is passed through the latches 71 to 76 without using the memory 41 and a selector corresponding to the load data selector 77 is provided and latched according to the output of the OR gate 91. When this method is applied, the WADR subtraction unit 44 (see FIG. 2) or the like is not necessary.

  Multiplexing of audio packets or the like is prohibited on a specific line of video. As information indicating that the signal is transmitted with a delay of 1H, there is CK12 (multiple position identification flag) of the audio clock phase information data, which also passes through the latches 73 and 74. The latch enable pulses of the latches 73 and 74 are generated once every 1H. The outputs of the latches 75 and 76 are delayed by exactly 1H with respect to the latches 73 and 74. When CK12 is “0”, it is output from the AND gates 85 and 86, and when CK12 is “1”, it is output from the AND gates 86 and 87. In the example shown in FIG. 3, an inverter 89 is provided on the input side of the AND gate 85, and an inverter 90 is provided on the input side of the AND gate 86.

  When the audio clock phase information data (CK0 to 11 or invalid data 4095) from the latches 73 to 76 coincides with the output of the H counter 78 that counts 0 to 2199, the comparison circuits 81 to 84 are “1”. Is output. When invalid data 4095 is input, “1” is not output because there is no coincidence.

  From the OR gate 91, the restored 48 KHz clock is output. On the other hand, the load data selector 77 selects and outputs the address information obtained by subtracting 1 from the address written in the memory and the pulses output from the AND gates 85 to 88. The outputs of the AND gates 85 to 88 do not simultaneously become “1”. For example, when the AND gate 85 is “1”, the load data selector 77 outputs the address information from the latch 75. As described above, the load data selector 77 selects and outputs four inputs. The counter control pulse selector 100 is a two-circuit 2: 1 selector. Here, it is assumed that the audio clock phase information data is used, and therefore, the counter control pulse selector 100 outputs the input “0” side.

  When the counter 43 (see FIG. 2) receives the restored 48 KHz clock from the OR gate 91, the output of the load data selector 77 is used as the output of the counter 43. That is, the counter 43 does not count as a counter. Note that an OR gate 101 is provided on the output side of the counter 43.

  If bi-phase modulation or the like is performed on the output signals of the output terminal 3 and the output terminal 4, it can be converted into AES / EBU (European Broadcasting Union) digital audio. The jitter standard of AES / EBU digital audio is ± 20 ns or less. In addition to the jitter of the original AES / EBU digital audio, at least jitter of a video clock increment is added. Therefore, the jitter is reduced by the PLL 102. The configuration described so far is the same as the configuration used in a general audio demultiplexer.

  Signals at various parts of the audio demultiplexer (here, particularly the parts shown in FIGS. 2 and 3) will be described. FIG. 5 is a signal timing chart of each part of the audio demultiplexer (particularly the part shown in FIGS. 2 and 3). (A)-(r) shown in FIG. 5 shows the signal of the location shown with the same code | symbol ((a)-(r)) in FIG. 2 and FIG. For example, (a) shown in FIG. 5 is a WADR signal of the memory 41 shown in FIG. In FIG. 5, the description on the right side of each symbol (a) to (r) is merely a comment and does not represent a signal name.

  In the example shown in FIG. 5 (k), invalid data 4095 used when 2 samples per 1H do not come is added to organize 2 samples per 1H. Since the audio cannot be multiplexed after the video start timing, the data of 2 samples changing every 1H are rearranged at the same time.

  In the example shown in FIG. 5C, a 1H gap is formed between “890” and “235”.

  The signal shown in FIG. 5 (s) is a virtual signal not shown in FIG. 2 or FIG. The signal shown in FIG. 5 (s) is a collection of audio clock phase data to be finally used.

  FIG. 5 (p) shows the information of the H counter, and shows that it is counting up from 0 to 2199 in a sawtooth shape.

  The signal shown in FIG. 5 (r) designates the read address of the memory 41. Therefore, in the example of the address “7”, the delay time from writing to the memory 41 to reading is approximately a value obtained by adding the time difference between EAV and SAV, the 1H period of video, and one cycle of 48 KHz. At the address “0”, the value is obtained by adding the time difference between EAV and SAV and one cycle of 48 KHz. The WADR subtraction unit 44 (see FIG. 2) adds one period (ie, about 20.8 microseconds) at 48 KHz. The 1H delay time differs depending on CK12 (multiple position identification flag). Thus, the delay time is constant.

  FIG. 6 is a signal timing chart of each part of the audio demultiplexer (particularly, the part shown in FIGS. 2 and 3). The meaning of each symbol such as (a) shown in FIG. 6 is the same as the meaning of each symbol shown in FIG. There are several advantages to using audio clock phase information data. On the other hand, there are devices that do not conform to the standard defined in Non-Patent Document 1, and there are cases where there are fewer problems if audio clock phase information data is not used. The timing chart shown in FIG. 6 illustrates a case where an error is mixed. In FIG. 6, the multiple line error when the signal shown in FIG. 6C is “0” and the multiple position identification flag when the signal shown in FIG. 6C is “2017” (see FIG. 6B). ) Shows the behavior of each part in case of forgetting to add. In the example shown in FIG. 6, as a result of such an error being mixed, the restored 48 KHz is not a normal equally-spaced clock (see FIG. 6 (q)), and the load data order is 1, 2, 4, 3 (See FIG. 6 (r)).

  The present invention has a function of outputting an alarm when there is an error in the audio clock phase information data. In the present invention, since the alarm detection may be delayed, the latch 217 and the latch 218 (see FIG. 3) are delayed by 1H. In the following description, it is assumed that the latches 217 and 218 shown in FIG. 3 are provided.

  The selectors 201 and 203 output the audio clock phase information data (CK0 to CK11) from the latches 75 and 76 when the CK12 of 1H past is “0”. On the other hand, when 1H past CK12 is “1”, invalid data 4095 is output. The selectors 201 and 203 replace the second sample with the output of the first sample when only the CK12 of the first sample is “1”. The selectors 202 and 204 interrupt and output the audio clock phase information data (CK0 to CK11) from the latches 217 and 218 when CK12 is “1” at the same time. Further, when only the first sample CK12 is "1", the selectors 202 and 204 output the first sample input to the first sample or the second sample depending on the result of the comparison circuit 216. The outputs of the selector 202 and the selector 204 are obtained by restoring the original signal after the processing of the CK12 which is no longer affected by the multiple prohibition line.

  FIG. 7 is a timing chart of signals at various parts of the audio demultiplexer. Reference numerals (t) to (z) and (ac), (p), (q), (aa), and (ab) shown in FIG. 7 are denoted by the same reference numerals in FIG. 2, FIG. 3, and FIG. The signal at the specified location The code (s) is the same as the code (s) shown in FIG.

  The alarm is output from the OR gate 215 via the latch 220 and the OR gate 219 with the error time extended by 1H.

  The magnitude comparison circuit 207 outputs “1” when the second sample is smaller than the first sample. The comparison circuit 210 outputs “1” when the first sample is an invalid value 4095. The comparison circuit 211 outputs “1” when the second sample in the past 1H is an invalid value 4095, and indicates whether the last sample before 1H is the second sample or the first sample. The output of the magnitude comparison circuit 208 and the subsequent AND gate 213 becomes “1” when the output is larger than the first sample in the past 1H. The output of the AND gate 214 following the magnitude comparison circuit 209 is “1” when it is larger than the second sample in the past 1H. That is, in other words, it is normal that the second sample on the same line is large and that it decreases when crossing 1H.

  In the example shown in FIG. 4, a latch 205 is provided on the input side of the magnitude comparison circuit 208, and a latch 206 is provided on the input side of the magnitude comparison circuit 209. An inverter 212 is provided on the output side of the comparison circuit 211.

  The output of the OR gate 219 is sent to the alarm output terminal 5 and the counter control pulse selector 100. An alternative 48 kHz clock is supplied to the counter control pulse selector 100. When there is an error in the audio clock phase information data, the counter control pulse selector 100 stops the load pulse of the counter 43 and outputs an alternative 48 KHz clock as a count enable pulse. When an alarm relating to the audio clock phase information data is output, the counter 43 (see FIG. 2) receives the enable pulse and counts up.

  The alternative 48 KHz clock is realized by two counters 301 and 304. The counter 301 repeatedly counts in the range of 0 to 1544 (1545 cycles) and 0 to 1545 (1546 cycles). The counter 304 receives a reset pulse from the selector 303 and counts from 0 to 90 (91 periods). The decoder 306 outputs “1” to the selector 303 when the count value of the counter 304 is divisible by 3 (for example, 3, 6, 9,... 90). The cycle of the counter 304 is (1545 × 91 + 30 = 140625) clock.

  The relationship is ((74.25 MHz / 1.001) / (140625)) × 91 = 48 KHz, and the output of the selector 303 has a jitter of 1 clock, but the average is 48 KHz.

  A decoder 305 is provided on the output side of the counter 304. The decoder 305 outputs “1” when the input is “90”. A decoder 302 is provided on the output side of the counter 301. The decoder 302 has an output terminal that outputs “1” when the input is “1544”, and an output terminal that outputs “1” when the input is “1545”.

  The OR gates 307 and 308 are supplied with a reset signal from the counter control pulse selector 100 when no alarm is issued. Note that an AND gate 309 is provided on the input side of the OR gate 307.

  Also, if the number of multiplexed samples is determined while monitoring the increase / decrease between the audio samples on the audio multiplexer side, it is possible to avoid making an error from the beginning. Using this simple increase / decrease rule, audio clock phase information data is created every 48 KHz of audio data, and if it is increased from the previous sample, it is the second sample data, If it is reduced, it can be multiplexed without mistake if it is multiplexed to the next line. Audio clock phase information data that is paired for each audio data is created, and if it has increased with respect to the previous sample, it is the data of the second sample, and if it has decreased with respect to the previous sample, the next It can be simplified if it is multiplexed on the line.

  Next, the minimum configuration of the present invention will be described. FIG. 8 is a block diagram showing an example of the minimum configuration of the audio demultiplexer according to the present invention. The audio demultiplexer 500 according to the present invention includes a determination unit 501, an alarm output unit 502, and a clock output unit 503.

  When two audio samples are multiplexed on the same line, the determination unit 501 uses the audio clock phase information data attached to the first sample to the audio clock phase information data attached to the second sample. And the audio clock phase information data attached to the first sample in the line is smaller than the audio clock phase information data of the last sample multiplexed one horizontal period before the line. It is determined whether or not is satisfied.

The alarm output means 502 outputs an alarm when it is determined that the condition is not satisfied. When the alarm is detected, the clock output means 503 outputs a clock generated from the video.

  With such a configuration, even if wrong audio clock phase information data is attached to the signal, the occurrence of audio noise can be prevented.

  FIG. 9 is a block diagram showing an example of the minimum configuration of the audio multiplexer of the present invention. The audio multiplexer 550 of the present invention adds the audio clock phase information data to the audio sample, and the audio clock phase information data of the next sample increases with respect to the audio clock phase information data of the first sample. If so, the next sample is multiplexed as the second sample, and if the audio clock phase information data of the next sample is reduced with respect to the audio clock phase information data of the first sample, Multiplexing means 551 for multiplexing the sample to the next line is provided.

  Such a configuration can prevent wrong audio clock phase information data from being attached to the signal.

  The present invention is suitably applied to HDTV.

DESCRIPTION OF SYMBOLS 1 Input terminal 2 Clock input terminal 3 Output terminal 5 Alarm output terminal 10-28 Latch 29 Latch 31-34 Latch 35 Decoder 36 Parallel latch pulse generation part 41 Memory 42-43 Counter 44 WADR subtraction part 51-54 Latch 55 TRS decoder 61 Counter 62 Decoder 63 OR gate 64-65 AND gate 66 OR gate 67-68 Latch 69 OR gate 70 Selector 71-76 Latch 77 Load data selector 78 H counter 81-84 Comparison circuit 85-88 AND gate 89-90 Inverter 91 OR Gate 100 Counter control pulse selector 101 OR gate 102 PLL clock regeneration 103 Latch 201-204 Selector 205-206 Latch 207-209 Size comparison 210 to 211: comparison circuit 212 inverter 213 to 214 AND gate 215 OR gate 216 comparison circuit 217 to 218 latch 219 OR gate 220 latch 301 counter 302 decoder 303 selector 304 counter 307 to 308 OR gate 309 AND gate 1001 input terminal 1002 AUD detection Unit 1003 memory 1004 output terminal 1005 48 kHz clock generation unit 1006 AUCK detection unit 1007 H counter 1008 AUCK alarm output unit 1009 selector 1010 alarm output terminal

Claims (4)

An audio demultiplexer applied to a receiving method in HDTV,
When two samples, which are units of audio data multiplexed on the horizontal line of the video, are multiplexed on the same horizontal line of the video, the audio clock phase information data attached to the second sample is the first sample. Compared to the audio clock phase information data of the last sample which is larger than the audio clock phase information data attached to the horizontal line and multiplexed one horizontal period before the horizontal line, the first sample in the horizontal line Determination means for determining whether or not a condition that the attached audio clock phase information data is small is satisfied;
An alarm output means for outputting an alarm when it is determined that the condition is not satisfied;
Upon detecting the alarm, voice demultiplexer characterized in that it comprises a clock output means for outputting the audio clock made from the video. An audio demultiplexing method applied to a receiving method in HDTV,
When two samples, which are units of audio data multiplexed on the horizontal line of the video, are multiplexed on the same horizontal line of the video, the audio clock phase information data attached to the second sample is the first sample. Compared to the audio clock phase information data of the last sample which is larger than the audio clock phase information data attached to the horizontal line and multiplexed one horizontal period before the horizontal line, the first sample in the horizontal line Determine whether the condition that the attached audio clock phase information data is small is satisfied,
When it is determined that the above conditions are not satisfied, an alarm is output,
An audio demultiplexing method, comprising: outputting an audio clock generated from the video when the alarm is detected. An audio multiplexer applied to a transmission method in HDTV,
Audio clock phase information data is added to a sample, which is a unit of audio data multiplexed on a horizontal line of video, and the audio clock phase information of the next sample is added to the audio clock phase information data of the first sample. If the data has increased, the next sample is multiplexed as the second sample on the same horizontal line as the first sample, and the audio clock phase information data of the first sample is If the audio clock phase information data of the second sample is reduced, a multiplexing means for multiplexing the next sample on the horizontal line next to the horizontal line on which the first sample is multiplexed is provided. Audio multiplexer. An audio multiplexing method applied to a transmission method in HDTV,
Audio clock phase information data is added to a sample, which is a unit of audio data multiplexed on a horizontal line of video, and the audio clock phase information of the next sample is added to the audio clock phase information data of the first sample. If the data has increased, the next sample is multiplexed as the second sample on the same horizontal line as the first sample, and the audio clock phase information data of the first sample is If the audio clock phase information data of the first sample is reduced, the next sample is multiplexed on the horizontal line next to the horizontal line on which the first sample is multiplexed .

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