JP2007129458A - Audio data processing circuit, and electronic apparatus mounting it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress synchronization shift of a video image and sound regardless of inserting method on the transmission side when such a data as audio data is inserted into the blanking section of video data is received and processed. <P>SOLUTION: In the audio data processing circuit, an audio data buffer 52 holds separated audio data temporarily. A format conversion circuit 54 converts the audio data thus held into other format. A plurality of first subbuffer 521b through n-th subbuffer 52nb hold a plurality of packets describing the separated audio data for every packet. A plurality of first flag 521f through n-th flag 52nf indicate whether input to a corresponding subbuffer is permitted. A load address control circuit 530 specifies a subbuffer for inputting a delivered packet. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an audio data processing circuit that receives data in which audio data is inserted in a blanking interval of video data and processes the audio data, and an electronic device equipped with the audio data processing circuit.

  HDMI (High-Definition Multimedia Interface) has backward compatibility with DVI (Digital Visual Interface), and has become widespread as a digital interface between video equipment such as DVD players and set-top boxes and displays such as televisions. HDMI transfers 4-channel serial data using the physical layer of DVI. Of the four channels, one channel is assigned to each of the three RGB colors, and the remaining one channel is assigned to the clock. HDMI inserts a data island for transmitting audio data and various control information into a video blanking section. As a result, high-quality audiovisual data can be transmitted, including HDTV (High Definition TeleVision). Up to 8 channels of audio can be played back.

In HDMI transmission or DVI transmission, when transmitting audio information as quantized digital information, an audio clock is not transmitted, and ratio information with a transmitted video clock can be transmitted to the receiving side (for example, , See Patent Document 1).
Japanese Patent Laying-Open No. 2005-065093

  Various control information other than audio data is inserted in the video blanking interval, but the transmitting side inserts audio data and control information in a free format in each video blanking interval. For example, not only audio data and control information are inserted into a video blanking interval at a fixed ratio, but also audio data is inserted up to the maximum number of packets specified in one video blanking interval, and the next video blanking interval is inserted into the next video blanking interval. Processing such as inserting almost no audio data is also possible.

  On the receiving side, the audio and video may be out of synchronization depending on how the audio data is inserted into the video blanking interval.

  The present invention has been made in view of such a situation, and the purpose of the present invention is to receive and process data in which audio data is inserted into a blanking interval of video data regardless of the insertion method on the transmission side. An audio data processing circuit capable of suppressing a synchronization error between the sound and the sound and an electronic device equipped with the same.

  In order to solve the above problems, an audio data processing circuit according to an aspect of the present invention is an audio data processing circuit that receives data in which audio data is inserted in a blanking interval of video data and processes the audio data. And an audio data buffer that temporarily holds the audio data separated from the received data, and a format conversion unit that converts the held audio data into another format. The audio data buffer is provided in each of a plurality of sub-buffers and a plurality of sub-buffers for holding a plurality of packets describing audio data separated from each blanking interval for each packet, and corresponding to each of the sub-buffers. A plurality of flags for indicating whether or not input to the sub-buffer is permitted, a load address control circuit for designating a sub-buffer to which a packet to be transferred is input with reference to the flag, and a flag An unload address control circuit for designating a sub-buffer to which the held packet is to be output to the format conversion unit. The unload address control circuit outputs a packet from the sub-buffer in response to a signal permitting input from the format conversion unit. The “load address control circuit” may specify a buffer whose flag is inactive. The “unload address control circuit” may specify a buffer whose flag is active.

  According to this aspect, a buffer capable of holding a plurality of packets is provided, and the speed of audio data input to the format conversion unit can be adjusted, so that the transmission side can be inserted into each blanking interval. Regardless, it is possible to suppress the synchronization error between video and audio. Further, by providing a flag for each sub-buffer, it is possible to prevent the input process to the buffer and the output process from the buffer from occurring at the same opportunity.

  The separation unit that separates audio data from the received data, the audio data buffer, and the format conversion unit may be controlled by a video clock that processes the video data. Thereby, pipeline processing and real-time processing of audio data can be realized.

  For a plurality of packets describing the separated audio data, an error check unit that checks a code error of the audio data included in the packet using an error check code included in each packet may be further provided. The error checker may be controlled by the video clock and output the checked packet to the audio data buffer. By controlling the error checker with the video clock, it is possible to realize pipeline processing and real-time processing of audio data.

  The audio data that has been subjected to format conversion is read from the format conversion unit by controlling the video clock, and the stored audio data is output by controlling the conversion data holding register that temporarily holds the audio data and the audio clock having a frequency lower than the video clock. A conversion data output register. The format conversion unit receives a signal that permits input from the conversion data holding register, and then outputs the audio data to be held to the conversion data holding register. The conversion data holding register receives a signal that permits input from the conversion data output register. After the reception, the held audio data may be output to the conversion data output register. As a result, audio data can be accurately transferred from the video clock domain to the audio data clock domain.

  The audio data buffer may further include a load address counter that supplies an address to be specified to the load address control circuit, and an unload address count that supplies an address to be specified to the unload address control circuit. When the unload address counter receives a signal prohibiting input from the format conversion unit, the counter may stop counting. Thereby, audio data can be accurately transferred from the audio data buffer to the format conversion unit.

  Another embodiment of the present invention is an electronic device. The electronic apparatus includes an audio data processing circuit and a speaker that outputs audio data reproduced by the audio data processing circuit.

  According to this aspect, it is possible to adjust the speed of the audio data input to the format conversion unit, and to suppress the synchronization deviation between video and audio regardless of the insertion method in each blanking section on the transmission side. Can do.

  It should be noted that any combination of the above-described constituent elements and a representation obtained by converting the expression of the present invention between apparatuses, methods, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, when receiving and processing data in which audio data is inserted into a blanking interval of video data, it is possible to suppress a synchronization error between video and audio regardless of the insertion method on the transmission side. .

  FIG. 1 is a block diagram illustrating a configuration of a data reproduction circuit including an audio data processing circuit according to an embodiment of the present invention. The data reproduction circuit 100 in this embodiment is a circuit that receives and reproduces data transmitted in accordance with the HDMI standard from a device such as a DVD player. Installed in TVs. Like DVI, HDMI has a total of four channels, corresponding to the three primary colors, R channel, G channel, B channel, and CLK channel corresponding to the system clock. Audio data and control signals are inserted into blanking intervals of the R channel, G channel, and B channel.

  The data reproduction circuit 100 includes a serial data reproduction circuit 10, a TMDS (Transition Minimized Differential Signaling) decoder 20, an A / V separation circuit 30, an error detection circuit 40, an audio data processing circuit 50, and a panel interface 60. These may be integrated on a single semiconductor substrate. The CLK channel is input to a video PLL circuit (not shown), and the PLL circuit supplies a clock to each of the circuits 10 to 60 described above.

  The serial data reproduction circuit 10 corrects the jitter and skew of the serial data of the R channel, G channel, and B channel, synchronizes them, and supplies them to the TMDS decoder 20 at the next stage. The TMDS decoder 20 decodes the TMDS encoded signal and supplies a 3-channel video signal to the A / V separation circuit 30 together with the horizontal and vertical synchronization signals. The A / V separation circuit 30 extracts an audio signal and a control signal for each channel from the blanking interval of the supplied video signal. The A / V separation circuit 30 supplies the video signal from which the audio signal and the control signal have been removed to the panel interface 60, and supplies the audio signal and the control signal to the error detection circuit 40.

  The panel interface 60 changes the supplied video signal to a display panel signal and outputs it to the display unit 120 described later. For example, the RGB format is converted to the YUV format.

  The error detection circuit 40 includes a BCH (Bose-Chaudhuri Hocquenghem Code) error detection circuit 42 and an ECC (Error Correcting Code) correction circuit 44. The BCH code in the HDMI standard is a code word system in which the distance between code words is less than 2. A 1-bit error can be corrected for a 64-bit codeword. On the other hand, an error of 2 bits or more can be detected but cannot be corrected. The BCH error detection circuit 42 generates a BCH remainder (hereinafter referred to as “syndrome”) for each channel, thereby determining whether or not the reception is successful. When the syndrome is zero, it can be determined that the reception was successful. In the case of a 1-bit error with reference to the syndrome, the ECC correction circuit 44 specifies the error position and corrects the error.

  The audio data processing circuit 50 converts the audio data contained in the HDMI island packet extracted from the horizontal or vertical blanking interval of the TMDS channel into another format. For example, it is converted into an S / PDIF (Sony Philips Digital Interface) format, an I2S (Inter-IC Sound) format, or the like. These converted data are output to the speaker 110 described later.

Hereinafter, details of the audio data processing circuit 50 will be described based on an example of converting audio data described in the HDMI island packet into the S / PDIF format.
FIG. 2 is a diagram showing an HDMI island packet inserted in the horizontal synchronization or vertical synchronization blanking interval of the TMDS channel. Audio data and packet header information are encoded into data islands in the horizontal synchronization or vertical synchronization blanking interval of the TMDS channel. A maximum of 18 packets can be inserted into the synchronous blanking interval.

  In FIG. 2, the preamble and guard band in the synchronous blanking interval are omitted. Of the three TMDS channels, a packet header is described in one channel, and data is described in the remaining two channels as a packet body (denoted as Packet data in the figure). Each packet header is composed of 32 bits, that is, 4 bytes, of which 1 byte is used as a parity code. The packet header describes a packet type indicating what data is described in the packet body. There are various types of packet types, such as a frame type when the packet body describes target data, NULL, and ACR (Audio Clock Regeneration). Each packet body is composed of 64 bits or 8 bytes.

  FIG. 3 is a diagram illustrating a configuration of the packet body. The subpacket + BCH code is composed of 8 bytes, of which 7 bytes constitute data, and 1 byte constitutes a BCH code. A subpacket represents one audio sample frame with 56 bits and no preamble. The subpacket + BCH code is divided into odd bits and even bits and assigned to packet bodies of different channels. Since each packet body is composed of 8 bytes, four odd or even bits of the subpacket + BCH code can be described. As described above, one audio sample frame is divided into odd bits and even bits and transmitted through two channels, whereby transmission of the header and body constituting one packet is started at the same time and transmission is ended at the same time. be able to.

  FIG. 4 is a diagram showing a block configuration of the S / PDIF signal. In S / PDIF, 192-bit channel status information and 384 user bits are distributed and transmitted in audio sample words. Therefore, one block is composed of 192 consecutive frames. In normal stereo transmission, a frame is composed of two subframes. Each subframe is composed of a preamble and a sample word. Each subframe consists of 32 bits, of which 4 bits are assigned to the preamble and 28 bits are assigned to the sample word. A subframe is composed of a preamble and sample words. Each subframe consists of 32 bits, of which 4 bits are assigned to the preamble and 28 bits are assigned to the sample word.

  Audio sample words are encoded by biphase mark modulation. There are three types of preambles as synchronization patterns: B preamble, W preamble, and M preamble. The synchronization pattern is a special pattern that can be distinguished from a sample word subjected to biphase mark modulation, and can uniquely identify each subframe.

  FIG. 5 is a block diagram showing the configuration of the audio data processing circuit. The audio data processing circuit 50 includes an audio data buffer 52, a format conversion circuit 54, a conversion data holding register 56, a conversion data output register 58, and a conversion data output counter 59. Among these, the audio data buffer 52 to the conversion data output register 58 are in the video clock VCLK domain, and the conversion data output register 58 and the conversion data output counter 59 are in the audio clock ACLK domain. In this embodiment, the video clock VCLK domain is controlled at 20 MHz or higher, and the audio clock ACLK domain is controlled at 200 kHz or lower.

  The audio data buffer 52 includes a first sub-buffer 521b to an n-th sub-buffer 52nb, a first flag 521f to an n-th flag 52nf, a load address control circuit 530, a load address counter 532, an unload address control circuit 534, and an unload address counter. 536 and a selector 538. A video clock VCLK is supplied to each of these elements including the error detection circuit 40 in the preceding stage, and pipeline processing is performed.

  Each of the plurality of sub-buffers 521 to nb has a capacity capable of storing data for one packet described above. As described above, since a maximum of 18 packets can be inserted in one synchronous blanking interval, 18 sub-buffers may be provided. However, since the audio data buffer 52 functions as a first-in first-out (FIFO), the previously input audio data is sequentially output, and an empty sub-buffer is generated. Since the input audio data can be stored there, the number of sub-buffers can be less than 18. The minimum number of sub-buffers can be determined within a range that does not overflow by experiment or simulation. For example, about 12 may be used.

  In the present embodiment, audio data is input from the error detection circuit 40 through nine buses. This bus branches to the same number as the set number of the sub-buffers, and is connected to the input side of the first sub-buffer 521b to the n-th sub-buffer 52nb through nine buses. The output side of each sub-buffer is connected to the selector 538 by nine buses. In this embodiment, an example in which nine buses are provided for each route will be described. However, each route may be configured by one, 32, 288, or the like.

  As described above, a header and a body constituting one data island, that is, one packet, is composed of 32 + 128 × 2 = 288 bits. When transferring 288 bits by the pipeline method, it can be transferred by the following method. (A) 288-cycle 1-bit transfer, (b) 32-cycle 9-bit transfer, (c) 9-cycle 32-bit transfer, (d) 1-cycle 288-bit transfer, and the like can be employed. Which method is adopted can be determined in consideration of a trade-off relationship between processing time and hardware cost such as the number of registers. If (a) is adopted, the lowest cost can be realized, and if (d) is adopted, the highest speed can be realized.

  Each element on the pipeline has a desirable processing cycle and bit width depending on the processing algorithm. In the case of the BCH error detection circuit 42 and the ECC correction circuit 44, (d) is desirable because error detection and error correction are performed after data is aligned to a predetermined number of bits. However, when (d) is adopted, the data queue of 288 buses increases, and there is a possibility that the timing restriction when performing logic synthesis becomes difficult. Therefore, (b) is adopted in this embodiment.

  In the audio data buffer 52, a first flag 521f to an nth flag 52nf are provided in one-to-one correspondence with the first subbuffer 521b to the nth subbuffer 52nb. Each flag may be a 1-bit flag. When the flag bit is inactive, input to the corresponding buffer is permitted, and when it is active, input to the buffer is prohibited. The first flag 521f to the nth flag 52nf are controlled by the load address control circuit 530 and the unload address control circuit 534. The load address control circuit 530 and the unload address control circuit 534 are each connected to the first flag 521f to the nth flag 52nf by one bus.

  The load address control circuit 530 receives a load address from the load address counter 532, and the unload address control circuit 534 receives an unload address from the unload address counter 536. The load address counter 532 and the unload address counter 536 count up from 1 to the same number as the number of sub-buffers installed in accordance with the video clock VCLK. In this embodiment, the count is incremented every 28 cycles of the video clock VCLK. As described above, the error detection circuit 40 receives a data island of 288 bits. Of these, 56 bits are a BCH code, and therefore 248 bits after error detection and correction. Therefore, when data is input to the audio data buffer 52 in units of 248 bits, when connected by nine buses, accumulation in one buffer constituting the audio data buffer 52 is completed in 28 cycles.

  In the present embodiment, data input from the error detection circuit 40 is sequentially written from the first sub-buffer 521b to the n-th sub-buffer 52nb for each data island. However, when the flag is in the active state, writing cannot be performed, and thus writing starts from the sub-buffer in which the flag is in the inactive state. Each sub-buffer changes a corresponding flag to an active state when data is written. For example, 1 is written in the flag.

  The load address control circuit 530 refers to the states of the first flag 521f to the nth flag 52nf corresponding to the first subbuffer 521b to the nth subbuffer 52nb, and designates the number, that is, the address of the subbuffer to start counting up. To do. For example, the address with the smallest number among the flags in the inactive state may be designated. The load address counter 532 starts counting up from that address. The load address control circuit 530 permits data input to the sub-buffer specified by the address supplied from the load address counter 532 and prohibits input to other sub-buffers. When all of the first flag 521f to the nth flag 52nf are in the active state, the load address control circuit 530 instructs the load address counter 532 to stop counting up.

  When each sub-buffer finishes outputting the accumulated data to the selector 538, each sub-buffer changes the corresponding flag to the inactive state. For example, 0 is written in the flag. The unload address control circuit 534 refers to the states of the first flag 521f to the nth flag 52nf corresponding to the first subbuffer 521b to the nth subbuffer 52nb, and specifies the address of the subbuffer to start counting up. . For example, the address having the smallest number among the flags in the active state may be designated. The unload address counter 536 starts counting up from that address. The unload address control circuit 534 permits data output from the sub-buffer specified by the address supplied from the unload address counter 536, and prohibits output from other sub-buffers.

  The unload address control circuit 534 instructs the load address counter 532 to stop counting up when all of the first flag 521f to the nth flag 52nf are inactive. The unload address counter 536 also stops counting up when the ready signal ready from the format conversion circuit 54 is inactive. The case where the ready signal ready is in an inactive state indicates a state in which the format conversion circuit 54 rejects input from the previous stage. The unload address counter 536 operates normally when the ready signal ready is in an active state.

  Further, the unload address control circuit 534 outputs a valid signal valid to the format conversion circuit 54. The format conversion circuit 54 outputs a valid signal valid in an inactive state when all of the first flag 521f to the nth flag 52nf are in an inactive state and when the self or unload address counter 536 is not operating normally. To do. The format conversion circuit 54 invalidates the signal from the selector 538 when the valid signal valid is inactive, and effectively receives the signal from the selector 538 when the valid signal valid is active. That is, the valid signal valid functions as an enable signal.

  The selector 538 merges the output paths of the first sub-buffer 521b to the n-th sub-buffer 52nb into one, and connects the paths to the format conversion circuit 54. Each output path is composed of nine buses, and the path connecting the selector 538 and the format conversion circuit 54 is also composed of nine buses. Normally, only one of the first sub-buffer 521b to the n-th sub-buffer 52nb is allowed to output, so that data does not collide within the selector 538.

  The format conversion circuit 54 converts the audio data input from the audio data buffer 52 into another format. In this embodiment, the HDMI island packet is converted into the S / PDIF format. As described above, in the S / PDIF format, the subframe is 28 bits excluding the 4 bits of the preamplifier, and one frame is 56 bits. One data island input from the audio data buffer 52 is 248 bits, and is 224 bits when the header is removed. Therefore, four frames in the S / PDIF format are formed from one data island.

  The output side of the format conversion circuit 54 is connected to the conversion data holding register 56 by 56 buses. The format conversion circuit 54 discards the header of each data island, and then receives 56 bits of data in 6 cycles of the video clock VCLK, and converts 56 bits in the conversion data holding register 56 in 1 cycle of the video clock VCLK. Output.

  The format conversion circuit 54 outputs a ready signal ready to the unload address counter 536, and outputs a valid signal valid to the conversion data holding register 56. Also, the ready signal ready is received from the conversion data holding register 56. The format conversion circuit 54 passes the held data to the conversion data output register 58 and accepts data from the audio data buffer 52 when a free space is created. The input timing from the audio data buffer 52 and the output timing to the conversion data holding register 56 can be adjusted by the ready signal ready and the valid signal valid.

  The output side of the conversion data holding register 56 is connected to the conversion data output register 58 by 56 buses. The conversion data holding register 56 outputs a ready signal ready to the format conversion circuit 54 and outputs a valid signal valid to the conversion data output register 58. In addition, the ready signal ready is received from the conversion data output register 58.

  The conversion data holding register 56 reads 56-bit data in one cycle of the video clock VCLK, and outputs the 56-bit data in one cycle of the audio clock ACLK. That is, the conversion data holding register 56 exchanges data between the video clock domain and the audio clock domain. In the present embodiment, the format conversion circuit 54 and the conversion data holding register 56 need only have a data capacity for holding 56 bits at a minimum, but may have a capacity of 64 bits or more.

  The conversion data output register 58 functions as a shift register, and outputs the input 56-bit data bit by bit in accordance with the count value set by the conversion data output counter 59 and the audio clock ACLK. Thereafter, a 4-bit preamplifier is attached to each 28-bit subframe, and audio data in the S / PDIF format is completed and output to the speaker 110 or the like.

  The conversion data output counter 59 is a loop counter that counts up from 0 to 55 and counts up from 0 again. The count value is set in the conversion data output register 58. The conversion data output register 58 outputs the inputted 56 bits one bit at a time between 0 and 55 of the count value. When the count value is 0, a ready signal ready is output to the conversion data holding register 56, and 56-bit data is taken from the conversion data holding register 56 in one cycle of the audio clock ACLK.

  As described above, according to the present embodiment, an audio data buffer capable of holding a plurality of packets is provided, and the speed of audio data input to the format conversion unit can be adjusted. Regardless of the insertion method in each blanking section, it is possible to suppress the synchronization shift between video and audio. Further, by providing a flag for each sub-buffer, it is possible to prevent the input process to the buffer and the output process from the buffer from occurring at the same opportunity.

  In this embodiment, even in comparison with a method in which a dual port memory is mounted instead of an audio data buffer, a test in a semiconductor production process such as BIST (built in self-test) can be omitted. Can be suppressed. Further, since each block is configured with a small number of registers, the circuit size and power consumption can be suppressed. By controlling each block up to the conversion data holding register 56 with the video clock VCLK, pipeline processing and real-time processing of audio data can be realized. Further, the accuracy of the transfer can be improved by performing the data transfer between the blocks by the handshake method. In particular, by adopting the handshake method for the transfer between the conversion data holding register 56 and the conversion data output register 58, the audio data can be accurately transferred from the video clock domain to the audio data clock domain.

  Next, an electronic apparatus equipped with the data reproduction circuit in the above embodiment will be described. FIG. 6 is a diagram showing a configuration of an electronic device equipped with a data reproduction circuit. The electronic device 200 corresponds to a set device such as a television and has a function of reproducing video data and audio data transmitted by HDMI transmission.

  The electronic device 200 includes a data reproduction circuit 100, a speaker 110, and a display unit 120. The speaker 110 outputs the data output from the audio data processing circuit 50 as a sound. The display unit 120 displays the data output from the panel interface 60 as an image.

  Since the electronic device 200 includes the audio data processing circuit 50 in the above embodiment, the speed of the audio data input to the format conversion unit is adjusted regardless of the insertion method in each blanking section on the transmission side. Therefore, it is possible to suppress a synchronization shift between video and audio.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there. In the above-described embodiment, the example in which the HDMI island packet is converted into the S / PDIF format has been described. In this regard, conversion of the HDMI island packet to the I2S format can also be realized by the same principle.

It is a block diagram which shows the structure of the data reproduction circuit provided with the audio data processing circuit in embodiment of this invention. It is a figure which shows the HDMI island packet inserted in the horizontal synchronization of a TMDS channel, or a vertical synchronization blanking area. It is a figure which shows the structure of a packet body. It is a figure which shows the block configuration of a S / PDIF signal. It is a block diagram which shows the structure of an audio data processing circuit. It is a figure which shows the structure of the electronic device carrying a data reproduction circuit.

Explanation of symbols

  50 audio data processing circuit, 52 audio data buffer, 52nb nth subbuffer, 52nf nth flag, 521b first subbuffer, 521f first flag, 522b second subbuffer, 522f second flag, 523b third subbuffer, 523f third flag, 530 load address control circuit, 532 load address counter, 534 unload address control circuit, 536 unload address counter, 538 selector, 54 format conversion circuit, 56 conversion data holding register, 58 conversion data output register, 59 Conversion data output counter.

Claims (7)

An audio data processing circuit that receives data in which audio data is inserted into a blanking interval of video data and processes the audio data,
An audio data buffer for temporarily holding audio data separated from received data;
A format conversion unit that converts the stored audio data into another format,
The audio data buffer is
A plurality of sub-buffers for holding a plurality of packets describing audio data separated from each blanking section for each packet;
A plurality of flags provided in each of the plurality of sub-buffers for indicating whether or not input to the corresponding sub-buffer is permitted;
Referring to the flag, a load address control circuit for designating a sub-buffer to which a packet to be passed is to be input;
An unload address control circuit that refers to the flag and designates a sub-buffer to output a held packet to the format conversion unit,
The audio data processing circuit, wherein the unload address control circuit outputs the packet from the sub-buffer in response to a signal permitting input from the format conversion unit.   The audio data processing circuit according to claim 1, wherein the separation unit that separates audio data from the received data, the audio data buffer, and the format conversion unit are controlled by a video clock that processes the video data. . For a plurality of packets describing the separated audio data, further comprising an error checking unit for checking a code error of the audio data included in the packet using an error check code included in each packet;
3. The audio data processing circuit according to claim 2, wherein the error checker is controlled by the video clock and outputs a checked packet to the audio data buffer. By the control of the video clock, the conversion data holding register that reads and temporarily holds the audio data that has undergone format conversion from the format conversion unit,
A conversion data output register for outputting accumulated audio data by controlling an audio clock having a frequency lower than that of the video clock; and
The format converter, after receiving a signal permitting input from the conversion data holding register, outputs the audio data to be held to the conversion data holding register,
4. The audio according to claim 2, wherein the conversion data holding register outputs the audio data to be held to the conversion data output register after receiving a signal permitting input from the conversion data output register. Data processing circuit. The audio data buffer is
A load address count for supplying an address to be designated to the load address control circuit;
An unload address counter for supplying an address to be specified to the unload address control circuit,
5. The audio data processing circuit according to claim 1, wherein the unload address counter stops counting when receiving a signal prohibiting input from the format conversion unit. 6.   6. The audio data processing circuit according to claim 1, wherein the audio data processing circuit is integrated on a single semiconductor substrate. The audio data processing circuit according to any one of claims 1 to 6,
A speaker for outputting audio data reproduced by the audio data processing circuit;
An electronic device comprising:

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