KR100699452B1 - System for serial transmission of video and packetized audiodata in multiple formats - Google Patents

Abstract

A communication system is disclosed that includes a transmitter (1), a receiver (2), and a serial link. In the communication system, encoded data (eg, video, audio, and optionally other auxiliary data) is transmitted from the transmitter to the receiver. The serial link can be a TMDS link or a TMDS-like link, but it is not necessary. In a general embodiment, packets of encoded audio data are transmitted on one or more respective channels of a link during a data island between encoded video data bursts. Another feature of the invention is a transmitter for encoding video data (with any of a number of formats) and serially encoding and packetizing audio data (with any of a number of formats) over a serial link, such data Receivers for receiving (and for reformatting), and methods of formatting, encoding, packetizing, decoding, and reformatting data received or to be transmitted over a serial link.

Description

System for serial transmission of video and packetized audio data in multiple formats}

This application is filed on June 14, 2002 and assigned to the assignee of this application, US Patent Application No. 10 / 171,860, filed on March 12, 2002 and assigned to the assignee of this application. 10 / 095,422, and US Patent Application No. 10 / 036,234, filed December 24, 2001 and assigned to the assignee of the present application.

The present invention provides a method and system for transmitting encoded video data and one or more other encoded data streams (e.g., encoded video data and encoded audio data and / or other additional data packets) over a serial link; The present invention relates to a transmitter and a receiver used in a system. In a preferred embodiment, the serial link may be a transition minimized differential signaling (TMDS) link or another link having some, but not all, features of the TMDS link.

In the previous part of the specification, the decimal number does not use additional prefixes or suffixes, and sometimes the following notation is used.

"bit 0" represents the least-significant bit of a byte or word.

The prefix "Ox" indicates that the following symbol is a number represented in hexadecimal (for example, "OxC" stands for binary 1100).

The prefix "Ob" indicates that the following symbol is a number represented in binary (binary) (for example, "Ob1000" represents decimal 8).

The components of the present invention are based on the characteristics of the serial link. Various serial links are known for transmitting data and clock signals.

As one of the conventional serial links mainly used for high speed transfer of video data from a host process (eg a personal computer) to a monitor, a transition minimized differential signaling interface (TMDS) link is known. The TMDS link includes the following features.

1. Video data is encoded and then transmitted in an encoded word (each 8-bit digital video data word is converted to an encoded 10-bit word before transmission);

a. The encoding determines "in-band" word sets and "out-of-band" word sets (even though the encoder can only generate "out-of-band" words in response to a control signal or a sync signal). Only "in-band" words can be generated in response to the data, each in-band word is an encoded word resulting from the encoding of one input video data word, not in-band words transmitted over the link. All words are "out-of-band" words);

b. Encoding of the video data is performed such that transitions in in-band words are minimized (the sequence of in-band words has a reduced or minimum number of transitions);

c. The encoding of the video data is performed such that the in-band words are DC balanced (the encoding ensures that each transmitted voltage waveform carrying the sequence of in-band words does not deviate more than a predetermined threshold voltage from the reference voltage. In particular, each The tenth bit of the "in-band" word indicates whether eight of the other nine bits of the in-band word have been inverted during the encoding process, and the running counts of ones and zeros in the stream of previously encoded data bits ( correct the imbalance between running counts);

2. The encoded video data and the video clock signal are transmitted as differential signals (the video clock and the encoded video data are transmitted as differential signals via a conductor pair);

3. Three conductor pairs transmit the encoded video signal, and a fourth conductor pair transmits the video clock signal;

4. The signal transmission takes place in one direction from the transmitter (typically associated with a desktop or portable computer, or other hosts) to the receiver (generally a monitor or other display device element).

One of the uses of the TMDS serial link is the "Digital Visual Interface" interface ("DVI" link) adopted by the Digital Display Working Group. This is explained with reference to FIG. 1. The DVI link can be configured to include two TMDS links or one TMDS link (which share a common conductor pair for transmitting video clock signals), as well as additional control lines between the transmitter and receiver. The DVI link of FIG. 1 includes the transmitter 1, the receiver 3 and the following conductors between the transmitter and the receiver: four conductor pairs (channel 0, channel 1, and channel 2 for video data, and video Channel C for clock signals), for bidirectional communication between a transmitter and a monitor with a receiver associated with a conventional Display Data Channel Standard ("Display Data Channel Standard" Version 2, Rev0 dated April 9, 1996 of the Video Electronics Standard Association). Display Data Channel (DDC) line, Hot Plug Detect (HPD) line (this allows the monitor to send signals that enable the processor associated with the transmitter to indicate the presence of the monitor), (to send analog video to the receiver) Analog line, power line (to supply DC power to the monitor associated with the receiver and receiver). Display data channel standards include the transmission of an Extended Display Identification (EDID) message between a transmitter and a monitor associated with a receiver and a monitor by the monitor and the transmission of a monitor control signal by the transmitter. Specifies protocols for The transmitter 1 comprises three identical encoder / serial converter units 2, 4, and 6 and additional circuitry (not shown). The receiver 3 comprises inter-channel array circuitry 14 and additional circuitry (not shown) connected as shown with three identical recovery / decoder units 8, 10, and 12.

As shown in FIG. 1, circuit 2 encodes data to be transmitted over channel 0 and serializes the encoded bits. Similarly, circuit 4 encodes the data to be transmitted over channel 1 (also serializes the encoded bits), and circuit 6 encodes the data to be transmitted over channel 2 (also encoded bits). Serialize them). Each of the circuits 2, 4 and 6 is a digital video word (in response to a DE having a high value) in response to a control signal (an active high binary control signal called a “data enable” or “DE” signal), or Selectively encode a control or sync signal pair (in response to a DE with a low value). Each of encoders 2, 4, and 6 receives a different pair of control or synchronization signals: encoder 2 receives vertical and horizontal synchronization signals HSYNC and VSYNC; The encoder 4 receives the control bits CTL0 and CTL1; Encoder 6 receives control bits CTL2 and CTL3. Thus, each of encoders 2, 4 and 6 generates in-band words representing video data (in response to a DE having a high value), and encoder 2 is HSYNC (in response to a DE having a low value). And generate out-of-band words representing the value of VSYNC, and encoder 4 generates out-of-band words representing the values of CTL0 and CTL1 (in response to DE having a low value), 6) generates out-of-band words representing the values of CTL2 and CTL3 (in response to DE having a low value). In response to the DE having a low value, the encoders 4 and 6 each have four specific out-of representing the values (00, 01, 10, or 11) of the control bits CTL0 and CTL1 (or CTL2 and CTL3), respectively. -band Generate words.

It has been proposed to encrypt video data transmitted over a serial link. For example, it has been proposed to use a cryptographic protocol known as "High Bandwidth Digital Content Protection" (HDCP), which encrypts digital video to be transmitted over a DVI link and decrypts the data in a DVI receiver. A DVI transmitter that implements HDCP outputs 24-bit buses known as cout [23: 0] during the video active period (ie, when DE is high). The 24-bit cout data is " Exclusive Ored " (within the logic circuitry of the transmitter) with 24-bit RGB video data input to the transmitter for encryption of the video data. The encrypted data is then encoded for transmission (according to the TMDS standard). In addition, the same cout data is generated at the receiver. Then, the encoded and encrypted data received at the receiver is subjected to TMDS decoding. The cout data is processed together with the decoded video within the logic circuit to decode the decoded data and to reconstruct the first input video data.

Before the transmitter starts transmitting HDCP encrypted and encoded video data, the transmitter and receiver (the receiver uses a shared secret used to authenticate protected content, encrypt the input data and decrypt the transmitted encrypted data). It communicates in both directions to perform an authentication protocol (proving that it establishes a secret value). After the receiver is authenticated, the transmitter calculates an initial set of encryption keys (for encrypting the first line of input video data) in response to the control signal, and the receiver calculates the received and encoded first line of transmitted video data. The control signal is sent to the receiver (for each vertical blank period when DE is low) to calculate an initial set of decryption keys. After generating an initial set of encryption / decryption keys, each of the transmitter and the receiver each re-keys during each blank (vertical or horizontal) interval to generate new key sets for encrypting (or decrypting) the next line of video data. re-keying), and the actual encryption of the input video data (or decryption of the received and decoded video data) is performed using the last key set only when DE is high (while not in the blank period).

Each of the transmitter and receiver includes an HDCP cipher circuitry comprising a linear feedback shift register (LFSR) module, a block module coupled to output the LFSR module, and an output module coupled to the output of the block module. Herein, sometimes referred to as "HDCP cipher". The LFSR module is used in the re-key block module in response to the assertion of each of the enable signals using the session key Ks and the frame key Ki. The block module generates a key Ks at the beginning of the session (also provides it to the LFSR module) and each frame of video data (in response to the rising edge of the control signal occurring in the first vertical blank period of the frame). Generates a new value of the key Ki at the beginning of (provides it to the LFMS module).

The block module includes two halves known as "Round Function K" and "Round Function B". Round Function K consists of 28-bit registers (Kx, Ky and Kz) and seven S-boxes (S-boxes with 4 output bits and 4 output bits, each with a look-up table), linear conversion unit (K) It includes. Round Function B consists of 28-bit registers (Bx, By and Bz), seven S-boxes (S-boxes of 4 output bits to 4 input bits each containing a look-up table), and a linear conversion unit (B ). Round Function K and Round Function B are similarly designed, but Round Function K responds to the output of the LFSR module, where 28-bit round keys (Ky and Kz) have different pairs (to output modules) in each clock cycle. One clock cipher round per clock cycle to assert, Round Function B responds to each 28-bit round key Ky from Round Function K, one block cipher per clock cycle The round is performed and output to the LFSR module, applying different pairs of 28-bit round keys (By and Bz) (to the output module) in each clock cycle.

The transmitter generates a value An at the beginning of the authentication protocol and the receiver responds to the value An during the authentication process. The value An is used to randomize the session key. The block module operates in response to an authentication value An and an initialization value Mi (or called integrity verification value) that is updated by the output module at the beginning of each frame.

Each of the linear conversion units K and B outputs 56 bits per clock cycle. These output bits are combined with the outputs of eight diffusion networks in each conversion unit. Each spreading network of the linear transformation unit K generates seven output bits in response to the seven current output bits of the registers Ky and Kz. Each of the four spreading networks of the new conversion unit B generates seven output bits in response to the seven current output bits of the registers By, Bz and Ky, and the other four of the linear conversion unit B. Each of the spreading networks produces seven output bits in response to the seven current output bits of registers By and Bz.

The output module performs a compression operation on the 28-bit keys (By, Bz, Ky, and Kz) input by the block module (all 112 bits) during each clock cycle, so that a pseudo-random of 24-bit blocks per clock cycle ( pseudo-random) bits cout [23: 0]. Each of the 24 output bits of the output module consists of 9 terms of exclusive OR ("XOR").

At the transmitter, the logic circuit receives the 24-bit block cout data and each input 24-bit RGB video data word, and processes the bitwise XOR operation there to encrypt the video data, thereby encrypting the encrypted RGB video data word. Create In general, encrypted data is sequentially TMDS encoded before being sent to the receiver. At the receiver, the logic circuit receives the 24-bit block of cout data and the reconstructed 24-bit RGB video data word, respectively (and then the reconstructed data is subjected to TMDS decoding), where there is a bitwise XOR operation. Processing to decode the reconstructed video data.

Throughout the specification, a representation of a " TMDS-like link " may transmit encoded data (i.e., encoded digital video data) and a clock for the encoded data from a transmitter to a receiver, and between one or more receivers and the receiver. It will be used when referring to a serial link that includes a TMDS link or a link having some but not all of the characteristics of a TMDS link, which may carry additional signals (ie, an encoded digital audio signal or other encoded data). Examples of TMDS-like links are links that differ only in encoding data into N-bit (eg N 10) TMDS code words, rather than TMDS links and 10-bit TMDS code words, and three TMDS links. Transmitting encoded video over more or less than three conductor pairs only includes links. There are several TMDS-like links in the prior art.

The term " transmitter " herein refers to the encoding of data and the transmission of the encoded data over a serial link (and the encryption of the data to be transmitted and other operations relating to the encoding, transmission or encryption of the data). In a broad sense to refer to any device) that selectively performs additional functions. The term " receiver " herein includes the operation of receiving and decoding data transmitted over a serial link (and decrypting the received data and other operations related to decoding, receiving or decrypting the received data). Used broadly to refer to a device) that selectively performs other additional functions. For example, the term transmitter may refer to a transceiver that performs not only the function of the transmitter but also the function of the receiver. For a more specific example, the term transmitter (with respect to a device that transmits non-audio auxiliary data over a TMDS-like link or other serial link) may receive video data and audio data over the link and over the link. It may refer to a transceiver configured to transmit non-audio assistance data.

Some TMDS-like links encode input video data (and other data) to be transmitted into encoded words containing more bits than the data entered using a coding algorithm other than the specific algorithm used in the TMDS link, and The encoded video data is transmitted to the in-band attribute and other encoded data is transmitted to the out-of-band attribute. The attributes need not be classified into in-band or out-of-band attributes based on whether they meet transition minimization and DC balance criteria. Rather, other classification criteria may be used. An example of an encoding algorithm that can be used on a TMDS-like link that is not used on a TMDS link is IBM 8b10b coding. The classification (between in-band and out-of-band attributes) need not be based solely on whether the number of transitions is large or small. For example, the number of transitions of each in-band and out-of-band attribute may be within a single range (in some embodiments) (ie, an intermediate range defined by the minimum and maximum number of transitions).

Data transmitted between the transmitter and receiver of a TMDS-like link can be transmitted differentially (via a pair of conductors), but is not necessary. Also, while TMDS links have four differential pairs (in a single pixel version), three pairs for video data and another pair for video clocks, TMDS-like links can have different conductor numbers or different conductor pairs.

In general, the main data transmitted by the TMDS link is video data. What is often of importance here is that the video data is not continuous, but instead has a blanking interval. These blank intervals provide an opportunity for auxiliary data to be transmitted (used in some embodiments of the present invention), and blank intervals represent unused bandwidth. On the other hand, many serial links do not transmit data with blank intervals and, therefore, do not encode input data (for transmission) in response to a data enable signal. For example, audio serial links generally carry continuous data.

The expression "auxiliary data" is used in a broad sense to refer to timing information (e.g. video clock) for data and video data in a form other than digital audio data or video data. For example, timing information for audio data (ie, clock for recovering transmitted audio data) corresponds to the range of "auxiliary data". Other examples of transmitted "auxiliary data" according to the present invention are computer keyboard signals, still image data (i.e. generated by a camera), text data, control signals for power supply, pictures in picture data, monitor control information. (Audio volume, brightness, power status), control signals for indicating light on a monitor or keyboard, non-audio or video control information, and the like.

The term "stream" as used herein refers to all of the data being in the same form and transmitted within the same clock frequency. The term "channel" as used herein refers to the portion of the serial link used to transmit data (i.e., a specific conductor or conductor pair between the transmitter and receiver to which data is transmitted, and the transmission and / or recovery of data. Specific circuitry within a transmitter and / or receiver) and a technique used to transmit data over the link. Since it is desirable to transmit many different auxiliary data streams in the important applications of the present invention, preferred embodiments of the present invention provide for the transmission of auxiliary data in both directions (i.e. video data direction and opposite direction) over the link. It provides a plurality of channels for the transmission of the auxiliary data including the channels. In some implementations, a channel is provided to transmit one or more auxiliary data streams. In one embodiment of the invention, two (or more than two) serial video data streams are transmitted (via one, two or more than two channels), and also one, two or more than two serial auxiliary data streams are transmitted. do.

US Patent No. 5,999,571, filed Dec. 7, 1999 (i.e. in col. 5), describes code words (representing video data) transmitted over a TMDS link (transition minimized words) (code word set). Synchronization words (distinguish from transition minimization code words) may be transmitted over the link during a “preamble” period in which encoded video data is not transmitted. It is disclosed that there is. The synchronization words may be transition minimization words that are members of a second subset (separated from the first subset) of the code word set. U. S. Patent No. 5,999, 571 discloses that a synchronization word is repeatedly transmitted several times (e.g. three times) in succession so that a particular transition (e.g., leading edge) of one of the synchronization words (e.g. ) Enabling the decoder to identify quickly and accurately so that synchronization with the encoder (in the transmitter) is completed.

US Patent No. 6,151,334, registered November 21, 200, discloses several different forms of transmission (over a TMDS link) of encoded control words, each of which can be distinguished from a transition minimization code representing data. At least some of the control words may be transition minimization words. One of the control words is a " data stream separation " word, transmitted before or after the data burst, indicating the beginning and end of the burst and the type of data transmitted during the burst. The other of the control words is generally a synchronization attribute transmitted at the beginning or end of the blank period, indicating the form of the blank period (ie horizontal or vertical), and distinguishing between the start and end of the blank period. Isochronous data transfer. For example, a first isochronous data transfer word indicates the beginning of a vertical blank interval, a first data stream separation word indicates the beginning of a data burst of a vertical blank interval, and a second data stream separation word indicates the end of such a data burst. The second isochronous data transfer word indicates the end of the vertical blank interval. Each of the first isochronous data transfer word, the first data stream splitting word, the second data stream splitting word, and the second isochronous data transfer word are transition minimizing code words, and the transition minimizing code words are (transmitted within the vertical blank interval). Each word of data in the data burst may be represented, and after the vertical blank interval, a third data stream separation word (indicative of the beginning of the video data stream) followed by a stream of transition minimization code words representing the video data subtraction. It may be followed by an active video cycle.

In embodiments of the invention, the invention relates to a transmitter, a receiver, an encoded video data stream and one or more other encoded data streams (e.g., encoded audio) over each of one or more channels of a link from the transmitter to the receiver. Communication system including a serial link (having one or more channels) for transmitting data. In a preferred embodiment, the serial link is a TMDS or TMDS-like link. In a preferred embodiment, the transmitter transmits encoded video to each of the at least one video channel of the link to the receiver during an active video period, and each of the one or more video channels during data islands. Transmits a packet including encoded auxiliary data (eg, audio data) to the receiver, wherein each of the data islands is a time period that does not occur simultaneously with or overlap with any of the active video periods. The transmitter is further configured to transmit control data over the video channel to the receiver during a control data period, wherein the control data period does not occur simultaneously with or overlap with any of the data islands. It does not occur at the same time or overlap. Another feature of the invention is a transmitter for formatting, encoding and transmitting a plurality of data streams, a receiver for receiving and decoding a plurality of encoded data streams transmitted over a serial link, and an encoded plurality Is a method of transmitting a data stream through a serial link.

One or more packets may be sent in each data island. Within each control data period (sometimes referred to as a "control data interval" or "control period") (including a sync word and a "preamble" word) Encoded control words can be transmitted.

In a system implemented by the present invention, a plurality of 8-bit video data words (each of which is a transition-minimization code word, each encoded 10-bit using a TMDS encoding algorithm) are used to transmit a TMDS link (or serial video) during an active video period. Is transmitted over video channels of another TMDS-like link having a channel of < RTI ID = 0.0 > During the data islands between the active video periods, each encoded 10-bit using a TMDS encoding algorithm and is a transition minimized code word, preferably a 10-bit golden word (generally comprising a 4-bit audio data word). Packets containing a 4-bit word are transmitted on each of several of the video channels. During the control data period between the active video period and the data island, the transmitter has a control word (encoded with 10-bits, respectively, and is a transition minimization code word representing CTL0 and CTL1, or CTL2 and CTL3) and A 10-bit encoded, sync word, which is a transition minimization code word representing two sync bits: HSYNC and VSYNC, is transmitted over the video channels. During each active video period, the receiver assumes that HSYNC, VSYNC, CTL0, CTL1, CTL2, and CTL3 maintain the values they had at the beginning of the active video period.

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Preferably, the transition minimization code words representing HSYNC and VSYNC bits (ie, one code word per pixel clock cycle, each word representing HSYNC bits, VSYNC bits, packet header bits, and other bits) are each data island. Is transmitted over one channel (ie CH0).

In one embodiment, the invention is a transmitter configured to be connected with a serial link having one or more video channels. The transmitter includes inputs for receiving video data and audio data comprising I ² S format audio data, one or more outputs configured to be connected to the link, and circuitry coupled between the inputs and each output. The circuit generates encoded video data by encoding the video data, generates code words representing packets of auxiliary data, applies the encoded video data to the one or more outputs during an active video period, and a data island. And said circuitry for applying said code words representing packets of auxiliary data to said one or more outputs. The auxiliary data includes audio data.

In another embodiment of the present invention, the receiver receives a plurality of streams of input audio data, which data may be I ² S format audio data and / or DSD format audio data, but need not be so. The receiver includes a multiplexer circuit and a data packetization circuit. The multiplexer circuit is coupled and configured to receive the audio data streams and apply a predetermined one of the streams to the data packetization circuit at a predetermined timing.

In another embodiment, the invention is a transmitter configured to be connected with a serial link having one or more video channels. The transmitter includes one or more inputs for receiving audio data and video data having an embedded clock, one or more outputs configured to be connected with the link, and a circuit portion connected between the inputs and each output. The circuitry generates encoded video data by encoding the video data, and generates resampled audio data by sampling the audio data stream with a second clock having an unknown phase relationship with the embedded clock, Generate code words representing data packets, apply the encoded video data to the one or more outputs in response to a pixel clock during an active video period, and represent the auxiliary data packet in response to the pixel clock during a data island. Configured to apply the at least one output to the code word, it comprises the circuit. The auxiliary data includes time code data and the resampled audio data, the time code data representing the second clock along with the pixel clock.

In another embodiment, a transmitter configured to be connected with a serial link having one or more video channels. The transmitter includes one or more inputs for receiving audio data and video data having an embedded clock, one or more outputs configured to be connected with the link, and a circuit portion connected between the inputs and each output. The circuitry generates encoded video data by encoding the video data, and resamples the audio data stream with a pixel clock having an unknown phase relationship with the embedded clock to generate resampled audio data, and auxiliary data. Generate code words representing packets, apply the encoded video data to the one or more outputs in response to a pixel clock during an active video period, and represent the auxiliary data packet in response to the pixel clock during a data island. Includes the circuitry, configured to apply code words to the one or more outputs. The auxiliary data includes the resampled audio data.

In some embodiments, a transmitter in accordance with the present invention generates code words representing auxiliary data packets, some of which are audio sample packets. Each audio sample packet has a header and may include one or more samples of the audio data. The header includes header data in one or more predetermined time slots indicating whether the audio sample packet contains audio data samples and whether each audio data sample is a flatline sample.

In other embodiments, the invention is a receiver configured to be connected with a serial link having one video clock channel and one or more video channels. The receiver comprises at least two inputs configured to be connected with the link and comprising a clock input configured to be connected with the video clock channel, outputs for applying video data and audio data recovered from the link, and the input. A reconstructed video connected between the modules and the respective outputs, receiving a pixel clock from the clock input, decoding the encoded video data received at the one or more inputs during an active video period in response to the pixel clock, and the like. Decoded data by generating data, applying the reconstructed video data to the one or more outputs, and decoding code words of encoded auxiliary data packets received at the one or more inputs during a data island in response to the pixel clock. To generate And circuitry configured to generate one or more streams of I ² S format audio data from the decoded data and to apply each stream of I ² S format audio data to the one or more outputs. Some or more of the decoded data is time code data representing a time stamp. The time code data together with the pixel clock represents an audio clock for the I ² S format audio data stream.
In some embodiments, a receiver in accordance with the present invention comprises multiplexer circuitry for restoring multiple streams of audio data and for applying each stream of recovered audio data to one or more of the outputs at a predetermined timing. .
In a preferred embodiment, the transmitter according to the invention is configured to generate encoded video data representing video with a second format in response to input video with the first format. In a preferred embodiment, the receiver according to the invention is configured to generate reconstructed video data having a first format in response to encoded video data representing video having a second format.

1 is a block diagram illustrating a system including a conventional DVI (Digital Visual Interface) link.

2 is a block diagram illustrating a system according to an embodiment of the present invention.

3 is a table showing a data pattern transmitted in the "secondary preamble" and "video preamble" portions of a control data period and a guard band code word transmitted after the auxiliary preamble and video preamble portions according to an embodiment of the present invention.

4A and 4B are tables illustrating 17 sets of code words of the present invention (including two guard band words), respectively, according to one embodiment of the present invention. Further, the table is a table showing other code words mapped to each of the 17 code words by a receiver designed according to the embodiment. 4A and 4B are collectively called "FIG. 4".

5 is a timing diagram of a signal input to a transmitter during a control data period and a data island of a system in accordance with an embodiment of the present invention, and an encoded signal transmitted over a TMDS link of the system in response to the signal.

6 illustrates a signal input to the transmitter during the video preamble portion of the control data period of the system (and during the next active video period) and a TMDS link of the system in response to the signal according to an embodiment of the present invention. A timing diagram of an encoded signal transmitted over.

7 maps clusters of received code words (ie, clusters S _a and S _b ) to each of the transmitted code words (ie, code words “a” and “b”) according to one embodiment of the invention. It is a drawing.

8 shows that in a preferred embodiment of the present invention, video data (and guard bands) are transmitted in an active video period, data packets (and guard bands) are transmitted during a data island, and preamble words and control words are controlled data periods. A diagram illustrating a format transmitted to a.

9 is a diagram illustrating a format in which data is transmitted in a packet (during a data island) in a preferred embodiment of the present invention.

9A is a block diagram illustrating a circuit for generating and transmitting a BCH parity bit included in packetized data according to a preferred embodiment of the present invention.

9B is a block diagram illustrating a circuit for generating and transmitting a BCH parity bit included in packetized data according to a preferred embodiment of the present invention.

9C is a block diagram illustrating a circuit for generating a syndrome from packetized data according to a preferred embodiment of the present invention.

9D is a block diagram illustrating a circuit for generating a syndrome from packetized data according to a preferred embodiment of the present invention.

10 is a timing diagram illustrating a format in which RGB video data is transmitted through a TMDS link in one embodiment of the present invention.

FIG. 11 is a timing diagram illustrating a format in which YCbCr 4: 4: 4 video data is transmitted through a TMDS link in one embodiment of the present invention.

12 is a timing diagram illustrating a format in which YCbCr 4; 2: 2 video data is transmitted through a TMDS link in one embodiment of the present invention.

13 is a block diagram illustrating a transmitter according to a preferred embodiment of the present invention.

13A is a block diagram illustrating circuitry for determining whether to insert a data island between active video periods used in a transmitter in accordance with one embodiment of the present invention.

FIG. 13B is a timing diagram illustrating some signals received and generated by the circuit of FIG. 13A in operation.

13C is a block diagram illustrating circuitry for inserting data islands between active video periods used in a transmitter in accordance with one embodiment of the present invention.

14 is a block diagram illustrating a receiver according to a preferred embodiment of the present invention.

FIG. 15 is a block diagram illustrating a complement data clock transfer and regeneration circuit for use in a system according to an embodiment of the present invention.

16 is a block diagram illustrating an auxiliary data clock regeneration circuit used in a receiver according to a general embodiment of the present invention.

17, 18, 19, 20 and 21 each illustrate a link integrity check operation that may be implemented in a system (or other system in which data is transmitted over a serial link) in accordance with one embodiment of the present invention. A timing diagram is shown.

22 is a timing diagram of an audio and pixel clock that may be applied to the transmitter of the present invention. The audio and pixel clocks are shown as not completely synchronized.

23 is a timing diagram of signals generated by a system according to a preferred embodiment of the present invention, showing how the CTS counts by the transmitter and receiver counting can be resynchronized.

As mentioned above, the term "stream" of data (as used herein) refers to data in which all its data is of the same type and transmitted according to the same clock frequency, and the term "channel" (as used herein) The portion of the serial link used to transmit data (e.g., a specific conductor or conductor pair between the transmitter and receiver to which data is transmitted, and the transmitter and / or receiver used to transmit and / or restore the data Specific circuitry) and techniques used to transmit data over the link.

When transmitting audio (or other auxiliary) data over a serial link, it is often necessary to send a plurality of auxiliary data streams, and also multiple channels of the link are often useful for transmitting auxiliary data. For example, 2 audio streams (left and right streams of stereo audio), 6 audio streams (eg, a stream of “5.1” surround sound), or 8 streams (eg, a stream of “7.1” surround sound). This can be. On the other hand, it may be desired to transmit more audio data streams with video, or to transmit non-audio auxiliary data streams (to provide a non-audio effect synchronized with video) with audio and video. All such auxiliary data streams are generally based on the same timing base, while some (or other auxiliary) data of the audio data may be based on different time bases or may have different sampling rates. For example, the transmission of six Pulse code modulated (PCM) audio data over a link may be based on one clock. Another two compressed audio data streams may be sent along with the video and PCM data, such as down-mix (to play at a reduced number of speakers).

In high-speed serial digital data transmissions, data is often encoded to maximize or minimize the number of transitions or to balance the DC level. For example, in a system including one or more TMDS links in accordance with one embodiment of the present invention, the transition minimized, DC balanced, TMDS encoded video data is transmitted over each of the three channels of the TMDS link, and encoded secondary Data (ie, audio data) may be transmitted over one or more of the three channels during the blank period between the active video periods. If the bandwidth required for auxiliary data is less than the bandwidth required for main data (video data) and the auxiliary data channel has severe ISI (which may arise from long cables), then the auxiliary data is used to encode the video data for transmission. It can preferably be encoded using subsets (including "golden words") of transition-minimized TMDS code words that become.

An embodiment according to the present invention may be implemented in a system of the type shown in FIG. 2. The TMDS link between the transmitters 1 'and 2' of FIG. 2 is the same as the TMDS link between the transmitters 1 and 3 of FIG. 1, but some of the conductors of the link shown in FIG. 1 are shown in FIG. 2. (For simplicity) The system of FIG. 2 also performs the functions of the system of FIG. 1, not only encodes video data in the same manner as the conventional system of FIG. 1, but also encodes audio data (or other auxiliary data), and channel 0 of the TMDS link. Transmit the encoded auxiliary data over one or more of channels 1 and 2, and also transmit encoded video data over each channel, as well as the encoded auxiliary data (as well as encoded video data). It is configured to decode.

The transmitter 1 ′ and the receiver 2 ′ of FIG. 2 correspond to the transmitter 1 and the receiver 3 of FIG. 1, respectively, but have not been performed by the transmitter 1 and the receiver 3 of FIG. 1. Perform data decoding, transmission, and decoding functions. The transmitter 1 ′ of FIG. 2 is a component of a source apparatus that also includes a combined MPEG2 decoder 13 and microcontroller 15 as shown. The decoder 13 applies an input video ("DigVideo") to the video data processing subsystem of the transmitter 1 ', and audio data ("SPDIF") and an audio reference clock to the audio data processing subsystem of the transmitter 1'. Input (“MCLK”) The input audio SPDIF may represent two or more streams of audio data (ie, left and right streams of stereo signals), and the EEPROM 14 transmits to the receiver 2 '. A key value and identification bits used for HDCP encryption of contents to be stored are stored.

The receiver 2 'of FIG. 2 also includes an EDID ROM 23, a microcontroller 25, a display circuit 26 and an audio digital-to-analog converter 27 ("DAC"), coupled as shown. (sink) A component of a device. The EDID ROM 23 is connected to the DDC channel of the TMDS link and stores state and configuration bits that can be read by the microcontroller 15 via the DDC channel. The receiver 2 'also includes an interface for communicating with the microcontroller 15 via the DDC channel (eg, interface 201 of FIG. 14). The microcontroller 25 is connected to the receiver 2 'for I2C communication. The EEPROM 24 stores key values and authentication bits used for HDCP decryption of the content received from the transmitter 1 '.

In addition, the sink device is a display circuit 26 for receiving analog and / or digital video restored by the receiver 2'and an audio digital for receiving digital audio restored by the receiver 2 '. -Analog converter 27 (DAC 27).

Advantageously, the system of FIG. 2 transmits a video clock over a pair of conductors (named "channel C" in FIG. 2) of the TMDS link, and also provides a clock for auxiliary data over one or more channels of the link. send. For example, the transmitter 1 'sends video data to the receiver 2' via channels 0, 1 and 2 (with the same reference numerals as those attached to the channels of the system of FIG. 1) during the active video period. Transmit audio data (eg, left and right signals of a stereo signal) over one or more of channels 0, 1, and 2 at a time other than during the active video period, and continue (eg, a binary waveform). Transmit a video clock over channel C (determined by the rising edge of) and transmit time stamp data (via one or more of channels 0, 1 and 2) with each burst of audio data. The time stamp data determines the clock for audio data, as disclosed in US Patent Application No. 09 / 954,663, filed Sep. 12, 2001, supra. Receiver 2 'is configured to process the time stamp data to regenerate an audio clock used to transmit audio data. Preferred methods and systems for regenerating the clock from the transmitted time stamp data are described in detail below.

In general, the clock for an audio data stream has a much lower frequency than the pixel clock for the video stream. However, in most applications the audio clock requires much more sophistication than the pixel clock to reduce jitter. Distortion of analog audio (generated from digital audio data with jitter) can be identified much more easily (for those skilled in analog audio) than distortion in displayed video programs generated from digital video with the same amount of jitter. Because.

In the system of FIG. 2, 8-bit source words of video data are encoded into transition-minimized 10-bit code words, then serialized and channel medium (one of the pair of conductors identified as channels 0, 1 and 2). Is sent through. At the receiver 2 'each 10-bit code word is decoded back to the original 8-bit word if no error exists. Each code word has a 9-bit base (2 ⁹ sets of transition-minimums of a ⁹ -bit pattern, the most significant bit of which is the transition-minimization of the base pattern, and the eight most insignificant bits of the base pattern are DC balanced. Pattern associated with the tenth bit indicating whether or not inverted according to the algorithm. At the transmitter 1 ', each 8-bit source word is first encoded into one of the 9-bit basic patterns, and then the 9-bit basic pattern stream is the 10-bit code word stream (transmitted 10- In a way to improve the DC balance of the bit code word stream). However, the decoded video data may contain errors (especially when the associated channel has severe ISI), depending on the particular channel media and the particular data pattern of the transmitted serial bit stream.

If the transmitter 1 'and the receiver 2' encode and decode auxiliary data in the same way as the encoding and decoding method of video data, and transmit both types of encoded data over the same channel of the serial link, The decoded auxiliary data will have errors at the same error rate. The error rate may be unacceptably high for auxiliary data (particularly when the auxiliary data is audio data), although it may be acceptable for video data. To reduce the error rate for the ancillary data, the transmitter 1 'can be configured to encode the ancillary data using "golden words" to be described below. Optionally, the transmitter 1 'may also be configured to encode video data using a "golden word" (or to operate in a mode of encoding both video data and auxiliary data using a "golden word"). Can be). However, data encoded using a "golden word" (a robust subset of a "full set" of code words) is the same encoded using a "full set" of the same code word. Necessarily have a lower data rate than data (assuming both encoded bit streams are transmitted at the same clock frequency). In many applications, video data is not actually transmitted at the proper rate if it is encoded using golden words. Thus, the system of FIG. 2 is generally implemented to encode auxiliary data (not video data) using golden words.

In one embodiment of the invention, the transmitter and receiver according to the invention distinguish each blank period (between active video periods) into three or more parts: after the initial part (where the "data island preamble" can be transmitted) This is followed by an auxiliary data part (sometimes called a "data island"), followed by the last part (where a "video preamble" can be transmitted). On the other hand, there are two or more data islands within a blank period (each comprising one or more auxiliary guard bands followed by a burst of different encoded auxiliary data streams). That is, an initial part between the falling edge of DE and the end of the first data island (at the beginning of the blank period), an additional part (including another data island preamble) before each successive data island in the blank period, There is a last part (including the video preamble) between the last data island and the next active video period. During the initial data island preamble of each blank period, a code word representing a specific pattern of control bits CTL3, CTL2, CTL1 and CTL0 is repeatedly transmitted, and optionally the initial bit patterns (e.g., channels CH2 and CH1). (At the beginning of the initial auxiliary preamble), patterns in the time interval indicated by " Rsvd " During the video preamble of each blank period, code words representing other specific patterns of the control bits CTL3, CTL2, CTL1 and CTL0 are repeatedly transmitted, and optionally the initial bit patterns (e.g., of channels CH2 and CH1). At the beginning of the video preamble, patterns in the time interval indicated by " Rsvd " Preferably, during each data island, code word packets are transmitted, each representing encoded auxiliary data and guard band words.

As mentioned above, two or more data islands may be transmitted continuously (without an active video period in between). Also, two or more active video periods may be sent continuously (without a data island in between), and a data island may also be sent alternately with the active video period.

In one embodiment of the invention, the following signals are transmitted during the video preamble (as shown in FIGS. 3 and 6): The code word " 0010101011 " representing CTL3 = 0, CTL2 = 0 is transmitted over CH2 (preferably). Preferably, after the initial bit pattern in the " Rsvd " interval, the code word " 0010101011 " representing CTL1 = 0, CTL0 = 0 is repeatedly transmitted through CH1 (preferably after the initial bit pattern). A code word that is transmitted and that represents one of four possible combinations of sync bits (HSYNC and VSYNC) is repeatedly transmitted over CH0. In normal operation, during the last 12 pixel clock cycles of the video preamble (before the transition from DE to 0 as shown in FIG. 6), both sync bits (HSYNC and VSYNC) have a value of 0, thus HSYNC = A code word (i.e. code word " 0010101011 " shown at the bottom of FIG. 6) indicating 0, VSYNC = 0 is transmitted over channel 0.

In one embodiment, the following signals are transmitted during the initial data island preamble (as shown in FIGS. 3 and 5): The code word " 1101010100 " representing CTL3 = 0, CTL2 = 1 is preferably over CH2 (preferably, Is repeatedly transmitted after the initial bit pattern in the " Rsvd " interval, and the code word " 0010101010 " representing CTL1 = 1, CTL0 = 0 is repeatedly transmitted (preferably after the initial bit pattern), A code word representing one of four possible combinations of sync bits (HSYNC and VSYNC) is repeatedly transmitted over CH0.

During the transmission of data over the serial link from the transmitter to the receiver, inter-symbol interference (ISI) causes an error such that the received data may be different from the transmitted data. The rate at which this error occurs depends on factors such as channel medium, when the data is a pattern of binary bits, and the particular bit pattern being transmitted. In a preferred embodiment of the invention, the data (e.g., audio data transmitted during a data island between active video periods) is, for transmission over a serial link, a pattern that is determined by the encoded version of the same conventional data. It is encoded in a bit pattern that is less sensitive to ISI during transmission over the link. Thus, in an embodiment of the present invention, data is transmitted more reliably and with a reduced error rate compared to conventional encoding integrity of the same data. More specifically, in a preferred embodiment, the data is encoded using a subset of the full set of code words (a subset of "robusted"). In general, code words in a full set have the same length (eg, each consisting of N bits). Robust subsets may sometimes be referred to herein as "selected" or "inventive" sets of code words, and code words in robust subsets are sometimes referred to as "code according" Or "golden word"). The robust subset is determined by a conventionally coded version of the same data transmitted (coded using not only the members of the code word set of the invention, but also the full set of code words that are not members of the code word set of the invention). It is selected to be transmitted in a stream of encoded data (coded using only the members of the code word set of the present invention) having a pattern that is less sensitive to ISI during transmission over the serial link than the pattern in which it is transmitted. Since the present invention has more full sets of code words than the code word set, if the transmitted data was encoded using only the code words of the present invention than the transmitted data is encoded using the full set of conventional code words, Less words of data per single time may be sent over the link.

The method of encoding data according to the invention is particularly well suited for applications in which the encoded data is transmitted via very long conductors or other conductors which may have a high risk of errors due to ISI during transmission if other methods are used. useful.

In one embodiment of the invention, the transmitter 1 'is configured to encode auxiliary data transmitted between different active video periods in the present invention as follows. A subset of the full set of 10-bit TMDS code words consists of each transmitted stream of 10-bit words of encoded auxiliary data (consisting of only the code words of the present invention, sometimes referred to as " golden words "). It has a pattern that has less sensitive intersymbol interference than the pattern determined by the transmitted stream of the TMDS encoded version of the same data, as well as the code word, as well as all members of the full set of non-code words of the present invention.

In one embodiment, a 2 ^M -bit subset (where M <8) of the 10-bit TMDS code word full set is selected as the code word set of the present invention. Optionally, the codeword set of the present invention also includes one or more codewords of the full set used as guard band words. The 17 inventive code words (each including 10 bits) described below with reference to FIGS. 3 and 4 are a subset of the 2 ^M -bits added by one additional guard band word (where M = 4). ). The receiver 2 'is implemented to decode each of the 10-bit code words of the present invention received as an auxiliary data word of M bit length. The receiver 2 'performs a decoding operation on the encoded auxiliary data received during the blank period, such as an operation performed on the video words encoded by the conventional method received during the active video period. However, while encoding the source assistance data (using the code words of the present invention), the transmitter 1 'is a conventional DC balancing step ("N + 1") that was performed during encoding according to the conventional method of source video data. When the eight most insignificant bits of the first encoded video word are inverted, the cumulative DC drift of the tenth, N previous encoded video words, which distinguishes nine bits, reaches a predetermined threshold. The most significant bit of, and otherwise the eight most insignificant bits of the "N + 1" th encoded video word are not inverted, but instead associate the word with the other most significant tenth bit being distinguished) Do not do it. On the other hand, the transmitter 1 'can be used to determine the angle of the auxiliary data regardless of the accumulation of the resulting DC drift of the code word stream of the present invention (and also whether the MSB of the code word of the present invention is 1 or 0). It is configured to simply replace the 4-bit source word with the corresponding code word of the code word of the present invention. The code word of the present invention preferably overwrites the bit pattern of these streams of the code word of the present invention when the bits of the code word stream of the present invention are transmitted in succession to the rising and falling of the voltage over the serial link. The voltage drift that determines the time is chosen to be DC balanced (or similar to DC balance) such that it is limited to an appropriate amount.

In one embodiment, the transmitter 1 'does not perform the same DC balancing step while encoding the source assistance data (using the codeword of the present invention) and while encoding the source video data through the conventional method. This is a consideration in selecting the code word set of the present invention. In particular, each code word of the code word set of the present invention, while encoding a 4-bit word of source assistance data (to replace it with the 10-bit code words of the present invention), is a 10-bit TMDS code. Having a 9-bit base pattern that is a member of a selected 9-bit base pattern space of the full set of words, the eight most insignificant bits of the 9-bit base pattern are inverted and have a first value having a first value; A result pattern associated with the (most important) bit or a (most important) 10 having a second value depending on whether the underlying pattern is not inverted and the cumulative DC drift of the previously encoded auxiliary word stream reaches a predetermined threshold value. Is associated with the first bit. In these embodiments, the receiver 2 'performs the same decoding operation on the encoded auxiliary data words received during the blank period as for the same decoding operation performed on conventionally encoded video data words received during the active video period. Mapping each 8-bit word into one of 2 ^M auxiliary data words each having an M-bit length (generated through decoding with one of the 10-bit encoded auxiliary data words). Is implemented.

In the embodiment shown the system of Figure 2, the size of the auxiliary data encoding region (the number of different auxiliary data words linking can be encoded with the foot had codeword set) 2 ^M (where at ²⁸ (256), according to the present invention M <8), so the effective rate of auxiliary data that can be transmitted (encoded according to the invention) is reduced from 8 bits per clock period per channel to M bits per clock per channel. By reducing the M value (i.e. by selecting a smaller set of code words of the present invention from the full set), a lower bit error rate (BER) can be achieved, but at the same time the data rate is also reduced. In comparison, increasing the parameter M can increase the data rate, but at the cost of increasing the BER.

3 and 4, an embodiment of the code word set of the present invention will be described. The code word set is a subset of a full set of conventional TMDS 10-bit code words and is suitable for transmitting auxiliary data at half of the data rate of the video data (in conventional methods). Also useful for the transmission of 4-bit words of encoded auxiliary data over a transmitted TMDS link (or TMDS-like link), which is encoded using a full set of TMDS 10-bit code words. In general, 8-bit input words of binary auxiliary data are buffered, and each of the four most significant bits is represented by 16 8-bit words (AD0-AD15) in the left column of FIG. 4 (indicated by "Input D7-D0"). Is encoded (in the transmitter 1 'of FIG. 2), and the four most significant bits of each 8-bit input word are also encoded into one of the 16 8-bit words AD0-AD15. Each word AD0-AD15 has a hexadecimal representation shown in the second column from the left of FIG. Each word AD0-AD15 is then encoded (as transmitter 1 ') into the corresponding one of the 10-bit patterns, as shown in the third column of FIG. 4 (indicated as "TMDS result"). Other columns of FIG. 4 are described below with reference to features of the present invention related to the mapping of code word clusters.

In Figure 4 (and Figure 3), the left bit of each code word is the LSB, and (for each 10-bit code word) the first bit to be transmitted over the serial link. In addition, the right bit of each code word is the MSB and (in the case of each 10-bit code word) the last bit to be transmitted over the serial link.

For example, the input auxiliary data word 10000000 (LSB equals 1) is divided into two parts 1000 and 0000, which are encoded as AD1 and AD0, respectively. Then, the 8-bit word AD0 is encoded into the 10-bit word "0011100101" of the present invention, and the 8-bit word AD1 is encoded into the 10-bit word "0110001101" of the present invention. The two inventive words are then serialized into bits "0011100101" representing the "most significant" half (0000) of the input word to be transmitted before the bit "0110001101" representing the most insignificant half (1000) of the input word. Is converted and transmitted over the serial link. At the receiver, each 10-bit word according to the present invention is decoded into one of the 8-bit words AD0-AD15, and one-to-one mapping between each word AD0-AD15 and half (4 bits) of each 8-bit input auxiliary data word. Because of this, the original 8-bit auxiliary data word can be reconstructed from the recovered words AD0-AD15.

Of course, the input auxiliary data applied to the transmitter (e.g., to the transmitter 1 ') may be a 4-bit word, in which case the transmitter may regard the received input auxiliary data word as a sequence of words AD0-AD15. There is no need to split (or wrap) into a 4-bit format before encoding. Meanwhile, the input auxiliary data may be pre-encoded as a sequence of 8-bit words AD0-AD15, and the pre-encoded auxiliary data is a sequence of 8-bit words AD0-AD15. It is provided to the transmitter in the form of.

In general, the encoded auxiliary data is transmitted on the same channel (CH0, CH1, and CH2) of the TMDS link through which video data is transmitted, but the auxiliary data is transmitted during the blank period between active video periods in which video data is transmitted. . 5 and 6 are timing diagrams showing signals transmitted according to this embodiment of the present invention. The upper nine signals of FIG. 5 represent signals input to the transmitter during the control data period and data island (in blank intervals), and the lower three signals of FIG. 5 represent control data in response to the upper nine signals. Auxiliary data (encoded using the 10-bit words of FIG. 4) and encoded control and sync signals (described below) transmitted over channels CH0, CH1 and CH2 during periods and data islands. Similarly, the upper nine signals of FIG. 6 represent signals input to the transmitter during the control data period and the active video period following the control data period at the end of the blank period (blank period of FIG. 5), and FIG. The lower three signals of six are supplemental data (encoded using the 10-bit word of FIG. 4) and conventional (to be transmitted) over the channels CH0, CH1 and CH2 in response to the upper nine signals. Video data encoded in a method, and encoded control and synchronization signals (to be described below).

In Figures 5 and 6:

The input data of the 24-bit word is provided to the encoding circuit of the transmitter for encoding. 5 relates to words that are auxiliary data words (each represented by D [23: 0] in FIG. 5). Figure 6 relates to words that are video data words (each represented by D [23: 0] in Figure 6). Eight bits of each input word (D {23:16]) are transmitted over channel CH2 (as a 10-bit encoded word CH2 [0: 9]) and the other eight bits of each input word (D [ 15: 8]) are transmitted over channel CH1 (as a 10-bit encoded word CH1 [0: 9]), and the other 8 bits (D [7: 0]) of each input word are channel CH0. Is sent (as a 10-bit encoded word CH0 [0: 9]). In one embodiment, the video data has an RGB format (and red, green and blue pixels are transmitted via CH2, CH1 and CH0, respectively), thus the channels CH2, CH1 and CH0 are each here (FIG. 3). Is sometimes referred to as a red (or R) channel, a green (or G) channel, or a blue (or B). On the other hand, the encoded (and transmitted) video data is in a luminance-chrominance format.

Waveform "DCK" represents the data clock. During each cycle of the data clock, 10 bits of each of the code words according to the present invention representing auxiliary data (or guard bands), or TMDS 10-bit code words each according to the conventional method of representing video data are channels CH0, CH1. And CH2) sequentially transmitted over the related channel. In some practical implementations, phase shifting circuitry is used to generate multiple, phase shifted versions of the clock DCK, and then (with the clock DCK itself) the timing of encoding, transmitting, and decoding operations. It is used to control. In some other implementations, a clock with a frequency 10 times the frequency of the DCK (but in phase with the DCK) can be used to control the timing of the encoding, transmission, and decoding operations, with one code bit It may be sent during each cycle of the faster clock.

Waveform "DE" in Fig. 6 is a video data enable signal, and waveform "AUX DE 'in Fig. 5 is an auxiliary data enable signal, if DE = 1 and AUX DE = 0, (D in Fig. 6). [23:16], D [15: 8] and D [7: 0] video data are encoded, and the serialized 10-bit word of the encoded video is transmitted through channels CH0, CH1 and CH2. If DE = 0 and AUX DE = 1, auxiliary data (shown as D [23:16], D [15: 8] and D [7: 0] in FIG. 5) is encoded and the encoded auxiliary A serially converted 10-bit word of data is transmitted over channels CH0, CH1 and CH2 If DE = 0 and AUX DE = 0, the transmitter ignores the signals applied to the data inputs, instead Control bits applied to its control inputs (bits CLT3 and CLT2, shown as CTL [3: 2] in FIGS. 5 and 6, and bits CTL1 and CLT0, shown as CTL [1: 0] in FIGS. 5 and 6). Encode pairs (in 10-bit TMDS code words) And serially convert the codewords, and transmit the serialized codewords over channels CH1 and CH2 In a DVI system, the transmitter sends the sync bit pair (HSYNC and VSYNC) applied to its sync input. Encode (in a 10-bit transition maximizing word), serially convert the encoded words, and transmit the serialized codewords over the channel CH0 when DE = 0. However, in a preferred embodiment of the present invention For each data island, a 10-bit transition-minimization code word representing HSYNC and VSYNC is transmitted in each pixel clock cycle unit over channel CH0 (e.g., one representing HSYNC, VSYNC and the other two bits). Code words are sent in pixel clock cycles.) In this way, HSYNC and VSYNC are repeatedly iterated with the 32-pixel clock period needed to transmit a packet during the data island. Can be sent. Preferably, each packet transmitted during the data island includes a 32-bit packet header, and each code word representing HSYNC and VSYNC transmitted during the data island also represents one bit of the packet header. Thus, 32-pixel clock cycles are required to transmit the entire 32-bit packet header.

Although FIGS. 5 and 6 have been described with reference to the two data enable signals "DE" and "AUX DE", the transmitter according to the present invention provides a logic for the signal data enable signals (e.g., signals DE and AUX DE). A portion (eg, a "core" processor of the transmitter 100 of FIG. 13 configured to perform the described encoding, serial conversion, and transmission in response to a combined enable signal indicative of the result of performing an "OR" operation. 114)). The core, an additional circuit outside of the transmitter, is a separate set of auxiliary data (eg 24-bit auxiliary data word) and video data (eg 24-bit video data word). And a video data enable signal DE, an auxiliary data enable signal AUX DE. It has an iterative sequence of values following the data enable signal: (DE = 0, AUX DE = 0), and (DE = 1, AUX DE = 0), and (DE = 0, AUX DE = 0). ), And (DE = 0, AUX DE = 1). Of course, the data enable signal may also occur as a sequence of other values, including a non-repeating sequence. For example, in some circumstances, ancillary data is transmitted only in a few blank intervals, not all video blank intervals. Therefore, the auxiliary data may be transmitted in one blank period and not in the next next blank period. The signals DE and AUX DE then have a sequence of values: (DE = 0, AUX DE = 0), and (DE = 1, AUX DE = 0), and (DE = 0, AUX DE = 0), and (DE = 0, AUX DE = 1), and (DE = 0, AUX DE = 0), and (DE = 1, AUX DE = 0), and (DE = 0, AUX DE = 0) , And (DE = 1, AUX DE = 0). The additional circuitry of the transmitter may include logic circuitry to OR the signals DE and AUX DE to generate a combined data enable signal. The additional circuitry may package the auxiliary data in a 4-bit format, encode each 4-bit portion of the auxiliary data into one of the words AD0-AD15 shown in FIG. 3, and encode a guard band word. It may be added to the stream of auxiliary data words AD0-AD15 at an appropriate timing, and the video guard band word may be added to the video data stream (or, at the appropriate timing, words of video data may be replaced with video guard band words). The additional circuitry includes a sequence of video data bursts (with video guard band words), and ancillary data (with guard band words) along with video data bursts and guard band words (e.g., with video guard band words). May be applied to the core in turn, and the combined data enable signal may also be applied to the core. The core performs all encoding, serial conversion, and transmission operations described with reference to FIGS. 5 and 6 in response to the combined data enable signal and video and auxiliary data bursts (rather than separate DE and AUX DE signals). do.

In a variation of the embodiments described in the previous paragraphs, the "additional circuitry" of the transmitter is coupled to receive and encode two or more auxiliary data sets (each set comprising a different type of auxiliary data) and It is composed. The additional circuit may further include an auxiliary data enable signal (eg, first and second auxiliary data enable signals AUX1 DE and AUX2 DE) for each of the video data set, the auxiliary data set, and the video data enable signal. (DE) is coupled and configured to receive a video data burst and a sequence of encoded auxiliary data bursts to the core of the transmitter: video data enable signal DE and auxiliary data enable signal AUX1 DE and AUX2 DE) has an iterative sequence of values: (DE = 0, AUX1 DE = 0, AUX2 DE = 0), and (DE = 1, AUX1 DE = 0, AUX2 DE = 0), and (DE = 0, AUX1 DE = 0, AUX2 DE = 0), and (DE = 0, AUX1 DE = 1, AUX2 DE = 0), and (DE = 0, AUX1 DE = 0, AUX2 DE = 1). The additional circuitry ORs the signals DE, AUX1 DE, and AUX2 DE to generate a combined data enable signal, and the combined data enable A signal (not the individual video data enable signal and the secondary data-enable signal) may include a logic circuit for applying to the core.

In each of one or more channels of the serial link (e.g. in each of the channels CH2 and CH1 in the data transmission according to the invention via a TMDS link), one word of the code word according to the invention (or the invention Suitable words of two or more of the guard band words in accordance with the &lt; RTI ID = 0.0 &gt; preferably &lt; / RTI &gt; preferably start at each of the encoded auxiliary data bursts (i.e. immediately after each "secondary preamble" of each blank interval), and at the end of each encoded auxiliary data burst. And at the beginning of each encoded video data burst (ie, immediately after the "video preamble" of each blank period) (as a guard band word or guard band word set).

In a preferred embodiment of the invention, the source data to be transmitted during the data island is encoded using a "robust" subset of the code word pool set. Each "robust" subset consists of a set of core words (sometimes referred to herein as "golden sets"), and each golden set consists of one or more core words (sometimes referred to herein as "golden words"). Each "golden word" of the golden set represents a single source data value (eg a source data word). If the golden set consists of two or more golden words, each of these golden words represents the same source data value. Clusters of core words in the full set are determined. Each cluster includes a "golden set" and, optionally, also one or more additional full sets of core words, where each additional core word is sent by each additional core word to transmit or transmit and decode the golden word. It is "similar to" the golden word of the golden set of the cluster in that it can be generated as a result of a bit error that may occur. Each received core word in one of the clusters is mapped to a source data value determined by the cluster golden set. Each mapping of a received code word from a cluster to a single source data value may provide error correction by remapping the word with an error in the cluster to a source data value most appropriately corresponding to the word with the error. have.                 

A full set of code words can be used to encode one type of data (eg, video data) for transmission over a channel of a serial link, the robust subset being transmitted over the same channel. Can be used to encode other kinds of data (e.g., other "auxiliary" data related to or useful with audio data or video data).

In one embodiment, each code word in each golden set (and each code word in a full set) is an N-bit word with an encoded version of M-bits, where M is an integer less than N. After a sequence transmission of N-bit golden words over the serial link, each of the received N-bit code words may be different from one of the golden words (if there is an error in transmission), or one of the transmitted golden words. May be the same as Each received N-bit code word in one of the clusters is decoded to produce a decoded M-bit word, each mapped to a source data value determined by the golden set of the cluster. do.

For example, in one embodiment, the full set of code words is a set of 10-bits and is a transition-minimizing TMDS-encoding word representing 256 8-bit source words. The robust subset of the full set consists of an 8-bit "golden word" representing a subset of the 256 8-bit source word pool set. In a preferred embodiment of the present invention, each of the 10-bit code words in one of the clusters received is decoded according to the TMDS decoding algorithm (or a modified version of the algorithm) to recover an 8-bit word, and the recovered 8 Each bit word is mapped to an 8-bit source word determined by the cluster.                 

Referring to Figure 7, for the preferred embodiment a cluster of the received word which is used in the Examples (e. G., The cluster (S _a and S _b) in FIG. 7) for each of the transmitted source data words (for example of the present invention, The concept of the method of mapping to words a and b) is explained. Next, a specific example of the mapping will be described with reference to FIG. 4.

7, the full set of (e.g., which may be used to encode the main data as auxiliary data is encoded by using only the "Golden word" in accordance with the invention of the full set) codeword 2 ^N of There are code words (2 ^N spaces) that can be used to encode other source data words, each source data word being a defined set of qubits. The golden word (2 ⁿ spaces) is a subset of a full set code word that can be used to encode 2n different source data words, each of which is an ordered set of n bits where " n " Integer less than N). Initially, the original source data (which may constitute words of any length) may be buffered and packed in ⁿ -bit format (ie, with ⁿ -bit members of a 2 ⁿ source data word set). Each other n-bit source data word can then be encoded as one of the golden words (in 2 ⁿ spaces) and transmitted over a serial link (typically over a single channel of the link). The transmission can be error prone or error free.

Clusters of a full set of code words may be pre-scheduled so that each cluster includes a "golden set" (which is one or more golden words), and optionally one or more full sets of additional code words, wherein the additional code Each word is similar to a golden word of the golden set of the cluster. In FIG. 7, for example, cluster S _a comprises a golden set constituting each of the golden words encoding source word a, and cluster S _b is a golden word encoding source word b. It includes a golden set that makes up each. Each received code word in one of the clusters is mapped to a source data value determined by the cluster golden set.

In one embodiment where N = 8 and n = 4, each code word in 2 ^N spaces is a 10-bit TMDS encoded word, and the 2 ⁿ spaces are a subset of the full set of 10-bit TMDS encoded words. Each transmitted 10-bit TMDS code word is decoded according to a TMDS decoding algorithm (or a modified version of the algorithm) to produce an 8-bit code word. In the above and other embodiments of the present invention, the transmission of the golden word (and any decoding of the golden word) may or may not be error.

For each particular golden word, some forms of transmission errors are expected when the channel has intersymbol interference or other degradation. Thus, for each golden word (ie, for each N-bit member of 2 ⁿ space), the cluster containing this golden word is preferably 2 ⁿ where a generation of a transmission error may occur during the transmission of the golden word. Contains all N-bit members of space. However, because the clusters are separate, the N-bit word in one cluster is excluded from all other clusters.

Each embodiment in accordance with the present invention utilizes one or more (and generally more than one) clusters containing one or more codes added to each golden word of the golden set. Some embodiments in accordance with the present invention utilize one or more clusters that include one or more codes added to each golden word of the golden set, and one or more other clusters that do not contain any code other than each golden word of the gold set. All clusters (e.g., of Figure 7 S _a, S _b etc) is (or during transmission, and decodes) each other because they are separated, during the transmission from each other, regardless of the error does not occur, or occurs, the cluster is received If it contains an N-bit code, the received code is remapped to a corrected source word.

In the embodiment of Figure 7, a full set of code words (2 ⁿ spaces) is a full set of 10-bit TMDS code words, where the 2 ⁿ spaces are TMDS codes representing a predetermined set of 16 different 8-bit source data words. It consists of words. Thus, each cluster contains a golden set of TMDS code words that includes a golden word representing one of 16 different source data words. In general, a 4-bit word of original source data is preliminarily encoded into 16 different 8-bit source data words, and each of the generated 8-bit source data words is then 10-bits of 2 ⁿ spaces for transmission. Encoded as one of the members. Thus, the robust subset (of the full set of TMDS code words) is 256 8-bit source data words determined when understood in the full set of TMDS code words (when decoded with the TMDS decoding algorithm or a variant of the algorithm). A) 10-bit TMDS code words that determine 16 predetermined 8-bit source data words. Each cluster is preferably "similar to" one of the golden words (i.e., a codeword similar to a golden word) in that it can occur not only from the golden word of the golden set, but also from bit errors during transmission of the golden word than other TMDS code words. Contains only one or more 10-bit TMDS code words.

The process of selecting a golden set from a full set of code words is very important. In general, the best choice for a particular golden set selected from a full set of binary code words depends on the particular coding implemented by the full set (ie, which of the bits of each code word of the full set is zero and which one is one. Specifics of cognition). As mentioned above, in some preferred embodiments, the code set of the golden set is chosen to be ones (e.g. on average) with serial sequences (in transit) having fewer consecutive zeros and ones, and thus selection Less sensitive to ISI during transmission than a full set of code words that are not (for example, the average number of consecutive zeros and ones per code word of a golden word is the full set of code words not selected as a golden word). Much smaller than).

In another preferred embodiment, the golden word is a criterion for which the Hamming distance between a golden word in one cluster and a golden word in another cluster exceeds a threshold and a hamming between golden words in other clusters. To satisfy a criterion that maximizes (in some sense) the actual distance that the distance is constrained to clusters separated from each other (e.g., the criterion where the average hamming distance between golden words in other clusters is maximized). Is selected. This allows the clusters to increase the number of members of "errored codes" (that is, codes other than the golden codes of one golden set) that can be included in each cluster, while keeping the constraints separate from each other. .

To implement the present invention, a receiver (eg, receiver 200 of FIG. 14) preferably responds to each input representing an element of the cluster (i.e., the cluster has one golden word and the golden word). In response to each of the four received code words, consisting of three code words similar to a word, configured to include a predetermined table that outputs one value (eg, source data word) determined by each cluster. The table maps each received code word in each cluster to a source word determined by the golden set of the cluster, or maps each received code word in each cluster to a golden word of the cluster's golden set ( Then, by the cluster golden set by conventional hardware or software within the receiver (or outside of the receiver) Or a decoded version of each received code word in each cluster to a source word determined by the cluster golden set, or a single decoded version of each decoded version of a received code word in each cluster. To a code word (then it is then mapped to a source word determined by the cluster golden set by conventional hardware or software, either in or outside the receiver at all times).                 

For example, receiver 200 of FIG. 14 includes a core processor (including core word recovery circuitry) that implements such a table, and mapping and decoding circuitry 20 (of system 208). Circuit 214 is configured to recover a 10-bit TMDS code word from data received on each of the TMDS channels CH0, CH1 and CH2. The circuit 20 maps each recovered word in one of the clusters (using a table) to a golden word of the cluster, decodes each of the golden words to produce an 8-bit decoding value (17 in the left column of FIG. 4). One of the 8-bit words). The 8-bit decoding value represents source words. In some embodiments of the invention, the mapping and decoding circuitry generates a 4-bit original source data word in response to each of the decoded 8-bit words (representing one of the words AD0-AD15 in FIG. 4). However, the circuit 20_ of FIG. 14 applies 8-bit decoded words to the decoding circuit 21.

The cluster (and input to the above-mentioned table in the receiver) may be part of a full set of code words (e.g., 2 ^N spaces in FIG. 7), and the combination of clusters may result in the total space of the code words For example, the entire 2 ^N space of FIG. 7), and the clusters are separated from each other. However, the possibility that one of the code words in the full set can be received in response to the transmission of one golden word can be very small or neglected, and thus such code words can be excluded from the cluster mode ( And may be missing from the table). In the latter case, the concatenation of the clusters does not cover the entire space of the code word (eg, the entire 2 ^N space of FIG. 7).

For convenience, in the claims, "to map each of the code words of a cluster to input data (or source data) values determined by the preferred word set (or golden set) of said cluster" or a modified representation of this representation is used. This representation refers to the direct mapping of each code word of a cluster to a source data (input data) value determined by the preferred word set (golden set) of the cluster, or in the golden word (or preferred word) of the cluster. Golden words of the cluster's golden set (or preferred word set), each of the code words of the cluster optionally followed by a mapping according to the conventional method to source data (input data) values determined by the golden set (or preferred word set). (Or to a preferred golden word), or to map a decoded version of each code word of a cluster to a source data (input data) value determined by the cluster's golden set (or preferred word set), Or the decoded code word to the Mapping the decoded version of each of the code words of the cluster optionally followed by mapping according to the conventional method to source data (input data) determined by the golden set of data (or preferred word sets). Point.

The mapping of the words in each cluster to the golden code is in some sense, for example, using clocked logic to replace the golden code for each received word belonging to a given cluster containing the golden code. The furnace may be performed in an "on the fly" manner. For example, in some embodiments, the receiver determines which bits of a received code word are likely to cause an error, and flips each bit that determines that the received code word is likely to be an error. and logic (in circuit 20 of FIG. 14) to apply the rules of mapping to golden codes by flipping. Meanwhile, the mapping method from words in each cluster to a golden code is performed using a look-up table that outputs a golden code in response to each word of the cluster including the golden code.

In general, an algorithm may be implemented (e.g., by software or logic circuitry) to determine which bits in the golden word (called "weak" bits) are most vulnerable to errors, and then include "errors." A process is implemented in which the vulnerable bits of the golden word are replaced with the erroneous version to determine a likely code word ", and then all (or a subset thereof) of" code words likely to contain an error ". A process is compared to the actual received code word is implemented to map each received code word that is a "code word likely to contain an error" to a corresponding golden word. The algorithm for identifying the vulnerable bits preferably identifies the bits most sensitive to intersymbol interference. An example is a single '0' bit in a stream of '1' bits.

If vulnerable bits are found, they are flipped within the golden word, thus generating a "code word likely to contain an error". One or more vulnerable bits may be flipped, depending on how vulnerable each of them is to an error. Alternatively, manually determine which bit pattern contains the vulnerable bits, and store the mask series in each bit pattern that the designer wants to address along the golden word. Then, the logic only needs to flip the appropriate bits in the golden word to generate a "code word likely to contain an error".

The process of selecting which code words are included in each cluster can be automated using logic circuitry (or software). For example, this process may include which bits in the golden word set are inverted (or missing) as a result of an error during transmission and / or restoration, and will contain the most error of each golden word and cluster with the golden word. The software (or logic circuit) for determining the version included therein may be systematically determined. As another example, for each code word already included in a cluster, four additional code words can be automatically added to the cluster: two left-shifted versions of the code word (one at open spot " 0 ", the other to" 1 "in the open spot); The second right-shifted version of the code word (one with "0" in open spot and one with "1" in open spot), to avoid assigning the same code word to two different clusters. Let the rule apply.

Although the clusters must be strictly separated, two or more clusters can conditionally contain the same code word (conventionally referred to as a "multi-value" code war), where the multi-value code word is predetermined It is "conditionally included" in the cluster in that it is mapped to the golden word of the cluster provided only when the condition of. The conditions associated with multi-value code words in different clusters must be different and only one of the conditions is selected so that it can be met in any particular case, so that the receiver selects a multi-value code word for each one particular cluster in a particular case. You should be able to map it to a golden word. In this embodiment, the receiver applies certain rules to previously-existing information to determine which of the above conditions are met in each particular case. For example, assume that word A containing the received error seems to have been transmitted as the word B most under condition X, and seems to have been transmitted as the most word C under another condition Y. The first cluster contains word B and conditionally includes word A (belonging to condition X). The second cluster contains word C and conditionally includes word A (belonging to condition Y). In this example, the receiver applies an algorithm to the already-existing information to determine which of the conditions (X and Y) is met during the transmission of the code word. For example, the receiver may determine whether the bit pattern of the most recent stream of code "Z" according to the present invention is DC balanced, and if condition X (not condition Y) is a bit pattern, It can be determined whether it meets DC-unbalanced in the forward direction, or whether condition (Y) (not condition (X)) is met. In this example, the already-existing information is the DC-balance level of the particular bit pattern. On the other hand, the already-existing information may be a recording in error form, or a pixel clock frequency, or jitter form, or other information.

Since a large number of possible errors can occur, it is possible that an expected error that would affect the transmission of two different golden words (of two different golden sets) can produce the same receive code. This includes two golden sets if one of the clusters is not intended to exclude the received code (or if the received code is not conditionally included within two or more clusters as described in the previous paragraph). It is possible to cause unwanted overlap in clusters. To avoid this overlap between clusters, preferably, less likely receive codes are excluded from the clusters involved. For example, the first cluster contains the first golden word, the second cluster contains the second golden word, and the received code word (not the golden word) is the result of the transmission of the first golden word. Is expected, and if the same received code word is expected to result in the transmission of the second golden word (possibility P2, where P2 is less than P1), then the first cluster contains the received code word, The received code word is not included in the second cluster.

For example, assume that word A containing the received error is most likely to be transmitted as the golden word B, and that the probability to be transmitted as word C is slightly smaller (word B and word C). ) Is only one bit different). In a preferred embodiment, two separate clusters comprising code words A, B and C are determined as follows: Golden word B and word A (which is generally another word similar to B) A first cluster comprising; A second cluster comprising a golden word (C) not included in the first cluster and one or more other words similar to C. With the clusters determined in this way, the transmission of word C, the result of an error during the transmission and / or restoration of the transmitted word C) the reception of word A, the received word A as a golden word B ), A bit error occurs. Preferably, the receiver comprises an error correction circuit (ECC), and the receiver is configured to apply to the ECC that the code word that is the result of the mapping of the received word (belonging to the cluster) is a golden word. Where appropriate, the ECC replaces word B in a block of code words with word C. For example, if the ECC determines that word B has one bad bit, the word B flips the bit into a word C, and then the bit is If there is only one bad bit for the entire ECC block, the ECC flips the bad bit to correct the error and converts word B to word C.

As mentioned above, in some implementations of the receiver according to the present invention, the receiver is configured to perform a two-step mapping of a received version of a golden word to a source data value: each received code word in a cluster is assigned to the cluster. A first step of mapping to a golden word of a golden set of; And a second step of mapping the golden word determined in the first step to a source word determined by the golden set of the cluster. In this implementation, an additional block of error correction code is sent with each golden word set, and the receiver corrects received code words containing errors that are not members of any cluster, and corrects them to golden words to the extent possible. To perform the first step of mapping before the error correction using the error correction code. In the latter implementation, the golden words and clusters according to the invention are preferably selected to implement a mapping using the degrees of freedom provided by performing error correction. For example, the golden word is minimized (or not maximized) such that the Hamming distance between any two golden words in other clusters is feasible, and the clusters are selected to satisfy a criterion of mutual separation. Can be. With the cluster containing this gold word, the number of error bits detected by the error correction circuit in the receiver can be minimized, and the overhead of the error correction code can be minimized.                 

For example, the receiver 200 of FIG. 14 may include a decoding circuit 21 for receiving and decoding an 8-bit decoded word from the " mapping and decoding " circuit 20, and the output from the circuit 21. And error correction circuit 22 coupled to receive the decoded and decoded words. Circuit 20 is configured to perform a first step of mapping to generate (and apply to circuit 21) a golden word in response to each received code word that is a member of one of the clusters in accordance with the present invention. Errors in some of the recovered words may prevent circuit 20 from mapping the restored words containing the error to a golden word. The decoded version of the golden word determined by the circuit 20, the restored word containing the error, and the error correction codes restored to the code word are applied to the error correction circuit 22. Circuit 22 corrects the error using an error correction code that passes through the received decoded golden word and corrects a code word containing an error that is not a member of any cluster in accordance with the present invention, and includes the error. Can be replaced with a golden word to the extent possible. As a variation of the implementation of the receiver 200 described, the circuit 22 can be omitted without error correction being performed.

Referring to Fig. 4, specific examples of the 17 golden word sets and the code word cluster set (each including one golden word) used in the preferred embodiment of the present invention will be described. In FIG. 4, the third column (from the left) represents the 17 golden words described above. 16 of the golden words are used to encode 16 different 8-bit source data words (8-bit source data words each representing 4 bits of original source data), and the other golden words (the first raw) The word " 1100110010 " is used only as a guard band word. Each golden word is a 10-bit TMDS encoded word. The fourth column (from the left) shows some possible error cases for each of the 10-bit golden words, and the fifth column is the result of decoding the 10-bit words in the corresponding fourth column according to the conventional TMDS decoding algorithm. 8-bit word, where the sixth column is simply the hexadecimal representation of the elements in the corresponding fifth column. The seventh column (from the left) includes an indication of whether each word in the corresponding fourth column is a member of a cluster that includes a golden word in the corresponding third column. In particular, the term " IGNORE " in the seventh column indicates that the word in the corresponding fourth column is not a member of the cluster comprising the golden word in the corresponding third column.

There are 17 clusters (separated by horizontal lines in FIG. 4): including golden word “1100110010” and code words “1110110010”, “1100010010” (all mapped to “free data” auxiliary guard band word “01010101”) A first cluster; A first word (for encoding the source data AD0) including the golden word "0011100101" and the code words "1011100101", "0001100101", "0011110101", and "0011100001" (all mapped to the source word AD0). 2 clusters; A third cluster (for encoding source word AD1) comprising a golden word “0110001101” and code words “0111001101” and “0110000101” (mapped to mode source word AD1); Another 14 representing clusters (each containing a different one of 14 different golden words, including words mapped to another one of source words AD2-AD15).                 

When the receiver recovers a code word (in the fourth column in FIG. 4) within one of the indicated clusters (here there is no "IGNORE" symbol in the seventh column corresponding to the restored code word), The receiver will map the reconstructed code word to the source word determined in the cluster's golden word (in the first column of FIG. 4) (this maps the reconstructed code word to the golden word of the cluster in the third column). Same as).

These code words in the fourth column labeled "IGNORE" in the seventh column are not members of the cluster containing the corresponding golden word. For example, the code word "1100111010" in the third row of Figure 4 is a member of the first cluster (including the golden word "1100110010") because the code word is a member of the cluster that contains the golden word "1000111010". The clusters must be separated from each other. The receiver results in a single bit error (with a relatively high likelihood) during transmission of golden word “1100110010” (in the first row of FIG. 4), and golden word “1000111010” (in the 45th row of FIG. 4). Although the receiver recovers the code word "1100111010" as a result of a single bit error (also having a relatively high probability) during the transmission of the source word ("01010101") determined by the golden word "1100110010" Rather than mapping to, it will map to an 8-bit source word AD10 (equivalent to mapping the received word to the golden word “1000111010”).

For another example, when the transmitter transmits the golden word “1100110010” (in the first row of FIG. 4), the receiver will recover the code word “1100110010” if there is no error (with a very high likelihood) during transmission. The receiver decodes the recovered word according to a conventional TMDS decoding algorithm to determine a decoded 8-bit word "01010101", and converts the recovered 8-bit word into a source word (which is a pre-data secondary guard band word). Will map to "01010101". The receiver restores a single bit error result (with a relatively low likelihood) word "0011001111" (in the 52th row of FIG. 4) during transmission of the golden word "0011001101", and the receiver also recovers this restored word. Decoding with a conventional TMDS-decoding algorithm (which inverts the eight most insignificant bits as a result of the value of the DC balancing bits) will determine the same decoded 8-bit word ("01010101"). The receiver will map the received word (same as mapping the received word to the golden word “1000111010”) to the source word “01010101”.

Occasionally, the term "golden word" refers to an 8-bit word source word (e.g., in FIG. Word in the left column).

Referring to the guard band words according to the present invention described above, each guard band word may have clusters for each guard band word, each of which includes two or more code words (including guard band words). In this case, it may be a golden word (as in the example of FIG. 4). On the other hand, the guard word is not a golden word, and can be surely distinguished from the golden word.

In each embodiment of the present invention, where one or more guard band words have been used, each guard band word is defined by a receiver between an encoded control (or synchronous) word transmission and an encoded data transmission (by a guard band word or words). Should have a bit pattern that makes it possible to more clearly identify the associated transition. Thus, an additional element in the selection of the golden set according to the invention is that the golden set must contain an appropriate guard band word (ie, the guard band word is a golden word), or each of the golden words of the golden set It must be clearly distinguished from each guard band word used. For example, the 17 golden word sets shown in FIG. 4 are used to identify the start of an auxiliary data burst (with the bit pattern “1100110010” shown in the third column of the first row of FIG. 4). Contains a word. As shown in Figure 5, this "pre-data" auxiliary guard band word is preferably repeated twice each channel (CH2 and CH1) at the beginning of each of the encoded auxiliary data (i.e. immediately after each auxiliary preamble). Is sent from). Since the last bit of each specific encoded control word transmitted to the channels CH2 and CH1 (during the auxiliary preamble) is "0" as described above, the first transmitted of the code word selected as the pre-data secondary guard band word is transmitted. The bit becomes " 1 ", increasing the reliability of the receiver identifying the beginning of the transmitted auxiliary data burst.

In addition, the set of 17 golden words shown in FIG. 4 includes a word (golden word "0011001101" corresponding to input word AD11) used to identify the end of the auxiliary data burst, and also a video guard band word. It is used as. As shown in Figure 5, this "post-data" auxiliary guard band word is preferably 2 at the end of each of the encoded auxiliary data bursts (i.e., just before each video preamble) on each of the channels CH2 and CH1. Is sent repeatedly.

The pre-data auxiliary guard band word need not be repeated (transmitted twice) at the beginning of each auxiliary data burst, and the post-data auxiliary guard band word need not be repeated at the end of each auxiliary data burst. . In a preferred embodiment (as shown by Figure 5), data shift errors between channels that may occur during the transmission and restoration of data (e.g., trace length of data received on channel CH1 and channel CH2 Each error is repeated to make it easier for the receiver to find and correct). In another embodiment of the present invention, the auxiliary guard band words are repeatedly transmitted (or transmitted only once) at the beginning of each auxiliary data burst, and repeatedly transmitted at least twice at the end of each auxiliary data burst. (Or just once).

4, the golden word " 0011001101 " (corresponding to the input word AD11) is used as a codeword for encoding a 4-bit amount of auxiliary data representing the input word AD11, and post-data. In addition to being used as an auxiliary guard band word, it is used as a video guard band word that identifies the beginning of a video data burst. As shown in Fig. 6, the video guard band word is preferably transmitted repeatedly two times at the beginning of each burst of encoded video data (i.e. immediately after each video preamble). The first two bits of the video guard band word, since the last two bits of the encoded control or sync word transmitted (at the end of the video preamble) in each of the channels CH1 and CH2 are likely to be "11" as described above. The transmitted bits are selected as "00" to increase the reliability with which the receiver can identify the beginning of the transmitted video data burst.

The video guard band word need not be repeated (transmitted twice) at the beginning of each video data burst. In the embodiment of FIG. 6, it has been repeatedly transmitted to secure transmission (through each of channels CH0, CH1 and CH2) of code words representing even numbers of pixels during a burst. In another embodiment, the video guard band word is repeated (or transmitted only once) two or more times at the beginning of each video data burst.

In some embodiments of the invention, two (or more than two) streams of video data are transmitted (via one, two, or more than one channel). For example, two or more video data streams may be transmitted in a time-multiplexed fashion over each of one or more channels (0, 1, 2) of FIG. When bursts of different streams of video data are transmitted sequentially over one channel, different video guard band words are identified at the beginning (and / or end) of each burst, each of which is identified by a different video guard band word. Can be sent. Similarly, two (or more than two) auxiliary data streams may be transmitted over one, two or more than two channels. If bursts of different auxiliary data streams are sent sequentially over one channel, then different auxiliary guard band words are transmitted at the beginning (and / or end) of each burst, each of which is identified by a different guard band word. Can be.

Where encoded data is transmitted sequentially over multiple independent channels, the DE shift in each individual channel can be independently corrected (according to the invention) using the guard band words of each channel. Bits transmitted over multiple channels of a TMDS link (or TMDS-like link or other serial link) by one pixel clock cycle (or one or more pixel clock cycles) in any direction (by ISI or other noise source on the link) Since there may be a mismatch between the DE transitions represented by the same guard band word set (each of which is a member of the code word set according to the present invention), the code word according to the present invention transmitted over each channel is preferably used. The beginning and / or end of each encoded data burst (e.g., the end of each channel's auxiliary preamble, the bottom / or beginning of each channel's video preamble, and / or the end of each channel's video preamble). In the method according to the invention. This can improve channel to channel alignment and data integrity. The necessity of having an adequate number of guard band words available is one element of the choice of another set of code words in the present invention.

The guard band word (transition between the expected bit pattern and the burst of data encoded according to the invention following this pattern, or the transition between the burst of data encoded according to the invention and the expected bit pattern following this data The purpose of repetitive transmission is to avoid two kinds of transition mismatches: identifying transitions too early and transitions too late. By repeatedly transmitting a sequence of N guard band words, the present invention prevents this pixel shift error from exceeding N pixels in either direction. For example, if a sequence of N post-data guard band words is added to an encoded data burst, the present invention ensures that the last data value was not lost when an N pixel shift to the left occurred (post -Only data guard band words are lost). In general, only a sequence of N post-data guard band words need to be used with the N pre-data guard band words.

In the preferred embodiment (shown in FIG. 5), the auxiliary guard band words transmitted at the beginning and end of each auxiliary data burst on channels CH2 and CH1 are at the beginning and end of each auxiliary data burst on channel CH0. Not sent. Rather, a specific encoding method is used to determine the code word according to the invention of the first two and the last two 10-bits transmitted in each auxiliary data burst on channel CH0. In particular, the first of each auxiliary data burst Two bits of auxiliary data input during each of the two and last two pixel clock cycles are encoded and transmitted (in contrast, four of the auxiliary data input during every other pixel clock cycle of each respective burst of burst as described above). Bits are encoded and transmitted). Two bits of input auxiliary data to be transmitted during the first clock cycle are encoded into one of words AD0, AD1, AD2 and AD3 of FIG. 4, and two bits of input auxiliary data to be transmitted during the second clock cycle are represented by the word AD0, Encoded to the other one of AD1, AD2 and AD3). Thus, the first two 10-bit words transmitted in the burst are variations of the code words according to the invention representing these two words (AD0, AD1, AD2 and AD3) (thus the first four bits of the input assistance data). ). Similarly, two bits of input auxiliary data to be transmitted during a cycle before the last clock cycle are encoded into one of the words AD0, AD1, AD2 and AD3 in FIG. 4, and two bits of input auxiliary data to be transmitted during the last clock cycle. The bits are encoded into one of the words AD0, AD1, AD2 and AD3. The last two 10-bit words transmitted in bursts are variations of the code words according to the invention representing these two words (AD0, AD1, AD2 and AD) (thus representing the last four bits of the input assistance data). . This method of encoding a two-bit auxiliary data word using four 10-bit golden words encodes a four-bit auxiliary data word using sixteen 10-bit golden words, sometimes referred to herein as "TERC4" encoding. In contrast to this, sometimes referred to as "TERC2".

More generally, when ISI is present on a serial data transmission channel, other control or sync bits (e.g., a 10-bit control character representing bits CTL0; CTL1 or CTL2: CTL3 in the DVI description) may be controlled. It may cause other errors on the video (or auxiliary) data bits to be transmitted immediately after the character Preferably, this is recognized and used as an element for selecting a code word according to the invention used for transmitting video (or auxiliary) data. On the other hand, the control code transmitted immediately before the data (encoded according to the invention) is controlled to reduce the ISI impact.

In another embodiment of the invention, the encoded auxiliary data burst and the encoded video data burst are transmitted over a serial link (not necessarily a TMDS link), the auxiliary data using a code word set according to the invention. Encoded according to the method of the present invention. The code word set according to the invention comprises a "video" guard band word transmitted at the beginning of each encoded video data burst, and a "secondary" guard band word transmitted at the beginning of each encoded auxiliary data burst. In one embodiment, the video guard band word is also used for the second purpose: encoding auxiliary data. In a preferred implementation of this embodiment, the encoded video data is transmitted during an active video period when the video data enable signal is high (ie, when the control signal "DE" satisfies DE = 1), and encoded control (or synchronization). Signal and encoded auxiliary data are transmitted during a blank period between the active video stock price (the video data enable signal is low). The video guard band word is transmitted at the beginning of each active video period. Each blank interval is a "secondary" preamble interval (between the falling edge of the video data enable signal and the beginning of the secondary data burst), in which a particular type of control (or sync) signal is transmitted, one after the secondary preamble interval. The above auxiliary data periods (each auxiliary data period includes an auxiliary guard band word followed by an encoded auxiliary data burst), and a "video" preamble period between the last auxiliary data period and the next active video period. In general, the purpose of using a guard band word in accordance with the present invention is to provide a receiver with a transition between a first guard band word transmitted at the beginning of an encoded data burst and the last bit transmitted before this guard band word, It is to be able to recognize the transition between the last guard band word transmitted at the end of the encoded data burst and the first bit transmitted after this guard band word.

In this embodiment of the invention, conventional encoding algorithms are used to encode the main data (which may be video data but need not be) for burst transmission over a serial link, and auxiliary data (e.g., Audio data or other forms of data that may be transmitted at a lower data rate than the main data) are encoded in accordance with the invention for transmission in bursts (between encoded main data bursts) over a serial link. The full set of code words used to encode the main data has one or more code words for each of the 2 ^N different words of main data (sometimes called the source data word). A subset according to the present invention of this full set has one or more code words for each other word less than 2 ^M (where M <N) of auxiliary data (also sometimes referred to as source data words). The data is buffered and packed in M-bit format (ie, in words each composed of M bits). Each possible value of the M-bit source data has a preselected code in the 2 ^M word spaces provided by the code word according to the invention. The M-bit words of the supplementary data are mapped to code words according to the invention in the 2 ^M word space, which are transmitted over the link.

When selecting a golden word according to the invention which is used to transmit data encoded according to the invention (e.g. auxiliary data separate from video data), which bits are different bits (among multi-bit encoded words). It is important to observe whether there is a greater risk that an error may occur than the For example, when using TMDS-encoded golden words to transmit auxiliary data, the DC balancing bits and the transition control bits (eg, bits Q [9], and Q [8]) are more than other bits. Has a large risk of error. Every bit that occurs during the processing of the DC balancing and transition control bits can affect other bits of the multi-bit encoded words. Thus, the 1-bit error in one of the critical bits can be changed to a burst error. Preferably this influence is taken into account in the selection of the code word according to the invention from a full set of TMDS-encoded words.

2 and 8, a format and timing of data to be transmitted through a TMDS link in a system according to a preferred embodiment of the present invention will be described. In these embodiments, the transmitter (i.e., the transmitter 1 'of FIG. 2) performs the TMDS encoding algorithm (respectively through the TMDS encoding algorithms) on the video channels CH0, CH1 and CH2 of the TMDS link during the active video period when the control signal DE is high. Transmit an 8-bit video data word (encoded into a 10-bit transition-minimization code word) during the data island between active video periods (also DE is high). An algorithm is used to transmit packets containing a 4-bit word (generally a 4-bit audio data word) encoded with a 10-bit transition-minimizing code word, preferably a 10-bit golden word. And during the " control data " period (DE is low) between the data islands, the transmitter indicates a control word (2 control bits: CTL0 and CTL1 or CTL2 and CTL3, respectively) via channels CH1 and CH2. I transmit a control word encoded in a 10-bit, transition-maximized code word, and a 10-bit, transition-maximization code representing two sync bits: HSYNC and VSYNC, respectively, through channel CH0. Transmits a synchronous word, encoded during the active video period, during each active video period (e.g., receiver 2 'of FIG. 2), HSYNC, VSSYNC, CTL0, CTL1, CTL2 and CTL3 are the active video periods. Assume that they maintain their values when is started.

Each data island contains one or more packets, each packet being transmitted over a period of 32 pixel clock cycles. As shown in FIG. 8, a portion of each packet is transmitted on each of the channels CH0, CH1 and CH2 during the 32-pixel clock period. It can be seen that during each pixel clock cycle, the transmitter transmits one serialized 10-bit TMDS code word on each of the channels CH0, CH1 and CH2. Thus, each packet contains 96 (= 3 * 32) TMDS code words, each code word representing a 4-bit source word.

During each data island, a transition-minimization code word representing HSYNC and VSYNC bits is transmitted over channel CH0 (e.g., one code word representing HSYNC bits, VSYNC bits, and two other bits is the pixel clock). Transmitted in cycles). Preferably, each packet transmitted during the data island includes a 32-bit packet header, and each code word representing HSYNC and VSYNC transmitted during the data island also represents one bit of the packet header.

In the mode in which no data islands are transmitted, each control data period is the entire horizontal (or vertical) blank period between two consecutive active video periods. In another mode, the transmitter inserts one or more data islands into each of the horizontal blank period and the vertical blank period (or within each of the subset of the blank periods).

In each of the channels CH1 and CH2, a "data island" preamble word is repeatedly transmitted (in the control data period) immediately before each data island, and the video preamble word is in the control data period just before each active video period. Transmitted repeatedly. In each of these channels, a burst of eight identical data island preamble words is preferably transmitted immediately before each data island, and preferably a burst of eight identical video preamble words is transmitted immediately before each active video period. Each data island preamble word transmitted on channel CH1 is a 10-bit TMDS code word representing CTL0 = 1 and CTL1 = 0, and each data island preamble word transmitted on channel CH2 is CTL2 = 1. And a 10-bit TMDS code word representing CTL3 = 0. Each video preamble word transmitted on channel CH1 is a 10-bit TMDS code word representing CTL0 = 1 and CTL1 = 0, and each video preamble word transmitted on channel CH2 is CTL2 = 0 and CTL3 = 0. Is a 10-bit TMDS code word.

In the preferred embodiment described with reference to FIGS. 2 and 8, each data island in each of the channels CH1 and CH2 has two identical guard band words (the above described data island guard band words “DATA Island GB” = 0b1100110010). Each active video period starts and ends with a burst of two identical guard band words (the above mentioned words " Video GB (CH0, CH2) " = 0b0011001101 in channel 2 (CH0 and CH2), and the details in channel CH1). Start with a burst of one word "Video GB (CH1) = 0b1100110010). These guard band words and preamble words described in the previous paragraph are selected to have a pattern that allows the receiver to reliably identify each leading and trailing edge of each data island and each leading edge of an active video period. . Each data island of channel CH0 has two identical guard band words (0xC, 0xD, 0xE, and 0xF values, depending on the HSYNC and VSYNC values so that the receiver can reliably identify each leading and trailing edge of the data island). The transitions begin and end with a burst of a minimized TMDS 10-bit code word).

In a preferred embodiment, the example (sometimes referred to as "TERC4 coding") encoding method below, rather than the version described with reference to Figure 4, is a 10-bit transition-minimized TMDS serialized and transmitted during each data island. Used to encode four bits of audio data (or other auxiliary data) representing a code word (the TMDS code words listed are "golden words"):

Source WordTMDS Code Word

(bit3, bit2, bit2, bit0)

0000: q_out [0: 9] = 0b0011100101;

0001: q_out [0: 9] = 0b1100011001;

0010: q_out [0: 9] = 0b0010011101;

0011: q_out [0: 9] = 0b0100011101;

0100: q_out [0: 9] = 0b1000111010;

0101: q_out [0: 9] = 0b0111100010;                 

0110: q_out [0: 9] = 0b0111000110;

0111: q_out [0: 9] = 0b0011110010;

1000: q_out [0: 9] = 0b0011001101;

1001: q_out [0: 9] = 0b1001110010;

1010: q_out [0: 9] = 0b0011100110;

1011: q_out [0: 9] = 0b0110001101;

1100: q_out [0: 9] = 0b0111000101;

1101: q_out [0: 9] = 0b1000111001;

1110: q_out [0: 9] = 0b1100011010;

1111: q_out [0: 9] = 0b1100001101;

Video GB: q_out [0: 9] = 0b1100110010;

(CH1)

Video GB: q_out [0: 9] = 0b0011001101;

(CH0, CH2)

Data Island GB: q_out [0: 9] = 0b1100110010;

(CH1, CH2)

In the TMDS code words listed above, the most insignificant bit (q_out [0]) of each code word is the first transmitted bit, the most significant bit (q_out [9]) is the last transmitted bit, and the word Video GB (CH1). )) Is the video guard band word transmitted on channel CH1, and the word Video GB (CH0, CH2) is the video guard band word transmitted on channels CH0 and HC2, and the word Data Island GB (CH1). , CH2)) is the data island guard band word transmitted on channels CH1 and HC2. In an embodiment in which the golden words listed above are transmitted during a data island on the channels CH0, CH1 and CH2 of the TMDS link, the video words transmitted on the channels CH0, CH1 and CH2 during the active video period are transition-minimized. It can be encoded using a full set of TMDS code words.

When the code words listed above are used, the video preamble is a 10-bit transition-maximized TMDS code word (transmitted in CH1) indicating control bit values CTL0, CTL1 = 1, 0, and control bit values CTL2, CTL3 = The repetition (preferably 8 repetitions) of a 10-bit transition-maximized TMDS code word (sent at CH2) representing 0,0 is determined, and the data island preamble is the control bit values CTL0, CTL1 = 1,0 Repetition of the 10-bit transition-maximized TMDS code word (transmitted in CH1), and the 10-bit transition-maximized TMDS code word (transmitted in CH2), indicating the control bit values CTL2, CTL3 = 1,0. (Preferably 8 iterations). This combination of guard band words and preambles allows the receiver to reliably identify the beginning of each active video period and the beginning and end of each data island.

Using the list of codewords and preamble words described in the previous two paragraphs, a particular encoding method is preferably used in the invention of the first two and the last two 10-bits transmitted on each data island on channel CH0. Used to determine the code word accordingly. In particular, two bits of input auxiliary data are preferably encoded and transmitted on channel CH0 for each of the first two and last two pixel clock cycles of each data island (where the four bits of the input auxiliary data are As described above, Giga is encoded and transmitted on channel CH0 for all other pixel clock cycles of the data island). The two bits of input auxiliary data to be transmitted on CH0 during each of the first, second, last previous and last pixel clock cycles of each data island are preferably encoded with one of the above-listed code words 0b0111000101, 0b1000111001, 0b1100011010, and 0b1100001101. do.

In the system according to the preferred embodiment of the invention described with reference to Figs. 2 and 8, each data island has one or more packets (the minimum duration of which is two pixel clock cycles for the leading guard band and the trailing guard). Limited to 36 pixel clock cycles, including two pixel clock cycles for the band). Each data island must contain an integer number of packets, and preferably the maximum number of packets in each data island is 14 (to ensure the reliability of the data in the data islands). Error detection and correction (preferably BCH error detection and correction technique, a well-known error detection and correction technique named after developers Bose, Chauduri, and Hocquenghem) is applied to each packet during each data island.

A preferred format method for each packet is described with reference to FIG. Each packet has a 32-bit (4-byte) packet header and four sub-packets (each consisting of 64 bits = 8 bytes), as in packet P of FIG. In FIG. 9, the subpackets are represented by subpacket 0 (or SP0), subpacket 1, subpacket 2 and subpacket 3. Each subpacket contains 56 data bits followed by eight BCH parity bits (ie, seven bytes, each byte corresponding to one 10-bit TMDS code word). Nine data bit packets are sent in pixel clock cycles. Of these, one bit data (header bit) is transmitted in the unit of pixel clock cycles (in the form of one 10-bit TMDS code word encoding HSYNC and VSYNC bits) on the channel CH0, and four bit data are transmitted. Each of the channels CH1 and CH2 is transmitted in pixel clock cycle units (in the form of one TMDS code word). During each pixel clock cycle, the TMDS decoding circuit in the receiver recovers 4 bits of data from channel CH0 (ie, from one TMDS code word), recovers 4 or more bits of data from channel CH1, 4 or more bits of data are recovered from the channel CH2.

In FIG. 9, data and parity bits of subpacket 0 are identified as "BCH block0", data and parity bits of subpacket 1 are identified as "BCH block1", and data and parity bits of subpacket 2 are referred to as "BCH block2". ", And the data and parity bits of subpacket 3 are identified by" BCH block3 ". The packet header includes 24 data bits (3 bytes of data) followed by 8 BCH parity bits (these data and parity bits are identified as "BCH block4" in FIG. 9).

Preferably, the BCH parity bit for each packet header is a BCH generated using the polynomial G (x) = 1 + x ⁶ + x ⁷ + x ⁸ (with 127 iteration cycles) by the generator of FIG. 9A. (32, 24). Preferably, the BCH parity bits for the sub-packets are generated by the generator of FIG. 9B using the polynomial G (x) = 1 + x ⁶ + x ⁷ + x ⁸ (with 127 iteration cycles). 64, 56). Preferably, the transmitter according to the embodiment of the present invention comprises the circuit of FIG. 9B for generating BCH parity bits for 56 data bits of each subpacket, and BCH parity bits for 24 data bits of each packet header. Circuit for FIG. 9A.

A receiver in accordance with a preferred embodiment of the present invention, in which a BCH parity bit is received using FIG. 9A and FIG. 9B, receives a received packet from the circuit of FIG. 9D (for generating a BCH syndrome from 64 bits of each subpacket). And the circuit of FIG. 9C (for generating a BCH syndrome from the 32 bits of each packet header).

More generally, the circuits of FIGS. 9B and 9D generate error correction code bits (e.g., parity bits or syndrome bits) from a parallel stream of input data, and generate error correction bits from a cyclic polynomial such as a BCH polynomial. It implements features in accordance with the present invention that are useful for a variety of contexts, reducing the number of cycles needed to generate and reducing the number of cycles needed to calculate the syndrome code generated by a cyclic polynomial. This feature of the invention is that an error correction code (e.g., BCH parity bits, and syndromes generated from BCH parity bits and data) must be generated from a partially parallelized data stream, and the small size of the next block of input data must be generated. It is useful for a variety of systems, where a number (e.g. 2) of input bits may be used while generating an error correction code for the current block of input data. In such a system, the even bits of each block of input data are simultaneously (with odd bits from each of the input data blocks according to the present invention) to generate an error correction code for each block in a reduced number of clock cycles. In parallel). Without using the present invention, in order to generate the same error correction code within the same time that the code can be generated (using the system clock) in accordance with the present invention, it is used in the system for other purposes than generating the error correction code. It is necessary to use a clock having a frequency several times the frequency (for example, 2x, 3x, or 4x). Implementing multiple system clocks is disadvantageous in that clocked logic that can operate faster and a system clock version with multiple frequencies are required to exist. Generating a clock with frequency is usually expensive because a clock multiplier circuit that typically includes a PLL is required).

Each of the error correction code generating circuits of FIGS. 9A and 9B includes a control bit C1 that controls whether the circuit passes the input data received at the input to its output and whether the circuit applies the error correction code to its output. Use Referring to FIG. 9A, during the first " z " clock cycle, the J bit C1 is high, causing a z-bit block of input data INPUT to be provided to the shift register, and an error correction code is generated, The clock is passed through the multiplexer 300 to the output. When the circuit of Figure 9A is implemented in a transmitter according to the present invention (e.g., a preferred implementation of transmitter 100 of Figure 13), a 24-bit block of packet header bits is input while C1 is high (and To the output). Then, C1 goes low and causes the multiplexer 300 to pass the output of register Q7 instead of the input data. While C1 is low, eight BCH parity bit sequences are shifted for eight clock cycles to exit register Q7. While C1 is low, the source of input data is inactive.

The circuit of FIG. 9B operates similarly to the circuit of FIG. 9A. However, the circuit of FIG. 9B includes a shift register having two input nodes and two output nodes where each input node receives a different subset of input bits (rather than a shift register having one input in FIG. 9A), Only (N / 2) +1 clock cycles are needed to generate 8 BCH parity bits (compared to FIG. 9A circuit, requiring N + 1 clock cycles to generate the same bits), (4 Four additional clock cycles are required to shift out the eight BCH parity bits (by shifting the four BCH parity bits from the register Q6) while shifting the BCH parity bits from the register Q7. At the end of the current block of input data, the register value (each of registers Q0-Q7 in FIG. 9B), the first even bit ("IN [0]") and the first odd bit (") of the next block of input data. Given IN [1] "), the BCH parity bits (applied to the multiplexers 301 and 302 from two shift registers) for the current block of input data are always determined. If the circuit of Figure 9B is implemented in a transmitter in a preferred embodiment of the present invention (e.g., a preferred implementation in transmitter 100 of Figure 13), then a sub-packet of 56 data bits is generated during 28 clock cycles where C1 is high. It is received at the input (and passed to the output) along with the other pairs of subpacket bits, IN [0], IN [1], received in clock cycles. Typically, you have a shift register with "m" input nodes, and generate the error correction code for the current block, while writing the "m" bit of the next block of input data (one of the "m" bits in each shift register input). The modified design of FIG. 9B, which receives, may generate an error correction code (eg, BCH parity bit) for the current block of input data in a “k / m + p” clock cycle, and (C1 low one). When the error correction code is shifted out in the "n / m" cycle, "n", "p" and "k" are the size of each input block and the error correction code generated for each input block. This parameter is determined by the number of bits.

In the general operation of the circuit of FIG. 9B, the first even bit ("IN [0]") and the first odd bit ("IN [1]") of the next block of input data are shown in FIG. 9B at the timing at which C1 transitions high-low. Is applied to the input of the circuit, and the IN [0] and IN [1] values continue to be applied to the input while C1 remains low. At the timing at which C1 transitions high-low, to refer to each bit of the registers Q0, Q1, Q2, Q3, Q4, Q5, Q6 or Q7, "Q0, Q1, Q2, Q3, Q4, Q5, Use the notation Q6 or Q7 ". When C1 is low, bits Q0, Q2, Q4 and Q6 are shifted out from one shift register to multiplexer 301 (because during this process the output of AND gate 308 is low) and bit Q1 , Q3, Q5 and Q7 are shifted out from one shift register to multiplexer 302 (because during this process the output of AND gate 309 is low). The values of these bits are as follows:

Q0 = ((Q7 ^ IN [0]) ^ (Q6 ^ IN [1])) &C1;

Q1 = (Q7 ^ IN [0]) &C1;                 

Q2 = Q0;

Q3 = Q1;

Q4 = Q2;

Q5 = Q3;

Q6 = Q4 ^ (((Q7 ^ IN [0]) ^ (Q6 ^ IN [1])) &C1; and

Q7 = Q5 ^ ((Q6 ^ IN [1]) & C1),

Where "^" represents an exclusive OR operation and "&" represents an AND operation.

Bits Q0, Q1, Q2, Q3, Q4, Q5, Q6 and Q7 are generated when C1 is high. If C1 is low, the circuit of FIG. 9B functions as a simple shift register, shifts Q0, Q2, Q4, and Q6 to multiplexer 301, and shifts Q1, Q3, Q5, and Q7 to multiplexer 302. .

The same values of the bits Q0, Q1, Q2, Q3, Q4, Q5, Q6 and Q7 output from the circuit of FIG. 9B are output from the circuit of FIG. 9A (FIG. 9A and FIG. 9 before C1 transitions to high-low). Suppose that the same input values are applied to the circuit of 9b, and the first odd bit IN [1] of the next block is applied as the input value and the control bit C1 transitions high-low at the next clock edge. The circuit 9a requires eight clock cycles to shift these values to the multiplexer 300, while the circuit of FIG. 9B only requires four clock cycles to shift these values to the multiplexers 301 and 302.                 

The syndrome indicates whether the transmitted sequence with its error correction code has been modulated. If no modulation has occurred, the syndrome is zero. If any bit is modulated, the syndrome will not be zero. Depending on the number of modulated bits and the hamming distance of the encoded sequence, the syndrome may be used to correct the modulated bits.

Each of the syndrome generating circuits of FIGS. 9C and 9D has a control bit C2 that controls whether the circuit passes input data received at the input to its output and whether the circuit applies the syndrome bit to its thrust. I use it. Referring to FIG. 9C, during the first " z " clock cycle, control bit C2 is high and provides the input data INPUT of the z-bit block to the shift register, passing through the multiplex 303 to the output. Be sure to If the receiver of FIG. 9C is implemented in a receiver in accordance with a preferred embodiment of the present invention (e.g., a preferred implementation of receiver 200 of FIG. 14), a 32-bit packet header is input for each interval where C2 is high ( And passed to the output). When C2 transitions low, the multiplexer 303 passes the output of the register Q7 instead of the input data. When C2 is low, the sequence of eight syndrome bits is shifted out in register Q7 for eight clock cycles.

The circuit of FIG. 9D operates similarly to FIG. 9C, but the circuit of FIG. 9D has two input nodes and two output nodes (unlike shift registers with only one input node in FIG. 9C), each input node having an input. A shift register that receives another subset of bits, and only (N / 2) +1 clock cycles to generate eight syndrome bits (N + 1 clock cycles to generate the same bits in FIG. 9C). On the other hand, it only requires four additional clock cycles (by shifting four syndrome bits from register Q6 and four syndrome bits from register Q7) to shift out the eight syndrome bits. . At the end of the application of the current block of input data, the register value (each of registers Q0-Q7 in FIG. 9D), the first even bit ("IN [0]") and the first odd bit (") of the next block of input data. Given IN [1] "), the syndrome bits (applied from registers Q6 and Q7 to multiplexers 304 and 305) for the current block of input data are always determined. If the circuit of Figure 9D is implemented in a receiver in a preferred embodiment of the present invention (e.g., a preferred implementation in receiver 200 of Figure 14), then a 64-bit subpacket will be generated during 32 clock cycles where C2 is high. Received at the input with another pair of subpacket bits received in clock cycles, IN [0], IN [1] and another pair of subpacket bits output in clock cycles OUT [0], OUT [1] (And passed to the output). Typically, you have a shift register with "m" input nodes and receive the "m" bit (one of the "m" bits in each shift register input) of the next block of input data while generating the syndrome for the current block. 9D, the modified design of FIG. 9D may generate syndrome bits for the current block of input data in a “k / m + p” clock cycle, and “n / m” (eg, when C2 is low). The syndrome bits may be shifted out in a cycle, where "n", "p", and "k" are parameters determined by the size of each input block and the number of syndrome bits generated for each input block.

In the general operation of the FIG. 9D circuit, the first even bits ("IN [0]") and the first odd bits ("IN [1]") of the next block of input data are plotted at the timing when C2 transitions high-low. Applied to the input of the circuit of 9d, and the IN [0] and IN [1] values continue to be applied to the input while C2 remains low. At the timing at which C2 transitions high-low, to refer to each bit of the registers Q0, Q1, Q2, Q3, Q4, Q5, Q6 or Q7, "Q0, Q1, Q2, Q3, Q4, Q5, Use the notation Q6 or Q7 ". When C2 is low, bits Q0, Q2, Q4 and Q6 are shifted out from one shift register to multiplexer 305 (because during this process the output of AND gate 311 is low) and bit Q1 , Q3, Q5 and Q7 are shifted out from one shift register to multiplexer 304 (because during this process the output of AND gate 310 is low). The values of these syndrome bits are as follows:

Q0 = IN [1] ^ ((Q6 ^ Q7) &C2);

Q1 = IN [0] ^ (Q7 &C2);

Q2 = Q0;

Q3 = Q1;

Q4 = Q2;

Q5 = Q3;

Q6 = Q4 ^ ((Q6 ^ Q7) &C2); And

Q7 = Q5 ^ Q6,

Where "^" represents an exclusive OR operation and "&" represents an AND operation.                 

Bits Q0, Q1, Q2, Q3, Q4, Q5, Q6 and Q7 are generated when C2 is high. If C2 is low, the circuit of FIG. 9D functions as a simple shift register, shifts Q0, Q2, Q4, and Q6 to multiplexer 305, and shifts Q1, Q3, Q5, and Q7 to multiplexer 304. .

The same values of the bits Q0, Q1, Q2, Q3, Q4, Q5, Q6 and Q7 output from the circuit of FIG. 9D are output from the circuit of FIG. 9C, but before C2 transitions to high-low, FIG. 9C and FIG. Suppose that the same input values are applied to the circuit of 9d, the first odd bit IN [1] of the next block is applied as the input value, and then the control bit C2 transitions high-low at the clock edge), The circuit of FIG. 9C requires eight clock cycles to shift these values to the multiplexer 303, while the circuit of FIG. 9D requires only four clock cycles to shift these values to the multiplexers 304 and 305.

Further, preferably, in the system according to the present invention, in order to improve the reliability of BCH error detection, the transmitter is arranged to automatically insert zero bits (when the input data stream is grouped into subpackets) in the input data stream. And the inserted zero bits can occur at a known position among the 56 slots of each subpacket available for each data bit. The error detection circuitry in the receiver (used with such a transmitter) is configured to check the zeros in the expected slots of the subpacket of each recovered data and use the resulting information representing the error of each subpacket of each recovered data. Should be.

The third bit (“bit2” in FIG. 9) of each 4-bit word determined by the 10-bit code word transmitted on CH0 during any one of the 32 pixel clock cycles of the packet transfer, bits of the packet header. Is one bit. The 4-bit word determined by the 10-bit code word transmitted on CH1 during the 32 pixel clock cycle of packet transmission is the even bits of the subpacket. The 4-bit word determined by the 10-bit code word transmitted on CH2 during the 32 pixel clock cycle of the packet transfer is the odd bits of the subpacket.

More specifically, as shown in FIG. 9, each of the code words transmitted on CH1 during an "N" th pixel clock cycle determines the even bits of each of subpackets 0, 1, 2, and 3, and the "N" th pixel. Each code word transmitted on CH2 during a clock cycle determines the odd bits of each of subpackets 0, 1, 2, and 3. Each code word transmitted on CH0 during the " N " th pixel clock cycle determines the packet header 1 bit (as well as the HSYNC bit and the VSYNC bit). Each code word transmitted on CH1 during the " N + 1 " th pixel clock cycle determines the next even bit of each of subpackets 0, 1, 2, and 3, and is transmitted on CH2 during the " N + 1 " th pixel clock cycle. Each code word determines the next odd bit of each of subpackets 0, 1, 2, and 3. Each code word transmitted on CH0 during the " N + 1 " th pixel clock cycle determines the packet header of the next bit (as well as the next HSYNC bit and the next VSYNC bit).

The BCH parity bit (the last 8 bits of the packet header) of the packet header is calculated over the 24 data bits of the packet header and is determined through the code word transmitted over CH0 during the last 8 pixel clock cycles of the packet. The BCH parity bit for each subpacket is calculated by the 56 data bits of the subpacket and is determined by the code word transmitted over CH1 and CH2 during the last 4 pixel clock cycles of the packet (in each subpacket). Parity bits for the two channels include bits transmitted on CH1 and CH2).

Thus, in a preferred embodiment, the transmitter is a packet in which a packet is spread over three channels (CH0, CH1 and CH2) of a TMDS link and each subpacket of the packet is spread over two channels (CH1 and CH2) of a link. In addition to transmitting each (during data islands), the transmitter separately generates BCH parity bits for each subpacket of the packet and subpackets such that these BCH parity bits are spread over two channels (CH1 and CH2) of the link. Send BCH parity bits for each.

Preferably, the first byte of each packet header is a "Packet Type" code, and each of the second and third bytes of each packet header represents packet-specific data. Preferably, the transmitter may generate four or more types of packets: null packets (indicated by packet type code 0x00 = 0b00000000); An audio clock regeneration (ACR) packet (indicated by packet type code 0x01 = 0b00000001); An audio sample packet (indicated by packet type code 0x02 = 0b00000010); (Represented by packet type code 0x80 + InfoFrame Type = 0b1xxxxxxx, where seven LSBs represent the type of InfoFrmae defined by the EIA / CEA-861B specification).

Next, the format and use of each of the four types of these packets according to the preferred embodiment will be described.

The transmitter can send a null packet at any time, but the receiver does not recover data from the null packet. If the receiver identifies a null packet (by identifying a value of 0x00 in the first byte of the packet header), the receiver ignores all values in the null packet after the first byte of the packet header (as "undefined"). Is considered).

The audio clock regeneration (ACR) packet includes both a Cycle Time Stamp (CTS) value and an N value (described below) used for audio clock regeneration. The four subpackets of the ACR packet are identical. Each subpacket contains a 20-bit "N" value and a 20-bit "CTS" value. The CTS value is zero to indicate that there is no new value for the CTS.

The audio sample packet may comprise one, two, three or four pairs of audio samples, each pair of samples determined by a different subpacket of the packet. These may be other samples, other partial samples (eg, two of six channels), or repeated samples. The bits in the second and third bytes of the header of the audio sample packet indicate the configuration of each of the subpackets of the packet, and indicate whether each subpacket contains a sample, and each subpacket has a "flatline ( flatline) "sample (ie zero size). Preferably, each of the 4 LSBs of the second byte of the packet header indicates whether the corresponding subpacket contains an audio packet, and the 4 LSBs of the third byte of the packet header indicate that the corresponding subpacket is a "flatline" sample. Indicates whether or not to include. However, a value of "1" (indicative of a flatline sample) of a certain LSB of the third byte indicates that the corresponding "current" bit (one of 4 LSBs of the second byte) of the second byte is a subpacket sample. If it is included, the value is meaningless. Each subpacket of an audio sample packet may include channel status bits and parity bits as well as bits representing audio samples.

Preferably, the audio data of each subpacket (of the audio sample packet) is very similar to the IEC_60958 or IEC_61937 frame, but multiplexes of each sub-frame of the IEC_60598 or IEC) 61937 frame (of the packet header). Formatted in a structure replaced with a bit preamble. Each subpacket of an audio sample packet may contain two 28-bit words (eg, a 28-bit word of the left stereo stream and a 28-bit word of the right stereo stream), each 28-bit word being IEC_60958 Corresponds to one of the two sub-frames of the frame and includes 24 bits of audio data as well as valid bits, parity bits, channel status bits and user data bits. Preferably, all regions in each subpacket of the audio sample packet comply with the corresponding rules in the IEC_60958 or IEC_61937 specification.

In a preferred embodiment, each of the 4 LSBs of the third byte of the packet header of the audio sample packet is a "start" bit indicating whether the corresponding subpacket contains the first frame of the IEC_60958 (or IEC_61937) frame of the audio sample. The transmitter sets the start bit to "1" if the corresponding subpacket contains the first "B, W" frame of the block, and if the corresponding subpacket contains the first "M, W" frame of the block. , Clear the start bit to "0".                 

Preferably, the system according to the invention is capable of transmitting IEC_60958 or IEC_61937 audio streams with sample rates of 32 kHz, 44.1 kHz or 48 kHz (which can determine stereo or compressed surround-sound streams) and samples up to 96 kHz. Up to four streams (eg, 8 stereo channels) of IEC_60958 or IEC_61937 data at a rate, or one or more streams of IEC_60958 or IEC_61937 data at a sample rate of 192 kHz.

The InfoFrame packet may include format information and related information related to audio and / or video data to be transmitted. The EIA / CEA-861B standard defines an "InfoPacket" data structure consisting of one or more "InfoFrames" containing format information and related information related to transmitted digital audio and / or digital video data. In a preferred embodiment, each InfoFrame packet sent by the system according to the invention comprises the information of the EIA / CEA-861B InfoPacket with the following limitations: An InfoFrame packet according to the invention has a maximum size of 30 bytes. May include only information of the EIA / CEA-861B InfoFrame (the first byte of the packet header indicating the InfoFrame type code, the second byte of the packet header indicating the version number region, and the third of the packet header indicating the InfoFrame length region). Includes seven LSBs of bytes); The type code must be in the range 0 to 127 (since the type code is represented by 7 LSBs in the first byte of the packet header). Examples of InfoFrame type codes include 0x02 (indicating that an InfoFrame packet contains data of Auxiliary Video information (AVI) InfoFrame), 0x03 (indicating that an InfoFrame packet contains data of an Audio InfoFrame), and (in which InfoFrame packet is DVD control). 0x04), indicating that it contains InforFrame data. Preferably, the InfoFrame length field contains 3 bytes of the packet header and meaningless bytes in the packet including a checksum (to have a maximum value of "31" in length), the InfoFrame in EIA / CEA-861B standard units. Indicates the length of the packet in bytes.

The AVI (Auxiliary video information) InfoFrame packet indicates whether the video data of the current video stream sent (or to be sent) to the receiver is in RGB, YCbCr 4: 2: 2, YCbCr 4: 4: 4 format, and the video Whether the data represents an overscanned or underscanned picture aspect ratio (and whether the picture is scaled horizontally or vertically), the bit depth of the video element, the number of pixels per line And number of lines per frame, number of pixel repetitions (ie, each pixel is not repeated or is transmitted N times, where N is an integer greater than one). Audio InfoFrame packets represent various features of the transmitted (or to be transmitted) audio data, such as the number of streams of audio data, the sampling frequency for each stream, and the sample size (number of bits).

Preferably, the system according to the invention can use as many copies of video pixels as necessary to provide sufficient audio bandwidth. For example, a frame of video consists of L lines (these pixels are sent in a non-repeating fashion at the first pixel clock frequency), and 2L data islands (each inserted within a blank period following the video line). If it is necessary to transmit audio bits corresponding to one frame of video, the system can preferably operate in a mode in which the transmission of each pixel is repeated. If the pixel clock frequency does not change, repeated transmission of each pixel has the effect of halving the video transmission rate (because the lines of the two repeated pixels are needed to transmit every pixel of each non-repeatable line), but not repeated. The audio bit for a full frame of video that is not video is transmitted in a 2L data island that follows one of the 2L active video periods in which the pixels of the frame are repeatedly transmitted. In general, the pixel clock frequency is increased (relative to the pixel clock frequency used for non-repeatable transmissions) during each mode in which pixels are transmitted repeatedly. For example, in a mode where the pixel clock frequency is doubled and the transmission of each pixel is repeated once, the audio data can be transmitted at a data rate that is doubled (with a time stamp based on the doubled pixel clock) between active video periods. Although, the effective video pixel transfer rate does not change. In some repeated pixel transfer modes, the transmission of each pixel is repeated one or more times (eg, each is transmitted three times using a version with three times the frequency of the pixel clock). When receiving video data transmitted in any repeated pixel transmission mode, the receiver discards all but one of each set of identical video samples received during each active video period (e.g., the receiver discards each pixel). Discarding all odd video samples or discarding all even video samples when transmitted twice), the receiver processes all samples of packetized data received during the data island between active video gazes.

The use of pixel-repetition of the transmitter is preferably represented by the Pixel Repetition Count field in the transmitted AVI InfoFrame packet. This area indicates to the receiver how repeatedly each unique pixel has been transmitted. In the non-repeating pixel transfer mode, the value of the region is zero. In the mode of pixel repetition, the value of this region represents the number of pixels (in each set of consecutively received pixels) to be discarded by the receiver. Preferably, video samples transmitted during the first pixel clock cycle of each line are unique (and not discarded), but each repetition of these samples is discarded in pixel repetition mode.

In a preferred embodiment, the system according to the invention is configured to transmit video data in several different formats over a TMDS link, and the receiver is configured to recover data in any of these formats. Advantageously, the system is capable of transmitting video data, in either YCbCr 4: 4: 4 format, YCbCr 4: 2: 2 format, or RGB format, over the CH0, CH1, and CH2 channels of this link without pixel repetition or repetition. have. In all cases, up to 24 bits per pixel clock cycle can be sent over these channels. As shown in Fig. 10, during the transmission of RGB video, during each pixel clock cycle, an 8-bit red color element may be transmitted over channel CH2, and the 8-bit green color element is channel CH1. Can be transmitted, and an 8-bit blue color element can be transmitted on channel CH0. The R, G, and B elements of the first pixel of each line are transmitted after the video guard band, followed by the first pixel clock cycle pattern (e.g., after the second time that the video guard band code has been transmitted twice in succession).

As shown in FIG. 11, during the transmission of TCbCr 4: 4: 4 video, during each pixel clock phase, an 8-bit " Cr " sample can be transmitted over channel CH2, and an 8-bit " Y " "Samples may be sent on channel CH1, and 8-bit" Cb "samples may be sent on channel CH0.

Since 4: 2: 2 data only requires transmission of two components (Y and Cr or Y and Cb) per pixel clock cycle, more bits can be allocated to each component stage. The 24 bits available are broken into 12 bits for the Y component and 12 bits for the C component. As shown in FIG. 12, during the N th pixel clock cycle of the transmission of YCbCr 4: 2: 2 video, a 12-bit luminance Y component can be transmitted on channels CH0 and CH1, Cb samples may be sent on the channels CH0 and CH2. The four most insignificant bits of the Y sample and the four most insignificant bits of the Cb sample are determined by the TMDS code word transmitted over the channel CH0. Then, during the next " N + 1 " th pixel clock cycle, the next 12 bit Y samples can be sent on channels CH0 and CH1, and the 12 bit Cr samples can be sent on channels CH0 and CH2. . The four most insignificant bits of the Y sample and the four most insignificant bits of the Cr sample are determined by the TMDS code word transmitted on CH0. The bits of the Cb sample transmitted during the N th clock cycle are for the pixel containing the Y samples transmitted during the same clock cycle. Cr sample bits transmitted during an "N + 1" th clock cycle are for a pixel containing Y samples transmitted during the same "N + 1" th clock cycle. If it consists of fewer than 12 bits of each of the Y, Cr, and Cb samples, valid bits must be left-aligned (most significant significant bits must be aligned), and zeros must be padded below the least significant bit.

During a video transfer mode with pixel-doubling, all data transmitted during the Nth pixel clock cycle is transmitted again during the next "N + 1" th pixel clock cycle, and the next data set is the next "N + 2. Proceeds during the "th pixel clock cycle.

In a preferred embodiment, the transmitter according to the present invention supports HDCP encryption of data, initiates an HDCP authentication exchange with the receiver, and asks the receiver (e.g., to query if it is properly connected to implement HDCP content protection). And a processor (eg, microcontroller 15 of FIG. 2) programmed to communicate over the DDC channel of the TMDS link. The processor preferably takes HDCP encryption during data island mode operation (described below) to set up a transmitter (eg, via interface 101 of FIG. 13) and a receiver (eg, via a DDC channel). It is programmed with the system software to do this. In particular, the system software causes the transmitter to enter the data island mode and send a packet to the receiver (as described below) to cause the receiver's entry to enter the data island mode and then cause the receiver to register the appropriate register in the receiver. Ask questions to prove that you have definitely transitioned to data island mode. If both the receiver and the transmitter are in data island mode, the processor in the transmitter runs HDCP authentication software (if the authentication exchange is successfully completed) to allow the transmitter to encrypt data to be transmitted during the active video period and data island.                 

In a preferred embodiment of the data island mode, all video data transmitted over the channels CH0, CH1, and CH2 of the TMDS link during the active video period are HDCP encrypted, except that the video guard band words are not encrypted. During a data island, the code words transmitted over the channels CH1 and CH2 are HDCP encrypted (but the leading data island guard band words or trailing data island guard band words are not encrypted).

In DVI mode (with HDCP encryption enabled), a high value of DE indicates that video data has been transmitted (or ancillary data has been transmitted between active video cycles), and all data transmitted while DE is high is encrypted. do. HDCP rekeying is also caused by each of the DE's transitions to high-low. No actual "DE" signal is transmitted: rather, a transition-maximized code word indicating that DE is low and a transition-minimizing code word indicating that DE is high.

In a preferred implementation of data island mode, instead of a single DE value indicating that the transmitted data is encrypted, two binary cryptographic mode values effectively determine whether the data is encrypted. In practice, the high value of the first cryptographic mode signal M1 indicates that the video data pixels have been encrypted, and the high value of the second cryptographic mode signal M2 indicates that the supplementary data (transmitted during the data island) is encrypted. Any of M1 and M2 or the value of M1 logically ORed with M2 corresponds to the DE value used in the DVI mode. M1 is high only when a transition-minimization codeword representing video data (not the video guard band) is transmitted over the channels (CH0, CH1 and CH2) of the TMDS link. M2 is high only when a transition-minimization code word (not a leading data island guard band word or trailing data island guard band word) is transmitted over channels CH1 and CH2 during a data island. Thus, while transmitting the video guard band, DE is high, but M1 and M2 are not high.

To encrypt 24-bit video pixels (when M1 is high), the HDCP cipher engine of the transmitter uses a stream of 24-bit pseudo-random values generated in a well-known manner (described above). Performs a bitwise XOR operation at. To encrypt 8-bit audio data to be transmitted in pixel clock cycles on a data island in a preferred embodiment according to the present invention (when M2 is high), 4 bits of such audio data for transmission over CH1. Encoded using a 10-bit TMDS golden word, and the other 4-bits of this audio data are encoded using a 10-bit TMDS golden word for transmission over CH2). A bitwise XOR operation is performed on the eight audio data bits using a selected 8-bit subpet of each bit of the 24-bit pseudo-random value of the pseudo-random value stream generated according to FIG.

In a preferred implementation of the data island mode, HDCP rekeying is performed in response to each transition of M1 to high-low (ie, at the end of each active video period). Advantageously, said rekeying must be accomplished within a Y pixel clock cycle (eg within a 58 pixel clock cycle of M1's transition to high-low) and the transmitter is said to have its HDCP cryptography enabled for rekeying. It is configured to place each data island only in time slots between the completion of active video cycles, and prepares to encrypt packetized data to be transmitted in the data island.

In a preferred implementation of the data island mode, the transmitter according to the invention has a specific set of values of HDCP encryption indicators (four control bits CTL0, CTL1, CTL2 and CTL3), preferably CTL3 = 1, CTL2 = 0, CTL1 = 0 and CTL0 = 1) to the receiver to indicate that the receiver's HDCP cyber engine should initiate the frame key calculation, and the receiver is configured to respond to this HDCP encryption indicator by performing frame key calculation. Preferably, the HDCP encryption indicator is transmitted over channels CH1 and CH2 of the TMDS link (control bits CTL0, CTL1) during a blank period (not a data island or active video period), preferably a vertical blank period. , CTL2 and CTL3), represented by two transition-maximizing TMDS control words. In the second and third rows from the bottom of FIG. 3, code words representing such HDCP encryption indicators are shown.

The use of such HDCP cryptographic indicators (sometimes referred to as "key control" data or "decryption control" data) for determining when the receiver performs frame key calculations (after completion of HDCP authentication exchanges by the transmitter and receiver). Increase reliability. Since this encryption indicator depends on all four control bits (not just control bit CTL3), reliability is improved and future scalability is also possible.

Preferably, the receiver has a code word representing a predetermined value of bits CTL0, CTL1, CTL2 and CTL3 (e.g., CTL3 = 1, CTL2 = 0, CTL1 = 0 and CTL0 = 1). A predetermined number of consecutive pixel clock cycles during a window of opportunity (WOO) with a predetermined duration (preferably 72 pixel clock cycles) following the active edge (i.e., following detection of the code word representing the rising edge of VSYNC). Only when detected during each of the minimum number (preferably 16 consecutive pixel clock cycles) is configured to detect the HDCP encryption indicator. The constraints of these HDCP cryptographic indicators are added to improve the reliability of the receiver detecting the indicator when the indicator is sent by the transmitter and expected by the receiver.

As described above, in the preamble preceding the data island or active video period, the control character (CTL0, CTL1, CTL2 and CTL3 set to a specific value) is preferably whether the upcoming DE-high period is a data island or active video period. Identifies Preferably, the first two code words (transmitted during the first two pixel clock cycles) of all data islands and active video periods are guard band codes designed to produce a very robust DE rising edge. The transmitter should be configured to never encrypt guard band word codes, and the receiver should be configured to never decrypt guard band code words.

In a preferred embodiment, the transmitters and receivers of the system according to the invention are connected by one or more TMDS links and are operable in a digital visual interface (DVI) mode or a "data island" mode. In the DVI mode, the receiver waits for a conventional out-of-band codeword indicating HSYNC and VSYNC on the TMDS channel CH0 from the transmitter and enters the code input on the channels CH0, CH1 and CH2. From the active video period (and also optionally from the auxiliary data burst in the blank period) by identifying whether the word is an out-of-band code word (in the blank period) or an in-band code word (in the active video period and auxiliary data burst). Discriminates the blank interval and monitors whether the incoming data for the indication is coming into the data island mode. In data island mode, the receiver waits for a packet of audio data (or other auxiliary data) in the data island between active video periods, and transition-minimization code indicating HSYNC, VSYNC and packet header bits on channel CH0 during the data island. Wait for a word and identify the active video cycle by detecting the leading video guard band. Preferably, the transmitter and receiver undergo a synchronized (and nearly simultaneous) transition from DVI mode to data island mode.

Preferably, the transition to each DVI-data island mode occurs when the transmitter enters the data island mode and transmits the data islands detected by the receiver. A preamble (transmitted in CH1 and CH2 mode, preferably with a code word indicating CTL3, CTL2 = 01 on CH2, a code word indicating CTL1, CTL0 = 01 on CH1) indicating that the data island follows, and the The data islands are represented by one or more special guard band codes following the preamble (preferably two consecutive identical guard band codes, each with a value of 0x55 on each of CH1 and CH2). In response to detecting the data island (e.g., detecting the data island preamble, then detecting the guard band word 0x55 (within the first pixel clock cycle after the data island preamble), and then (the data island Within the second pixel clock cycle after the preamble (by detecting guard band word 0x55), the receiver enters data island mode. Preferably, as soon as the receiver enters data island mode, the receiver sets a bit (indicating data island mode operation) in a register that is readable to the transmitter. For example, the receiver sets the bits in the registers into the HDCP register space (eg, register 203 in FIG. 14) that the transmitter can read over the DDC channel. Preferably, this bit can be cleared only through a hardware reset of the receiver.

In data island mode, circuitry in the receiver monitors each preamble / guard band combination representing an active video period and input data for each preamble / guard band defect representing a data island.

In a preferred embodiment, the transmitter can determine the receiver mode state over the DDC channel (e.g., whether the receiver is in DVI or data island mode, and what type of HDCP encryption the receiver can perform). If the transmitter reads (via the DDC channel) a register bit that indicates that the receiver is in data island mode and supports a particular type of HDCP, the transmitter may be read by a transition-minimizing TMDS code word rather than a transition-maximization code word. It will operate in data island mode, sending VSYNC and HSYNC during the data island with the determined bits, inserting the video guard band code into the video stream, and using the appropriate HDCP state machine to encrypt the data to be transmitted (but no video guard). Don't encrypt the band).

In data island mode, the transmitter preferably performs the capability of the receiver (eg from the ROM 23 of FIG. 2) by reading the EDID data structure (preferably including the EIA / CEA-861B defined therein in the EDID). And using the DDC channel to determine the characteristics. The transmitter can also use the DDC channel to determine its own physical device address, for use in various cluster-wide control operations. Preferably, the transmitter determines what type of encryption to use in response to the determination of the decryption capability (anything) of the receiver and notifies the receiver of the selected encryption mode.

In a preferred embodiment, the following steps should be taken by the transmitter to begin data island mode operation with HDCP encryption of the transmitted data:

1. The state of the transmitter is reset to the initial state;

2. The transmitter reads the receiver's EDID data (eg, the EDID data is stored in ROM 23 of FIG. 2 via the DDC channel) to determine whether the receiver is capable of data island mode operation;

3. If the receiver is capable of data island mode operation, the transmitter writes a special mode bit (eg, data island mode = 1) (in the transmitter's configuration register);

4. The transmitter sends a data island packet to the receiver (eg a null packet);

5. The transmitter reads the special mode bits in the register of the receiver via the DDC channel (eg, the data island mode bits at a location in register 203 of FIG. 14);

6. If the special mode bit of the receiver is set (eg, data island mode bit = 1), the transmitter and receiver go to step 7. Otherwise, the transmitter and the receiver go to step 4;

7. Here, the transmitter and receiver operate in data island mode. And the transmitter starts the HDCP authentication procedure; And

8. After step 7, when HDCP authentication is complete, in response to the HDCP engine of all transmitters being enabled, the transmitter sets a bit in the transmitter's configuration register (eg, bit "HDCP Authenticated"). do.

Preferably, during startup, the receiver is configured to provide video and audio output because there is time during startup, where the transmitter is in data island mode but the receiver is still in DVI mode, where unwanted video output may occur from the receiver. Disable it.

13 is a block diagram of a transmitter 100 as a transmitter according to an embodiment of the present invention. Transmitter 100 may use pipelined encryption and other pipeline processing (e.g., reformat, upsampling, and / or color space conversion) to video data D [23: 0] received from an external source. Video subsystem 106 that performs the operation. In general, the video data clock (IDCK, referred to herein as the "pixel clock"), the video data enable signal DE, and the horizontal and vertical sync control signals HSYNC and VSYNC are received together with the video data input from an external source. do. The transmitter 100 is generally configured to operate in response to a pixel clock having a frequency in the range from 25 MHz to 112 MHz. Subsystem 106 encrypts the input video data (or reformatted or otherwise processed version of the input video) using pseudo-random values from cipher engine 104 and stores the encrypted video in the multiplexer. Applies to 1 input. During operation, the cipher engine 104 utilizes the bits in the register 103. The register 103 may be loaded with values received via the interface 101 and / or interface 102.

In general, the interface 101 is connected for I2C communication with a microcontroller (eg, microcontroller 15 of FIG. 2). In addition, the microcontroller is connected to the DDC channel of the TMDS link and an input data source (eg, a video source). Interface 101 allows the I2C slave protocol to receive information and configuration bits (e.g., InfoFrame bits) and other bits (e.g., key values received during the HDCP authentication procedure), and registers these bits in registers ( 105 and 103).

If the transmitter 100 is implemented as an integrated circuit, the EEPROM, preloaded with key values and authentication bits (used for decryption), is a separate chip within a secure multi-chip module (MCM) that includes both the transmitter 100 and the EEPROM. Can be implemented. An example of such an EEPROM is the EEPROM 14 of FIG. The interface 102 provides an interface between the transmitter 100 and the EEPROM. The interface 102 may extract values from the EEPROM at appropriate times, such as during an HDCP authentication exchange with the receiver. Interface 102 outputs (typically having a frequency between 64 MHz or 51.2 MHz to 76.8 MHz) of ring oscillator 113 to generate a clock (e.g., 100 kHz clock) used for I2C communication with the EEPROM. Use

Transmitter 100 also includes an audio subsystem 108 that performs pipelined format, packetization, encryption, and other pipeline processing on audio data (AUD) received from an external source (AUD audio It may be auxiliary data rather than data, but this is referred to simply as audio data here). In a typical embodiment, the transmitter 100 is in S / PDIF format with a sample rate (Fs) in the range of 32 kHz to 48 kHz, or any number of other formats (eg, 2-channel uncompressed PCM data or multi Audio data (AUD) can also be accepted as compressed bit streams representing channel data. The audio reference clock MCLK is received with the input data AUD. The clock MCLK (also referred to as the master clock) has a frequency of 256 * Fs (or 384 * Fs) in the preferred embodiment.

The main phase lock loop (PLL) 116 creates a stable version of the pixel clock IDCK.

Reset circuit 112 is coupled with a reset pin to receive a reset bit from an external processor. The transmitter 100 is configured to reset the transmitter to an initial state in response to a reset bit having a predetermined value. The test circuit 110 is coupled with the test bits to receive the test mode bits from an external source. The transmitter 100 is configured to operate in a test mode or a normal operation mode according to the test mode bit value.

Subsystem 108 may sample the heldh data using a (stable pixel clock provided with a pixel clock frequency greater than 2 * 128 Fs), clock MCLK, or a multiplied frequency version of MCLK. Subsystem 108 generates a packet containing the sampled audio data, encrypts the data within the packet, encodes the encrypted data using TERC2 or TERC4 encoding, and multiplexes the packets containing the encoded and encrypted data. To the second input of 118. When performing TERC4 encoding, the subsystem 108 may assign the four most insignificant bits of each of the encrypted samples to sixteen "golden words" (eg, the eight-bit words "AD0-AD15" in the left column of FIG. 4). ) And the four most significant bits of each encrypted sample into another golden word.

Subsystem 108 also determines the timing (with respect to DE) that the data island is applied to multiplexer 118 (each data comprising one or more packets). Subsystem 108 time-division-multiplexes the control words including a control word to indicate a data island: a data island preamble (e.g., subsystem 108 may include each data). Insert 8 pixel clock cycles of the auxiliary data preamble word immediately before the island), HSYNC and VSYNC (eg, subsystem 108 inserts 12 or more pixel clock cycles of the sync word before the burst of auxiliary data preamble words). ), And the leading and trailing data island guard bands (e.g., subsystem 108) trails two pixel clock cycles of leading guard band words to the first two words of each data island and trailing to the last two words of each data island. Insert a two pixel clock cycle of the ring guard band word), the video preamble (e.g., the subsystem 108 is each data isle Insert a video preamble word after the land), and a video guard band (eg, subsystem 108 inserts a two pixel clock cycle of the video guard band word after each video preamble).

In response to the control signal indicative of the DE (DE signal received at interface 9107), multiplexer 118 may display video data from subsystem 106 (when DE is high) or subsystem (when DE is low). The output from 108 is sent to the TMDS core processor 114.

The core processor 114 operates in response to a stable pixel clock (generated by the PLL 116), encodes the aforementioned 8-bit data word into a 10-bit TMDS code word, and serializes the data. And transmitting the serialized encoded data (and the serialized pixel clock) to a receiver 200 of FIG. 14 (a receiver according to an embodiment of the present invention) via a TMDS link.

As shown in FIG. 14, the receiver 200 includes a core processor 214 that operates in conjunction with a TMDS link. Processor 214 recovers the pixel clock from the clock channel of the link, and main PLL 216 stabilizes the pixel clock in response to the restored pixel clock. In response to the stabilized and reconstructed pixel clock, processor 214 de-serializing the data received over the constant link, decoding the deserialized 10-bit TMDS code word. Restoring to an 8-bit code word, and applying the 8-bit codeword to a splitting unit 218.                 

Unit 218 also receives a signal representing the DE and a stabilized reconstructed pixel clock from processor 214. Unit 218 detects the beginning and end of each data island and each active video period in the code word stream from processor 214 (by identifying guard bands and preamble code words of the type described above), and (each data island I) send each audio data packet to pipeline audio subsystem 208 and send the remaining data (including all bursts of video data) to pipeline video subsystem 206. In some modes of operation, data applied to subsystem 206 by unit 218 includes HSYNC and VSYNC code words.

Video subsystem 206 performs decoding and other processing (eg, reformat, upsampling or subsampling, and / or color space conversion) on the video data received from unit 218. Subsystem 206 decodes the video data from unit 218 using a pseudo-random value from cypher engine 204 (to generate an 8-bit decoded word), and decodes the decoded video to another. Apply to pipelined circuitry to perform processing (eg, reformatting, subsampling, and color space conversion). The pipelined circuit generally outputs the decoded and processed video bits Q [23: 0] with the corresponding DE, HSYNC and VSYNC signals and pixel clock after the last reformat. Subsystem 206, on the other hand, is also an analog video signal (AnRPr, AnGY, and AnBPb), which may be a red, green, and blue color element signal or a luminance and chrominance signal, in response to an 8-bit decoded and processed video word. Digital-to-analog converter for generating and outputting During operation, the cipher engine 204 uses the bits in the register 203. Register 203 may be loaded with values received through interface 201 and / or interface 202.

If the receiver 200 is implemented as an integrated circuit, the EEPROM preloaded with key values and authentication bits (used for decryption) is a separate chip within a secure multi-chip module (MCM) that includes both the receiver 200 and the EEPROM. Can be implemented. An example of such an EEPROM is the EEPROM 24 of FIG. The interface 202 provides an interface between the receiver 200 and the EEPROM. Interface 202 may extract values from EEPROM at appropriate times, such as during an HDCP authentication exchange with a transmitter. Interface 202 uses the output of ring oscillator 213 (typically having a frequency between 64 MHz or 51.2 MHz to 76.8 MHz) to generate a clock that is used for I2C communication with the EEPROM.

The interface 201 may be coupled with the DDC channel of the TMDS link, and includes loading the key value received from the transmitter into the register 203 for communication with the transmitter via the DDC channel (eg, via the DDC channel). I2C slave protocol can be implemented to perform HDCP authentication.

On the other hand, when the receiver 200 is a repeater (configured to operate as a transmitter for transmitting data to another receiver, in addition to being configured to receive data from the transmitter 100), the receiver 200 is an interface 207 ). The interface 207 can be coupled with a host device and can implement the information and configuration bits and the I2C slave protocol for loading these bits into registers 205 and 203. At the appropriate time (ie, in response to a predetermined state, information, or error condition), an interrupt INT is applied from the register 205 to the host device to request software processing.

Receiver 200 also includes a pipelined audio subsystem 208 for receiving and processing audio data packets from unit 218. Subsystem 208 decodes the golden words in the packet to determine the 8-bit words represented by each pair of golden words (when the transmitter used the TERC4 encoding method to encode the audio data), and the transmitter transmits the audio data. Determine the 4-bit word represented by each pair of golden words). Subsystem 208 also decodes the decoded audio samples (using pseudo-random bits from the cipher engine 204), performs error correction on the decoded and decoded samples, and removes the error- from the packets. Unpack the corrected, decoded and decoded samples (and send configuration and status information from the packet to the appropriate registers), and perform other processing on the unpacked audio samples (e.g., S / PDIF and Audio data organization for the I ² S output engine, processing the organized data of one or both of these engines to produce output data in either or both of the S / PDIF or I ² S format). In general, subsystem 208 may output audio data having any number of different formats (eg, as two-channel uncompressed PCM data or as a compressed bitstream representing multi-channel data). ). In another mode of operation, the subsystem 208 may include one or more bit clocks (SCK) whose frequency is an audio bit rate, an audio reference clock (MCLK), which is a reconstructed version of the MCLK clock used by the transmitter 100, and two audio channels. A serial data output clock SDO and a word select clock WS (along with the output audio data) used for demultiplexing the time-division multiplexed output audio data stream, are applied.

The main PLL 216 generates a stabilized version of the pixel clock recovered from the clock channel of the TMDS link for use by the interface 214 and other elements of the receiver 200.

Reset circuit 212 is coupled with a reset pin to receive a reset bit from an external processor. The receiver 200 is configured to reset the receiver to an initial state in response to a reset bit having a predetermined value. The test circuit 210 is coupled with the test bits to receive the test mode bits from an external source. The receiver 200 is configured to operate in one of the test mode and the normal operation mode according to the test mode bit value.

In general, each transmitter and receiver used in a system according to an embodiment of the present invention is designed to meet the contents of the detailed description. Preferably, each of the transmitter and receiver is fabricated in a way that can be effectively tested according to the above specification.

For example, in embodiments according to the present invention, the transmitter according to the present invention includes a test pattern generator (eg, the test pattern generator 119 of the transmitter 100 of FIG. 13) and according to the present invention. The receiver includes the same test pattern generator (eg, test circuit 210 of receiver 200 of FIG. 14). The test pattern generator in the receiver can preferably be controlled by the transmitter in test mode or by the test pattern generator in the transmitter, and the receiver can be individually controlled (eg, by a host device) to It is possible to detect the error rate on the serial link between receivers. For example, in a test mode, the test pattern generator 119 of the transmitter 100 applies test data through the multiplexer 118 to the core processor 114, and the processor 114 encodes the test data to encode the test data. The test data to the receiver 200 through the TMDS link. In the test mode, the receiver 200 receives and decodes the data and applies the reconstructed data to the test circuit 210. The error detection and accumulation logic in the test circuit 210 compares the recovered data with test data generated by the test pattern generator of the circuit 210. The test result, including the measured error rate of the recovered test data, may be re-transmitted to the transmitter 100 via the link's DDC channel (eg, via interface 201), and / or the hose device May be applied (eg, via interface 207). Preferably, the test pattern generator in the transmitter (e.g., pattern generator 119) and the same pattern generator in the receiver comprise a linear feedback shift register (LFSR) that generates a pseudo-random test pattern, and both pattern generators Start in the same initial state (during test mode operation) and generate the same pseudo-random test pattern during test mode operation.

The use of the DDC channel as a back-channel during this test mode (or other test mode operation) allows the transmitter (e.g., microcontroller 15 of Figure 2) to determine the state of the receiver's test pattern generator and error detection and accumulation logic. Allow to water. Preferably, the transmitter can also control test mode operation of the receiver via the DDC channel or other channel. Using the DDC channel (or other channel of the serial link) as an error-detecting back-channel during test mode operation allows the transmitter (e.g., microcontroller 15 of FIG. 2) to change one or more parameters of the transmitter. It is possible to detect (at the receiver) the error rate occurring from each of the transmitter parameter sets. Thus, the transmitter can determine the reliability of the link as a function of various sets of operating parameters, and the transmitter can optimize the operating parameters to reduce or minimize the error rate at the receiver.

Preferably, the receiver according to the invention and the transmitter according to the invention have a rover of test characteristics enabled through the application of test pins (pins connected with the test circuit 110 of FIG. 13 or the test circuit 210 of FIG. 14). The individual test modes can be selected via inputable pins or register bits re-designed with test modification pins during test mode operation, while test mode enabling may, for example, include an I2C interface ( Register the bits via the interface 207 of FIG. 14 or the interface 107 of FIG. 13 (eg, the register 205 of the receiver 200 of FIG. 14 or the register 100 of the transmitter 100 of FIG. This can be accomplished by loading the bits into 105. Enabling test mode through loading of register bits requires a larger set of vectors to enable the test mode. However, this makes it possible to be seolge to the transmitter or receiver fewer input pins to enable the 8-bit test mode register 64 different test modes.

Preferably, the test mode is a logic test (e.g., full scan), an EEPROM test (e.g., checksum BIST, or a built-in-self-test), TMDS core test (e.g., core 114 or 214 is isolated and then tested), DAC test (e.g., receiver DAC circuit is isolated and then tested using a test pattern), PLL test, Ring oscillator tests, and one or more debug tests (eg, internal signals are multiplexed with input / output pins).

In general, full scan logic tests require dedicated input and output pins, which are configured as test pins during logic test mode operation. In general, the checksum-based BIST method is implemented to test foreign key EEPROM (eg, EEPROM 14 or EEPROM 24 of FIG. 2). When enabled, the test circuit reads the contents of the EEPROM, performs a checksum calculation, and then compares it with the checksum read from the EEPROM. Preferably, only a single Pass / Fail indicator is applied to the test circuit to maintain security.

In a typical TMDS core test of the receiver according to the present invention, the digital output of the core 214 (in FIG. 14) is multiplexed directly to the output of the circuit 206 or 208. Preferably, the regenerated pixel clock can also be multiplexed to the output pin to enable eye diagram testing. In a typical DAC test of a receiver in accordance with the present invention, the input clock pin provides a test clock directly to the DAC (e.g. in circuit 206 or 208) for testing so that an external device can directly control the clock of the DAC. have. Then, through counters and state machines, specific test patterns are applied to the DAC to provide well-controlled tests. In a typical PLL test, the LOCK indicator (from each PLL to be tested) is multiplexed to the output pin. In a typical ring oscillator test, the clock signal of the ring oscillator being tested (eg, ring oscillator 113 or 213) is multiplexed to the output pin.

As described above, in embodiments, the receiver according to the present invention includes a preamble code word transmitted by the serial link (by the transmitter) during the control data period (ie not during the data island and active video period). In response to a control signal. Each of these control signals is determined by a bit pattern (eg, a 10-bit TMDS code word representing bits CTL0 and CTL1, or CTL2 and CTL3). In a preferred embodiment, the receiver responds to the control signal only when it detects the minimum number of repetitions of the bit pattern, or the bit pattern (or the minimum number of repeated repetitions of the bit pattern) within a predetermined area (time window) of the control data period. Respond to control signals only when detected. In general, the receiver is configured to detect whether Y or more received bit patterns within the last X pixel clock cycle have a predetermined pattern Z matched. The receiver then responds to the control signal determined by the pattern Z. For example, the receiver preferably matches, within the last 8 pixel cycles, a matched 10-bit transition-maximization in which at least eight bit patterns received on the channel CH1 represent control bit values CTL0, CTL1 = 1,0. Has a pattern of TMDS code words, and at least 8 bit patterns received on channel CH2 have a pattern of matched 10-bit transition-maximization TMDS code words representing control bit values CTL2, CTL3 = 0,0. Recognize the video preamble only by judging. As another example, the receiver preferably matches, within the last 8 pixel cycles, a matched 10-bit transition-maximization TMDS in which at least 8 bit patterns received on the channel CH1 represent control bit values CTL0, CTL1 = 1,0. Has a pattern of code words, and determines that at least eight bit patterns received on channel CH2 have a pattern of matched 10-bit transition-maximization TMDS code words representing control bit values CTL2, CTL3 = 1,0 Only by recognizing the data island preamble.

In a preferred embodiment, the receiver according to the invention is a channel (CH0, CH1 and CH2) of the TMDS link in a manner designed to compensate for the degradation of the signal during transmission (generally through a long cable) from the transmitter to the receiver. By filtering the input signal of the phase, equalization is realized. For example, the preferred implementation of core processor 214 of receiver 9200 of FIG. 14 includes such a filter. To design an equalization filter, the filtering effect of the cable is analyzed to determine which "cable filter" is effectively applied to the signal by the transmitted cable, and an inverted version of the cable filter is selected as an equalization filter. Thus, an equalization filter compensates for (and preferably cancels out) the cable filter.

Some preferred embodiments of the system according to the invention use not only an equalization filter in the receiver during the restoration of transmitted auxiliary and video data, but also a subset of the full set of code words described above to encode auxiliary data for transmission. ), "Golden Word", both techniques are effective in reducing the error rate of the recovered data.

In a preferred embodiment, the receiver according to the invention is adapted to correct a detected error in at least audio data (or other auxiliary data) transmitted during the data island, and optionally also in the video data transmitted during the active video period. Error correction circuitry (e. G. Circuitry 22 of receiver 200 of FIG. 14).

For example, each code word of a packet transmitted on a data island may be transmitted repeatedly. With three repeated codings (where each code word to be transmitted is transmitted three times for three consecutive clock cycles), the packetized data may, for example, contain a particular out-of-band word that defines a blank interval. Using the same techniques conventionally used in the video channel of the TMDS link to identify, it can be reliably restored. Errors that occur during the transmission of encoded data that has been repeated three times can generally be corrected by implementing "buffer correction" error correction in the receiver.

Bubble correction is the removal and replacement of suspect data values (with a single clock width) with their neighboring data values. Next, one code word is transmitted in clock cycles, three repeated codings are used (each different code word is transmitted three times), and the receiver has a 10-bit TMDS code word (each 10-bit TMDS code). The word is decoded into a 4-bit word). An example of bubble correction is assumed to produce four single sequences in response to each sequence. In this example, the receiver indicates that the same Nth bit and the N + 2th bit are separated by another bit (ie, the N + 1th bit is different from the Nth bit) (any of four sequences of restored single bits). When identifying, the error correction circuit in the receiver replaces the middle bit (N + 1 th bit) with any one of the neighboring bits (ie, the Nth bit) and completes the bubble correction.

After bubble correction is performed, the sampling point for each sequence of single recovered auxiliary data bits is the same as that performed by conventional methods by the digital PLL of the TMDS receiver to identify the blank period of the TMDS encoded video data stream. Can be determined in substantially the same manner. However, circuitry for detecting sampling points for auxiliary data generally does not need to operate as fast as the digital PLL of the TMDS receiver during identification of the blank period of the TMDS encoded video data stream. In addition, this does not necessarily require the use of a digital PLL to select the optimal sampling point during restoration of the auxiliary data. Rather, the inventors generally simply select a second sample (of each sequence of a single recovered auxiliary data bit) after some transition (e.g., the beginning of a data island) and all third samples until the next transition thereafter. I know it's enough.

In another embodiment, a receiver in accordance with the present invention includes an error correction circuit that uses interpolation to hide errors detected in the recovered data. Any variation of the interpolation technique can be implemented including linear interpolation techniques using higher order curve-fitting.

In a preferred embodiment, the transmitter according to the invention ensures that the cryptographic protocol (e.g. HDCP) is taken into account without the data islands colliding with the transmission of other signals (e.g., signals used by the re-keying cipher engine). Determine the temporary placement and duration of each data island to be transmitted between two active video cycles. In a preferred embodiment, the following constraints are imposed on the transmitter's data island format: The data island must contain one or more packets (thus the minimum duration is 36 pixel clock cycles); Each island must contain an integer number of packets; And no data island can contain more than 14 packets (to ensure the reliability of the data in the data island).

Advantageously, the transmitter is configured to automatically determine, from the previous line or frame, where the active video period and the blank period of the sequence of video frames (to be encoded for transmission) occur where: It is known when a sequence of frames and lines to be transmitted occurs and when other events (such as HDCP re-keying events) need to occur within consecutive frames and lines. Automatic detection of such blank periods requires that the transmitter require a minimum of 44 pixel clock cycles before the data island (this is the next active video cycle or the next HDCP re-keying or other necessary event: 44 pixel clock cycles = 32 pixel cycles for the packet + data). 4 clock cycles for the island guard band word + 8 pixel clock cycles for the video preamble code word, assuming all necessary sync signals have been transmitted), or a data island with another packet (this is at least 42 pixel clock cycles) 42 pixel clock cycles = 32 pixel cycles for the packet + 2 clock cycles for the trailing guard band word + 8 pixel clock cycles for the video preamble code word). If the transmitter expects another active video period (or other necessary event) to begin before the transmission of the data island (or additional packet) can be completed, then the transmitter will generally transmit the transmission of the data island (or other packets in the data island). Postpone). If the transmitter was transmitting a data island when a new line of video data was applied from the video source to the transmitter, the transmitter ignores the incoming video pixel from the source until it can complete the data island (in the preferred embodiment) It is necessary to transmit the necessary synchronization signal, which requires 12 pixel clock cycles in the control data period, and then to transmit the video leading guard band, and then to transmit the encoded video pixel. Of course, it is undesirable to discard the pixel that the transmitter was about to display.

In another preferred embodiment, the transmitter is configured to initialize the data island transmission based on the register indication of the blank interval duration time. In such an embodiment, the transmitter may determine when the active video and blank periods of the video frame sequence occur in the subsequence frames and lines to be transmitted and other necessary events (such as HDCP re-keying events) in the subsequence frames and lines. And a register (e.g., register 105 in FIG. 13) that can store a bit indicating whether it should occur during the transmission of the &lt; RTI ID = 0.0 &gt; The host device (e.g. video source) can load the bits representing the significant values into a register. This should include circuitry for the transmitter to automatically determine the active video and blank periods of the sequence of video frames from the previous line or frame and when significant events occur (as in the embodiment described in the previous paragraph). Eliminate the need The important values represented by the bits in the registers are some of the timings of which the timing is known to the transmitter, such as the generation of HSYNC or the application of the rising edge (to the transmitter) of the Video DE from the video source (beginning of the active video cycle). It needs to be connected to the event. For example, the transmitter may include a register to store a bit indicating that the rising edge of Video De occurs after the X pixel after the rising edge of HSYNC (or rising or falling of Video De). When the transmitter knows the next rising edge of HSYNC (or the next rising or polling of Video De), the counter in the transmitter starts to count. If the transmitter determines that it wants to send a data island, the transmitter checks the counter and has enough time between the current time and the next expected rising edge of the video DE (or next other necessary event) to send the entire data island from the current counter. Determine whether there are pixel clock cycles.

The circuits of FIGS. 13A and 13C determine whether to insert data islands between two active video periods, determine the temporary placement and duration of each data island to be inserted, and insert each data island into an appropriate time slot. It is implemented in a transmitter according to a preferred embodiment of the invention. 13A and 13C are connected to the multiplexer 118, the core 114, and the subsystems 106 and 108 in the preferred embodiment of the transmitter 100 of FIG. 13.                 

The circuit of FIG. 13A generates a signal ok_to_xmit indicating whether there is enough time left for transmission within the current blank period to insert a data island within the blank period (or to add another packet to an already inserted data island). . The counters 140 and 142 and logic units 141 and 143 of FIG. 13A each receive a pixel clock and data enable signal DE applied to the transmitter, and a reset signal. FIG. 13B is a timing diagram of the signals v_blk_inc, ok_to_xmit_h, ok_to_xmit_v, and ok_to_xmit generated by the circuit of FIG. 13A and the signal DE received by the FIG. 13A circuit in operation.

During the vertical blank period, unit 141 applies to counters 140 and 142 a timing signal v_blank_inc (a sequence of pulses that are in phase with the rising edge of De and in which the rising edge occurs once per line of input video applied to the transmitter). do.

During the vertical blank period, the counter 142, in response to the signals "v_blank_inc", DE, and the pixel clock "clk", counts "v_blk_count [5:" indicating the number of pixel clocks that have elapsed from the start of the vertical blank period. 0]) The counter 140 counts the number of pixel clock cycles that have elapsed from occurring after the last rising edge of DE or the last rising edge of “v_blank_inc” (“h_count [11: 0]”). Counter 140 continues to generate h_count [11: 0] even during the vertical blank period. Logical unit 143 generates the value " v_blk_count [5: 0] " Receive a value of "v_blank_lt [5: 0]" (typically from the transmitter's configuration register) indicating a predetermined length of each vertical blank period of the input video applied to the transmitter. ok_to_xmit_v ", the output signal" ok + to_xmit_v " The rising edge occurs simultaneously with the edge of the first pulse of 'v_blank_inc' received in the vertical blank interval, and the falling edge of the output signal "ok + to_xmit_v" leaves more than enough time left to insert the data island in the vertical blank interval. Occurs when it is not. The logic unit 141 receives a value of "h_count" from the counter 140 and a value of "h_total [11: 0]" (typically from the transmitter's configuration register) indicating a predetermined length of each horizontal line of input video applied to the transmitter. Receive. In response, the unit 141 generates the output signal "ok_to_xmit_h". The output signal "ok + to_xmit_h" has a rising edge when a predetermined number of pixel clock cycles have elapsed from the end of the last horizontal blank section (or the last pulse of "v_blank_inc"), and no more sufficient time to insert a data island within the horizontal blank section. It has a falling edge when it is not left.

When the input of the OR gate 144 receives the "ok_to_xmit_h" signal and the other input of the OR gate 144 receives the "ok_to_xmit_v" signal, the OR gate 144 applies the "ok_to_xmit" signal to the output.

The logic unit 151 circuit of FIG. 13C receives the "ok_to_xmit" signal from the OR gate 144. The logic unit 151 also outputs the output of the VSWOO ("VSYNC windows of opportunity") generator 150, and "packet_req" (indicating that the transmitter is ready to transmit a packet in the data island), the transmitter in the data island. "HDMI_mode", which indicates whether the packet is operating in the mode of applying the serial link, and the "hdcp_enc_en" signal (indicating whether the transmitter's HDCP cipher engine is enabled). Logic unit 151 is configured to insert a data island between active video periods and generate the timing and control signals necessary to transmit each guard band and packet to be transmitted within the data island. Preferably, unit 151 outputs the following signals: (to indicate the portion of the active video period that does not include any video guard band, and the portion of the data island that does not contain any data island guard band, respectively). VidDEnoGB and audDEnoGB (applied to the HDCP cipher engine), vidDe and audDE (indicating the active video period and data island, respectively), DE (vidDE logically "OR" -operated with name DE), (transmitter channel (CH1 and CH2) Hdcp_vs, which represents a time interval in which a code word representing the above-described HDCP cryptographic indicator can be transmitted, video data, video guard band, leading or trailing data island guard band, or packetized data island data during a control data period Data_set [2: 0], indicating whether it is transmitted at timing other than Control [3: 0], which indicates the CTL0, CTL1, CTL2 and CTL3 values to be encoded, and the load_pkt signal (indicating that the data island data has been packetized for transmission) Unit 151 is a general purpose counter; ) Operates in response to a count cnt from and applies a control bit ld_cnt to the counter 152 that causes the counter 152 to determine the value to be counted. It is coupled with the receiver to receive the clock and reset signals.

The VSWOO generator 150 receives the data enable (DE), pixel clock ("clk") and VSYNC signals, and the reset signal, which are input to the transmitter, and the subsequent VSYNC that the transmitter should transmit the HDCP cryptographic indicator described above. A signal representing the above described windows of opportunity (WOO) with a predetermined duration of each active edge is generated. Preferably, the generator 150 is configured to set the duration of the WOO to 72 pixel clock cycles, and the generator 150 outputs the following signals: (high during WOO) vswoo, (starting and ending WOO) Vswoo_start_p and vswoo_end_p, indicating vswoo_48_p (indicating the 48th pixel clock cycle after the end of the application of the VSYNC pulse to the transmitter), vsync_end_p (indicating the end of the application of the VSYNC pulse to the transmitter), and (the beginning of each blank interval and De_start_p and de_end_p) to indicate the end.

Preferably, the timing signal applied by unit 151 causes each of the data island preambles to be transmitted (not earlier than) 48 pixel clock cycles after each polling edge of vidDEnoGB. As described above, the transmitter according to the preferred embodiment of the present invention, through each of the channels CH1 and CH2 of the TMDS link, eight identical data island preamble code word bursts, immediately before each data island, eight identical video preambles A code word burst is sent just before each active video period. In a preferred embodiment, the transmitter transmits a "idle" control word on each of the channels CH1 and CH2 during the control data period prior to application of the data island preamble code word.

Changing the pixel clock rate causes the system according to the invention to miss synchronization frequently between the transmitter and the receiver. By causing the transmitter and receiver to enter a "mute" state (prior to changing the pixel clock rate) in accordance with an embodiment of the present invention, the encryption and decryption circuitry within the transmitter and receiver allows the pixel clock rate to be lost without losing synchronization. Can respond to changes in In general, this is accomplished by sending an alert (usually represented by a control bit) to the transmitter. In response to the alert, the transmitter enters a silent state, includes a receiver alert (generally indicated by one or more silent control bits) in the packet, and sends the packet to the receiver during the data island. In response to the receiver alert, the receiver enters a silent state.

In response to the alert, the transmitter typically sets a flag ("AVMUTE" flag). In the general implementation of the transmitter 100 of FIG. 13, the alert is received at the interface 101 and causes the transmitter to set the "AVMUTE" flag in the register 103 and / or the register 105. In the general implementation of receiver 200 of FIG. 14, the receiver alert causes the receiver to set the AVMUTE flag in register 203 and / or register 205. In response to the AVMUTE flag in the transmitter, an encryption circuit (eg, the cipher engine 104 in the transmitter 100 of FIG. 13) transitions to an idle state after completing processing of the current frame of video. In response to the AVMUTE flag in the receiver, the cipher engine 204 in the decoding circuit (eg, the receiver 9200 of FIG. 14) transitions to an idle state after completing processing of the current frame of video. The transmitter enters a silent state when the encryption circuit transitions to an inactive state, and the receiver enters a silent state when the decryption circuit transitions to an inactive state.

In a transmitter according to a preferred embodiment of the present invention, the operation of the cryptographic circuit at the end of the window of opportunity (described above) following the active edge of VSYNC of the next vertical blank interval occurring after the setting of the AVMUTE flag results in freezing ( freeze) (and enter inactive state). At this time, the transmitter enters a silent state, stops transmitting useful auxiliary data (e.g., audio data) in packet state, and stops transmitting useful video information (e.g., the video and audio output of the transmitter Unchanged in response to input audio and video applied there). The transmitter (in silence) then transmits one or more packets to the receiver during the data island (e.g., preferably within one HSYNC period of the previous active video period, in the form of packets transmitted during the data island when VSYNC is inactive). Send alarms to control bits).

In the receiver according to the preferred embodiment of the present invention, the operation of the decoding circuit at the end of the window of opportunity (described above) following the active edge of VSYNC of the next vertical blank interval occurring after the setting of the AVMUTE flag in the receiver Freezes (and enters inactive state). At this point, the receiver enters a silent state and stops the application of useful auxiliary data (eg, audio data extracted from the packet) at its output and the application of useful video information at its output. Thus, even if the transmitter does not stop transmitting useful information (e.g., video and / or audio) to the receiver via a link during a silent operation, the receiver in the silent state will not receive any useful information from anywhere on its output. Prevent it from being seen, heard, or re-transmitted.                 

When the encryption circuit of the transmitter and the decryption circuit of the receiver enter their inactive state, a change in pixel clock rate can occur. Once the pixel clock has stabilized and all PLLs in the receiver have stabilized, a message is preferably sent to permit the transmitter and receiver to leave the silence (in response to a "silent off" command) to resume encryption and decryption and to audio And "unmuting" the video. While the pixel clock rate is changing, a typical receiver in accordance with an embodiment of the present invention loses the ability to reliably decode the received data. During this time, fake signals of the mode type may be output at the receiver's decoder. For this reason, preferably a change in pixel clock rate occurs when the receiver is silent, and the output of the receiver is silent during the silent state.

Leaving in the silent state is preferably completed by sending a "mute off" signal (generally indicated by the control bits) to the transmitter. In response to the silence off signal (and preferably also the cryptographic indicator), the transmitter leaves the silence state, includes the " receiver silence off " data (generally represented by one or more silence control bits) in the packet, and Send the packet to the receiver during the data island. In response to the receiver silence off signal (and also preferably an encryption indicator), the receiver leaves a silence state.

In general, the silence off signal causes the transmitter to clear the AVMUTE flag described above and the "receiver silence off" data to cause the receiver to clear the AVMUTE flag. In response to the clearing of the AVMUTE flag in the transmitter, an encryption circuit in the transmitter (e.g., the cipher engine 104) may be applied to the transmitter following the active edge of VSYNC in the next vertical blank period that occurs after the AVMUTE flag is cleared. In response to the cryptographic indicator being present, it is left inactive (the sender is silent as soon as it receives the cryptographic indicator). In response to the clearing of the AVMUTE flag in the receiver, the decoding circuitry in the receiver (e.g., the cipher engine 204) causes a WOO (window of) following the active edge of the VSYNC in the next vertical blank period that occurs after the AVMUTE flag is cleared. In response to a cryptographic indicator (eg, the HDCP cryptographic indicator described above) that may be received within an opportunity, the inactivity is left out. The receiver leaves silence as soon as it receives the encryption indicator.

In some preferred embodiments, the invention provides a first chip (eg, receiver 2 'of FIG. 2, or EEPROM 24) that includes most or all of the circuitry needed to recover and process the transmitted data. 2 is a multi-chip module (MCM) including at least another chip (generally implemented as an EPROM) including a receiver 2 'of FIG. 2) and an Enhanced Display Identification Data (EDID) ROM. At the factory, the EDID PROM chip can be programmed with data representing the configuration and / or capabilities of the receiver, and also optionally the key and authentication data (eg HDCP key) used for decryption. The MCM may include a third chip including an EEPROM (eg, the EEPROM 24 of FIG. 2) that securely stores a key and authentication data used for decryption.

In another preferred embodiment, the transmitter according to the invention comprises a PROM (e.g., EEPROM 14 of Figure 2) for securely storing key and authentication data used for encryption and also for storing InfoFrame data. As mentioned above, the EIA / CEA-861B standard specifies an InfoPacket data structure consisting of one or more InfoFrames that contain format information and related information about digital audio and / or digital video data. In some embodiments, the PROM is implemented as a separate chip within the MCM, and the MCM may also include most of the circuitry required for encoding and transmitting data (circuit 1 'in FIG. 2) or And may include one or more other chips that implement the mode. It can be programmed into InfoFrame data and safely embedded within MCOM.

In another embodiment, the transmitter or receiver according to the present invention comprises a selectable host micro-accessible region (e.g., during test mode operation, for example reading a test result or configuring the transmitter or receiver for testing). A region accessible by the host, such as, and a ROM having a non-host accessible region (eg, which can be used to securely store keys and authentication data used for encryption and decryption). MCM containing the chip. For example, the EEPROM 14 of FIG. 2 may be implemented with such a chip, the transmitter 1 'of FIG. 2 may be implemented with another chip, and both chips may be included in an MCM. The non-host accessible area of this integrated circuit implementation of the EEPROM 14 is only accessible by the integrated circuit implementation of the transmitter 1 'and is inaccessible to any device other than the transmitter 1'. Keys and / or other cryptographic key data (and optionally other data as well) may be stored.                 

In another embodiment, the transmitter and receiver according to the present invention comprise one or more PROMs for storing keys and authentication data (e.g. HDCP keys) and / or Enhanced Display Identification Data (EDID) used for encryption or encryption. It is implemented in an integrated circuit. The PROM implemented with this integrated circuit of the transmitter according to an embodiment of the present invention can be programmed with HDCP or other cryptographic keys at the factory. The PROM implemented with this integrated circuit of the receiver according to an embodiment of the present invention may be programmed at the factory with HDCP or other decryption keys and / or EDID data indicating the configuration and / or capabilities of the receiver.

In an embodiment of the invention, the transmitter according to the invention is preferably configured to transmit packets (in data islands) having any of a variety of formats, including information packets having an InfoFramde packet format and other formats described above. If the receiver is configured to receive packets of a particular format, the receiver is preferably configured to store data indicative of this format (eg in an EDID ROM), and the transmitter preferably stores this data (eg, a TMDS link). And respond to it by sending a packet to the receiver in this format). Otherwise, the receiver may signal the transmitter to define the format used by the transmitter to send the packet to the receiver.

Implementing the transmitter in this way allows for future definition of the packet format (eg, information packet format), either for one transmission to the receiver or for repeated transmissions to the receiver.                 

Preferably, the transmitter and receiver are configured to use a two-bit semaphore (or some other signaling scheme on the one hand) to control the automatic transmission of the packet (eg a changeable packet). For example, the transmitter and receiver are configured to transmit a 2-bit code for controlling each other to transmit InfoFrame packets and information packets having different formats. One bit is the "send" bit. The receiver sends the transmit bit to the transmitter, causing the transmitter to transmit or stop the packet. The second bit is the "repeat" bit. The transmitter responds to the send bit from the receiver by causing the transmitter to overwrite the "repeat" bit with a value indicating that the transmitter is transmitting a repeated packet and includes two "repeat" bits. -May be configured to send the bit code to the receiver. The receiver can then respond by applying another send bit to the transmitter. In some embodiments, the 2-bit code is transmitted over a DDC link (or other bidirectional channel between the transmitter and the receiver) such that one or more other channels (eg, channels CH0, CH1, and CH2 of the TMDS link). Causes packet transmission over the network.

Preferably, the transmitter and / or receiver according to the invention comprises an InfoFrame packet (or other format) such as audio and / or video format information and related information about the audio and / or video data to be transmitted or transmitted. And a register space accessible (eg, via an I ² C link) at an external device for storing data extracted from (or contained within) an information packet having a (i). For example, an external source may load this data into this register in the transmitter (eg, register 105 in FIG. 13), and the transmitter may include data to be included in the packet for transmission to the receiver during the data island. You can read the register to get. Preferably, the transmitter is configured to read a bit (received from an external source and loaded into a register), for example, from a register and insert the bit into a certain predetermined time slot of the data stream aggregated into InfoFrame packets for transmission. By including the configured circuitry, it is configured to map the register space into InfoFrame packets (or other information packets). Preferably, the receiver extracts data from packets sent to the receiver (e.g., via CH0, CH1 and CH2 of the TMDS link during the data island) and registers the extracted data with an accessible register (e.g., FIG. 14 registers 205). The external device can then access the register of the receiver, preferably via an I ² C link. For example, the transmitter may access a register in the receiver via the DDC channel of the TMDS link, or the hose device may access this register in the receiver via an I ² C link that is not the DDC channel of the TMDS link.

Preferably, the receiver is configured to store unrecognized information packets (received via TMDS or other serial link) such that a host (e.g., a CPU or other processor coupled with the receiver) can access the stored packets. Can be. This allows the host programmed with the appropriate software to parse each of these stored packets and preferably configure the receiver to process the audio and / or video data to be transmitted over the link in the manner specified by the analyzed packet. Bit can be loaded into a register in the receiver.

Preferably, the receiver according to the invention is a hardware, auto-configured color space conversion CSC (Auxiliary Video information) InfoFrame packet (or other information packet) received over a TMDS link (or other serial link). Circuit), chroma up / down sample rate circuitry, and other video processing circuitry within a receiver, optionally in a packet-determined manner. Thus, once an AVI information packet is combined with video (eg, within a data island) and sent to a receiver, the receiver can respond to the data in the AVI InfrFrame packet by properly configuring its video processing circuitry to process the video. .

Preferably, the receiver according to the invention is a hardware which analyzes an AI (Audio InfoFrame) packet (or other information packet) received over a TMDS link (or other serial link), an automatic in the receiver having a manner determined by the packet. -Configuration audio data processing circuit. Thus, if an AI packet is combined with audio and sent in a data island, the receiver can respond to the data in the AI packet by appropriately configuring the audio data processing circuitry to process the audio data.

In a preferred embodiment, the transmitter according to the present invention has an input interface (eg, a preferred implementation of interface 109 of FIG. 13) configured to receive audio and other auxiliary data over one or more I ² S links, Transmit input data received on each I ² S link as a packet over the serial link (preferably over the CH0, CH1, and CH2 channels of the TMDS link during the data island in audio sample format with the above-described format) To format in order to do so. The expression "I ² S" denotes Left / Right identifying the first conductor of data (typically audio data), the second conductor of the bit clock, and the word clock (e.g., the channel of data to be transmitted through the first conductor). It is used in a broad sense to refer to a three-conductor link that includes a third conductor to a word select clock .. Preferably, the receiver has one or more I ² S output ports and transmits a packet (e.g., audio Sample packets), re-format the extracted data as needed to apply over one or more I ² S links, and convert the extracted data into one or more I ² S output ports in I ² S format. It is configured to apply.

Preferably, the receiver according to the invention accepts PCM input data (i.e. non-compressed I ² S data) from an I ² S link and is used in a system according to the preferred embodiment of the invention described above in response thereto. Reformat the data and transmit the S / PDIF audio data for transmission in an audio sample packet having the same format as that shown. Preferably, the transmitter uses a register programmed with channel status bits that indicate the input data format (from the input data source) to perform the necessary re-format. For example, in the first cycle of the I ² S data word clock, the transmitter samples the input data at the selected edge of the I ² S data bit clock and takes the sample (via FIFO) to the “left” channel S / PDIF sample. Inserted into the time slot of the subpacket for and in the next cycle of the I ² S data word clock, the transmitter continues sampling the input data at the selected edge of the I ² S data bit clock but taking the sample to the right (via FIFO). Insert into time slot of subpacket for channel S / PDIF sample. With the audio data sample, the appropriate channel state, valid user data, and parity bits are preferably inserted into the appropriate time slots of the subpacket, and the start bits are inserted into the packet header (via FIFO) at the appropriate timing.

In a preferred embodiment, the transmitter according to the invention has an input interface capable of accepting input audio data from 1-4 I ² S links. In some such embodiments, the transmitter can accept input audio data from a multichannel system on one, two, three or four I ² S links, where the I ² S links use the same bit and word clocks of mode and (Thus, all the information in the 2, 6. 9 or 12 input I ² S conductors is contained within 3, 4, 5 or 6 input I ² S conductors: one bit clock conductor; one data clock conductor, and 1 2, 3 or 4 data conductors) format the data for transmission into a packet (preferably an audio sample format having the above-described format). In another embodiment, the transmitter can accept input audio data from 1-4 I2S inputs, even when each I2S input has an independent clock (and therefore the bits received at all input I2S conductors must be packetized). It has an input interface and formats the data for transmission into packets (preferably in an audio sample format having the above-described format).

In a preferred embodiment, the transmitter according to the invention can reconstruct (e.g., stream / channel mapping of the input audio data within the constraints imposed by the available channel / speaker arrangement for packetizing the data for transmission). Multiplexer circuitry (in the data capture block of interface 109 of FIG. 13). Thus, such a transmitter can accept input audio data (e.g., input audio from one or more I ² S links) in any format set (each with a unique stream / channel mapping) and receive the data in packets ( Preferably in another set of formats that are accepted for transmission (in audio sample format having the above-described format).

S / PDIF data streams have their own clocks (embedded in data samples). In some embodiments, a transmitter in accordance with the present invention samples an input stream of S / PDIF data (generally, S / PDIF audio data) with a pixel clock having an unknown phase relationship with a clock embedded in the input data. And transmit pixel-clock-sampled data. In another embodiment, the transmitter has a frequency of at least 256 * Fs (or 384 * Fs in the preferred embodiment) when Fs is the sample rate of the S / PDIF data and there is an unknown phase relationship with the clock embedded in the input data. And is configured to sample the input stream of S / PDIF data into an audio reference clock (sometimes referred to as "MCLK" or master clock).

In a preferred embodiment, the transmitter according to the invention is configured to accept and synchronize multiple independent, synchronous S / PDIF streams.

Preferably, the transmitter according to the invention is configured to transform the flatline S / PDIF input (consisting of all zeros) into a format for efficient transmission in packets. For example, the transmitter is configured to set four bits of the packet header to indicate whether the corresponding subpacket contains a "flatline" sample (ie, a sample consisting of all zeros). For example, the transmitter is configured to set 4 LSBs of the third byte of the packet header (as described above) to indicate whether the corresponding subpacket contains a "flatline" sample, in which case the receiver is preferably a header. A value of "1" of any of these LSBs is considered valid only if the corresponding "current" bit of the second byte of (one of the 4 LSBs of the second byte) indicates that the corresponding subpacket contains samples. It is configured to.

In a preferred embodiment, the transmitter according to the invention is configured to accept Direct Stream Digital (DSD) input data and format it for transmission to IEC60958-type during the data island. Audio data (eg, SACD or “Super Audio CD” data) in conventional DSD (Direct Sream Digital) format may be a three-conductor link: one link to the bit clock; 2 conductors (ie, one left channel conductor and one right channel conductor) for each of the other channels. Preferably, the receiver has one or more DSD outputs, extract audio data from transmitted packets (e.g., audio sample packets), reformat the extracted data as needed to apply it to the DSD output stream, Apply extracted data in DSD format to one or more DSD output ports.

Preferably, the transmitter according to the present invention accepts DSD input data and transmits it in an audio sample packet having the same format as used in the system according to the preferred embodiment of the present invention described above for transmitting S / PDIF audio data. And has an input interface configured to respond to DSD input data by reformatting the data. Preferably, the transmitter uses a register programmed with channel status bits that represent the input data format (from the input data source) to perform the necessary reformat.

In a preferred embodiment, the transmitter according to the invention has an input interface capable of accepting multiple streams of DSD format input audio. In some such embodiments, the transmitter can accept DSD format input audio data from multiple DSD links even when each DSD stream has an independent clock (and therefore the bits received at all input DSD conductors must be packetized). It has an input interface that can be formatted to transmit data in packets (preferably in audio sample packets having the format described above).

When the transmitter is configured to accept input audio data in I ² S format (on three conductors: one conductor for the bit clock; one conductor for the L / R clock; the other conductor for the data): The transmitter is also preferably configured to accept and transmit audio data in DSD format at the same three-conductor input port. Such a transmitter preferably comprises a multiplexer which maps three input streams into circuitry for formatting the input data for transmission in an audio sample packet having the above-mentioned format as appropriate.

In a preferred embodiment, the receiver according to the invention has one or more I ² S output interfaces, recovers PCM data from an audio sample packet, and restores the recovered data in an I ² S format (e.g., by audio by a transmitter). And a register programmed with channel status bits transmitted in the Audio InfoFrame (AI) packet sent to the receiver with the sample packet.

In a preferred embodiment, the receiver is configured to output audio data (reconstructed from an audio sample packet) in I ² S format on 1 to 4 I ² S outputs (each output configured to be connected to a 3-conductor I ² S link). Is configured to output.

In a preferred embodiment, the receiver according to the invention is in an I ² S format on 1 to 4 I ² S outputs (including applying different I ² S data streams with different independent clocks to different outputs). And output audio data output from the audio sample packet.

In a preferred embodiment, the receiver according to the invention comprises a multiplexer circuit capable of reconstructing the stream / channel mapping of the audio data extracted from the packet into a format within the constraints imposed by the available channel / speaker arrangement for packetizing the data. Include. Thus, such a receiver extracts data from a packet (preferably an audio sample packet having the above-described format), reformats the extracted data from one of the other sets of packetized recognized formats, and then the audio Data can be output in any format set (eg, on one or more I ² S links) (each with a unique stream / channel mapping).

In a preferred embodiment, the receiver according to the invention is configured to output S / PDIF format data. Preferably, the receiver is configured to transform the packetized code representing flatline S / PDIF data (consisting of all zeros) into flatline S / PDIF format output data. In some embodiments, the receiver is configured to recognize whether four bits of the packet header indicate whether the corresponding subpacket contains a "flatline" sample (ie, a sample consisting entirely of zeros). For example, the receiver is configured to recognize whether 4 LSBs of the third byte of the packet header (as described above) indicate whether the corresponding subpacket contains a "flatline" sample, and the second byte of the header Only when the corresponding "current" bit (one of the 4 LSBs of the second byte) indicates that the corresponding subpacket contains samples, the value of "1" of any of these LSBs is configured to be valid.

Preferably, the receiver according to the invention is configured to output the data in DSD format in response to an audio sample packet comprising an encoded version of the DSD data. Preferably, the receiver is configured to output multiple DSD data streams with an independent clock, in response to an audio sample packet containing an encoded version of the DSD data. The receiver responds to the audio sample packet with an I ² at the output port (for connection to a three-conductor link containing one conductor for the bit clock; one for the L / R; and one conductor for the data). Is configured to output audio data in the S format, preferably the receiver is also configured to output audio data in the DSD format at the same output port (e.g., the receiver outputs three input streams recovered from the audio sample packets). Includes a multiplexer that maps to the appropriate conductor of the port).

In preferred embodiments of the present invention, the transmission of audio data over the serial link is driven only by the pixel clock so that the original audio sample clock must be regenerated at the receiver in an operation known as ACR (Audio Clock Regeneration). Next, some embodiments of the present invention, which are implemented by ACR as a preferred method, will be described.

As mentioned above, a system according to a preferred embodiment of the present invention transmits a time stamp (“CTS” value) indicating an audio clock (for audio data to be transmitted on a data island over a TMDS or other serial link), and preferably Preferably transmit an "audio clock regeneration" packet containing both the "CTS" value and the "N" value used for the audio clock regeneration. The "N" value is a "molecular" value that represents the numerator of the fraction by which the receiver multiplies the frequency of the pixel clock to regenerate the audio clock.

There are various methods of clock regeneration that can be implemented in the receiver of the system of the present invention. In many video source devices, audio and video clocks are generated from a common clock. In this case, there is a ratio (integer divided by integer) relationship between the audio and video clocks. The clock regeneration scheme can take advantage of these ratio relationships and can also operate in environments where there is no such relationship between these two clocks.

15 is a block diagram of a structural model of the overall system used by the preferred embodiment of the system according to the present invention for audio clock regeneration. The transmitter is known as the pixel clock (video clock) and audio reference clock ("MCLK" or master clock), where MCLK has a frequency equal to Z * Fs, where Fs is the audio sample rate and Z is typically Y * 128. Where Y is a small integer such as 1, 2 or 3). The transmitter delivers the numerator (N) and denominator (CTS), and pixel clock for this ratio to the receiver (through the transmitter's format, encoding and transmission circuitry 138) over the serial link. The recovery and decoding circuitry 139 in the receiver then recovers the data representing the pixel clock and the N and CTS values, and the receiver uses the clock divider 132 and clock multiplier 133 (the frequency is referred to as "PixelClock"). Regenerate the MCLK clock from the pixel clock. The clock multiplier 133 is typically a PLL including a phase detector 134, a low-pass filter 135, a voltage-controlled oscillator 136 and a frequency divider 137, connected as shown in FIG. 16. Is implemented. The exact relationship between MCLK and pixel clock frequency is Z * Fs = PixelClock * N / CTS.

The transmitter determines the molecular "N" value (generally input by the input data source) as shown in FIG. 15 and stores the data representing "N" in register 129. The N value is used in clock divider 130, which also receives MCLK (with a frequency of Z * Fs) to generate an intermediate clock that is slower by a factor N than the MCLK clock. The pixel clock and the intermediate clock are applied to the counter 131. The counter 131 generates a cycle time stamp (CTS) count by counting the number of pixel clock cycles that have elapsed (after the last CTS value has been applied) for each clock of the intermediate clock.

Data representing the N and CTS values is transmitted to the receiver (preferably in each of the audio clock regeneration packets transmitted by the format, encoding and transmission circuitry 138 via the TMDS link during the data island) and the pixel clock is applied to the receiver. do. The pixel clock is preferably transmitted to the receiver (e.g., by circuit 138 of FIG. 15) on the clock channel (e.g., channel CHC of FIG. 2) of the TMDS link.

If there is a constant ratio relationship between the MCLK and the pixel clock, these two clocks are synchronized exactly, and successive CTS values quickly converge to a constant. If the MCLK and pixel clock are not synchronized or there is some amount of jitter between them, successive CTS values generally repeat two or three other possible values.                 

In a preferred embodiment, the transmitter according to the invention accepts an MCLK with a frequency several times 128 * Fs (not an MCLK with a frequency of 128 * Fs), each of which uses the same molecular value "N". Configured to frequency divide.

In another preferred embodiment (with different types of audio data each having different sample rates, such as data with Fs = 32 kHz, data with Fs = 44.1 kHz, and days with Fs = 48 kHz, etc.), The transmitter according to the invention is configured to accept an audio clock based on a "divided down" version of the audio clock (frequency is the greatest common factor of all possible audio sample frequencies). The frequency of this audio clock is Z * Fs / M, where Z and M are integers, Fs is the audio sample frequency, and Fs / M is the greatest common divisor of all possible audio sample frequencies. To use such a transmitter, the receiver is configured to regenerate a "divided down" version of the audio clock from the transmitted time stamp, and preferably also multiplies the regenerated clock by an appropriate factor And regenerate the original audio clock from the regenerated clock. This factor is communicated to the receiver, preferably in an "audio clock regeneration" packet.

If a communication link is required to support several clock frequencies that are multiples of a small set of the lowest frequencies (called "base frequencies"), then only the base frequencies corresponding to the desired frequencies need to be transmitted. The desired frequency at the receiver can be regenerated by multiplying the fundamental frequency by an appropriate factor. This has the advantage that the receiver can be implemented with a simpler and possibly more reliable clock regeneration PLL.

For example, in commonly used audio formats, the data rate is a multiple of 32 kHz or 48 kHz. PLLs designed to support both of these frequencies require reference frequencies in the 32kHz to 48kHz range. When data is transmitted using a divided audio clock (frequency is the greatest common factor 16 kHz), the clock regeneration PLL may include a frequency multiplier circuit, with a scaling factor of 2 and 3, in order for the receiver to regenerate some original audio clock. May be implemented such that the reference clock is 16 kHz.

On the other hand, a more specific implementation uses 32 kHz as the transmitted clock frequency. When transmitting audio data with a rate of 48 kHz, this has two drawbacks that make the implementation ineffective. First, on the transmitter side, the 48 kHz clock needs to be synchronized to the 32 kHz clock using a 2/3 magnification circuit, which requires a complex PLL on the transmitter side, whereas the implementation described in the previous paragraph is hardware dependent. It only requires a divider (counter) on the transmitter side that can be implemented more effectively. The receiver side also requires a 3/2 clock regeneration circuit to resynchronize the received 32 kHz clock to the desired 48 kHz clock. This is possible in two possible implementations: a frequency divider (half the frequency of the regenerated 32 kHz clock) before phase detection of the PLL (eg, before phase detection 134 of FIG. 16), and divide-by three) including a frequency divider (implementation of frequency divider 137 of FIG. 16 with N = 3); Or a PLL having a divide-by three frequency divider (implementation of the frequency divider 137 of FIG. 16 at N = 3) followed by a frequency divider that halves the 96 kHz frequency generated in the PLL. One requires a complex clock regeneration circuit in the receiver having: Although the second common implementation has the problem of requiring a higher VCO output (96 kHz) than the highest actual desired frequency (48 kHz), which unnecessarily increases the difficulty of the PLL VCO design, reuse of these process techniques and previous designs. Depending on such factors, one of these PLL designs will be most efficient.

The above example assumes that the audio clock frequencies are 32 kHz and 48 kHz, but for illustrative purposes. In practice, the commonly used audio frequencies are now x1, x2 and x4 times 32 kHz, 44.1 kHz and 48 kHz, and both higher and lower multipliers (/ 2, / 4) are under development.

Even for the three commonly used frequencies of 32 kHz, 44.1 kHz, and 48 kHz, the simplification of the receiver implementation is based on fundamental frequencies such as 16 kHz (= 32 kHz / 2 = 48 kHz / 3) or 22.05 kHz (= 44.1 kHz / 2). B) or an audio clock having a multiple of each fundamental frequency (MB) is applied to the transmitter, and in response to this audio clock a time stamp (CTS value), molecular values "N" and "L", denominator value "D", And operating the transmitter to apply a pixel clock to the receiver. The receiver includes a frequency divider (implementing circuit 132 of FIG. 15) that regenerates the intermediary clock (with frequency B / N) from the time stamp and pixel clock, and a PLL and appropriately multiplies the intermediary clock to "N". And a regeneration circuit (implementation of circuit 133 of FIG. 15) which regenerates the audio clock having any of the desired frequencies BL = 32 kHz, BL = 44.1 kHz or BL = 48 kHz from the “L” value. This alleviates the design requirements because the reference frequency range of the PLL in the regeneration circuit of the receiver is reduced from 32 kHz-48 kHz to 16 kHz-22.05 kHz. In this embodiment, the transmitter does not need any PLL and the PLL implementation requirements in the receiver are reduced. Since a larger range of input audio frequencies is supported, the simplification of implementation in the receiver is correspondingly greater.

More generally, in a preferred embodiment of the present invention, the transmitter accepts and responds to an audio clock based on a "divided" version of the input audio clock (this frequency b is the greatest common divisor of all possible input audio clock frequencies). To apply a time stamp (CTS value), molecular value "N", "L", denominator value "D", and pixel clock to the receiver. The receiver includes a frequency divider (implementing circuit 132 of FIG. 15) that regenerates an intermediate clock (with frequency B / N) from the time stamp and pixel clock, and a PLL, and the intermediate clock and "N" and "L". Implementation of a regeneration circuit (circuit 133 of FIG. 15) appropriately fulfilling the frequency magnification of the arbitration clock to regenerate an audio clock having a frequency BL from which value BL is equal to any of the possible audio sample frequencies. Is implemented as Optionally, the transmitter does not apply an "L value" and the regeneration circuit in the receiver regenerates only a "divided" version of the input audio clock (with a frequency equal to B) from the intermediate clock and the "N" value.

In a system according to a preferred embodiment of the invention in which an audio clock is transmitted by sending a time stamp value (“CTS” value) and a pixel clock to the receiver, when it is clear that these clocks are all drawn from a common clock. The transmitter is configured to implement auto-phase alignment to synchronize the pixel clock with the audio clock (eg MCLK applied to the transmitter of FIG. 15). This ensures that the time stamp value does not change over time.

If the pixel clock (also referred to below as the "video clock") and the audio clock are synchronous or nearly synchronous, the audio clock information can be transmitted over the link by counting the number of video clock cycles in audio clock cycles. If the audio and video are synchronized, this number must be constant. However, if the rising edge of the audio clock occurs very near the rising edge of the video clock, a very small amount of jitter can move the audio clock edge back and forth of the video clock edge. This causes the count of " video clock period per audio clock period " (" CTS " value) to vary over time. This jitter of the CTS value potentially affects the quality of the regenerated audio clock and contributes to the extent that a small amount of jitter in the original audio clock is amplified (the regenerated audio clock has a worse quality than the original audio clock). In that it has).

To address the jitter problem in the CTS due to jitter in the audio clock, a preferred embodiment of the present invention uses an oversampling technique in the clock domain “boundary” (boundary on the audio and video clock) to automatically select a delay. And maximize hold time. That is, various phase-shifted versions of the audio clock are generated (eg, by "oversampling" the audio clock using various versions of the video clock, such as the video clock itself and inversion of the video clock), and the minimum CTS. One of the resulting streams of samples making jitter is selected. This can prevent any "CTS jitter" as long as the video and audio clocks are synchronized and reasonably stable. An important advantage of this design is that it can simplify system-level design (since the present invention eliminates the need to worry about audio and video clock skew).

In some embodiments, the transmitter counts audio clock edges using video clock VCLK and inverted video clock VCLK_bar to generate two sets of CTS values, and compares the two sets of CTS values to determine which It is determined that this represents less variation with time. The output of the VCLK-based can be selected initially (as the CTS value to be sent to the receiver) with the option that it will switch to the VCLK_bar-based output if it shows less CTS value variation over time. These embodiments have the advantage of having a pure digital design, and the circuitry to achieve this can be automatically implemented (placed or routed) into an integrated circuit, and more easily transformed into a new integrated circuit fabrication process.

Other embodiments generate several sets of CTS values by using several delay cells to generate various phase versions of the video clock, and generating a set of CTS values each using a different version of the video clock. The transmitter then monitors the set of CTS values for transition and selects the set with the least transition. This method uses a very small area on the transmitter chip but requires layout for hand design and timing critical sections.

The rate at which "autoaligning" is done (switching between different sets of CTS values) should be kept quite low (on a time scale in seconds, or only at the start and when the audio or video frequency changes). This is because without a slightly slow (ie temperature related) phase shift between the audio and video clocks, the audio clock and video clock timings do not much predict in a particular design whether coherent audio and video have been transmitted. . If the relative timing of the video and audio clocks fluctuates quite often (ie, for non-interfering video and video), the CTS value transmitted over the link, which is the purpose of the CTS counting method, is changed.

If automatic alignment continues to be performed, additional logic is required to ensure that the transmitted CTS value is correct if the audio and video clocks are not fully synchronized (ie, slow drift between the two clock signals). This can be seen by observing FIG.

Referring to FIG. 22, first, an audio clock for VCLK timing is shown in Case 1, and the falling edge of VCLK is used as a reference, and a small CTS count is calculated based on both the rising edge and the falling edge of the VCLK counter (ie, based on VCLK). One CTS count and another CTS count based on the inversion of the VCLK). Then, if the audio clock edge drifts to the right as shown in case 2, it goes beyond the VCLK falling edge, the "rising edge VCLK" CTS value remains constant, and the "poring edge VCLK" CTS value is the audio clock edge. Increases by 1 when it crosses the VCLK falling edge (if there is jitter between clocks, the falling edge CTS value will shake to +1 and -1 of the normal value, but the lining edge VCLK when finally settled on the right side of the edge) Remains 1 below). At this time, the automatic alignment circuit in the transmitter according to the present invention should select the "rising edge VCLK" CTS value. As a clue to the discussion, assume that a transition (to rising edge VCLK CTS Aux) is made and returned when the audio clock crosses the falling edge. In this case, the transmitted CTS value is bound around an average value of 27,000, but the overall average value continues to be 27,000. Then, it is used when the "rising edge VCLK" CTS value is a constant of 27,000. And in case 3, time passes further, so the audio clock edge again passes the rising edge of VCLK. We again assume that the same thing happened: switching when the audio clock edge is jittered back and forth near the VCLK rising edge and the audio clock edge is still to the left of the VCLK rising edge before the auto-align circuit switches the VCLK clock edge. do. Again, the average CTS value sent by the rising edge CTS counter is 27,000. The transmitter then switches to the "falling edge VCLK" CTS counter and delivers a constant value of 27,000. Thus, the transmitted CTS value always remains 27,000, but the actual accumulated CTS value is one high. To operate with this result, the transmitter according to the preferred embodiment counts the difference between the accumulated CTS value and the " rising and falling edge VCLK " CTS value, and when the auto-align circuit is switched to the new VCLK edge, The difference count (between the count value and the cumulative count based on the selected new VCLK edge) should be sent to the receiver to avoid this error.

With jitter in the audio clock (derived from the audio alignment described above and phase alignment in the pixel clock), which is an alternative to the automatic alignment technique described above (selecting different CTS values based on different versions of the pixel clock used to sample the audio clock). Another method of reducing amplified jitter in the regenerated audio clock (regenerated using the transmitted CTS value) is to implement the transmitter to sample the audio clock with a clock having a higher frequency than the pixel clock. As described above, jitter in the original audio clock can cause jitter in the CTS value, which can affect the quality of the regenerated audio clock, and (the regenerated audio clock has a worse quality than the original audio clock). At this point, a small amount of jitter in the original audio clock may be amplified. The worst-case state is that the audio clock edge is near the video clock edge but moves back and forth of the edge. In this case, small amounts of audio and video clock jitter (eg, 1 ns jitter) can produce more jitter if the CTS values toggle back and forth (up to 40 ns if a 25 MHz pixel clock is used). This CTS jitter can occur on low quality reconstructed audio clocks.

Another advantage of more accurate measurements of the audio clock (by sampling at higher frequencies) is to allow the actual jitter in the regenerated audio clock to be tracked more closely. More accurate measurements of jitter can also reduce the frequency range required for MCLK regeneration circuits to cover, and in some circumstances make receiver design easier to implement.

A simple oversampling method for making finer resolution measurements of audio clock periods is to measure the audio clock period using both the rising and falling edges of the video clock. If the video clock duty cycle is close to 50%, the method can measure at twice the resolution achievable using only the rising (or polling) edge of the video clock. Another oversampling method involves oversampling pixel clocks (generally generated for other purposes in TMDS core processes, such as processor 114 in transmitter 100 of FIG. 13), which can increase the time resolution to 10x or 30x. However, this requires more complex circuitry and requires the use of a packet with a format suitable for transmitting this more delicate resolution measurement over the link.

If it is correlated in that both MCLK and pixel clocks are extracted from a common clock (and therefore, CTS values representing a count of "pixel clock periods per audio clock period" are not expected to fluctuate during transmission of a single stream or set of streams of audio data). The transmitter according to the present invention may be implemented to include a programmable CTS register (not a circuit, for example elements 130 and 131 of the transmitter of FIG. 15 to generate a CTS value). The external device sometimes loads the updated CTS value into the CTS register from time to time (preferably periodically), and the transmitter includes the current CTS value (in the CTS register) in each Audio Clock Regeneration Packet sent to the receiver. Is configured to.

In a receiver in accordance with a preferred implementation of the invention, an audio clock regeneration (ACR) circuit is provided with a pixel clock, a time stamp value CTS, one or more other values from the transmitter (e.g., some other values from the transmitter). Responsive to a single value of one molecular value "N" and a frequency fold value "M"), with a frequency of M * Z * Fs that is several times the first frequency Z * Fs, where Z is generally 128 Configured to apply a version of the audio clock (MCLK) (to an output). For example, the receiver may have an MCLK having a frequency of 128 * Fs in response to M = 1, an MCLK having a frequency of 256 * Fs in response to M = 2, and a frequency of 384 * Fs in response to M = 3. Outputs MCLK with

In a preferred implementation, the receiver according to the invention is configured to operate in two modes; A first mode using an internal audio clock regeneration (ACR) circuit (including PLL) to regenerate the audio clock MCLK and optionally also generate one or more clocks having a frequency equal to a multiple of this audio clock; The second ARC circuit is ignored and instead the CTS and N values and pixel clock received from the transmitter are applied to an external device (eg, external PLL unit 160 of FIG. 15) for MCLK clock regeneration. The receiver in the second mode can use the regenerated MCLK from an external device (including by stabilizing in an internal PLL circuit with VCO) and / or send it to another device. In some preferred embodiments, the device of FIG. 15 is an intermediary clock generated by a clock divider 132 in a second mode of operation of a receiver to drive an external ACR device, the intermediate clock being Z * Fs / N. And a regenerated MCLK from an external ACR device. This slight modification of the receiver of FIG. 15 further outputs a regenerated MCLK that is received from an external device or by stabilizing the regenerated MCLK (either in a PLL implementing clock multiplier 133, or in another internal PLL with a VCO). Can be processed. In some embodiments, an external ACR device providing a reconstructed MCLK with the modified receiver of FIG. 15 (operating in a second mode) may provide a PLL (e.g., a PLL that provides stable recovered MCKL only within a relatively narrow frequency range). Voltage controlled crystal oscillators or those comprising a voltage controlled crystal oscillator (VCXO). In this case, the receiver can be either through automatic clock stretching or shrinking (ie, to generate a reduced or increased frequency version of the MCLK signal regenerated from an external PLL when needed), or by automatic sample repetition or By using the MCLK signal regenerated from an external PLL to sample the audio data recovered from the packet, to generate an output audio sample stream having a sampling rate that is different from the frequency of the recovered MCLK signal, however, the output By inserting the repeated sample into the reconstructed audio sample or by removing some sample therefrom).

In some preferred embodiments, the receiver according to the present invention utilizes a "very small-N" frequency synthesizer PLL for audio clock regeneration. For example, the PLL implementation of clock multiplier 133 of FIG. 15 receiver is effectively configured by multiplying the frequency of the clock signal from circuit 132 by a non-integer value "N". For example, such a frequency synthesizer PLL may be implemented by elements 134, 135, 136 and 137 of FIG. 16 when the frequency divider 137 is a dual-modulus frequency divider. In such a PLL, the phase detector 134 receives and responds to the outputs of the frequency dividers 132 and 137 to produce a signal representing this relative phase, and the loop filter 135 loop-pass filter and phase detector 134 Receives an output of and generates an error signal representing the relative phase of the outputs of the dividers 134 and 137, wherein the VCO 136 has a frequency approximately equal to (Z * Fs) in response to the error signal from the filter 135. ) Apply the output clock. When "N" is a non-integer that satisfies I <N <I + 1 (where I is an integer), frequency divider 137 receives the output clock and in response Z * Fs / I or Z * Fs / I Outputs a clock with a frequency of +1. When the divider 137 operates cyclically with both modulus (modulus I, then modulus I + 1, then modulus I, in this order), the duty cycle and divider at which the divider 137 operates at modulus I ( The control of the duty cycle in which 137 operates at modulus I + 1 produces a time-averaged value of the following output clock frequency:

(Z * Fs) _av = W * Fs, Z <W <(Z + 1).

The divider 137 should be configured such that its duty cycle is set to the difference between N and the nearest integer to N, such that the time average value of the output clock frequency does not differ significantly from Z * Fs by more than a reasonable amount.

In a preferred embodiment, the receiver according to the invention uses a circuit comprising a narrow range of PLLs for audio clock recovery (e.g., a narrow VCO frequency range of the incoming clock from frequency divider 132 to it). Stable and accurate PLL implementation of the clock multiplier 133 of the receiver of FIG. The ACR circuit in such a receiver multiplies the frequency of the regenerated clock signal output from the narrow-range PLL by any one of several different numbers, where the PLL is capable of outputting only a regenerated clock with a narrow range of frequencies and in this range. A regenerated clock with an outside frequency may be needed or required. However, the frequency multiplier itself generally requires a PLL, and this embodiment of the present invention provides that a narrow-range PLL (for clock regeneration) with one or more additional PLLs (for frequency multiplier) is capable of clock regeneration. It is generally useful if it is simpler or less expensive than a wide-range PLL.

In some embodiments, the receiver according to the invention consists of two or more chips. The first chip contains most or all of the necessary circuits except for the PLL used for audio clock regeneration, and the second chip includes the PLL. This multi-chip module (MCM) implementation can significantly reduce noise compared to a single-chip implementation of the same circuit. Meanwhile, the second chip (for example, the circuit 161 of FIG. 16) implements only a low-pass filter used for the PLL, and a clock recovery circuit different from the rest of the PLL is implemented in the first chip. In a variant of the FIG. 16 implementation according to the latter embodiment, the low-pass filter 135 may be removed, the function performed by the external filter 161 or the filter 135 may be included, and the receiver may be an internal filter. Configured to operate using either 135 or external filter 161.

In another embodiment, a receiver in accordance with the present invention comprises a stable clock (STS) for generating a "stable" time stamp (CTSx) from the same pixel clock at the same time that the transmitter generates a time stamp (CTSv) from the same pixel clock. audio clock regeneration circuitry using a stable clock (e.g., a crystal clock). The receiver is typically a time stamp (CTSv) transmitted from the receiver in a timely manner to reduce errors caused by jitter in the regenerated audio clock (either the audio clock regenerated using either the CTSx or CTSv time stamp) or jitter in the picel clock. Use a stable time stamp instead.

A preferred embodiment of the system according to the invention uses a time-stamping method for transmitting an audio clock (eg MCLK) between a transmitter and a receiver, where the digital cycle time stamp (CTS) value is the MCLK and CTS value. This is determined by counting the number of pixel clock cycles (VCLK cycles) of each period transmitted to this receiver. At the receiver, the MCLK is reconfigured by counting off the "CTS" VCLK cycles per cycle of the regenerated MCLK. In this process, there may be many jitter sources such as jitter on the original MCLK as well as jitter by the phase alignment of the original MCLK and VCLK (“VCLK” refers to the pixel clock). Since MCLK and VCLK have independent sources, the CTS value generally varies over time and therefore inserts jitter into the reconstructed MCLK. While these and other sources of jitter are important and can affect the final audio quality, they are managed by other techniques (disclosed here), except for VCLK jitter, so as not to degrade restored audio quality. .

The problem presented by the embodiments to be described next is the degradation of the reconstructed audio quality for VCLK jitter. This deterioration can be clearly seen in the following cases. Assume that the MCLK frequency is 1 kHz (1 ms period) and the VCLK has a 0.5 kHz (2 ms period) jitter element, and the CTS value is (CTS period is longer than the average, for example, CTS than when the average period is used). Assuming that the count value is measured during the first half cycle of VCLK jitter, a smaller than average CTS value is transmitted over the link (when the VCLK period is shorter than average) and during the second half cycle of VCLK jitter. It is used to regenerate MCLK. Using a CTS value less than the average to count out VCLK periods shorter than the average causes the regenerated MCLK period to be shorter than the ideal MCLK. In fact, MCLK jitter is an amplified (doubled) version of VCLK jitter. This is the result of using VCLK on each side of the link. This is the worst case and can potentially seriously degrade audio quality.

In summary, a problem during the transmission of VCLK jitter to MCLK occurs when the jitter on VCLK is in one phase during the measurement of the CTS and then in another phase during MCLK regeneration. In the worst case described above, the specific time interval between CTS measurement and MCLK regeneration is important only when it affects the maximum frequency of VCLK jitter that is corrected according to the present invention. Basically, if VCLK jitter changes quickly relative to the time needed to measure, transmit, and use a particular CTS value, VCLK jitter cannot be effectively filtered out and removed. Thus, longer delays in the CTS path mean that only VCLK jitter up to 500 Hz (best case for 1 kHz CTS clock rate) can be filtered out, for example, filtering has a frequency below 500 Hz. Only jitter can be corrected.

To solve the VCLK jitter problem, a stable time base (which can ignore jitter) is used at the receiver, and to measure the MCLK period, a stable time base is created at the same time that the "CTS" VCLK cycle is counted off in the transmitter. "CTS" VCLK cycles are counted off in the receiver. Once the count of the receiver using a stable time base is known, it can be used at any time later to regenerate the MCLK without inserting jitter since once the stable time base has been used.

The stable time basis at the receiver is preferably implemented by using a crystal external to the receiver to provide a stable clock (XCLK).

There are two main difficulties in implementing the above scheme. First, the procedure requires the measurement of the number of CVCv occurrences of the VCLK in the MCLK cycle on the transmitter side at the same time that the number of XCLK cycles CTSx for the same MCLK cycle is counted off in the receiver. That is, counting must begin simultaneously (or nearly simultaneously) on both sides of the link. This requires a method of synchronizing the start of counting in the transmitter and receiver. The second difficulty is that the receiver needs to count (within XCLK cycles) the same number of CTSv of VCLK cycles to be measured simultaneously in the transmitter, and because the CTSv value changes each time it is measured, the receiver will not be able to receive packets containing CTSv values. It is not known exactly what value is measured within the transmitter until it is transmitted over the link. This requires a way for the receiver to anticipate the CTSv value currently being measured at the transmitter and to stop counting at the same (or nearly the same) time on both sides of the link.

Many other ways of synchronizing counts by transmitter and receiver counting may be acceptable. Synchronization generally requires the use of a signal common to both the transmitter and receiver as an origin defining an interval (such as the number of VCLK cycles) at the time when counting should begin. By transmitting this signal over the link, CTSx counting in the receiver, which may start early, may be delayed by an appropriate amount to synchronize counting in the transmitter and receiver. Any re-sync process must be able to handle situations where the MCLK and video signal sources are independent.

The method by which the receiver anticipates the CTSv value currently measured within the transmitter, causing the counting to stop at the same (or nearly the same) time on both sides of the link, suggests that the CTS value is generally expected to not vary widely over time. The facts can be used (generally, the CTS value is expected to vary only as little as +1 or -1 from the normal value). This allows the receiver to count and store CTSX values for a small range of CTSv values, and then when the actual CTSv values are sent over the link, the receiver only uses the actual CTSv values as a pointer to correct the CTSx values. . This method requires that the CTSx value be buffered until the worst time delay of the CTSv packet sent over the link before the CTSx value can be used for regeneration of the MCLK period. This method is generally suitable because a stable time base allows this latency without the use of jitter.

The timing diagram of FIG. 23 is an example showing how transmitter and receiver counting can be re-synchronized. The value of the CTSv counter in the transmitter is captured at the leading edge of VSYNC (this value is indicated as “CTS_sync” in FIG. 23) and is sent over the link at high priority. Using CTS_sync and the CTSv value for the corresponding period (denoted as “CTSv_0” in FIG. 23), the delay between transmitter counting and receiver counting can be determined if receiver counting first started at the leading edge of VSYNC. have. Then, at the point when VCLK jitter no longer affects the regenerated MCLK (since the receiver will use the appropriate CTSx value for MCLK regeneration), the counting in the receiver is properly synchronized with the transmitter counting.

In some variations, the time stamp for the reference clock (generated from MCLK) is sent over the link instead of the time stamp for MCLK itself. The regenerated reference clock is then used to regenerate the MCLK.

In a preferred implementation, the latency of synchronization between the transmitter and the receiver is handled with care. This latency may employ a fixed offset between the transmitter and the receiver since the receiver is actually synchronous with the delayed version of the VSYNC signal applied to the transmitter. This is acceptable if this offset is small, but the maximum latency needs to be controlled. Another option is to send the transmitter latency over the link as a packet so that the receiver can use it to determine whether to make appropriate adjustments.

Since the receiver counts only a few common CTSv values, the starting point of counting needs to be corrected in an ongoing manner until the actual CTSv values are available at the receiver. Since neither the VCLK cycle nor the XCLK cycle is removed or added to the counting (to prevent long term drift), it is dangerous, if the start of counting is adjusted, the change is made by adjusting the previous CTSx value. Will need to be considered.

In a variation of the above embodiments, the CTS_sync value is transmitted once per video frame (assuming VSYNC is based). This allows the receiver to make small corrections to the frame basis that prevent long term drift of transmitter-receiver counting synchronization. In another implementation, the receiver applies an interrupt to the host at an appropriate time indicating to the host that the transmitter needs to send a CTS_sync value to synchronize the counting.

If VCLK jitter is not excessively severe, in some cases it is possible to use the receiver without a crystal clock in standard mode operation where VCLK jitter is not addressed (according to the invention) for lower quality audio applications, while more For high audio quality applications, an external crystal is provided and used as described above to eliminate the effects of VCLK jitter.

The above-described techniques for preventing the transmission of VCLK jitter to regenerate MCLK can enable spread spectrum clocking on the link (where the frequency of VCLK is deliberately changed to reduce EMI). Implementation in the receiver needs to support the worst case of frequency variation.

Another way to store many CTSx values and use the CTSv value to select the correct stored value is to implement the receiver to measure only the CTSx value corresponding to the general CTSv value and calculate a correction to the CTSx when the CTSv value is available. . The latter method is expected to be useful in situations where the CTSv change is greater than +/- 1. This may be the case when using spread spectrum clocking on the link. Since there will be many clock cycles to make this calculation, the hardware implementation will not require the disadvantage of many areas. Synchronizing and adjusting the start of counting in the receiver is still required.

Another preferred embodiment implements digital filtering (low pass filtering) of the CTS values sent to the receiver. Quantization errors as well as pixel clock jitter (jitter in the clock used to sample the clock to be regenerated) while regenerating the clock (e.g., audio clock regeneration) using the transmitted CTS value (time-stamp methodology) The actual CTS value transmitted may vary from the mean value (averaged over a short period). This variation produces jitter on the regenerated clock.

In some preferred embodiments, the CTS values may be digitally filtered to reduce jitter in the regenerated clock caused by quantized error and pixel clock jitter. The digital filter functions as a low-pass filter to suppress higher frequency components of time-stamp variations, and correspondingly suppresses higher frequencies of the regenerated clock jitter.

The word length required for the filter output can be larger than the original time-stamp value. That is, the digitally filtered timestamp value has a fractional part compared to the original integer timestamp (ie 74.25 instead of 74). If longer time-stamp words are simply truncated to the end and become an integer, the filter will still function to weaken higher frequency jitter. However, it can be seen that the average of the time-stamp values truncated by the truncated number is equal to the average of the sequence of original time-stamps, the regenerated clock frequency is not accurate and the clock has a long term drift compared to the original clock. If there is also a stream of constant data being transmitted that is to be clocked by the regenerated clock, this drift in the regenerated clock causes a data-rate mismatch between the data source and the sink, A gap or dropped data can be generated on the side. In addition to the long term drift, truncation of the end of the filtered time-stamp value causes truncation errors that increase the jitter of the regenerated clock.

Therefore, it is important to maintain the fractional portion of the filtered CTS value when regenerating the clock. In some embodiments, fractional-N type PLLs are used in the receiver (as described above) to protect longer words.

One important application in these embodiments is the transmission of a digital audio clock using a time-stamping method. In particular, when the time-stamp update rate is near or within the audio band, the jitter generated by the time-stamp variation can be modulated into the final analog audio and cause degradation of the audio quality. By using digital filters to suppress, the effect of jitter on audio quality can be reduced or eliminated. To achieve the same benefits using analog technology, a very low bandwidth clock regeneration PLL (eg 100 Hz bandwidth) that is difficult to integrate and requires considerable effort to design and test (both IC and board levels). PLL). As you can see, once a properly designed digital method is simple to build and test, it is easily adaptable to a board-level design.

In a preferred embodiment, the transmitter according to the invention accepts input video in the ITU-BT.656 or YCbCr 4: 2: 2 format and converts the ITU-BT.656 format to the YCbCr 4: 2: 2 format for transmission. It is composed. Preferably, the transmitter comprises two streams (time-division-multiplexed) of ITU-BT.656 or YCbCr 4: 2: 2 video (in one channel) (each stream comprising N-bit components). It can accept and convert the input video to YCbCr 4: 2: 2 format (including 2N-bit components, each 2N-bit component representing two components of the input video) for transmission.

In another preferred embodiment, the transmitter according to the invention is configured to accept input video in DDR YCbCr 4: 4: 4 format (DDR refers to “double data rate” and video in DDR format Can be written to DDR RAM, a type of synchronous DRAM, on the rising clock edge as well as on the falling clock edge). The transmitter may put the input video in the conventional YCbCr 4: 4: 4 format (not DDR) for transmission. Alternatively, or alternatively, the transmitter is configured to accept input video in DDR YCbCr 4: 4: 4 format and place the input video in conventional YCbCr 4: 4: 4 format for transmission. Preferably, the transmitter accepts two streams (on time-division-multiplexed) of the DDR ITU-BT.656 format input video (on one channel), and transmits the input video for transmission in a conventional YCbCr 4: 2: Can be placed in 2 formats.

In another preferred embodiment, the transmitter according to the invention is adapted to accept input video in any variant of the YCbCr format, with embedded data or sync bits embedded with separate HSYNC and VSYNC (to support a large number of source devices). And reformat the input video into YCbCr 4: 4: 4 or YCbCr 4: 2: 2 format video for transmission.

In another preferred embodiment, the transmitter according to the invention is configured to accept input video in YCbCr 4: 2: 2 format, and upconversion for converting the input data to YCbCr 4: 4: 4 format for transmission. ) Circuits.

In another preferred embodiment, the transmitter according to the invention is configured to accept input video in any variant of the YCbCr format and the input video and color space conversion circuit from YCbCr to RGB (with programmable or fixed coefficients) for transmission. It includes a universal mapping circuit for converting the to RGB format.

In a preferred embodiment, the receiver according to the present invention is configured to output a video stream in the ITU-BT.656 format and convert the Y, Cr and Cb components of the video reconstructed in the YCbCr 4: 2: 2 format into the ITU-BT.656 format. And a multiplexer circuit positioned at. Advantageously, the receiver may apply separate HSYNC and VSYNC signals, along with the ITU.BT.656 output video stream (where the timing matches the timing of the sync bits embedded in the ITU-Bt.656 stream). Preferably, the receiver comprises two streams (in one channel) in response to the reconstructed YCbCr 4: 2: 2 video (including 2N-bit components, each 2N-bit component representing two components of the input video). And output the ITU-BT.656 video (each stream contains components of N-bits) (time-division-multiplexed together). More preferably, the receiver is output separately from a stream of sync bits embedded in the output Y, Cr and Cb components (e.g., ITU-BT.656) and / or output Y, Cr and Cb components. It is configured to place the reconstructed video in YCbCr 4: 2: 2 format into the desired output format, which may include HSYNC and VSYNC.

In another preferred embodiment, the receiver according to the invention is configured to output video in DDR YCbCr 4: 4: 2, DDr YCbCr 4: 2: 2 or DDR ITU-BT.656 format (DDR is a "double data rate" Video reconstructed in conventional YCbCr 4: 4: 4 or YCbCr 4: 2: 2 format (not DDR); Includes circuitry for reformatting to the BT.656 output format.

In another preferred embodiment, the receiver according to the present invention is configured to output video in any variant of the YCbCr format and the recovered video in the conventional YCbCr 4: 4: 4 or YCbCr 4: 2: 2 format, whichever of the output format is desired. It includes a universal mapping circuit that converts to a format.

In another preferred embodiment, the receiver according to the invention comprises circuitry for performing downconverting or upconverting on the reconstructed video (e.g., reconstructing a video in YCbCr 4: 4: 4 format for YCbCr 4: 2: Circuitry for switching to output video in two formats, or for converting video in YCbCr 4: 2: 2 format to output video in YCbCr 4: 4: 4 format.

In another preferred embodiment, the receiver according to the present invention is configured to output video in any bottle of the YCbCr format, and to output the RGB to YCbCr color space conversion circuit and the reconstructed video of the RGB format (with programmable or fixed coefficients). It includes a generic mapping circuit for converting to one of the output formats.

Next, embodiments of the present invention for implementing an improved method for link complete check are described.

Content protection systems, including a system according to a preferred embodiment of the present invention for encrypting video data and / or packetized auxiliary data for transmission over a serial link, generally provide some evidence of whether the system is still operating correctly. There is a need. Correct operation of the system generally includes the requirement that data transmitted over the link is encrypted by the transmitter and decrypted by the receiver, and that the correct synchronization of the encryption and decryption operations must be maintained.

One proof method is to periodically read the "result" vector on each side of the link. If the vector changes and changes to the expected sequence (usually with the same value on each side of the link), it is a strong indication that the system is working correctly. The conventional HDCP protocol uses this method known as "link integrity check."

However, link finalization is not a very simple method. This method itself cannot sample both sides of the link exactly at the same time. In addition, the sampling rate can be different from the rate at which the result vector changes (in fact, the two events can be completely asynchronous). These factors lead to anomalous situations where a link may appear to be broken even when the link is not broken. Worse, if the link is really bad, the link may appear to be good.

Preferred embodiments of the system according to the invention implement an improved method for checking link integrity.

Although the description below assumes that an HDCP content protection protocol has been used, some embodiments of the system according to the present invention utilizing the link integrity check feature of the present invention implement a content protection protocol other than HDCP. Link integrity check methods and apparatus according to the present invention may also be configured to transmit serial packets regardless of whether the system is configured to transmit packets of encrypted audio data (or other auxiliary data) over a link between data islands or active island periods. This is useful in systems that send encrypted video over a link.

In some embodiments, the transmitter of the system according to the present invention uses HDCP to encrypt packets and video of audio data, and performs link integrity check function every 128 video frames to provide 16-bit result vectors from both transmitter and receiver. capture burinda) to R _i and check if they match or compare the results every two seconds. This scheme has the following drawbacks:

There is no guarantee that the cipher engines in the transmitter and receiver are correctly synchronized. If the cipher engines are only slightly off, the R _i value appears to be mostly time matched;

The rate at which "snapshots" (samples) of R _i values are taken is not related to the rate at which they are compared. These rates will be completely asynchronous if the transmitter and receiver sometimes show different values because the sample is across the snapshot boundary; And

In contrast, the sample rate is synchronous (or nearly synchronous). This prevents receive straddling errors. However, if the integrity check spans at the snapshot boundary, the situation is abnormal and may never be resolved.

To illustrate this problem, reference is first made to FIG. 17. As shown in FIG. 17, the R _i snapshots of the transmitter and receiver synchronize exactly as they should be. Link integrity checks occur similarly even with slightly different rates. Both the transmitter integrity check and the receiver integrity check mostly occur within the same "window" between the R _i snapshots. This means that both R _i values are matched and the link integrity check will succeed. However, in one case, some of the transmitter and receiver integrity checks span the R _i snapshot. This means that the visible R _i values are different. In general, a system implementing DHCP performs a check for integrity again in a short time when such an event occurs.

Next, referring to FIGS. 18 and 19, a case in which link integrity check occurs at the same rate as the R _i snapshot will be described. A typical conventional HDCP system performs a link integrity check in this manner. In general, as shown in FIG. 18, since the link integrity check always occurs at the same relative point in time, the R _i values are always matched. As such, as shown in FIG. 19, there is an unusual (and therefore very bad) case where a link integrity check spans an R _i snapshot, where the R _i values never match.

In all of the above cases, retrying link integrity checks at the earliest opportunity (when a single check of R _i values does not match) provides a reliable mechanism for establishing actual link integrity, but this method is complex. This adds to the unexpected additional burden.

Next, referring to FIGS. 20 and 21, a case where the transmitter and receiver cipher engines are not properly aligned will be described. This can happen, for example, when there is a VSYNC failure. In this case, no available video is sent over the link. However, as shown in FIG. 20, this can occur in many cases, the link integrity check occurs in the same window between snapshots, and the R _i value will appear to be correct. Thus, even if the actual system is not normal, it will appear to be operating normally.

Finally, the completeness check can span the R _i snapshot (like the fourth completeness check from the left in FIG. 20), but there is no guarantee that this will happen in time or no such correction at all. The length of time elapsed between these lucky events is inversely proportional to the bit frequency formed by the R _i snapshot interval and the link integrity interval, which may be zero.

The worst case scenario is shown in FIG. 21. Here, the link integrity frequency is synchronous (or nearly synchronous) to the R _i snapshot, but there is an out-of-phase that is too large to avoid seeing sequence errors in the cipher state machine. The system does not operate normally, but the link integrity check does not realize it until there is interference from some external element (eg a disappointed user).

In order to avoid the above mentioned problems and to ensure that abnormal operation of the system is quickly and accurately detected, one or more of the following improvements are made in accordance with the invention:                 

The transmitter and receiver are implemented to reduce or eliminate errors that cause the transmitter and receiver cipher engines to have out-of-phase;

The link integrity check is done in a manner that ensures that R _i snapshots occur at the same time at both the transmitter and receiver regardless of phase;

The link integrity check is done in a known relationship with the R _i snapshot. This does not mean that they must be synchronized, but they cannot be completely asynchronous. In particular, it must be possible to ensure that the link integrity check does not span the R _i snapshot; And

A method is implemented for directly checking received, decoded data for a state indicative of normal system behavior (eg, a "snow" state). For example, periodically (or sometimes), a known data pattern is input to the transmitter, encrypted, transmitted, received, decrypted, and checked to see if the received and decrypted pattern matches the known data pattern. Should be.

The transmitter and receiver cipher engines can be out of phase if any control signal fails. For example, if the receiver does not see the VSYNC signal, it falls behind. When the receiver receives the extra VSYNC signal, it goes ahead. If this happens and the receiver is unable to decode normally, the screen shows "snow."

If the point at which the receiver takes a "snapshot" of the R _i value moves in the same way (either behind or ahead), the receiver will continue to produce the correct R _i value. This is because the R _i sequence is a function of only constant and frame sequences. This does not depend on intermediate data. This leads to a situation very similar to FIG. 20 or 21, where the link integrity check is correct most of the time. Indeed, if the receiver goes forward or backward one frame, this R _i value will exactly match that in the transmitter on 127 of 128 frames. This is a very large window and can be taken for a while before an error is found.

One way to reduce the likelihood of this scenario is to separate from the state machine controlling the state machine driving the cipher when the R _i snapshot occurs by using different signals to control each advance. In this way, signal failure can cause one machine to go out of sync, but has little effect on the other. For example, VSYNC can be used to control the advance of the cipher engine, and CTL3 can be used to control the advance of the snapshot counter. If the snapshot occurs at another relative point in the cypher engine cycle, the R _i sequence will be very different and this will immediately become apparent.

Another alternative is to give the transmitter or receiver the " interrupt " ability to signal when a link integrity check occurs. This functionality is usually in the elements of the system that initializes these locks (for example, in the transmitter_ of a system that implements HDCP.) This method works well when the interrupt latency time is always less than one video frame. There is no straddling in the receiver, and the receiver can guarantee that one or more frames detect a leading error, since a failure can cause additional VSYNC edges rather than completely eliminate VSYNC. This is expected to be a more general case: this method does not work well if the interrupt latency time spans several times the frame (unless this is otherwise unexpected), or if the receiver cipher engine lags behind one or more frames.

A better approach is to design the transmitter and / or receiver to take a snapshot only when some form of external stimulus is applied. In this way, it is possible to ensure that the transmitter and receiver always take a snapshot at the same time (thus also highlight any contradictions in the state of the cipher engine). For example, the transmitter provides a command for the transmitter to send a request for a snapshot to both the transmitter's cipher engine and the receiver's cipher engine. And both the transmitter and receiver wait for the appropriate sync event (such as the next leading edge of VSYNC) and then both for the snapshot. The transmitter and / or receiver then signal that it has completed the original command. Since no new snapshot can occur until the next time the command is issued, at this point the system (eg, software or firmware implemented by the system) can have time to perform a link integrity check.

This method has many advantages. First, snapshots always happen on both sides of the link at the same time. Secondly, the link integrity check can be surely completed (by interlocks assembled in the protocol) before the next snapshot. Third, link integrity checks can be done often or very occasionally to meet the needs of the system. This rate may change from one time period to the next as needed. In this last point, it may be useful or desirable to include a "deadman timer" in the receiver to prove that the link integrity check is performed at least in an acceptable cycle. On the other hand, although the receiver may be configured to include a deadman timer, it is generally desirable for the transmitter to include it. This is because the transmitter is generally responsible for ensuring that the protected content will not leave the system without proper encryption, and therefore the transmitter is a logical supporter that corrects that the proper checks and balances are in place.

According to another feature of the invention, a receiver in one embodiment of the system of the invention uses only data transmitted from the transmitter to the receiver. It is directly determined whether the synchronization between the cipher engines in the transmitter and the receiver is lost. In a preferred embodiment embodying this aspect of the invention, the transmitter transmits the encrypted video data to the receiver over the video channel of the TMDS link (during the active video period) and includes encrypted audio (or other auxiliary data). The packet is transmitted over the video channel in the interval between active video periods. Each packet includes a header and two or more sub-packets, the header of each packet includes BCH parity bits for header data and header data (usually unencrypted), and each sub-packet contains data and sub-packets. BCH parity bits for the data of the. The receiver is configured to check the type of error that occurs in the received and decoded data and to determine from this information whether most of the error is a transmission error or an HDCP decoding error. In particular, when encrypted data is encoded using the TERC4 encoding technique described above, the receiver detects non-golden code reception with little (or no) of its TERC4 encoding operation and the BCH error correction circuit decrypts the subpacket data. Upon detecting and correcting a coherent error in the receiver, the receiver concludes that HDCP decoding failed. Similarly, if the receiver determines that there is a significant difference between the BCH error correction rate of the subpacket data (transmitted with encrypted data and decoded at the receiver) and the packet header data (transmitted with non-encrypted data), The receiver concludes that HDCP decoding has failed. The receiver can be implemented to use simple processing that makes this conclusion reliable. Filtering the detected error rate information (generated at the receiver) through multiple packets (e.g., through a video field or frame, or through a predetermined number of pixels or a predetermined time) may provide a complete or near perfect detection. Can be.

In a typical implementation, a transmitter frequently sends packets (in a data island) to carry audio and other auxiliary data. Each such packet preferably contains 24-bit packet header data and four 56-bit subpacket data blocks. The receiver performs BCH (32, 24) error detection and correction on the packet header data, and performs BCH (64, 56) error detection and correction on each subpacket. HDCP encryption is performed for each 4-bit amount to be encoded into a TMDS code word for transmission on channel 1 or channel 2, but no HDCP encryption is performed on the data encoded for transmission on channel 0. The transmitter performs TERC4 encoding on data to be transmitted on channel 0 (packet header data) and transmission data (subpacket data) on channels 1 and 2. The receiver performs the reverse of the above procedure: TERC4 decoding of data received on channels 0, 1 and 2; HDCP decoding of decoded data received on channels 1 and 2; BCH error correction and detection of data decoded from channel 0 and data decoded and decoded from channels 1 and 2; And de-packetization.

Circuitry for implementing some of these operations in the receiver generally has the ability to detect (and sometimes correct) some type of error (or can be easily modified to have this capability). This allows the receiver to detect an appropriate point-of-failure for errors that occur. Transmission errors are generally detected by the TERC4 decoding circuitry by determining whether the received value directly matches one of the possible values of the transmitted value (ie, one of the golden code words). HDCP loss-of-synchronization errors that cause decoding errors can be easily detected by the general implementation of the BCH error detection and correction circuit. If the BCH error detection and correction circuit exhibits low level errors when the TERC4 decoding circuit exhibits low levels of error, this strongly suggests that all or most of the errors have occurred in the HDCP decoding process.

When the packet header data is not encrypted but the subpacket data is encrypted by the transmitter, the receiver can determine whether decryption failed by comparing the error rates for these two types of data. The BCH error rate for subpacket data is much higher than the BCH error rate for packet header data, which also suggests that decoding is a major cause.

Integrating two or more error rate detection and comparison mechanisms into one receiver means that the receiver detects a failure to decrypt, does not reach a "false positive" marriage that the decryption circuit is functioning normally, and the receiver fails to function. Can provide a strong degree of confidence in concluding that

In other embodiments, a known data pattern is provided to the transmitter, or existing data is modified in some way, and the result is encrypted and transmitted. Then, the receiver checks whether the result is expected when decoding the data. If the receiver finds the expected result, it can be considered that the decoding is working correctly. Otherwise, the encryption / decryption function does not work correctly. This method has a very direct advantage: it does not rely on indirect evidence from result vectors such as R _i . This method is also inversely comparable with existing protocols, with only a small amount of external or internal logic added to a conventional HDCP system, and no other changes to link operation. For example, assume that the first two pixels of every frame are defined as "A" and "B", respectively. These pixels are displayed in very small portions in the upper left portion of the screen. These may be background colors and may be the same color periodically or very often. The transmitter may be configured to modify the most insignificant bits of pixels A and B so that they are always the same before encrypting and transmitting the altered video. For example, the transmitter has three colors of pixels A and B such that A red [0] = B red [0], A green [0] = B green [0], A blue [0] = B blue [0]. You can modify bit [0] in each component. The exact algorithm can be changed to various implementations and adapted to have the fewest possible impacts on the screen. All that is needed is that the final result is transform data with a predetermined (known) form.

When the modified frame is encrypted and decrypted, the receiver may check a predetermined pattern in the decrypted data. The receiver should check in a way that counts a small number of bit errors in the link. You can check by setting a threshold on the recognized result. For example, only two of the three requirements described above may be satisfied. Or it can average the results over several frames. In other cases, the receiver should be configured to find a normal value only when the encryption / encryption function is operating normally. The receiver can signal this result back to the host in several ways. One way to do this is to directly set the bits in the register. Another way to signal this result is indirectly (for example, by deliberately changing the value of R _i ). The latter method has the advantage of working well in a repeater environment, where the interruption of any link (the link between any transmitter-receiver pair) can be easily made to deliver upstream towards the host.

The method described in the previous two paragraphs is backward compatible in the following way: A "new" transmitter can implement this without any adverse effect on a "old" receiver; A "new" receiver can implement this, but cannot enable the check when used with a "old" transmitter; “Older” transmitters and receivers can easily add this functionality to external logic by simply tapping the data path in an appropriate manner.

If backward compatibility is not important, known data patterns can be implemented in other ways that do not affect the video picture in any way. For example, certain "test" packets may be inserted into the data stream, or "test" data may be inserted in other packets or locations. The video line may also be stretched to accommodate the "test" data and then shrink back to its original size at the receiver.

While certain forms of the invention have been shown and described herein, it is to be understood that the invention is defined by the claims and not limited to the specific embodiments described and illustrated herein.

Claims (70)

A transmitter configured to be connected with a serial link having one or more video channels, the transmitter comprising: Inputs for receiving video data and audio data comprising I ² S format audio data; One or more outputs configured to be connected with the link; And Circuitry coupled between the inputs and each output, the circuitry generates encoded video data by encoding the video data, generates code words representing packets of auxiliary data, and encodes the encoded code during an active video period. The circuitry for applying video data to the one or more outputs and applying the code words representing packets of auxiliary data to the one or more outputs during a data island, Wherein each data island is a time period that does not occur or overlap with any of the active video periods, and wherein the auxiliary data includes audio data. The method of claim 1, At least some of said packets are audio sample packets having a header and at least two sub-packets, said sub-packets comprising samples of said audio data. The method of claim 2, Wherein each sub-packet of the one or more audio sample packets contains two N-bit words, each N-bit word comprising M bits of audio sample data determined by I ² S format audio data Transmitter. The method of claim 3, wherein N = 28, M = 24, characterized in that the transmitter. The method of claim 3, wherein Wherein each N-bit word has a format corresponding to a sub-frame format of an IEC_60958 frame. The method of claim 3, wherein The circuitry is configured to use a programmed register indicating the format of the I ² S format audio data to generate code words representing the audio sample packets. The method of claim 2, The inputs are configured to receive the I ² S format audio data on 2 + M conductors, the conductors being one bit clock conductor, one word clock conductor and M data conductors, 1 ≦ M ≦ 4, wherein the audio sample packets comprise audio sample data determined by the I ² S format audio received on the respective data conductors. The method of claim 7, wherein The circuitry applies the encoded video data to the one or more outputs in response to a pixel clock, applies the code words representing packets to the one or more outputs in response to the pixel clock, and times within the several or more packets. And time code data together with the pixel clock to represent an audio clock for I ² S format audio data. The method of claim 8, And the audio clock is a bit clock received at the bit clock conductor. The method of claim 2, The inputs are configured to receive the I ² S format audio data on 3M conductors, the conductors having M bit clock conductors, M word clock conductors and M data conductors, 1 ≦ M ≤ 4, wherein the audio sample packets include audio sample data determined by the I ² S format audio received on the respective data conductors, The circuitry applies the encoded video data to the one or more outputs in response to a pixel clock, applies the code words representing packets to the one or more outputs in response to the pixel clock, and times within the several or more packets. And time code data together with the pixel clock to represent an audio clock for each of the I ² S format audio streams received at the data conductor. The method of claim 1, The circuitry is configured to apply control data to the one or more outputs during a control data period, wherein the control data period does not occur simultaneously with or overlap with any of the data islands, or simultaneously with any active video period or Transmitter characterized in that it does not overlap. A transmitter configured to be connected with a serial link having one or more video channels, the transmitter comprising: Inputs for receiving a plurality of audio data streams, the video data including audio data streams having a first format and audio data streams having a second format; One or more outputs configured to be connected with the link; And Circuitry coupled between the inputs and each output, the circuitry generating encoded video data by encoding the video data, generating code words representing auxiliary data packets, and encoding the encoded video during an active video period. Apply data to the one or more outputs and apply code words representing the auxiliary data packets to the one or more outputs during a data island, each data island occurring or overlapping simultaneously with any of the active video periods. A non-time period, wherein the auxiliary data includes the circuit unit, including the audio data, The circuit portion includes a multiplexer circuit and a data packetization circuit coupled to the multiplexer circuit, the multiplexer circuit receiving the audio data streams and applying a predetermined one of the streams to the data packetization circuit at a predetermined timing. Transmitter connected and configured. The method of claim 12, Some of the packets are audio sample packets, and the packetization circuitry is configured to format the audio data for inclusion in the audio packets, each of the audio sample packets comprising N-bit audio sample words; Wherein each audio sample word includes audio sample bits determined by the audio data, each audio sample word having a format corresponding to a sub-frame format of an IEC_60958 frame. The method of claim 12, The inputs are in I ² S format audio data comprising two clock streams and an I ² S data stream, and the DSD format audio comprising a DSD bit clock stream, a first DSD data stream, and a second DSD data stream. Configured to receive data, wherein the multiplexer circuit is configured to apply data of the I ² S data stream to the data packetization circuit at a predetermined timing when the inputs receive audio data in an I ² S format, and And a multiplexer circuit is configured to apply the data of the first DSD data stream and the second DSD data stream to the data packetization circuit at a predetermined timing when the input units receive audio data in a DSD format. . A transmitter configured to be connected with a serial link having one or more video channels, the transmitter comprising: Inputs for receiving one or more audio data streams and video data having an embedded clock; One or more outputs configured to be connected with the link; And Circuitry coupled between the inputs and the respective outputs, the circuitry generating encoded video data by encoding the video data and a second clock having an unknown phase relationship with the embedded clock Generate resampled audio data by generating a sample, generate code words representing auxiliary data packets, apply the encoded video data to the one or more outputs in response to a pixel clock during an active video period, and And apply code words representing the auxiliary data packet to the one or more outputs in response to a pixel clock, each data island having a time interval that does not occur or overlap with any of the active video periods. The auxiliary data is time code data and an audio data, the re-sampling, the time code data transmitter comprising the said circuit representing the second clock with the pixel clock. The method of claim 15, The audio data stream has an input audio sample rate, the second clock has a frequency of Z * 128 * Fs, where Z is an integer not less than 2, and Fs is the input audio sample rate transmitter. A transmitter configured to be connected with a serial link having one or more video channels, the transmitter comprising: Inputs for receiving one or more audio data streams and video data having an embedded clock; One or more outputs configured to be connected with the link; And Circuitry coupled between the inputs and each output, the circuitry generating encoded video data by encoding the video data and converting the audio data stream into a pixel clock having an unknown phase relationship with the embedded clock. Sampling to generate resampled audio data, generating code words representing auxiliary data packets, applying the encoded video data to the one or more outputs in response to a pixel clock during an active video period, and during the data island And apply code words representing the auxiliary data packet to the one or more outputs in response to a clock, wherein each data island has a time period that does not occur or overlap with any of the active video periods. And wherein the auxiliary data comprises the circuitry section including the resampled audio data. A transmitter configured to be connected with a serial link having one or more video channels, the transmitter comprising: Inputs for receiving video data and audio data; One or more outputs configured to be connected with the link; And Circuitry coupled between the inputs and each output, the circuitry generating encoded video data by encoding the video data, generating code words representing auxiliary data packets, and generating the encoded video during an active video period. Apply data to the one or more outputs and apply code words representing the auxiliary data packet to the one or more outputs during a data island, each data island occurring or overlapping simultaneously with any of the active video periods. A non-time period, wherein the auxiliary data includes the circuit portion, including audio data, Some of the packets are audio sample packets, wherein each audio packet has a header and may include samples for one or more of the audio data, wherein the header includes an audio data sample. And header data in one or more predetermined time slots indicating whether each audio data sample is a flatline sample. The method of claim 18, Wherein each audio sample packet has two or more sub-packets, each of the sub-packets may comprise one or more samples of audio data, and the header data indicates whether each of the sub-packets contains an audio data sample. And data in a first predetermined time slot indicating, wherein the header data also includes data in a second predetermined time slot in which each audio data sample represents a flatline sample. A transmitter configured to be connected with a serial link having one or more video channels, the transmitter comprising: Inputs for receiving audio data including video data and audio data in a DSD format; One or more outputs configured to be connected with the link; And Circuitry between the inputs and the respective outputs, the circuitry generating encoded video data by encoding the video data, generating code words representing auxiliary data packets, and generating the encoded video data during an active video period. Is applied to the one or more outputs, and code words representing the auxiliary data packet to the one or more outputs during the data island, wherein each data island does not occur or overlap with any of the active video periods simultaneously. And the auxiliary data includes the circuit unit, wherein the auxiliary data includes the audio data. The method of claim 20, At least some of said packets are audio sample packets having a header and at least two sub-packets, said sub-packets comprising samples of audio data. The method of claim 21, Wherein each sub-packet of one or more of the audio sample packets includes two N-bit words, each N-bit word comprising M bit audio sample data determined by audio data in the DSD format Transmitter. The method of claim 22, Wherein each N-bit word has a format corresponding to a sub-frame format of an IEC_60958 frame. The method of claim 22, The circuitry is configured such that the DSD format uses programmed register bits representing an audio data format to generate code words representing the audio sample packets. The method of claim 21, The inputs are configured to receive audio data in the DSD format on 1 + 2M conductors, the conductors comprising one bit clock conductor, 2M data conductors, 1 ≦ M ≦ 4, Sample packets including audio sample data determined by the DSD format audio received on the respective data conductors. The method of claim 25, The circuitry applies the encoded video data to the one or more outputs in response to a pixel clock, applies the code words representing packets to the one or more outputs in response to the pixel clock, and at least several of the packets. And is configured to include time code data, wherein the time code data together with the pixel clock represent an audio clock for audio data of the DSD format. The method of claim 21, The input is configured to receive audio data in the DSD format on 3M conductors, the conductors comprising M bit clock conductors and 2M data conductors, 1 ≦ M ≦ 4, and the audio sample packet Includes audio sample data determined by the DSD format audio received on the data conductors, and The circuitry applies the encoded video data to the one or more outputs in response to a pixel clock, applies the code words representing packets to the one or more outputs in response to the pixel clock, and at least several of the packets. And time code data in the data stream, wherein the time code data together with the pixel clock is indicative of an audio clock for each stream of the DSD format audio received on the data conductors. Following a receiver configured to be connected with a serial link having one video clock channel and one or more video channels, the receiver is: Two or more inputs configured to be connected with the link and comprising a clock input configured to be connected with the video clock channel; Outputs for applying video data and audio data reconstructed from the link; And Coupled between the inputs and the respective outputs, receiving a pixel clock from the clock input, decoding the encoded video data received at the one or more inputs during an active video period in response to the pixel clock, and the like. Generating reconstructed video data, applying the reconstructed video data to the one or more outputs, and decoding code words of encoded auxiliary data packets received at the one or more inputs during a data island in response to the pixel clock. Circuitry configured to generate decoded data, generate a stream of one or more I ² S format audio data from the decoded data, and apply the stream of each I ² S format audio data to the one or more outputs; Data island Group which active video period and also occur at the same time or a time interval that does not overlap also, includes the circuitry, And at least some of said decoded data is time code data representing a time stamp, said time code data together with said pixel clock representing an audio clock for said I ² S format audio data stream. The method of claim 28, The circuitry generates N I ² S format audio data streams from the decoded data, where N is greater than 1 and is configured to apply each I ² S format audio data stream to a different subset of the outputs. Receiver characterized in that. The method of claim 29, Each of said I ² S format audio data streams sharing said audio clock. The method of claim 29, The time code data is indicative of a different audio clock for each of the I ² S format audio data streams with the pixel clock. The method of claim 29, N = 4 receivers. A receiver configured to be connected with a serial link having one or more video channels, the receiver comprising: At least one input configured to be connected with the link; Outputs for applying video data and audio data reconstructed from the link; And A reconstructed video data connected between the inputs and the respective outputs, by performing decoding or the like on encoded video data received at the one or more inputs during an active video period, and generating the reconstructed video data. Circuitry configured to apply to at least one output, to generate decoded data by decoding code words of encoded auxiliary data packets received at the at least one input during a data island, and to generate at least one audio data stream from the decoded data. Each of the data islands includes the circuitry, which is a time interval that does not occur simultaneously or overlap with any of the active video periods. And the circuitry comprises multiplexer circuitry coupled and configured to apply the respective streams of recovered audio data to one or more of the outputs at predetermined timing. The method of claim 33, wherein Some or more of the packets are audio sample packets, each audio sample packet including audio sample words, each audio sample word including N audio sample bits, and the audio sample bit being the recovered audio. Determine data, wherein each audio sample word has a format corresponding to a sub-frame format of an IEC_60958 frame. The method of claim 33, wherein The output unit applies either I ² S format audio data including two clock streams and one I ² S data stream, or DSD format audio data including one DSD bit clock stream and two DSD data streams. And the circuitry is operable in a mode of generating three recovered audio data streams from the decoded data, the multiplexer circuitry converting the three recovered audio data streams into the three outputs in an I ² S format. And apply as either audio data or DSD format audio data. A receiver configured to be connected with a serial link having one or more video channels, the receiver comprising: At least one input configured to be connected with the link; Outputs for applying video data and audio data reconstructed from the link; And A reconstructed video data coupled between the outputs and the respective inputs to generate reconstructed video data by performing decoding or the like on encoded video data received at the at least one input during an active video period, and converting the reconstructed video data to the at least one. Generates decoded data by applying to an output, performing codewords of encoded auxiliary data packets received at the one or more inputs during a data island, and the like, and generating one or more recovered audio data streams from the decoded data. And wherein each data island is a time interval that does not occur or overlap with any of the active video periods, wherein at least some of the packets are audio sample packets, and each audio sample packet is encoded. And one or more samples of the audio data, wherein the header is one or more indicating whether the audio sample packet includes audio data samples and whether each audio data sample is a flatline sample. Including said circuitry, including header data in a predetermined time slot, The circuitry is configured to include flatline data in the one or more recovered audio data streams in response to receiving header data indicating that one of the packets is an audio sample packet comprising a flatline sample. . A receiver configured to be connected with a serial link having one video clock channel and one or more video channels, the receiver comprising: One or more inputs configured to be connected with the link and comprising a clock input configured to be connected with the video clock channel; Outputs for applying video data and audio data reconstructed from the link; And Connected between the outputs and each of the inputs, and receiving a pixel clock from the clock input and performing decoding or the like on the encoded video data received at the one or more inputs during an active video period in response to the pixel clock. Generate the decoded video data, apply the reconstructed video data to the one or more outputs, decode codewords of the encoded auxiliary data packet received at the one or more inputs during the data island in response to the pixel clock, and the like. Circuitry configured to generate decoded data, to generate one or more DSD format audio data streams from the decoded data, and to apply each of the DSD format audio data to the one or more outputs, wherein each of the data islands comprises: Wherein said circuitry is a time period that does not occur simultaneously with, or overlap with, the active video period, And at least some of the decoded data is time code data representing a time stamp, wherein the time code data together with the pixel clock represents an audio clock for the DSD format audio data stream. The method of claim 37, The circuitry generates N DSD format audio data streams from the decoded data, where N is greater than 1 and is configured to apply each DSD format audio data stream to a different subset of the outputs. receiving set. The method of claim 38, Wherein each DSD format audio data stream shares the audio clock. The method of claim 38, The time code data is indicative of a different audio clock for each DSD format audio data stream with the pixel clock. The method of claim 38, N = 4 receivers. A transmitter configured to be connected with a serial link having one or more video channels, the transmitter comprising: Inputs for receiving input video data and audio data; One or more outputs configured to be connected with the link; And Circuitry coupled between the inputs and each output, the circuitry generating encoded video data by encoding the video data, generating code words representing an auxiliary data packet, and generating the encoded video data active. Apply to the one or more outputs during a video period, and apply code words representing the auxiliary data packet to the one or more outputs during a data island, each data island being simultaneously generated or overlapping with any of the active video periods. A time period, wherein the auxiliary data includes the circuit portion, including the audio data, The circuitry is configured to generate the encoded video data indicative of video having a second format in response to input video having a first format. The method of claim 42, Said circuitry being configured to generate said encoded video data representing video having a YCbCr 4: 2: 2 format in response to an input video having either an ITU-BT, 656 format or a YCbCr 4: 2: 2 format. Characterized by a transmitter. The method of claim 42, The circuitry is configured to respond to an input video comprising two time-division-multiplexed input video streams having an ITU-BT.656 format or a YCbCr 4: 2: 2 format of an N-bit component. And generate the encoded video data representing video having a YCbCr 4: 2: 2 format. The method of claim 42, The circuit portion has a conventional YCbCr 4: 4: 4 format or a conventional YCbCr 4: 2: 2 format in response to an input video having a DDR YCbCr 4: 4: 4 format or a DDR YCbCr 4: 2: 2 format. And generate the encoded video data representative of the video. The method of claim 42, The circuitry is configured to generate the encoded video data representing the video having a conventional YCbCr 4: 2: 2 format in response to two time-division-multiplexed input video streams having an ITU-BT.656 format. Transmitter, characterized in that. The method of claim 42, The circuitry is responsive to input data having any one of two or more YCbCr formats, including one or more formats in which sync bits are embedded in input video samples and one or more formats in which sync bits are not embedded in input video samples. And generate the encoded video data representative of the video having a YCbCr 4: 4: 4 format. The method of claim 42, The circuitry is responsive to input data having any one of two or more YCbCr formats, including one or more formats in which sync bits are embedded in input video samples and one or more formats in which sync bits are not embedded in input video samples. And generate the encoded video data representative of the video having a YCbCr 4: 2: 2 format. The method of claim 42, The circuitry includes upconversion circuitry coupled to receive input video in YCbCr 4: 2: 2 format, and the circuitry is YCbCr 4: 4: 4 in response to the input video in YCbCr 4: 2: 2 format. And generate the encoded video data representative of the video having a format. The method of claim 42, The circuitry includes a color space conversion circuit from YCbCr to RGB, the circuitry being configured to generate the encoded video data representing video having an RGB format in response to an input video of YCbCr format. A receiver configured to be connected with a serial link having one or more video channels, the receiver comprising: At least one input configured to be connected with the link; Outputs for applying video data and audio data reconstructed from the link; And A reconstructed video data coupled between the outputs and the respective inputs to generate reconstructed video data by performing decoding or the like on encoded video data received at the at least one input during an active video period, and converting the reconstructed video data to the at least one. One or more streams of audio data reconstructed from the decoded data, applying to an output, and generating data decoded by performing one or more code words of an encoded auxiliary data packet received at the input during the data island, and the like. A circuit portion configured to generate a data element, wherein each data island comprises a circuit portion that is a time period that does not occur simultaneously or overlap with any of the active video periods, The circuitry is configured to generate the reconstructed video data having the first format in response to the encoded video data representing the video having the second format. The method of claim 51, wherein The circuitry is configured to generate the reconstructed video data having an ITU-BT.656 format in response to the encoded video data representing the video having a YCbCr 4: 2: 2 format. The method of claim 51, wherein The circuitry comprises two pieces of the reconstructed video data each having an ITU-BT.656 format of N-bit components, in response to encoded video data representing video having a YCbCr 4: 2: 2 format of 2N-bit components. And configured to generate streams. The method of claim 51, wherein The circuitry is configured to respond to encoded video data representing video having a YCbCr 4: 2: 2 format in which one or more formats have sync bits embedded in the input video samples, and wherein the sync bits are not embedded in the input video samples. And generate the reconstructed video data having any one of two or more YCbCr formats, including one or more formats. The method of claim 51, wherein The circuitry is in response to encoded video data representing a video having a conventional YCbCr 4: 4: 4 format or a conventional YCbCr 4: 2: 2 format, the DDR YCbCr 4: 4: 4 format, DDR YCbCr 4: 2 And generate the reconstructed video data having a: 2 format, or a DDR ITU-BT.656 format. The method of claim 51, wherein The circuitry is configured to generate the reconstructed video data having a first YCbCr format in response to the encoded video data representing the video having a second YCbCr format. The method of claim 51, wherein The circuitry is configured to generate the reconstructed video data having the first YCbCr format, such as in response to encoded video data representing the video having a second YCbCr format, by performing one or more of downconverting and upconverting. A receiver, which is configured. The method of claim 51, wherein The circuitry is configured to generate the reconstructed video data having a YCbCr format in response to encoded video data representing video having an RGB format. A circuit for generating an error correction code for data blocks, the circuit comprising: Inputs comprising a first input coupled to receive a first data stream and a second input coupled to receive a second data stream; Output units including a first output unit and a second output unit; And An error correction code generation logic coupled between the first input unit, the second input unit, the first output unit, and the second output unit, wherein the error correction code generation logic unit comprises: a first subset of the data block; In response to the first data stream comprising one or more data bits of the data block, and the second data stream comprising one or more other data bits of the subsequent data block and the second subset of the data blocks; The error correction code, configured to apply a first subset of the error correction code for the data block to the first output, and to apply a second subset of the error correction code for the block to the second output. And a generation logic section. The method of claim 59, The error correction code generation logic unit includes a shift register, the block consists of Z bits, the subsequent block consists of Z bits, and the error correction code for the block is Y error correction code. And the error correction code generation logic is configured to be operable in a mode of shifting out the Y error correction code bits for the block from the shift register for a clock cycle not greater than Y / 2. Circuit. The method of claim 59, And the error correction code consists of BCH parity bits. The method of claim 59, And the error correction code consists of syndrome bits. 13. A transmitter configured to be connected with a serial link comprising one or more video channels, the transmitter comprising: At least one input coupled to receive video data and at least one input coupled to receive auxiliary data; One or more outputs configured to be connected with the link; And Coupled between each input and each output, generating encoded video data and encoded auxiliary data by encoding the video data and auxiliary data, and transferring the encoded video data to the one or more outputs during an active video period. Circuitry configured to apply, and to the one or more outputs, packets that contain the encoded auxiliary data during a data island, wherein each data island is a time period that does not occur or overlap with any of the active video periods. Including the circuit portion, Each of the at least some of the packets represents one or more data blocks and BCH parity bits for the block, wherein the circuitry generates a parity bit having a first input, a second input, a first output, and a second output. And a parity bit generation logic unit for each block in response to two or more data streams including a first data stream received at the first input unit and a second data stream received at the second input unit. Generate a BCH parity bit, the first data stream consisting of the first subset of the data block and one or more data bits of a subsequent data block, and the second subset of the data block and one or more other data of the subsequent data block In response to the second data stream of bits, the BCH packet for the block And is configured to apply a first subset of the utility bits to the first output and to apply a second subset of the BCH parity bits for the block to the second output. The method of claim 63, wherein The parity bit generation logic unit comprises a shift register, wherein the parity bit generation logic unit is configured to operate in a mode in which two or more BCH parity bits are shifted out of the shift register during each clock cycle. The method of claim 64, wherein Each of the block and the subsequent block consists of Z bits, the BCH parity bit for the block consists of Y parity bits, and the parity bit generation logic is configured to perform the clock cycle no more than Y / 2. And operate in the mode of shifting out Y parity bits for the block from the shift register. 66. The method of claim 65, The data of the first stream is composed of the first subset of the data block and the first data bits of the subsequent block, and the data of the second stream is composed of the second subset of the data block and the subsequent data block. A second data bit, wherein the parity bit generation logic is configured to operate in the mode of shifting out Y parity bits for the block from the shift register for Y / 2 clock cycles. The method of claim 63, wherein The circuitry applies the packets such that each packet has a header and two or more sub-packets, the header for each packet includes header data and header parity bits, and each sub-packet contains sub-packet data. And sub-packet parity bits for the sub-packet data, wherein the BCH parity bit generated by the parity bit generation logic for each block of the sub-packet data is the sub-packet parity bit. And a transmitter. A receiver configured to be connected to a serial link comprising one or more video channels, the receiver comprising: At least one input configured to be connected with the link; At least one video output for applying video data reconstructed from the link and at least one audio output for applying audio data reconstructed from the link; And A reconstructed video data connected between each input unit and each output unit and generating reconstructed video data by performing decoding or the like on encoded video data received at the at least one input unit during an active video period, and converting the reconstructed video data to the one One or more audio data streams from the data extracted from the restored packets by applying to one or more video outputs, decoding code words representing the packets received at the one or more inputs during a data island, or the like, and extracting data from the recovered packets. A circuit portion configured to generate a signal and to apply each of the audio data streams to the one or more audio outputs, wherein each data island is a time interval that does not occur or overlap with any of the active video periods. And also, Data extracted from several or more of the recovered packets represents a sequence of data blocks, and wherein the circuitry is configured to generate syndrome bits for each block in response to two or more streams of the data blocks, and the syndrome The generation logic unit includes an input unit including a first input unit connected to receive a first data stream and a second input unit connected to receive a second data stream, a first output unit, and a second output unit, wherein the syndrome generation logic unit includes: A first stream of data consisting of the first subset of data of each block and one or more data bits of the next block of the block, and the second subset of data of each block and one or more data bits of the next block of the block The syndrome bit for each block, in response to the data of the two streams. Of the first subsets and applying said first output portion, a receiver for a second subset of the syndrome bits for each block characterized in that the connection part is configured to apply the second output. The method of claim 68, wherein The syndrome generation logic section includes a shift register, each block consisting of Z bits, Y syndrome bits are present for each block, and the syndrome generation logic section is for a clock cycle not greater than Y / 2. And operate in a mode of shifting the Y syndrome bits for each block from the shift register. The method of claim 68, wherein The data of the first stream consists of the first subset of data for each block and the first data bits of the next block of the block, and the data of the second stream is the second subset for each block. And a second data bit of a next block of the block, wherein the syndrome generating logic is configured to operate in a mode that shifts the Y syndrome bits for each block from the shift register during a Y / 2 clock cycle. Receiver characterized in that the.

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