JP5708026B2 - Optical semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to an optical semiconductor element and a method for manufacturing the same.

In recent years, technologies have been developed to realize optical semiconductor devices that can be used in optical communications such as optical networks and optical interconnections, by applying semiconductor processes that can be configured with electronic circuits and that have advanced inexpensive and large-scale integration technologies to optical circuits. Yes. For example, various optical semiconductor devices such as optical switches are proposed, in which a rib-type waveguide structure having a silicon (Si) waveguide core layer and a slab layer is formed on an insulating layer such as silicon oxide (SiO ₂ ). Has been.

JP 2009-252921 A JP 2009-258527 A JP-T 9-503869

  In an optical semiconductor element formed using a semiconductor process, the width of the waveguide core layer affects the equivalent refractive index. When the equivalent refractive index of the waveguide core layer changes, the phase of light propagating through the waveguide core layer changes. For this reason, while light propagates through the waveguide core layer, a phase change due to variations in the width of the waveguide core layer is applied, and light having a predetermined phase may not be output. For example, in the case of an interferometer type optical switch including a pair of waveguide core layers, the initial interference state may become indefinite due to a phase change caused by variations in the widths of both or one of the waveguide core layers. . Conventional optical semiconductor devices have a problem that the allowable range for the variation in the width of the waveguide core layer is narrow.

According to one aspect of the present invention, a cladding layer, a slab layer thinner than the waveguide core layer, provided on the cladding layer, connected to both sides of the waveguide core layer and the waveguide core layer. A first semiconductor layer comprising: an insulating layer covering a side surface of the waveguide core layer and an upper surface of the slab layer; and on the side of the waveguide core layer, above the slab layer, with the insulating layer interposed therebetween. And an optical semiconductor element including a second semiconductor layer optically connected to the waveguide core layer. Here, the sum of the thickness of the slab layer and the thickness of the main part of the second semiconductor layer is not less than half the thickness of the waveguide core layer and not more than the thickness of the waveguide core layer. One of the slab layers on both sides of the waveguide core layer has a p-type region, and the other has an n-type region.

  According to the disclosed optical semiconductor element, it is possible to allow variation in the width of the waveguide core layer and suppress the influence of the variation on the propagation of light.

It is a figure which shows the structural example of an optical semiconductor element. It is a principal part top schematic diagram of an example of an optical switch. It is a principal part cross-sectional schematic diagram of an example of an optical switch (the 1). FIG. 3 is a schematic cross-sectional view of a main part of an example of an optical switch (part 2). FIG. 6 is a schematic cross-sectional view (No. 3) of an essential part of an example of an optical switch. It is a figure (the 1) which shows an example of the optical switch of another form. It is FIG. (2) which shows an example of the optical switch of another form. It is a figure which shows an example of the relationship of the dispersion | variation in the width | variety of a waveguide core layer, and a phase change. It is a figure which shows an example of the relationship of the phase change rate with respect to total slab thickness. FIG. 6 is a schematic cross-sectional view (No. 4) of an essential part of an example of an optical switch. It is a figure (the 1) which shows the modification of a semiconductor layer. FIG. 11 is a second diagram illustrating a modification of the semiconductor layer. It is a principal part cross-sectional schematic diagram of another example of an optical switch. It is explanatory drawing of the 1st formation process of an optical switch. It is explanatory drawing of the 2nd formation process of an optical switch. It is explanatory drawing of the 3rd formation process of an optical switch. It is explanatory drawing of the 4th formation process of an optical switch. It is explanatory drawing of the 5th formation process of an optical switch. It is explanatory drawing of the 6th formation process of an optical switch. It is explanatory drawing of the 7th formation process of an optical switch. It is explanatory drawing of the 8th formation process of an optical switch. It is explanatory drawing of the 9th formation process of an optical switch. It is a figure which shows an example of the optical switch integrated with the electronic circuit. It is a figure which shows an example of the optical switch which performs phase modulation by heating.

FIG. 1 is a diagram showing a configuration example of an optical semiconductor element.
An optical semiconductor element 1 shown in FIG. 1 has a cladding layer 2, a first semiconductor layer 3, an insulating layer 4, and a second semiconductor layer 5. The first semiconductor layer 3 includes a waveguide core layer 3a and a slab layer 3b.

The cladding layer 2 is made of a material having a refractive index lower than that of the first semiconductor layer 3 including the waveguide core layer 3a and the slab layer 3b. For example, an insulating material such as SiO ₂ is used for the cladding layer 2.

  The first semiconductor layer 3 is provided on the cladding layer 2. A semiconductor such as Si is used for the first semiconductor layer 3, and a waveguide core layer 3 a and a slab layer 3 b are provided on the first semiconductor layer 3. The waveguide core layer 3a is provided on the cladding layer 2 so as to have a predetermined thickness and width. The slab layer 3b is provided on the cladding layer 2 so as to be connected to both sides of the waveguide core layer 3a and to be thinner than the waveguide core layer 3a.

  The insulating layer 4 is provided so as to cover at least the side surface of the waveguide core layer 3a of the first semiconductor layer 3 and the upper surface of the slab layer 3b. The second semiconductor layer 5 is provided on the side of the waveguide core layer 3a and above the slab layer 3b with the insulating layer 4 interposed therebetween. The waveguide core layer 3 a and the slab layer 3 b of the first semiconductor layer 3 and the second semiconductor layer 5 are electrically separated by the insulating layer 4.

  In the optical semiconductor element 1, when light propagates through the waveguide core layer 3 a of the first semiconductor layer 3, the light field spreads also to the second semiconductor layer 5 provided via the insulating layer 4. Thereby, even if the width of the waveguide core layer 3a varies, it is possible to suppress the phase change of the propagation light due to the variation.

Hereinafter, the optical semiconductor element will be described in more detail.
Here, an optical switch will be described as an example of the optical semiconductor element.
FIG. 2 is a schematic plan view of an essential part of an example of an optical switch. 3 to 5 are schematic cross-sectional views of an essential part of an example of an optical switch. FIG. 2 schematically shows a planar layout of main elements included in the optical switch. 3 is a schematic diagram of a cross section corresponding to the XX position in FIG. 2, FIG. 4 is a schematic diagram of a cross section corresponding to the YY position in FIG. 2, and FIG. 5 is equivalent to a ZZ position in FIG. It is a schematic diagram of the cross section to do.

  As shown in FIG. 2, the optical switch 10 includes a Mach-Zehnder interferometer in which two arm portions 20A and 20B having a function as a phase shifter are connected to two 2-input 2-output optical couplers 30A and 30B. An optical interference type optical switch provided. For example, a multimode interference optical coupler having a branching ratio of 50:50 can be used as the optical couplers 30A and 30B. Two waveguides 40A and 40B are further connected to one optical coupler 30A, and two waveguides 40C and 40D are similarly connected to the other optical coupler 30B.

The arm portions 20A and 20B can have the same type of structure. Here, the structure of one arm portion 20A will be described as an example.
As shown in FIG. 2, the arm portion 20 </ b> A includes a waveguide structure portion 21 that connects the two optical couplers 30 </ b> A and 30 </ b> B, and a pair of electrodes 22 that are provided across the waveguide structure portion 21. . A portion of the waveguide structure 21 sandwiched between the pair of electrodes 22 functions as a phase shifter.

  In the waveguide structure portion 21 of the arm portion 20A, the phase shifter portion sandwiched between the pair of electrodes 22 is a waveguide core layer 21a provided on the lower cladding layer 23, as shown in FIG. It has a slab layer 21b connected to both sides of the waveguide core layer 21a. That is, a so-called rib-type waveguide structure including the waveguide core layer 21a and the slab layer 21b is formed. Furthermore, the waveguide structure 21 is a semiconductor layer provided on the side of the waveguide core layer 21a and above the slab layer 21b via an insulating layer 21c (shown as a layer integral with the upper cladding layer 24). 21d. In FIG. 2, the slab layer 21b and the insulating layer 21c are not shown.

  For the waveguide core layer 21a, a material that is transparent to signal light in the communication wavelength band propagating through the waveguide core layer 21a is used. A crystalline semiconductor can be used for the waveguide core layer 21a. Examples of the crystalline semiconductor that can be used for the waveguide core layer 21a include Si, silicon germanium (SiGe), indium phosphide (InP), gallium arsenide (GaAs), and mixed crystals thereof. For the slab layer 21b, for example, the same material as that of the waveguide core layer 21a is used.

  The waveguide core layer 21a and the slab layer 21b include, for example, a semiconductor layer provided on the lower cladding layer 23, a raised portion that becomes the waveguide core layer 21a, and a thin layer portion that becomes the slab layers 21b on both sides thereof. It can form by processing so that. For example, an SOI substrate in which a semiconductor layer (SOI (Semiconductor On Insulator) layer) is provided over a semiconductor substrate with an insulating layer (BOX layer) interposed therebetween is used. The BOX layer is used as the lower clad layer 23, and the SOI layer thereon is processed into a predetermined shape, thereby obtaining the waveguide core layer 21a and the slab layer 21b.

  Of the slab layers 21b provided on both sides of the waveguide core layer 21a, one slab layer 21b is provided with a p-type doping region 21e doped with a p-type impurity such as boron (B). The other slab layer 21b is provided with an n-type doped region 21f doped with an n-type impurity such as phosphorus (P). The waveguide core layer 21a is i-type that is non-doped or doped so that the number of p-type and n-type carriers is the same. The p-type and n-type slab layers 21b provided on both sides of the i-type waveguide core layer 21a are connected to the electrodes 22 to form a pin type diode.

A semiconductor layer 21d is provided on the side of the waveguide core layer 21a and above the slab layer 21b via an insulating layer 21c.
As with the waveguide core layer 21a, the semiconductor layer 21d is made of a material that is transparent to signal light in the communication wavelength band that propagates through the waveguide core layer 21a. For the semiconductor layer 21d, an amorphous semiconductor such as amorphous silicon, or a polycrystalline semiconductor such as polysilicon can be used. In addition, SiGe, InP, GaAs, or a mixed crystal thereof can be used for the semiconductor layer 21d. For example, a non-doped semiconductor layer is used for the semiconductor layer 21d. The semiconductor layer 21d serves to expand the light field when the signal light propagates through the waveguide core layer 21a.

The insulating layer 21c electrically separates the semiconductor layer 21d from the waveguide core layer 21a and the slab layer 21b. For example, SiO ₂ can be used for the insulating layer 21c. In addition, aluminum oxide (Al ₂ O ₃ ), SiO _x , silicon oxynitride (SiON), silicon nitride (SiN), or the like can be used for the insulating layer 21c. The insulating layer 21c has such a thickness that the semiconductor layer 21d and the waveguide core layer 21a are optically connected while electrically separating the semiconductor layer 21d, the waveguide core layer 21a, and the slab layer 21b. Is provided.

In addition to SiO ₂ , Al ₂ O ₃ , SiO _x , SiON, SiN, or the like can be used for the lower cladding layer 23 in which such a waveguide structure portion 21 is formed. Similarly, in addition to SiO ₂ , Al ₂ O ₃ , SiO _x , SiON, SiN, etc. can be used for the upper clad layer 24. Furthermore, for the upper cladding layer 24, polyimide, benzocyclobutene (BCB), and various polymers can be used. For the lower cladding layer 23 and the upper cladding layer 24, a material having a lower refractive index than that of the waveguide core layer 21a is used.

  As shown in FIG. 2, the waveguide structure portion 21 (waveguide core layer 21a) includes a linear portion, and a curved portion connecting the linear portion and the optical couplers 30A and 30B. The electrode 22 is provided so as to sandwich the linear portion of the waveguide structure portion 21, and the semiconductor layer 21 d is provided in the linear portion.

  The region where the semiconductor layer 21d is not provided in the waveguide structure 21 has a cross-sectional structure as shown in FIG. This region has a structure in which a waveguide core layer 21 a and a slab layer 21 b are provided on the lower cladding layer 23 and these are covered with the upper cladding layer 24. In the example of FIG. 4, the semiconductor layer 21d and the electrode 22 described above are not provided, and the slab layer 21b is not doped.

  For example, as shown in FIG. 5, the end portion of the semiconductor layer 21d has a structure that gradually decreases toward a region where the semiconductor layer 21d is not provided (such that it gradually increases toward the phase shifter). Can do. As an example, FIG. 5 shows a mode in which the thickness of the semiconductor layer 21d decreases stepwise toward a region where the semiconductor layer 21d is not provided.

Here, the structure of the one arm portion 20A has been described as an example, but the other arm portion 20B can also have the same structure.
In the optical switch 10 having the above-described configuration, for example, signal light from one of the waveguides 40A and 40B connected to the two input ports of one optical coupler 30A, here as an example, from the waveguide 40A. Is entered. The input output light is demultiplexed by the optical coupler 30A, and the demultiplexed signal light is output to the arm units 20A and 20B respectively connected to the two output ports of the optical coupler 30A.

  When the phase modulation is not performed in the arm portions 20A and 20B, the signal light propagating through the arm portions 20A and 20B is the other optical coupler 30B in which the arm portions 20A and 20B are connected to the two input ports, respectively. Is input. The signal light input to the optical coupler 30B is multiplexed by the optical coupler 30B, and the combined signal light is one of the waveguides 40C and 40D connected to the two output ports of the optical coupler 30B. Here, the light is output from the waveguide 40C as an example.

  Further, the phase of the signal light propagating through the arm portion 20A and the signal light propagating through the arm portion 20B are changed as necessary (phase modulation). At that time, carriers are injected into the waveguide core layer 21a by current injection through the electrode 22 and the slab layer 21b, the equivalent refractive index is changed, and the phase of the propagated signal light is changed. Such phase modulation is performed in the arm portion 20A, the arm portion 20B, or both the arm portions 20A and 20B. The light including the signal light after phase modulation is multiplexed by the optical coupler 30B. In the phase modulation, for example, phase modulation is performed such that the light combined by the optical coupler 30B is output from one of the waveguides 40C and 40D. Alternatively, phase modulation is performed such that no signal is output from either of the waveguides 40C and 40D.

  In the optical switch 10, as described above, the semiconductor layer 21d is provided on the side of the waveguide core layer 21a and above the slab layer 21b via the insulating layer 21c in the arm portions 20A and 20B through which the signal light propagates. ing. The semiconductor layer 21d is transparent to the propagated signal light, and is electrically separated from the waveguide core layer 21a and the slab layer 21b, while being optically connected to the waveguide core layer 21a.

  By providing such a semiconductor layer 21d, it is possible to widen the optical field when signal light propagates through the waveguide core layer 21a. That is, the signal light mainly propagates through the waveguide core layer 21a sandwiched between the lower clad layer 23 and the upper clad layer 24. At this time, the optical signal is provided along the waveguide core layer 21a. And spreads to the semiconductor layer 21d connected in general. In this way, by expanding the optical field by the semiconductor layer 21d, it becomes possible to increase the allowable range of variation in the width of the waveguide core layer 21a.

  Here, an example of another type of optical switch not provided with such a semiconductor layer 21d is shown in FIGS. FIG. 6 schematically shows a planar layout of main elements included in the optical switch. FIG. 7 is a schematic cross-sectional view corresponding to the position X ″ -X ″ in FIG. 6.

  The optical switch 100 shown in FIGS. 6 and 7 is different from the optical switch 10 in that the semiconductor layer 21d provided in the optical switch 10 is not provided. Other structures are the same as those of the optical switch 10.

  In other words, in the optical switch 100, for example, arm parts 200A and 200B having the same type of structure are connected to the optical couplers 300A and 300B. Furthermore, waveguides 400A and 400B are connected to the optical coupler 300A, and waveguides 400C and 400D are connected to the optical coupler 300B. Each of the arm portions 200A and 200B includes a waveguide structure portion 210 having a waveguide core layer 210a and a slab layer 210b provided between the lower cladding layer 230 and the upper cladding layer 240, and an electrode 220. The slab layer 210b is provided with a p-type doping region 210e and an n-type doping region 210f.

In the case of the optical switch 100 in which the semiconductor layer 21d as described above is not provided, the width of the waveguide core layer 210a tends to affect the equivalent refractive index. For example, when SiO ₂ is used for the lower clad layer 230 and the upper clad layer 240 and Si is used for the waveguide core layer 210a, the signal light is guided by the Si waveguide due to the relatively large refractive index difference between them. It becomes strongly localized in the core layer 210a. In such a situation, a relatively large phase change may occur with respect to the propagating signal light due to a change in equivalent refractive index due to a variation in the width of the waveguide core layer 210a. If the signal light propagating through the waveguide core layer 210a undergoes a phase change due to variations in its width, the signal light having a desired phase cannot be output.

  For example, as described above, when the phase modulation is not performed by the arm units 200A and 200B, the signal light input from either of the waveguides 400A and 400B propagates through the arm units 200A and 200B and is combined by the optical coupler 300B. And output from one of the waveguides 400C and 400D. However, if there is a variation in the width of both or both of the arm portions 200A and 200B and the waveguide core layer 210a, a phase change caused by the variation is added, so that signal light is output from both of the waveguides 400C and 400D. Can happen. That is, the initial interference state of the optical switch 100 may become indefinite.

  In such an indefinite state, a phase adjustment that cancels a phase change caused by a variation in the width of the waveguide core layer 210a is performed in advance by current injection using the pair of electrodes 220 and the slab layer 210b. It is possible to avoid it. However, there are problems that it takes time and effort to perform such phase adjustment, it is necessary to perform phase adjustment for each optical switch 100, and extra power is required for phase adjustment during operation of the optical switch 100.

  In contrast, in the optical switch 10 described above, the semiconductor layer 21d that is transparent to the propagating signal light is provided on both sides of the waveguide core layer 21a to widen the optical field when the signal light propagates. Thereby, even if the width of the waveguide core layer 21a varies, the influence of the variation on the phase of the signal light propagating can be suppressed. Therefore, in this optical switch 10, it is possible to tolerate variations in the width of the waveguide core layer 21a to some extent. Further, the optical switch 10 does not require the phase adjustment for canceling the phase change due to the variation in the width of the waveguide core layer 210a, which is performed in the optical switch 100 (FIGS. 6 and 7). .

  In the optical switch 10, since the semiconductor layer 21d is electrically separated from the waveguide core layer 21a and the slab layer 21b by the insulating layer 21c, no current flows through the semiconductor layer 21d and spreads to the semiconductor layer 21d. Loss of propagating signal light can be suppressed. Furthermore, the loss of signal light can be further suppressed by making the semiconductor layer 21d non-doped.

Here, an example of the relationship between the variation in the width of the waveguide core layer and the phase change is shown in FIG.
In FIG. 8, an example of the relationship between the variation (nm) in the width of the waveguide core layer 21a and the phase change (位相) in the optical switch 10 including the semiconductor layer 21d is indicated by a solid line. Here, for the optical switch 10 (FIGS. 2 and 3), the waveguide core layer 21a is a Si layer having a width Wa of about 500 nm and a thickness Ta of about 250 nm, and the slab layer 21b is made of a thickness Tb of about 50 nm. Si layer. The waveguide core layer 21a is doped with about 1 × 10 ¹⁹ cm ^{−3 of} both p-type and n-type impurities, and the p-type and n-type impurities are about 1 × 10 ¹⁹ cm respectively on the slab layers 21b on both sides thereof. ^-3 doping. The insulating layer 21c is a SiO ₂ layer having a thickness Tc of about 10 nm, and the semiconductor layer 21d is an amorphous silicon layer having a width Wd of about 2 μm and a thickness Td of about 150 nm. The phase shifter length (the length of the waveguide structure portion 21 sandwiched between the electrodes 22) is about 1 mm.

For comparison, FIG. 8 also shows an example of the relationship between the variation in the width (nm) of the waveguide core layer 210a and the phase change (Π) in the optical switch 100 that does not include the semiconductor layer 21d, with a dotted line and a chain line. It shows. Here, for the optical switch 100 (FIGS. 6 and 7), as in the optical switch 10, the waveguide core layer 210a is a Si layer having a width Wa of about 500 nm and a thickness Ta of about 250 nm, and the slab layer 210b is formed. The Si layer has a thickness Tb of about 50 nm or about 100 nm. In FIG. 8, the case where Tb is about 50 nm is indicated by a dotted line, and the case where Tb is 100 nm is indicated by a chain line. The waveguide core layer 210a, p-type, and n-type impurity are both about 1 × 10 ¹⁹ cm ^-3 doping, the slab layer 210b on both sides thereof, p-type, the n-type impurity are approximately 1 × 10 ¹⁹ cm ^-3 doping. The phase shifter length (the length of the waveguide structure 210 sandwiched between the electrodes 220) is about 1 mm.

  From FIG. 8, the optical switch 100 is first compared with the case where the thickness Tb of the slab layer 210b is about 50 nm (dotted line) and the case where the thickness Tb is about 100 nm (dashed line). In the optical switch 100, when the slab layer 210b is made as thick as about 100 nm, the phase change due to the variation in the waveguide core layer width can be suppressed as compared with the case where the slab layer 210b is made as thin as about 50 nm. This is because by increasing the thickness of the slab layer 210b, the signal light propagating through the waveguide core layer 210a spreads to the thick slab layer 210b.

  On the other hand, when the optical switches 10 and 100 are compared, even if the slab layers 21b and 210b have the same thickness Tb of about 50 nm, the optical switch 10 provided with the semiconductor layer 21d has a variation in the waveguide core layer width. The phase change with respect to is greatly suppressed. Further, in the optical switch 10 provided with the semiconductor layer 21d, the phase change due to the variation in the waveguide core layer width can be significantly suppressed as compared with the optical switch 100 in which the thickness Tb of the slab layer 210b is increased to about 100 nm. become.

FIG. 9 shows an example of the relationship between the phase change rate and the total slab thickness.
Here, the total slab thickness represents the thickness Tb of the slab layer 210b in the case of the optical switch 100 not provided with the semiconductor layer 21d as described above. In the case of the optical switch 10 provided with the semiconductor layer 21d, the total thickness Tb + Td of the thickness Tb of the slab layer 21b and the thickness Td of the semiconductor layer 21d is represented. In the case of the optical switch 10 illustrated with reference to FIG. 8, the total slab thickness is about 200 nm (Tb + Td = about 50 nm + about 150 nm).

Further, the phase change rate represents the slope in the relationship between the variation in the waveguide core layer width shown in FIG. 8 and the phase change.
9, the optical switch 10 provided with the semiconductor layer 21d having a total slab thickness of about 200 nm has a phase change rate higher than that of the optical switch 100 having a total slab thickness of about 50 nm and not provided with the semiconductor layer 21d. It can be suppressed to about 1/8. Furthermore, in the optical switch 10, the phase change rate can be suppressed to about 1/5 as compared with the optical switch 100 in which the total slab thickness is about 100 nm.

  8 and 9, according to the optical switch 10, by providing the semiconductor layer 21d on the side of the waveguide core layer 21a, the occurrence of phase shift due to the variation in the width of the waveguide core layer 21a is effectively suppressed. It can be said that.

  In order to sufficiently suppress the phase change rate with respect to the width variation of the waveguide core layer 21a, the total slab thickness Tb + Td in the optical switch 10 is set to half the thickness Ta of the waveguide core layer 21a (in the above example, about 250 nm). / 2 = about 125 nm) or more.

  Further, the total slab thickness Tb + Td in the optical switch 10 is preferably equal to or less than the thickness Ta of the waveguide core layer 21a. When the total slab thickness Tb + Td exceeds the thickness Ta of the waveguide core layer 21a, there is no structure for confining light in the waveguide core layer 21a, so that the light spreading in the semiconductor layer 21d increases and the loss may increase. Because there is. Further, in the case of the optical switch 100, since there is no structure for confining light in the waveguide core layer 210a, the loss may increase.

  In the optical switch 10, the semiconductor layer 21d can be provided on the linear portion of the waveguide core layer 21a (waveguide structure portion 21) and not on the curved portion (FIG. 2). By doing in this way, the curvature of the waveguide core layer 21a in the curved part of the waveguide structure part 21 can be made small. As a result, the interval between the adjacent waveguide structure portions 21 can be narrowed, or the size of each waveguide structure portion 21 itself can be reduced. It becomes possible to mitigate phase fluctuations.

In the above description, the doping concentration of the p-type doping region 21e and the n-type doping region 21f formed in the slab layer 21b is about 1 × 10 ¹⁹ cm ⁻³ for both p-type and n-type impurities. The doping concentration is not limited to this example. However, it should be noted that the lower the doping concentration, the smaller the amount of carriers injected into the waveguide core layer 21a, and the higher the doping concentration, the more light loss.

Further, in the above description, the case where the two arm portions 20A and 20B have the same type of structure is illustrated for the optical switch 10, but they can also have different structures.
For example, in the above example, both the arm portions 20A and 20B have the phase shifter function, but only one of them may have the phase shifter function. For example, in the optical switch 10, when only the arm portion 20A functions as a phase shifter, the cross section of the arm portion 20B that does not have the phase shifter function has a structure as shown in FIG. FIG. 10 is a schematic cross-sectional view corresponding to the position X′-X ′ in FIG.

  As shown in FIG. 10, in the arm portion 20B, p-type and n-type impurities are not doped into the slab layers 21b on both sides of the waveguide core layer 21a. About another part, it can be the same as that of 20 A of arm parts. When the arm portion 20B is not used as a phase shifter as described above, the electrode 22 of the arm portion 20B as shown in FIG. 2 is not necessarily provided.

  In the above description, the case where the thickness of the semiconductor layer 21d is decreased stepwise toward the end is illustrated (FIG. 5), but the structure of the semiconductor layer 21d is limited to this example. Instead, for example, the structure shown in FIGS. 11 and 12 can be used. 11 is a schematic cross-sectional view corresponding to the ZZ position in FIG. 2, and FIG. 12 is a schematic view of the vicinity of the end of the semiconductor layer as seen in a plan view.

  As shown in FIG. 11, the semiconductor layer 21d may have a structure in which the thickness is continuously reduced toward the end. Further, as shown in FIG. 12, the semiconductor layer 21d may have a structure in which the width is continuously reduced toward the end while the thickness is kept constant until reaching the end. The semiconductor layer 21d may have a structure in which the width is decreased stepwise toward the end while the thickness is constant.

  In the above description, the semiconductor layer 21d is provided on the side of the waveguide core layer 21a and above the slab layer 21b. However, the arrangement region and shape of the semiconductor layer 21d are not limited to the above example. .

FIG. 13 is a schematic cross-sectional view of an essential part of another example of the optical switch.
As shown in FIG. 13, if the semiconductor layer 21d is not optically coupled to the waveguide core layer 21a, for example, about 1 μm, and separated from the waveguide core layer 21a, the semiconductor layer 21d is also above the waveguide core layer 21a. It does not matter if it is provided. Between the waveguide core layer 21a and the semiconductor layer 21d thereabove, an upper cladding layer 25 having a lower refractive index than those is provided.

  In this case, the semiconductor layer 21d can be formed so as to cover the side wall of the upper cladding layer 25 in manufacturing. When the semiconductor layer 21d is formed with such a thickness that the upper surface of the main part M is lower than the upper surface of the waveguide core layer 21a, the semiconductor layer 21d is also formed in the portion Q corresponding to the height difference. Can be done. However, even if the semiconductor layer 21d is formed in such a part Q together with the main part M of the semiconductor layer 21d, the thickness Tq of the semiconductor layer 21d in the part Q does not affect optically, for example, 10 nm. If it is about the extent, the influence on the element characteristics can be avoided.

Next, a method for forming an example of an optical switch will be described in order with reference to FIGS.
FIG. 14 is an explanatory diagram of the first forming step of the optical switch.

First, an SOI substrate 610 as shown in FIG. 14 is prepared. The SOI substrate 610 includes a semiconductor substrate 611, a BOX layer 612, and an SOI layer 613. As the semiconductor substrate 611, for example, a Si substrate can be used. For the BOX layer 612, for example, a SiO ₂ layer having a thickness of about 3 μm can be used. As the SOI layer 613, for example, a Si layer having a thickness of about 250 nm can be used. The BOX layer 612 of the SOI substrate 610 is used as a lower cladding layer, and a waveguide core layer and a slab layer are formed on the SOI layer 613 as will be described later.

A hard mask 620 is formed on the SOI substrate 610 as shown in FIG. For the hard mask 620, for example, a SiO ₂ layer having a thickness of about 1 μm can be used. A part of the hard mask 620 becomes a part of an upper clad layer described later. In the following description, the hard mask 620 may be referred to as the upper clad layer 620.

FIG. 15 is an explanatory diagram of a second forming process of the optical switch.
After the hard mask 620 is formed, as shown in FIG. 15, the hard mask 620 is patterned so as to remain in the formation region of the waveguide core layer. For example, a line pattern having a width of about 500 nm including a linear portion and a curved portion is formed on the hard mask 620.

FIG. 16 is an explanatory diagram of the third step of forming the optical switch.
After the patterning of the hard mask 620, the SOI layer 613 is etched using the patterned hard mask 620 as a mask. When the SOI layer 613 is etched, as shown in FIG. 16, the region not covered with the hard mask 620 is etched so that the lower layer portion of the SOI layer 613 is left on the BOX layer 612. Thus, the waveguide core layer 613a is formed under the hard mask (upper clad layer) 620, and the waveguide core layer 613a is connected to the waveguide core layer 613a on both sides of the waveguide core layer 613a. A thin slab layer 613b is formed.

  When the SOI layer 613 is etched, if the SOI layer 613 having a thickness of, for example, about 50 nm is left on the BOX layer 612 in a region not covered with the hard mask 620, the waveguide core layer 613a having a thickness of about 250 nm is left. A slab layer 613b having a thickness of about 50 nm can be formed on both sides thereof.

FIG. 17 is an explanatory diagram of the fourth step of forming the optical switch.
After the waveguide core layer 613a and the slab layer 613b are formed, the slab layers 613b formed on both sides of the waveguide core layer 613a are doped with p-type and n-type impurities, respectively. As shown in FIG. 17, a p-type doping region 613c is formed in one slab layer 613b by doping p-type impurities such as B with about 1 × 10 ¹⁹ cm ⁻³ . In the other slab layer 613b, an n-type doping region 613d is formed by doping an n-type impurity such as P with about 1 × 10 ¹⁹ cm ⁻³ . After the doping, activation annealing is performed.

FIG. 18 is an explanatory diagram of a fifth forming step of the optical switch.
After doping the slab layer 613b, as shown in FIG. 18, an insulating layer 630 is formed on the top surface of the slab layer 613b, the side surface of the waveguide core layer 613a, and the side surface and top surface of the upper cladding layer (hard mask) 620. To do. As the insulating layer 630, for example, a SiO ₂ layer having a thickness of about 10 nm can be formed.

  The insulating layer 630 serves to electrically separate the waveguide core layer 613a and the slab layer 613b from a semiconductor layer described later while electrically connecting them. Therefore, the insulating layer 630 may be formed on at least the upper surface of the slab layer 613b and the side surface of the waveguide core layer 613a. In that case, for example, an oxide film may be formed on the upper surface of the slab layer 613b and the side surface of the waveguide core layer 613a by thermal oxidation and used as the insulating layer 630.

FIG. 19 is an explanatory diagram of a sixth forming step of the optical switch.
After the formation of the insulating layer 630, a semiconductor layer 640 is formed over the formed insulating layer 630 as shown in FIG. For example, an amorphous silicon layer can be used for the semiconductor layer 640.

  The semiconductor layer 640 has an upper surface of a main part formed on the slab layer 613b (a part on the slab layer 613b excluding a part formed along the sidewalls of the waveguide core layer 613a and the upper cladding layer 620). It is formed with a thickness that is lower than the upper surface of the waveguide core layer 613a. Furthermore, the semiconductor layer 640 is formed with a thickness that is at least half the thickness of the waveguide core layer 613a. In addition, the semiconductor layer 640 is formed so that the thickness of portions formed along the sidewalls of the waveguide core layer 613a and the upper cladding layer 620 is about 10 nm.

For example, an amorphous silicon layer with a thickness of about 150 nm is formed over the insulating layer 630 as the semiconductor layer 640. In the case where an amorphous silicon layer is used for the semiconductor layer 640, after the amorphous silicon layer is formed, sputtering is performed, and annealing is performed in an atmosphere containing hydrogen (H ₂ ), so that Si of the amorphous silicon layer is converted into hydrogen (H ) (Hydrogenated amorphous silicon).

FIG. 20 is an explanatory diagram of a seventh forming step of the optical switch.
After the formation of the semiconductor layer 640, an upper cladding layer 650 is formed on the formed semiconductor layer 640 as shown in FIG. As the upper clad layer 650, for example, a SiO ₂ layer having a thickness of about 1 μm can be formed.

FIG. 21 is an explanatory diagram of the eighth forming step of the optical switch.
After the formation of the upper clad layer 650, planarization by CMP (Chemical Mechanical Planarization) is performed as shown in FIG. As a result, the upper cladding layer (hard mask) 620 is exposed above the waveguide core layer 613a, and the upper cladding layer 650 is disposed above the slab layer 613b and the insulating layer 630 between the upper cladding layer 620 and the upper cladding layer 620. And the state exposed across the semiconductor layer 640 is obtained.

FIG. 22 is an explanatory diagram of a ninth forming step of the optical switch.
After planarization, as shown in FIG. 22, a pair of electrodes 660 is formed so as to be connected to the p-type doping region 613c and the n-type doping region 613d formed in the slab layer 613b. For example, a hole 660a that penetrates the upper cladding layer 650, the semiconductor layer 640, and the insulating layer 630 and reaches the p-type doping region 613c and the n-type doping region 613d is formed, and the electrode 660 is formed in the hole 660a. As a result, the bottom surface of the electrode 660 is connected to the p-type doping region 613c and the n-type doping region 613d. A metal material such as aluminum (Al) can be used for the electrode 660.

  Note that a hole 660a that penetrates part of the p-type doping region 613c and part of the n-type doping region 613d and reaches the BOX layer 612 may be formed, and the electrode 660 may be formed there. In this case, the p-type doping region 613c and the n-type doping region 613d are connected to the side surface of the electrode 660.

Through the above steps, an optical switch 600 as shown in FIG. 22 is obtained.
In this optical switch 600, the semiconductor layer 640 is formed along the sidewalls of the waveguide core layer 613a and the upper cladding layer 620. If the thickness is such that it does not optically affect, The semiconductor layer 640 may be formed in the portion.

The formation method of the optical switch 600 has been described above as an example.
FIGS. 14 to 22 focus on one arm portion of the optical switch 600 and exemplify the formation method. Of course, another arm portion included in the optical switch 600 is formed simultaneously with the arm portion. It is possible.

  The material used for the optical switch 600 is not limited to the above example. For example, in addition to Si, SiGe, InP, GaAs, or a mixed crystal thereof can be used for the SOI layer 613 that forms the waveguide core layer 613a and the slab layer 613b. In addition to amorphous silicon, polysilicon, InP, GaAs, or the like can be used for the semiconductor layer 640 provided on the side of the waveguide core layer 613a. For the SOI layer 613 and the semiconductor layer 640, a material that is transparent to signal light in the communication wavelength band can be used.

  As the semiconductor substrate 611, a substrate such as quartz, GaAs, or InP can be used in addition to the Si substrate. However, the Si substrate has advantages such as low cost and relatively easy integration with electronic circuits such as drivers. An example of an optical switch integrated with an electronic circuit is shown in FIG. FIG. 23 schematically shows a planar layout of main elements included in the optical switch.

  FIG. 23 illustrates an optical semiconductor element 700 in which an optical switch 10a and two complementary metal oxide semiconductor (CMOS) driver circuits 710 and 720 are integrated on a predetermined substrate, for example, a Si substrate. The optical switch 10a in the optical semiconductor device 700 of FIG. 23 is provided with a common electrode 22a used in both waveguide structure portions 21 in a region sandwiched between two opposing waveguide structure portions 21. Thus, the optical switch 10 is different.

  In the optical semiconductor device 700, one of the CMOS driver circuits 710 is electrically connected to the electrodes 22 and 22a sandwiching one waveguide structure portion 21 via conductive portions 711a and 712b (illustrated by dotted lines) including wirings and the like. It is connected. The other CMOS driver circuit 720 is electrically connected to the electrodes 22 and 22a sandwiching the other waveguide structure portion 21 via conductive portions 721a and 721b (illustrated by dotted lines) including wirings and the like. Has been. In the optical semiconductor element 700, the operation of the optical switch 10a (the phase adjustment of the signal light propagating through the waveguide structure) is controlled using the CMOS driver circuits 710 and 720.

  When a Si substrate is used as the substrate of such an optical semiconductor element 700, the CMOS driver circuits 710 and 720 and the optical switch 10a can all be formed using the Si process, and when other substrates are used. In comparison, they can be collected relatively easily.

  In the above description, the case where the phase modulation of the signal light propagating through each waveguide structure portion 21 is performed by current injection using the pair of electrodes 22 or the electrodes 22 and 22a is illustrated (this point is described above). The same applies to the optical switch 600). In addition, the phase modulation of the signal light can be performed by heating. An example of an optical switch that performs phase modulation by heating in this way is shown in FIG.

  As shown in FIG. 24, the heater electrode 26 is provided on the upper cladding layer 24 above the waveguide core layer 21a. By energizing the heater electrode 26, the heater electrode 26 generates heat and the waveguide core layer 21a is heated, thereby changing the equivalent refractive index and performing phase modulation of the signal light propagating through the waveguide core layer 21a. Do.

  Even when the heater electrode 26 is used in this way, the light field is expanded by providing the semiconductor layer 21d via the insulating layer 21c on the side of the waveguide core layer 21a and above the slab layer 21b. It becomes possible to allow variation in the width of the waveguide core layer 21a. Even when the heater electrode 26 is provided in this way, the semiconductor layer 21d can be structured as shown in FIG. 5, FIG. 11 or FIG. Further, when the heater electrode 26 is provided in this way, it is not necessary to form the electrode 22 and the p-type doping region 21e and the n-type doping region 21f of the slab layer 21b.

  In the above description, a multi-mode interference type optical coupler with two inputs and two outputs has been exemplified. However, usable optical couplers are not limited to this. For example, a directional coupler type 2-input 2-output optical coupler may be used. However, it should be noted that the directional coupler type optical coupler has a large wavelength dependency, and the optical switch may not have uniform characteristics with respect to the wavelength. Further, instead of 2-input 2-output, for example, a 1-input 2-output and 2-input 1-output optical coupler may be used in combination. However, it should be noted that in the case of an optical semiconductor element combined with such an optical coupler, it can be a modulator or a gate switch, but cannot be a path switching switch.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Appendix 1) a cladding layer;
A first semiconductor layer provided on the cladding layer and having a waveguide core layer and a slab layer thinner than the waveguide core layer connected to both sides of the waveguide core layer;
An insulating layer covering a side surface of the waveguide core layer and an upper surface of the slab layer;
A second semiconductor layer provided on the side of the waveguide core layer and above the slab layer via the insulating layer and optically connected to the waveguide core layer;
An optical semiconductor element comprising:

(Supplementary note 2) The optical semiconductor element according to supplementary note 1, wherein the second semiconductor layer is an amorphous semiconductor layer or a polycrystalline semiconductor layer.
(Additional remark 3) The said 2nd semiconductor layer is non-dope, The optical semiconductor element of Additional remark 1 or 2 characterized by the above-mentioned.

  (Supplementary Note 4) The sum of the thickness of the slab layer and the thickness of the main part of the second semiconductor layer is not less than half the thickness of the waveguide core layer and not more than the thickness of the waveguide core layer. 4. The optical semiconductor device according to any one of appendices 1 to 3, wherein the optical semiconductor device is characterized.

  (Supplementary Note 5) The supplementary notes 1 to 4, wherein the waveguide core layer is i-type, and one of the slab layers on both sides of the waveguide core layer is p-type and the other is n-type. Any one of the optical semiconductor elements.

(Additional remark 6) The optical semiconductor element in any one of additional remark 1 thru | or 4 with which the heater electrode is provided above the said waveguide core layer.
(Additional remark 7) The said waveguide core layer has a linear part and a curved part, The said 2nd semiconductor layer is provided in the side of the said linear part, Additional remark 1 thru | or 6 characterized by the above-mentioned. An optical semiconductor device according to any one of the above.

(Supplementary note 8) The optical semiconductor element according to any one of supplementary notes 1 to 7, wherein the second semiconductor layer is provided so that a thickness or a width decreases toward a terminal.
(Supplementary Note 9) A first waveguide core layer provided on the cladding layer and connected to both sides of the first waveguide core layer, the first slab layer being thinner than the first waveguide core layer. A first semiconductor layer having;
A first insulating layer covering a side surface of the first waveguide core layer and an upper surface of the first slab layer;
A second semiconductor layer provided on the side of the first waveguide core layer and above the first slab layer via the first insulating layer and optically connected to the first waveguide core layer; ,
A first waveguide structure comprising:
A third semiconductor provided on the cladding layer and having a second waveguide core layer and a second slab layer that is connected to both sides of the second waveguide core layer and is thinner than the second waveguide core layer Layers,
A second insulating layer covering a side surface of the second waveguide core layer and an upper surface of the second slab layer;
A fourth semiconductor layer provided on the side of the second waveguide core layer and above the second slab layer via the second insulating layer and optically connected to the second waveguide core layer; ,
A second waveguide structure comprising:
A first optical coupler connected to the first waveguide structure portion and the second waveguide structure portion and demultiplexing input light into the first waveguide core layer and the second waveguide core layer;
A second optical coupler connected to the first waveguide structure portion and the second waveguide structure portion, and configured to multiplex propagation light of the first waveguide core layer and the second waveguide core layer;
An optical semiconductor element comprising:

(Appendix 10) Forming a first semiconductor layer having a waveguide core layer and a slab layer thinner than the waveguide core layer connected to both sides of the waveguide core layer on the cladding layer;
Forming an insulating layer covering a side surface of the waveguide core layer and an upper surface of the slab layer;
Forming a second semiconductor layer via the insulating layer on the side of the waveguide core layer and above the slab layer so as to be optically connected to the waveguide core layer;
The manufacturing method of the optical semiconductor element characterized by the above-mentioned.

DESCRIPTION OF SYMBOLS 1,700 Opto-semiconductor element 2 Clad layer 3 1st semiconductor layer 3a, 21a, 210a, 613a Waveguide core layer 3b, 21b, 210b, 613b Slab layer 4, 21c, 630 Insulating layer 5 2nd semiconductor layer 10, 10a, 100, 600 Optical switch 20A, 20B, 200A, 200B Arm portion 21, 210 Waveguide structure portion 21d, 640 Semiconductor layer 21e, 210e, 613cp p-type doping region 21f, 210f, 613d n-type doping region 22, 22a, 220, 660 Electrode 23, 230 Lower clad layer 24, 25, 240, 650 Upper clad layer 26 Heater electrode 30A, 30B, 300A, 300B Optical coupler 40A, 40B, 40C, 40D, 400A, 400B, 400C, 400D Waveguide 610 SOI substrate 611 half Body substrate 612 BOX layer 613 SOI layer 620 hard mask 660a holes 710, 720 CMOS driver circuits 711a, 721a conductive portion

Claims (7)

A cladding layer;
A first semiconductor layer provided on the cladding layer and having a waveguide core layer and a slab layer thinner than the waveguide core layer connected to both sides of the waveguide core layer;
An insulating layer covering a side surface of the waveguide core layer and an upper surface of the slab layer;
A second semiconductor layer provided on the side of the waveguide core layer and above the slab layer via the insulating layer and optically connected to the waveguide core layer;
Only including,
The sum of the thickness of the slab layer and the thickness of the main part of the second semiconductor layer is not less than half the thickness of the waveguide core layer and not more than the thickness of the waveguide core layer. Semiconductor element. A cladding layer;
A first semiconductor layer provided on the cladding layer and having a waveguide core layer and a slab layer thinner than the waveguide core layer connected to both sides of the waveguide core layer;
An insulating layer covering a side surface of the waveguide core layer and an upper surface of the slab layer;
A second semiconductor layer provided on the side of the waveguide core layer and above the slab layer via the insulating layer and optically connected to the waveguide core layer;
Only including,
One of the slab layers on both sides of the waveguide core layer has a p-type region, and the other has an n-type region . Said second semiconductor layer, the optical semiconductor device according to claim 1 or 2, characterized in that an amorphous semiconductor layer or a polycrystalline semiconductor layer. The waveguide core layer, and a straight portion and a curved portion, said second semiconductor layer, any of claims 1 to 3, characterized in that provided on the side of the linear portion An optical semiconductor device according to 1. A first waveguide core layer provided on the first cladding layer, and having a first slab layer thinner than the first waveguide core layer and connected to both sides of the first waveguide core layer; 1 semiconductor layer;
A first insulating layer covering a side surface of the first waveguide core layer and an upper surface of the first slab layer;
A second semiconductor layer provided on the side of the first waveguide core layer and above the first slab layer via the first insulating layer and optically connected to the first waveguide core layer; ,
Only including,
The first slab layer on both sides of the first waveguide core layer, one of the first waveguide structures having a p-type region and the other having an n-type region ;
A second waveguide core layer provided on the second cladding layer and having a second slab layer thinner than the second waveguide core layer and connected to both sides of the second waveguide core layer; 3 semiconductor layers;
A second insulating layer covering a side surface of the second waveguide core layer and an upper surface of the second slab layer;
A fourth semiconductor layer provided on the side of the second waveguide core layer and above the second slab layer via the second insulating layer and optically connected to the second waveguide core layer; ,
A second waveguide structure comprising:
A first optical coupler connected to the first waveguide structure portion and the second waveguide structure portion and demultiplexing input light into the first waveguide core layer and the second waveguide core layer;
A second optical coupler connected to the first waveguide structure portion and the second waveguide structure portion, and configured to multiplex propagation light of the first waveguide core layer and the second waveguide core layer;
Electrodes respectively connected to the p-type region and the n-type region of the first waveguide structure;
An optical semiconductor element comprising: The upper cladding layer, a waveguide core layer, and forming the waveguide core layer respectively connected to both sides of the first semiconductor layer having said waveguide core layer thin slab layer than,
Forming an insulating layer covering a side surface of the waveguide core layer and an upper surface of the slab layer;
Forming a second semiconductor layer via the insulating layer on the side of the waveguide core layer and above the slab layer so as to be optically connected to the waveguide core layer;
Only including,
The sum of the thickness of the slab layer and the thickness of the main part of the second semiconductor layer is not less than half the thickness of the waveguide core layer and not more than the thickness of the waveguide core layer. A method for manufacturing a semiconductor device. The upper cladding layer, a waveguide core layer, and forming the waveguide core layer respectively connected to both sides of the first semiconductor layer having said waveguide core layer thin slab layer than,
Forming an insulating layer covering a side surface of the waveguide core layer and an upper surface of the slab layer;
Forming a second semiconductor layer via the insulating layer on the side of the waveguide core layer and above the slab layer so as to be optically connected to the waveguide core layer;
Only including,
One of the slab layers on both sides of the waveguide core layer has a p-type region, and the other has an n-type region .

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