JP5707964B2 - Latch circuit and data holding circuit - Google Patents

Description

  The present invention relates to a latch circuit and a data holding circuit.

  Circuits called latch circuits, flip-flops or data holding circuits that take in and hold input data in synchronization with a clock are widely used. Here, in order to simplify the description, one portion that holds input data is called a latch circuit, and two or more portions that hold input data are called data holding circuits.

  In recent years, in addition to a hard error in which a specific portion of a circuit is permanently destroyed, a transient soft error that can be reproduced in a normal state has been attracting attention, although a malfunction occurs randomly in a semiconductor chip. Soft errors are considered to occur due to the incidence of secondary cosmic rays such as neutrons and alpha rays from LSI materials.

  A soft error occurs in each part of the circuit, but even if a soft error occurs in the gate circuit, if the input of the gate circuit does not change, the output of the gate circuit immediately returns to the original value, so the influence is small. On the other hand, when the input data of the latch circuit or data holding circuit is captured (latched) by these circuits, if an error occurs in the input data due to a soft error, incorrect data is captured and retained. become. Since the data held in the latch circuit or the data holding circuit is not restored to the correct data and is output to the subsequent circuit, the influence of the error is increased. This is the same when a soft error occurs in the latch circuit or the data holding circuit and the held data changes.

  Therefore, generally, measures are taken to prevent the input data of the latch circuit or data holding circuit and the data held in the latch circuit or data holding circuit from being changed by a soft error.

  FIG. 1 is a diagram for explaining the operation of a data holding circuit having a master / slave type latch.

  As shown in FIG. 1A, the data holding circuit 10 includes a master latch 11 and a slave latch 12, captures and holds input data Din from the combinational circuit 1, and outputs output data Dout. . The master latch 11 operates in synchronization with CLK, takes in input data when CLK is “low (L)”, and receives data when CLK changes from L to “high (H)” while CLK is H. Hold and output to the slave latch 12. The slave latch 12 operates in synchronization with a reverse phase clock XCLK having a phase opposite to that of CLK. When XCLK is L, the slave latch 12 takes in data from the master latch 11, and when XCLK changes from L to H, XCLK is H And output as output Dout.

  Consider a case where CLK and XCLK change while Din is at L as shown in FIG. The master latch 11 takes in Din which is L when CLK changes from L to H and holds it while CLK is H. The slave latch 12 takes in the output data of the master latch 11 which is L when XCLK changes from L to H, that is, when CLK changes from H to L, and holds while XCLK is H, that is, CLK is L To do. Even if an error occurs in the input data Din due to a soft error in the combinational circuit 1 during a period other than when the CLK changes from L to H, the correct data is obtained before it is captured (latched) by the data holding circuit 10. No error is propagated when returning. However, as shown by the broken line in FIG. 1B, when an error occurs in the input data Din when CLK changes from L to H, the erroneous input data is taken into the data holding circuit 10 (latched). ), Incorrect output data Dout is output.

  Currently, various countermeasures against soft errors are being considered. One of the measures widely used is to detect that an error has occurred by a parity check or the like and execute a necessary measure, for example, to correct the error. For example, an error correction code (ECC) circuit can correct errors relatively easily. Thereby, even if an error occurs, the system is not affected. However, this measure requires an increase in the number of data bits, which causes problems such as a significant increase in circuit scale.

  Another countermeasure is a method that focuses on the fact that a soft error occurs in a limited range, and an error generated in the combinational circuit returns to a normal state in a short time.

  However, the proposed countermeasures have problems such as a slow response time due to the use of a delay element, and a large circuit that realizes the delay element increases the circuit size.

Japanese Patent Laid-Open No. 10-335992 JP 2009-130441 A JP 2007-312104 A

  According to the embodiment, a latch circuit and a data holding circuit that can be realized with a relatively small reduction in response speed and a small circuit size are realized.

  According to a first aspect of the present invention, there is provided a latch circuit that captures and holds input data according to a clock, and includes a transfer gate that allows the input data to pass according to the clock, and an even number of four or more. A series of inverters connected in series to form a loop, and a loop-shaped inverter array in which the first-stage input and the final-stage output are connected to the output of the transfer gate, and four or more of the loop-shaped inverter arrays A latch circuit is provided in which the driving force of the inverter is greater as it is further downstream than the previous stage.

  According to a second aspect of the present invention, a first latch path that captures and holds input data, a second latch path that captures and holds input data, an output of the first latch path, and an output of the second latch path, An output unit that changes output only when both the output of the first latch path and the output of the second latch path change. The first latch path and the second latch path each include a master latch and a slave latch, respectively. As the master latch of the latch path and the second latch path, a data holding circuit having the latch circuit according to the first aspect of the present invention is provided.

  According to the third aspect of the present invention, a master latch that captures and holds input data in synchronization with a clock, and a slave latch that captures and holds master data output from the master latch in synchronization with a reverse phase clock having the clock inverted. A master / slave type data holding circuit including the latch circuit according to the first aspect of the present invention is provided.

  According to the embodiment, a latch circuit and a data holding circuit that can be realized with a relatively small reduction in response speed and a small circuit size are realized.

FIG. 1 is a diagram for explaining the operation of a data holding circuit having a master / slave type latch. FIG. 2 is a diagram illustrating a countermeasure example when a soft error occurs in input data input to the data holding circuit. FIG. 3 is a diagram showing an example of a data holding circuit in which measures are taken to prevent malfunction when a soft error in input data and a soft error in held data occur. FIG. 4 is a diagram illustrating a configuration of the latch circuit according to the first embodiment. FIG. 5 is a diagram showing a data holding circuit of the second embodiment in which the latch circuit of the first embodiment shown in FIG. 4 is applied to a master / slave type data holding circuit. FIG. 6 is a diagram showing simulation results comparing the delay time, power consumption (power) at the time of 1 GHz operation, and circuit area between the data holding circuit using the delay element and the data holding circuit of the second embodiment. FIG. 7 is a diagram illustrating another circuit example in which the latch circuit of the first embodiment is used in a master / slave type data holding circuit.

  Before describing the embodiment, a basic configuration for soft error countermeasures in the data holding circuit will be described.

  FIG. 2 is a diagram illustrating a countermeasure example when a soft error occurs in input data input to the data holding circuit.

  As shown in FIG. 2A, the input data Din is output from the inverter 2 that forms the output section of the combinational circuit. A delay element (τ) 13 and a C element circuit 14 are provided before the data holding circuit 10. The delay element (τ) 13 delays Din by the delay time Td. The C element circuit 14 is connected in series between a high potential power supply (Vdd) and a low potential power supply (GND), and has two P-channel transistors and two N-channel transistors. Of the four transistors, Din is supplied to the gates of the outer P-channel transistor and N-channel transistor, and the output of the delay element 13 is supplied to the gates of the inner P-channel transistor and N-channel transistor. Here, the output of the delay element 13 is represented by A and Din is represented by B. An output Q is obtained from a connection node between the inner P-channel transistor and the N-channel transistor.

  As shown in FIG. 2C, the output Q of the C element circuit 14 is “1” (H) when both A and B are “0” (L), and both A and B are “1”. "0" when "", and when A and B are different values, the previous value is maintained.

  As shown in FIG. 2B, when the input data Din from the combinational circuit is “0” (L), a soft error occurs and a pulse that temporarily changes to “1” (H) is generated. In this case, a pulse of “1” (H) is generated between A and B with a time difference Td. When the time difference Td is larger than the pulse width, both A and B never become “1” (H), so that Q maintains the state of “1” (H). In other words, incorrect input data is not input to the data holding circuit 10. This is the same when the force data Din is “1” (H).

  FIG. 3 is a diagram showing an example of a data holding circuit in which measures are taken to prevent malfunction when a soft error in input data and a soft error in held data occur.

  As shown in FIG. 3A, this data holding circuit is of a master / slave type, and each of the preceding master latch and the succeeding slave latch has two latch paths. The master latch has an inverter IV1 that inverts input data Din, a first latch path, a second latch path, a C element circuit 22 shown in FIG. The first latch path includes a delay element (τ) 21 that delays the output of the inverter IV1, a transfer gate MTGA, and two inverters MIA1 and MIA2 connected in a loop. The second latch path has a transfer gate MTGB and two inverters MIB1 and MIB2 connected in a loop.

  The slave latch includes a first latch path, a second latch path, a C element circuit 24, and a keeper circuit 25. The first latch path has a transfer gate STGA and two inverters SIA1 and SIA2 connected in a loop. The second latch path has a transfer gate STGB and two inverters SIB1 and SIB2 connected in a loop.

  FIG. 3B shows a circuit configuration of keeper circuits 23 and 25. Keeper circuits 23 and 25 are circuits in which two inverters are connected in a loop, and act so as to stably maintain the state of the connected nodes.

  In the first latch path of the master latch, the output of the inverter IV1 is delayed by the delay element 21 and then input to the transfer gate MTGA. The output of the transfer gate MTGA is input to the inverter MIA1. The output of the inverter MIA1 is input to the inverter MIA2 and also input to the C element circuit 22. The output of the inverter MIA2 is input to the inverter MIA1. The two inverters MIA1 and MIA2 form a flip-flop. The state of the transfer gate MTGA changes in synchronization with the clock CLK. The transfer gate MTGA is in the passing state when CLK is L, and is in the cutoff state when CLK is H. The inverter MIA2 performs an operation of inverting the input, changes its state in synchronization with the clock CLK, changes to an output when the CLK is L, and holds an output when the CLK is H. .

  In the first latch path of the master latch, when CLK is L, the delayed inverted input data passes through the transfer gate MTGA and is input to the inverter MIA1. Further, the output of the inverter MIA1 is inverted by the inverter MIA2 in the operating state and input to the inverter MIA1, and the input data is held in the flip-flop formed by the inverter MIA1 and the inverter MIA2. When CLK changes from L to H, the transfer gate MTGA enters a cut-off state, and the output of the inverter MIA2 does not change. Therefore, the first path maintains the state when CLK changes from L to H. It will be. In other words, the first latch path takes in the input data Din delayed in synchronization with the change of CLK from L to H, and holds the fetched data.

  The second latch path of the master latch performs the same operation as the first latch path except that the output of the inverter IV1 is input without being delayed.

  When no soft error occurs in the input data Din, the same normal input data is captured and held in the first latch path and the second latch path of the master latch. Since there is a time delay in the input data captured by the first latch path and the second latch path, even if a soft error occurs in the input data Din and the pulsed erroneous data is generated, The latch path and the second latch path are not taken in. Specifically, if the pulse width of erroneous data in the input data Din is shorter than the delay time of the delay element 21, the same erroneous data is captured and held in both the first latch path and the second latch path of the master latch. It will never be done. As described above, the output of the C element circuit 22 changes only when the two inputs are the same, and maintains the previous output when the two inputs are different. Since both the data held in the first latch path and the second latch path of the master latch do not become erroneous data, even when a soft error occurs in the input data Din, the output of the C element circuit 22 becomes erroneous data. Don't be.

  Further, even if a soft error occurs in one of the first latch path and the second latch path of the master latch and the data held in one of them is changed to incorrect data, the data is held in the first latch path and the second latch path. Data is different. Therefore, the output of the C element circuit 22 does not change and does not become erroneous data.

  The first and second latch paths of the slave latch perform the same operation as the second latch path of the master latch except that the output of the C element circuit 22 is input and operates in synchronization with XCLK.

  As described above, since the C element circuit 22 of the master latch does not output erroneous data due to a soft error, it is not necessary to provide the delay element 21 unlike the first latch path of the master latch. Further, even when a soft error occurs in one of the first latch path and the second latch path of the slave latch and the data held in one of the slave latches is changed to incorrect data, the first latch path and the second latch path are also changed. The stored data is in a different state. Therefore, the output of the C element circuit 22 does not change and does not become erroneous data.

  As described above, the data holding circuit of FIG. 3 generates a soft error in the data held by the data holding circuit even if the input data becomes temporarily erroneous (in the form of a pulse) due to a soft error. However, it does not output incorrect data.

  Both the data holding circuits shown in FIGS. 2 and 3 use delay elements. The delay element is realized by, for example, a capacitive element, a resistor, and an inverter. However, there is a problem that the circuit size is generally increased. In addition, since a delay element is used, there is a problem that a response time until an output is obtained becomes long and it is difficult to realize a high-speed data holding circuit.

  The latch circuit and data holding circuit of the embodiments described below can be realized with a relatively small circuit size, have a relatively short response time, and can operate at high speed.

  FIG. 4 is a diagram illustrating a configuration of the latch circuit according to the first embodiment.

  As shown in FIG. 4, the latch circuit according to the first embodiment includes an inverter IV10, a transfer gate TG, four inverters IV11-IV14 connected in a loop, and an inverter IV15. The driving force (drive capability) of the inverters IV11 to IV14 becomes larger as it becomes later than the previous stage. In other words, the driving force of the inverter IV11 <the driving force of the inverter IV12 <the driving force of the inverter IV13 <the driving force of the inverter IV14. The driving force varies depending on the gate width of the transistor.

  The inverter IV10 inverts the input data Din and outputs it to the transfer gate TG. The output of transfer gate TG is input to inverters IV11 and IV15. The output of the inverter IV15 is output data Dout. Note that the output of the inverter IV11 can be used as the output data Dout without providing the inverter IV15.

  Since the four inverters IV11 to IV14 are connected in a loop, a flip-flop is formed. The state of the transfer gate TG changes in synchronization with the clock CLK, and is in a passing state when CLK is L and is in a blocking state when CLK is H. The inverter IV14 performs an operation of inverting the input, changes its state in synchronization with the clock CLK, changes to an output when the CLK is L, and holds an output when the CLK is H. .

  In the latch circuit of the first embodiment, when CLK is L, the inverted input data passes through the transfer gate TG and is input to the inverters IV11 and IV15. Further, the output of the inverter IV11 is transmitted in the order of the inverters IV12 and IV13 and the inverter IV14 in the operating state, and the output of the inverter IV14 is fed back to the input of the inverter IV11. Since the output of the inverter IV14 is fed back to the input of the inverter IV11, a signal that passes through the transfer gate TG and is input to the inverter IV11 has a certain level to change the state of the flip-flop formed by the four inverters. It takes time. In particular, since not only the inverted input data that has passed through the transfer gate TG but also the output of the inverter IV14 having a large driving force is applied to the input of the inverter IV11, a certain amount of time is required. Thus, the input data Din is held in the flip-flop formed by the four inverters after a certain amount of time has elapsed.

  When CLK changes from L to H, the transfer gate TG enters a cut-off state, and the outputs of the inverters IV11 and IV14 do not change. Therefore, the flip-flop maintains the state when CLK changes from L to H. Will do.

  As described above, the latch circuit of the first embodiment does not change the held data unless the state in which the input data Din has changed continues for a certain period of time. If the input data Din becomes temporarily wrong (in the form of a pulse) due to a soft error, the pulse width is narrow and the data held in the flip-flop formed by the four inverters cannot be changed. It does not hold incorrect input data due to errors. As described above, the latch circuit according to the first embodiment is not easily affected by the soft error of the input data Din.

  Next, consider a case where a pulse-like change due to a soft error occurs in any of the four inverters IV11 to IV14 in the latch circuit. As described above, since the erroneous data pulse width due to the soft error is small, the state of the flip-flop formed by the four inverters cannot be changed. For example, when a pulse-like change occurs due to a soft error in a previous inverter having a small driving force (for example, the inverter IV11), it is necessary to change the state of the inverters IV12, IV13, and IV14 in order, which requires a certain amount of time. It is. Therefore, the flip-flop state cannot be changed with erroneous data due to a soft error with a small pulse width. Further, when a pulse-like change due to a soft error occurs in a subsequent inverter having a large driving force (for example, the inverter IV14), the state of the flip-flop can be changed if the output of the inverter changes. However, the fact that the driving force of the inverter is large requires that the input of the inverter is also correspondingly large, and the state of the inverter having a large driving force cannot be changed in the first place. As described above, the latch circuit according to the first embodiment is not easily affected by the soft error of the stored data.

  As described above, the latch circuit of the first embodiment is not easily affected by the soft error. Further, since no delay element is used unlike the circuits of FIGS. 2 and 3, the circuit size can be reduced.

  The latch circuit of the first embodiment shown in FIG. 4 can be applied to various data holding circuits.

  FIG. 5 is a diagram showing a data holding circuit of the second embodiment in which the latch circuit of the first embodiment shown in FIG. 4 is applied to a master / slave type data holding circuit.

  The data holding circuit of the second embodiment includes an inverter IV1 that inverts input data Din, a first master / slave path, a second master / slave path, a C element circuit 31, a keeper circuit 32, and an inverter IV22. Have. The first master / slave path and the second master / slave path have the same configuration. The C element circuit 31 has the same configuration as that of the circuit 14 shown in FIG. 2, receives the outputs of the first master / slave path and the second master / slave path, and performs the corresponding output when both are the same. Keep previous output. The inverter IV22 inverts the output of the C element circuit 31 and outputs it as output data Dout. The keeper circuit 32 has the configuration shown in FIG. 3B and stably holds the output of the C element circuit 31.

  The first master / slave path includes a master latch and a slave latch. The master latch is substantially the same circuit as the latch circuit of the first embodiment shown in FIG. 4, except that an output is obtained from the first-stage inverter MIVA1 forming a flip-flop. The slave latch is substantially the same circuit as the slave latch shown in FIG. 3A, except that a clock synchronous inverter IGA is used instead of the transfer gate. The operation and characteristics of the master latch are substantially the same as those of the latch circuit of the first embodiment shown in FIG. 4, and the operation and characteristics of the slave latch are substantially the same as the example shown in FIG. Description is omitted.

  In the data holding circuit of the second embodiment, the master latches of the first and second master / slave paths are not easily affected by the soft error of the input data Din and are held similarly to the latch circuit of the first embodiment. Less susceptible to data soft errors. In the slave latches of the first and second master / slave paths, the stored data may change due to a soft error. However, since the C element circuit 31 is provided, erroneous data due to the soft error is generated. Is not output.

  6 shows the delay time, power consumption (power) and circuit area of the data holding circuit using the delay element of FIG. 3A and the data holding circuit of the second embodiment of FIG. A simulation result comparing the data holding circuit of FIG. In the data holding circuit of the second embodiment, the delay time and power are improved by 7 to 8%, and the area is improved by 18%.

  FIG. 7 is a diagram showing another circuit example in which the latch circuit of the first embodiment shown in FIG. 4 is used in a master / slave type data holding circuit.

  FIG. 7A shows an example in which the latch circuit of the first embodiment shown in FIG. 4 is used as a master latch of a general master / slave type data holding circuit.

  FIG. 7B shows an example in which the latch circuit of the first embodiment shown in FIG. 4 is used for both a master latch and a slave latch of a general master / slave type data holding circuit.

  Since the configuration, operation, and characteristics of the circuit shown in FIGS. 7A and 7B are clear from the above description, detailed description thereof is omitted.

  Although the embodiment has been described above, the number of inverters connected in a loop forming a flip-flop needs to be an even number, but may be four or more.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

DESCRIPTION OF SYMBOLS 1 Combination circuit 10 Data holding circuit 11 Master latch 12 Slave latch 31 C element circuit 32 Keeper circuit Din Input data TG Transfer gate IV11-IV15 Inverter

Claims (5)

A latch circuit that captures and holds input data according to a clock,
A transfer gate for passing the input data in response to the clock;
An even number of four or more inverters connected in series so as to form a loop, and a loop-like inverter array in which the input of the first stage and the output of the final stage are connected to the output of the transfer gate,
A latch circuit characterized in that the driving force of four or more inverters in the loop-shaped inverter array becomes larger as it goes to the subsequent stage. A first latch path for capturing and holding input data;
A second latch path for capturing and holding the input data;
An output unit that receives the output of the first latch path and the output of the second latch path, and the output changes only when both the output of the first latch path and the output of the second latch path change,
Each of the first latch path and the second latch path includes a master latch and a slave latch,
The data holding circuit according to claim 1, wherein the master latch of the first latch path and the second latch path includes the latch circuit according to claim 1. The output unit is
It has four transistors connected in series between a high potential power supply and a low potential power supply,
One of the output of the first latch path and the output of the second latch path is connected to the gates of the two inner transistors, and the gates of the two transistors on both sides of the four transistors connected in series. 3. The data holding circuit according to claim 2, wherein the other of the output of one latch path and the output of the second latch path is supplied. A master latch that captures and holds input data in synchronization with the clock;
A master / slave type data holding circuit comprising: a slave latch that captures and holds master data output from the master latch in synchronization with a reverse phase clock obtained by inverting the clock;
2. A master / slave type data holding circuit comprising the latch circuit according to claim 1.   5. The master / slave type data holding circuit according to claim 4, wherein the slave latch is the latch circuit according to claim 1.

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