JP6095466B2 - Delay difference detection circuit, semiconductor device, and delay difference detection method for semiconductor device - Google Patents

Description

  The embodiments referred to in this specification relate to a delay difference detection circuit, a semiconductor device, and a delay difference detection method for a semiconductor device.

  In recent years, semiconductor devices (chip: LSI) with macros are widely used, and timing constraints such as setup time and hold time are defined so that the macro can correctly capture the data at the time of input and generate an output signal. Has been.

  The input data is required to be stable between the minimum time before the clock edge (setup time) and the minimum time after the clock edge (hold time).

  That is, if the timing constraint is not defined, not only unstable data before and after the clock edge will be captured, but also the metastable in which the output is an intermediate level between the high level “H” and the low level “L”. Will occur.

  By the way, conventionally, various proposals have been made as techniques for detecting signal timing errors in semiconductor devices.

JP 2007-116435 A JP 2006-244556 A JP 2008-256491 A

  As described above, for example, in a chip equipped with a macro, timing constraints such as a setup time and a hold time are defined so that the macro can correctly capture data at the time of input and generate an output signal.

  Here, for example, the timing of data and clock for a macro cannot be measured directly, and the delay of data and clock is not equal from the terminal of the chip (pad) to the input of the macro. Is getting harder.

  Timing constraints such as the setup time and hold time described above have become important as the degree of integration of the chip improves and the clock speed increases.

  According to an embodiment, there is provided a delay difference detection circuit that measures a delay difference between a first signal and a second signal, and includes a first unit and a second unit.

  The first unit changes in accordance with a first logic signal of positive or negative logic in the first signal and a first logic signal of positive or negative in the second signal. Output the output. The second unit outputs a third logic signal opposite in logic to the first logic signal and a second output that changes in accordance with a fourth logic signal in opposite logic to the second logic signal.

  While sweeping the second signal, a first change point where the output of the first unit changes and a second change point where the output of the second unit changes are measured. A delay difference between the first signal and the second signal is obtained by obtaining an intermediate value between the measured first change point and the second change point.

  The disclosed delay difference detection circuit, semiconductor device, and delay difference detection method for a semiconductor device have an effect that a delay difference between two signals can be accurately measured.

FIG. 1 is a diagram for explaining a signal delay difference in a semiconductor device. FIG. 2 is a diagram for explaining an example of a delay difference detection method for a semiconductor device. FIG. 3 is a circuit diagram showing a D-type flip-flop applied to an example of the delay difference detection method of the semiconductor device shown in FIG. FIG. 4 is a diagram for explaining the operation of the D-type flip-flop shown in FIG. FIG. 5 is a diagram for explaining another example of the delay difference detection method of the semiconductor device. FIG. 6 is a diagram for explaining a problem in the delay difference detection method for the semiconductor device shown in FIG. FIG. 7 is a diagram for explaining a problem in a modification of the delay difference detection method for the semiconductor device shown in FIG. FIG. 8 is a circuit diagram showing a delay difference detection circuit in the semiconductor device according to the first embodiment. FIG. 9 is a diagram (part 1) for explaining the operation of the semiconductor device illustrated in FIG. FIG. 10 is a diagram (No. 2) for explaining the operation of the semiconductor device illustrated in FIG. FIG. 11 is a view (No. 3) for explaining the operation of the semiconductor device shown in FIG. FIG. 12 is a diagram for explaining the delay difference detection method of the semiconductor device according to the first example. FIG. 13 is a circuit diagram showing a delay difference detection circuit in the semiconductor device according to the second embodiment. FIG. 14 is a diagram (part 1) for explaining the operation of the semiconductor device illustrated in FIG. FIG. 15 is a diagram (part 2) for explaining the operation of the semiconductor device illustrated in FIG. FIG. 16 is a view (No. 3) for explaining the operation of the semiconductor device shown in FIG. FIG. 17 is a diagram for explaining a delay difference detection method for a semiconductor device according to the second embodiment.

  First, before describing embodiments of a delay difference detection circuit, a semiconductor device, and a delay difference detection method for a semiconductor device in detail, an example of a delay difference detection method for a semiconductor device and its problems will be described with reference to FIGS. explain.

  FIG. 1 is a diagram for explaining a delay difference between signals in a semiconductor device. FIG. 1A is a block diagram illustrating an example of a chip (semiconductor device) on which a macro is mounted. FIG. These are timing charts for explaining signal delay of the chip shown in FIG.

  1 (a) and 1 (b), reference numeral 1 is a chip, 2 is a macro, Cdin is input data of chip 1, Cclk is an input clock of chip 1, Mdin is input data of macro 2, and Mclk Indicates a macro 2 input clock.

  Dd represents the delay (data delay) from the data input of chip 1 to the data input of macro 2, and Dclk represents the delay (clock delay) from the clock input of chip 1 to the clock input of macro 2. Show.

  As shown in FIG. 1 (a), for example, various macros 2 (only one macro is shown in FIG. 1 (a) for simplification of description) are arranged (mounted) on the chip 1. Has been.

  In such a macro 2, since it is difficult to directly measure the setup time (hold time) of the input data Mdin with respect to the input clock Mclk, the delay time from the pad (terminal) of the chip 1 to the input of the macro 2 is set. Measuring is done.

That is, as shown in FIG. 1B, for example, when the setup time Tsum of the macro 2 and the setup time of the chip 1 are Tsuc, the following [Equation 1] holds.
Tsuc + Dclk = Dd + Tsum ... [Formula 1]

Therefore, the setup time Tsum of the macro 2 can be obtained by the following [Equation 2].
Tsum = Tsuc + Dclk−Dd …… [Formula 2]

  That is, Tsum measures the data delay Dd from the data input of chip 1 to the data input of macro 2, the clock delay Dclk from the clock input of chip 1 to the clock input of macro 2, and the setup time Tsuc of chip 1. Can be obtained.

  Here, the setup time Tsuc of the chip 1 can be measured by applying the clock CLK and the input data Din from the pad of the chip 1. Note that the data delay Dd and the clock delay Dclk (the delay difference between Dclk and Dd) can be obtained by, for example, the delay difference detection circuit of FIG.

  2 is a diagram for explaining an example of a delay difference detection method of the semiconductor device, and FIG. 2A is a block diagram showing a chip on which the macro 2 and the delay difference detection circuit 3 are mounted. FIG. 2B is a timing diagram for explaining signal delay of the chip shown in FIG.

  In FIG. 2 (a), reference numeral 3 denotes a delay difference detection circuit (D flip-flop (DFF)). In FIG. 2 (a), only one macro is shown to simplify the description, but it goes without saying that a plurality of macros are mounted on the chip 1.

  As shown in FIG. 2A, the chip 1 is provided with a DFF (delay difference detection circuit) 3 for measuring the delay difference between the data delay Dd and the clock delay Dclk. That is, the input data Cdin of the chip 1 is input to the data input of the DFF3, the input clock CClk of the chip 1 is input to the clock input of the DFF3, and the output (Q) of the DFF3 is extracted outside the chip 1. It is supposed to be.

  Here, for example, the distance between the data input of DFF3 and the data input of macro 2 and the distance between the clock input of DFF3 and the clock input of macro 2 are made substantially equal, and even if there is a delay between them, it cancels out. Thus, the delay difference between Dd and Dclk can be accurately detected.

  As shown in FIG. 2B, for example, the rising timing of the input data Cdin is temporally changed (swept), the DFF3 takes in the transition of the input data Cdin with the input clock CClk, and the rising timing of the output Q Is measured outside the chip 1.

  By measuring the rising edge (transition) of the input data Cdin, the input clock CClk and the output Q, the delay difference between the data delay Dd and the clock delay Dclk can be obtained.

  FIG. 3 is a circuit diagram showing a D-type flip-flop applied to an example of the delay difference detection method of the semiconductor device shown in FIG. 2, and a general D-type flip-flop used to capture (capture) a signal. (DFF3) is shown.

  As shown in FIG. 3, the DFF 3 includes inverters 301 to 307, p-channel MOS (pMOS) transistors 311 to 314, and n-channel MOS (nMOS) transistors 321 to 324.

  Here, the transistors 311 and 321 and the inverter 302, and the transistors 313 and 323 and the inverter 305 function as transfer gates, respectively. Inverters 303 and 304 and inverters 306 and 307 whose inputs and outputs are cross-connected function as latches, respectively.

  The transistors 311 and 321 and the transistors 313 and 323 are turned on / off by the clock CLK to control the operation of the transfer gate. In addition, the transistors 312 and 322 and the transistors 314 and 324 are turned on / off by the clock CLK to control the operation of the latch.

  The inverters 302, 303, 305 and 306 are connected in series. Data Din is input to the input of the first-stage inverter 302, and the output Q of the DFF 3 is extracted from the final-stage inverter 306.

  The transfer gates 302, 311 and 321 and the latches 306, 307, 314 and 324 are in an operating state (turned on) when the clock CLK is at a low level “L”, and are not operating when the clock CLK is at a high level “H”. It becomes a state (turns off).

  Conversely, the transfer gates 305, 313, and 323 and the latches 303, 304, 312, and 322 are turned off when the clock CLK is “L” and turned on when the clock CLK is “H”.

  FIG. 4 is a diagram for explaining the operation of the D-type flip-flop shown in FIG. Here, FIG. 4A is a timing chart showing a case where the change of the data Din (change from “L” to “H”) is sufficiently faster than the change of the clock CLK.

  Further, FIG. 4B is a timing diagram showing a case where the change of the data Din is close to the change of the clock CLK, and FIG. 4C is a case where the change of the data Din is sufficiently larger than the change of the clock CLK. It is a timing diagram which shows a case where it is late.

  First, as shown in FIG. 4A, when the change of the data Din is sufficiently faster than the change of the clock CLK, the DFF 3 changes the data CLK from “L” to “H”. And output Q that changes from “L” to “H”.

  Next, as shown in FIG. 4C, when the change in the data Din is sufficiently slower than the change in the clock CLK, the DFF 3 captures “L” of the data Din at the rising timing of the clock CLK. The output Q remains at “L”.

  On the other hand, as shown in FIG. 4B, the change in the data Din is close to the change in the clock CLK, and immediately after the data Din changes from “L” to “H”, the clock CLK changes from “L” to “H”. The DFF 3 outputs an output Q that rises to “H” for a moment and returns to “L” for a moment.

  That is, when the edge (rising edge) of the clock CLK and the transition (rising edge) of the data Din are almost the same time, the fetch timing by the latch and the data transfer timing by the transfer gate are almost equal, and a metastable state is temporarily generated. .

  In this metastable state, the latch may be determined in an unintended direction (level) due to a difference in charge supply capability between the latch and the transfer gate. As a result, the output Q of the DFF 3 cannot correctly reflect the order of transition between the edge of the clock CLK and the data Din, and it is difficult to accurately obtain the delay difference between the data delay Dd and the clock delay Dclk.

  FIG. 5 is a diagram for explaining another example of the delay difference detection method of the semiconductor device. Another example of the delay difference detection circuit 3, that is, the data Din without using the DFF (D type flip-flop). The transition of the clock CLK is detected by an RS flip-flop. Here, FIG. 5A is a circuit diagram showing another example of the delay difference detection circuit 3, and FIGS. 5B and 5C show the delay difference detection circuit 3 of FIG. 5A. It is a timing diagram for demonstrating operation | movement in FIG.

  As shown in FIG. 5A, another example of the delay difference detection circuit 3 includes an inverter 308 and NAND gates 331 to 333. The data Din is input to one input of the NAND gate 331 via the inverter 308, and the clock CLK is input to the other input of the NAND gate 331.

  The output (node n1) of the NAND gate 331 is input to one input of the NAND gate 332, and the output (Q) of the NAND gate 332 is taken out of the chip 1 as the output Q of the delay difference detection circuit 3, and Input to one input of the NAND gate 333.

  The output of the NAND gate 333 is input to the other input of the NAND gate 332, and these NAND gates 332 and 333 function as a latch. Note that the reset signal RSTX is input to the other input of the NAND gate 333, and the output Q held by the latches (332, 333) is reset.

  The circuit shown in FIG. 5A described above can detect the rising timing (time) of the data Din relative to the rising edge of the clock CLK without using a DFF.

  That is, as shown in FIG. 5B, when the rising transition of the data Din is earlier than the rising timing of the clock CLK, the node n1 maintains “H” and the output Q maintains “L”.

  On the other hand, as shown in FIG. 5 (c), when the rising transition of the data Din is later than the rising timing of the clock CLK, the node n1 has a pulse that changes to “L” corresponding to the timing difference therebetween. Occur. In FIGS. 5B and 5C, the reset signal RSTX is “H”.

  That is, the delay difference detection circuit shown in FIG. 5 (a) depends on whether or not a pulse changing to “L” is generated at the node n1, as shown in FIGS. 5 (b) and 5 (c). The rising timing of the data Din and the clock CLK is determined.

  However, when the transition times of the data Din and the clock CLK are substantially equal, the width of the pulse generated at the node n1 becomes very narrow, and the pulse may not be detected and reflected in the output Q.

  FIG. 6 is a diagram for explaining a problem in the delay difference detection method for the semiconductor device shown in FIG. Here, FIG. 6 (a) is the same circuit diagram as FIG. 5 (a) described above, and FIG. 6 (b) shows the transition time of the data Din and the clock CLK in FIG. It is a timing diagram in the case where they are equal (rising edge of Din is slightly later than the clock CLK).

  As shown in FIG. 6B, when the rising transition of the data Din with respect to the rising edge of the clock CLK is slightly later than the rising edge transition of the clock CLK, the output node n1 of the NAND gate 331 instantly changes from “H” to “L”. Outputs a very narrow pulse that changes.

  However, the pulse that instantaneously changes from “H” to “L” at the node n1 cannot be detected by, for example, the latch (NAND gate 332) in the subsequent stage, and the output Q is a broken line in FIG. The “L” is maintained as shown by the solid line. That is, there is a dead zone.

  FIG. 7 is a diagram for explaining a problem in the modification of the delay difference detection method for the semiconductor device shown in FIG. 5, and FIG. 7 (a) shows a circuit diagram of the delay difference detection circuit 3 of this modification. FIG. 7B is a timing chart for explaining the operation of the delay difference detection circuit shown in FIG.

  As is clear from the comparison between FIG. 7A and FIG. 5A (FIG. 6A) described above, in this modification, the inverter 308 provided at one input of the NAND gate 331 is deleted, and the input The data Din is directly input to one input of the NAND gate 331.

  That is, as shown in FIG. 7B, when the falling transition of the data Din is later than the rising timing of the clock CLK, the circuit shown in FIG. Is generated at the node n1.

  However, also in the delay difference detection circuit 3 shown in FIG. 7A, the pulse that changes from “H” to “L” for an instant at the node n1 cannot be detected by, for example, a latch in the subsequent stage, and is output. Q does not change as shown by a broken line in FIG. 7B, but maintains “L” as shown by a solid line. That is, there is a dead zone.

  Note that the problem of the metastable state and the dead zone is not limited to the circuit described above, but also exists in various circuits (delay difference detection circuit).

  Hereinafter, a delay difference detection circuit, a semiconductor device, and a delay difference detection method for a semiconductor device according to the present embodiment will be described in detail with reference to the accompanying drawings. FIG. 8 is a circuit diagram showing a delay difference detection circuit in the semiconductor device according to the first embodiment.

  Note that the entire semiconductor device (chip) 1 is formed by, for example, the macro 2 and the delay difference detection circuit 3 as in the above-described FIG. Needless to say, a plurality of macros are mounted on the chip 1.

  As shown in FIG. 8, the delay difference detection circuit 3 includes inverters (inverted logic elements) 31 and 32 and NAND gates 33 to 38. Here, the delay difference detection circuit 3 includes two units 3a and 3b. The first unit 3a includes an inverter 31 and NAND gates 33 to 35, and the second unit 3b includes an inverter 32 and NAND gates 36 to 36. 38.

  The clock (first signal) CLK input to the pad Pclk of the chip 1 is input to the other input of the NAND gate 33, and the data (second signal) Din input to the pad Pdin of the chip 1 passes through the inverter 31. To one input of the NAND gate 33.

  The output (node N3) of the NAND gate 33 is input to one input of the NAND gate 34. The output of the NAND gate 34 is taken out of the chip 1 as the first output Q1 of the delay difference detection circuit 3, and the NAND gate 34 The signal is input to one input of the gate 35. The first output Q1 is taken out from the pad Pq1 of the chip 1 to the outside.

  The output of the NAND gate 35 is input to the other input of the NAND gate 34, and these NAND gates 34 and 35 function as a latch. A reset signal RSTX is input to the other input of the NAND gate 35, and the first output Q1 held by the latches (34, 35) is reset. That is, for example, the reset signal RSTX resets the data held in the latch every time the rising timing of the data Din changes (sweep) with time.

  The data Din input to the pad Pdin is directly input to one input of the NAND gate 36, and the clock CLK input to the pad Pclk is input to the other input of the NAND gate 36 via the inverter 32. .

  The output (node N4) of the NAND gate 36 is input to one input of the NAND gate 37, and the output of the NAND gate 37 is taken out of the chip 1 as the second output Q2 of the delay difference detection circuit 3, and the NAND gate 37 The signal is input to one input of the gate 38. The second output Q2 is taken out from the pad Pq2 of the chip 1 to the outside.

  The output of the NAND gate 38 is input to the other input of the NAND gate 37, and these NAND gates 37 and 38 function as a latch. Note that the reset signal RSTX is input to the other input of the NAND gate 38, and the second output Q2 held by the latches (37, 38) is reset. That is, the reset signal RSTX resets the data held in the latch every time the rising timing of the data Din is swept, for example.

  By applying the delay difference detection circuit 3 shown in FIG. 8 described above, for example, the influence of the dead zone described with reference to FIGS. 5 and 6 is canceled, and the delay difference between the data Din and the clock CLK is more accurately determined. It becomes possible to measure.

  For example, a point at which the first output Q1 changes from pass to fail and a point at which the second output Q2 changes from pass to fail are read, and an intermediate value between the two is defined as a measured value.

  Here, the pass is a case where the first and second outputs Q1 and Q2 output to the pads Pq1 and Pq2 of the chip 1 become a high level “H” (expected value). In this case, the first and second outputs Q1 and Q2 are at the low level “L”.

  Although FIG. 8 shows an example in which the NAND gates 33 to 38 are applied, it goes without saying that, for example, the NAND gate can be replaced with a NOR gate. Furthermore, if the first unit 3a and the second unit 3b have the same circuit configuration, various modifications can be made.

  9 to 11 are diagrams for explaining the operation of the semiconductor device shown in FIG. First, in FIGS. 8 and 9, the difference between the time at which the clock CLK input from the outside to the pad Pclk of the chip 1 transitions and the time at which the data Din input from the outside to the pad Pdin of the chip 1 transitions is t0. .

  Assume that the delay time of signal inversion by the inverter 31 is t1, and the delay time of signal inversion by the NAND gate 33 is equal between the fall of the node N3 with respect to the rise of the clock CLK and the rise of the node N3 with respect to the fall of the node N1. .

  Note that a signal obtained by inverting the data Din by the inverter 31 (signal of the node N1: delay time t1) is input to one input of the NAND gate 33, and the clock CLK is input to the other input.

  At this time, the pulse width appearing at the node N3 is t0 + t1. If the pulse signal having the width of t0 + t1 is equal to or larger than the pulse width ti sufficient to invert the first output Q1 from the low level “L” to the high level “H”, Q1 transits to “H”. , Q1 is a path.

  Therefore, t0 + t1 = ti is established at the point where Q1 changes from fail to pass (change point, timing). Therefore, when t0 = ti-t1 at that time, that is, when the sweep is made with Q1 being strobe, the point where the fail changes to the pass is ti− rather than the point where the rising of the data Din and the rising of the clock CLK occur simultaneously. It shifts by t1.

  Next, in FIGS. 8 and 10, the difference between the time at which the clock CLK input from the outside to the pad Pclk of the chip 1 transitions and the time at which the data Din input from the outside to the pad Pdin of the chip 1 transitions is represented by t0 ′. And

  If the delay time of the signal inversion by the inverter 32 is t1 ′ and the delay time of the signal inversion by the NAND gate 33 is equal to the rise of the node N4 with respect to the rise of the data Din and the rise of the node N4 with respect to the fall of the node N2. To do.

  Note that data Din is input to one input of the NAND gate 36, and a signal (signal of the node N2: delay time t1 ′) obtained by inverting the clock CLK by the inverter 32 is input to the other input.

  At this time, the pulse width appearing at the node N4 is t0 ′ + t1 ′. If the pulse signal having the width of t0 ′ + t1 ′ is equal to or larger than the pulse width ti ′ sufficient to invert the second output Q2 from “L” to “H”, Q2 transits to “H”. , Q2 is a path.

  Accordingly, −t0 ′ + t1 ′ = ti ′ is established at a point where Q2 changes from fail to pass. Therefore, when t0 ′ = − (ti′−t1 ′) at that time, that is, when sweeping with Q2 being strobe, the rising point of the data Din and the rising edge of the clock CLK are simultaneous at the point of change from fail to path. It is deviated by − (ti′−t1 ′) from the point.

  Then, as shown in FIG. 11, the expected value for both Q1 and Q2 is set to “H”, and the data Din input to the pad Pdin is swept with respect to the clock CLK input to the pad Pclk with each strobe set. Perform the test.

At this time, the point P1 at which the first output Q1 changes from fail to path, that is, Din−CLK (t0) can be expressed by the following [Equation 3].
Din−CLK (t0) = t1−ti (Equation 3)

Furthermore, the point P2 where the second output Q2 changes from fail to path, that is, Din−CLK (t0 ′) can be expressed by the following [Equation 4].
Din−CLK (t0 ′) = − (ti′−t1 ′) (Equation 4)

  Here, by laying out the inverters 31 and 32 and the NAND gates 33 and 36 so as to have the same load with the same dimensions, t1 = t1 ′ and ti = ti ′ can be obtained.

  Therefore, as shown in FIG. 11, it can be said that the intermediate point (intermediate value) between the two points P1 and P2 is a point (timing) at which the data Din and the clock CLK change at the same time. That is, the influence of the dead zone (ti, ti ′) and the influence of the delay (t1, t1 ′) by the inverters 31 and 32 are offset by obtaining an intermediate value between the two change points (points) P1 and P2. .

  FIG. 12 is a diagram for explaining the delay difference detection method of the semiconductor device according to the first example. Here, as shown in FIG. 12A, the signal propagation delay time from the pad Pdin (Cdin) of the chip 1 to the data input (Mdin) of the macro 2 is assumed to be TDdin for the data Din. Further, regarding the clock CLK, the signal propagation delay time from the pad Pclk (Cdin) of the chip 1 to the clock input (Mdin) of the macro 2 is assumed to be TDclk.

  As shown in the timing diagram of FIG. 12B, Tr + TDdin = TDclk is obtained, and therefore Tr = TDclk−TDdin is obtained.

  That is, at the intermediate point between the change point of Q1 and the change point of Q2, the signal transition time reading value (Tr) of Pdin with respect to the signal transition time of Pclk is a signal from the pad of data Din and clock CLK to the delay measurement target point. It can be seen that this is consistent with the difference in propagation delay time.

  Here, as is clear from the comparison with FIG. 1 described above, the pad data Din corresponds to the input data Cdin of the chip 1, and the pad clock CLK corresponds to the input clock Cclk of the chip 1. The delay measurement target point data Din corresponds to the macro 2 input data Mdin, and the delay measurement target point clock CLK corresponds to the macro 2 input clock.

  Therefore, for example, the setup time Tsum of the macro 2 can be obtained from the setup time Tsuc of the chip 1 and the delay difference Dclk−Dd (Tr = TDclk−TDdin) as in [Equation 2] described above.

  Thereby, timing constraints such as setup time and hold time of a macro provided in the semiconductor device can be correctly defined, and the performance of the semiconductor device can be sufficiently exhibited.

  FIG. 13 is a circuit diagram showing a delay difference detection circuit in the semiconductor device according to the second embodiment. Note that the entire semiconductor device (chip) 1 is formed by, for example, the macro 2 and the delay difference detection circuit 3 as in FIG. 2A and the first embodiment. Needless to say, a plurality of macros are mounted on the chip 1.

  As is apparent from the comparison between FIG. 13 and FIG. 8 described above, the delay difference detection circuit 3 of the second embodiment eliminates the inverter 31 provided at one input of the NAND gate 31 in the first embodiment. This corresponds to an inverter 30 added to one input of the gate 36.

  As shown in FIG. 13, the delay difference detection circuit 3 includes two units 3a and 3b. The first unit 3a includes NAND gates 33 to 35, and the second unit 3b includes inverters 30, 32 and NAND gates 36-38 are included.

  Data (first signal) Din input to the pad Pdin of the chip 1 is input to one input of the NAND gate 33 and one input of the NAND gate 36 via the inverter 30.

  The clock (second signal) CLK input to the pad Pclk of the chip 1 is input to the other input of the NAND gate 33 and the other input of the NAND gate 36 via the inverter 32.

  The output (node N13) of the NAND gate 33 is input to one input of the NAND gate 34. The output of the NAND gate 34 is taken out of the chip 1 as the first output Q11 of the delay difference detection circuit 3, and the NAND gate 34 The signal is input to one input of the gate 35. The first output Q11 is taken out from the pad Pq1 of the chip 1.

  The output of the NAND gate 35 is input to the other input of the NAND gate 34, and these NAND gates 34 and 35 function as a latch. A reset signal RSTX is input to the other input of the NAND gate 35, and the first output Q11 held by the latches (34, 35) is reset. That is, for example, the reset signal RSTX resets the data held in the latch every time the rising timing of the data Din changes (sweep) with time.

  The output of the NAND gate 36 (node N14) is input to one input of the NAND gate 37, and the output of the NAND gate 37 is taken out of the chip 1 as the second output Q12 of the delay difference detection circuit 3. , Input to one input of the NAND gate 38. The second output Q12 is taken out from the pad Pq2 of the chip 1 to the outside.

  The output of the NAND gate 38 is input to the other input of the NAND gate 37, and these NAND gates 37 and 38 function as a latch. A reset signal RSTX is input to the other input of the NAND gate 38, and the second output Q12 held by the latches (37, 38) is reset. That is, the reset signal RSTX resets the data held in the latch every time the rising timing of the data Din is swept, for example.

  In the delay difference detection circuit of the second embodiment shown in FIG. 13, NAND gate 33 directly receives data Din and clock CLK, and NAND gate 36 receives inverted data Din and clock CLK through inverters 30 and 32. receive.

  Here, the delays by the inverters 30 and 32 are assumed to be equal. At this time, since the delay of the data Din by the inverter 30 and the delay of the clock CLK by the inverter 32 are equal, the NAND gate 36 outputs the same pulse as when the inverters 30 and 32 are not provided.

  By applying the delay difference detection circuit 3 shown in FIG. 13 described above, for example, the influence of the dead zone described with reference to FIGS. 5 and 6 is canceled, and the delay difference between the data Din and the clock CLK is more accurately determined. It becomes possible to measure.

  For example, a point at which the first output Q11 changes from pass to fail and a point at which the second output Q12 changes from pass to fail are read, and an intermediate value between the two is defined as a measured value. Although FIG. 13 shows an example in which the NAND gates 33 to 38 are applied, for example, the NAND gate can be replaced with a NOR gate as described above.

  Further, if the first unit 3a has the same circuit configuration as a part of the common circuit configuration part (for example, the part excluding the inverters 30 and 32) of the second unit 3b, various modifications can be made. It is.

  14 to 16 are diagrams for explaining the operation of the semiconductor device shown in FIG. First, in FIGS. 13 and 14, the difference between the time at which the clock CLK input from the outside to the pad Pclk of the chip 1 transitions and the time at which the data Din input from the outside to the pad Pdin of the chip 1 transitions is defined as t10. .

  Assume that the delay time of signal inversion by the NAND gate 33 is equal between the falling edge of the node N13 with respect to the rising edge of the clock CLK and the rising edge of the node N13 with respect to the falling edge of the data Din.

  At this time, the pulse width appearing at the node N13 is t10. If the pulse signal having the width of t10 is greater than or equal to the pulse width ti sufficient to invert the first output Q1 from “L” to “H”, Q11 transitions to “H”, and Q11 passes It becomes.

  Therefore, t10 = ti holds at the point where Q11 changes from fail to pass. Therefore, when t10 = ti at that time, that is, when sweeping is performed with Q1 being strobe, the point where the fail changes to the pass is shifted by ti from the point where the rising edge of the data Din and the rising edge of the clock CLK are simultaneous.

  Next, in FIGS. 13 and 15, the difference between the time at which the clock CLK input from the outside to the pad Pclk of the chip 1 transitions and the time at which the data Din input from the outside to the pad Pdin of the chip 1 transitions is expressed as t10 ′. And

  In addition, delay times of signal inversion by the inverters 30 and 32 are t11 and t12, respectively. Assume that the delay time of signal inversion by the NAND gate 33 is equal between the falling edge of the node N14 with respect to the rising edge of the data Din and the rising edge of the node N14 with respect to the falling edge of the node N12.

  Note that a signal obtained by inverting the data Din by the inverter 30 (signal of the node N11: delay time t11) is input to one input of the NAND gate 36. In addition, a signal obtained by inverting the clock CLK by the inverter 32 (signal of the node N12: delay time t12) is input to the other input of the NAND gate 36.

  At this time, the pulse width appearing at the node N14 is −t10′−t11 + t12. If the pulse signal having the width of −t10′−t11 + t12 is equal to or larger than the pulse width ti ′ sufficient to invert the second output Q12 from “L” to “H”, Q12 transits to “H”. Q12 becomes a path.

  Therefore, −t10−t11 + t12 = ti ′ is established at a point where Q12 changes from fail to pass. Therefore, t10 '=-(ti' + t11-t12) at that time, that is, when the strobe is swept in Q12, the point where the failure changes to the path is from the point where the rise of Din and the rise of CLK are simultaneous. Is shifted by − (ti ′ + t11−t12).

  Then, as shown in FIG. 16, the expected value for both Q11 and Q12 is set to “H”, and the data Din input to the pad Pdin is swept with respect to the clock CLK input to the pad Pclk with each strobe set. Perform the test.

At this time, the point P11 at which the first output Q11 changes from fail to path, that is, Din−CLK (t10) can be expressed by the following [Equation 5].
Din−CLK (t10) = ti ...... [Formula 5]

Furthermore, the point P12 at which the second output Q12 changes from fail to path, that is, Din−CLK (t10 ′) can be expressed by the following [Equation 6].
Din−CLK (t10 ′) = − (ti ′ + t11−t12) (Equation 6)

  Here, by laying out the inverters 30 and 32 and the NAND gates 33 and 36 so as to have the same load with the same dimensions, t11 = t12 and ti = ti ′ can be obtained.

  Therefore, as shown in FIG. 16, it can be said that the intermediate point (intermediate value) between the two points P1 and P2 is a point (timing) at which the data Din and the clock CLK transit at the same time. That is, the influence of the delay (t11, t12) by the inverters 30 and 32 is canceled when the change point P2 is generated by the NAND gates 36 to 38, and the influence of the dead band (ti, ti ′) is two changes. It is offset by obtaining an intermediate value between points P1 and P2.

  FIG. 17 is a diagram for explaining a delay difference detection method for a semiconductor device according to the second embodiment. Here, as shown in FIG. 17 (a), regarding the data Din, the signal propagation delay time from the pad Pdin (Cdin) of the chip 1 to the data input (Mdin) of the macro 2 is defined as TDdin. Further, regarding the clock CLK, the signal propagation delay time from the pad Pclk (Cdin) of the chip 1 to the clock input (Mdin) of the macro 2 is assumed to be TDclk.

  As shown in the timing diagram of FIG. 17 (b), Tr + TDdin = TDclk is obtained, and therefore Tr = TDclk−TDdin is obtained.

  That is, at the intermediate point between the change point of Q1 and the change point of Q2, the signal transition time reading value (Tr) of Pdin with respect to the signal transition time of Pclk is a signal from the pad of data Din and clock CLK to the delay measurement target point. It can be seen that this is consistent with the difference in propagation delay time.

  Thereby, as described with reference to FIG. 12, timing constraints such as the setup time and hold time of the macro provided in the semiconductor device can be correctly defined, and the performance of the semiconductor device can be sufficiently exhibited. It becomes possible.

  In the above, the example of the delay difference detection circuit has been described using the NAND gate. However, for example, various circuit configurations such as a NOR gate can be used, and a clock and data can be used. It goes without saying that the logic of the signal can be changed as appropriate.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention. Nor does such a description of the specification indicate an advantage or disadvantage of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
A delay difference detection circuit for measuring a delay difference between a first signal and a second signal,
A first output that changes in accordance with either a first logic signal of positive or negative logic in the first signal and a second logic signal of either positive or negative in the second signal. Unit,
A second logic unit that outputs a third logic signal opposite in logic to the first logic signal and a second output that changes in accordance with a fourth logic signal opposite in logic to the second logic signal;
While sweeping the second signal, a first change point where the output of the first unit changes and a second change point where the output of the second unit changes are measured, and the measured first change point and the measured Obtaining an intermediate value of a second change point to obtain a delay difference between the first signal and the second signal;
A delay difference detection circuit characterized by the above.

(Appendix 2)
The first unit is:
A first logic gate for detecting a change timing of the first logic signal and the second logic signal;
A first latch circuit for detecting and holding a pulse at the output of the first logic gate;
The second unit is
A second logic gate for detecting a change timing of the third logic signal and the fourth logic signal;
A second latch circuit for detecting and holding a pulse at the output of the second logic gate;
The delay difference detection circuit according to appendix 1, characterized by the above.

(Appendix 3)
The first latch circuit and the second latch circuit reset data held by a reset signal;
3. The delay difference detection circuit according to appendix 2, wherein:

(Appendix 4)
A first logic inversion element provided in the first unit receives the second signal and inverts the logic to output the second logic signal;
A second logic inversion element provided in the second unit receives the first signal and inverts the logic to output the third logic signal;
The delay difference detection circuit according to any one of Supplementary Note 1 to Supplementary Note 3, wherein

(Appendix 5)
The delay due to the first logic inverting element and the delay due to the second logic inverting element are offset when obtaining an intermediate value between the measured first change point and the second change point.
The delay difference detection circuit according to appendix 4, wherein:

(Appendix 6)
The second unit is
The common circuit component;
A first logic inverting element that receives the second signal and logically inverts and outputs the fourth logic signal;
A second logic inverting element that receives the first signal and inverts the logic to output the third logic signal;
The delay difference detection circuit according to any one of Supplementary Note 1 to Supplementary Note 3, wherein

(Appendix 7)
The delay due to the first logic inverting element and the delay due to the second logic inverting element are offset when the second unit generates the second change point,
The delay difference detection circuit according to appendix 6, wherein

(Appendix 8)
A semiconductor device provided with a macro,
A first input pad to which a first signal is input;
A second input pad for receiving a second signal;
A first delay that occurs when the first signal is input from the first input pad to the macro, and a second delay that occurs when the second signal is input from the second input pad to the macro. A delay difference detection circuit capable of measuring the delay difference of the delay;
A first output pad for outputting a first output from the delay difference detection circuit;
A second output pad for outputting a second output from the delay difference detection circuit,
The delay difference detection circuit is the delay difference detection circuit according to any one of appendix 1 to appendix 7,
The first output is an output of the first unit in the delay difference detection circuit,
The second output is an output of the second unit in the delay difference detection circuit.
A semiconductor device.

(Appendix 9)
In the semiconductor device provided with the macro, the first delay until the first signal from the first input pad is input to the macro and the second signal from the second input pad until the second signal is input to the macro. A method for detecting a delay difference of a semiconductor device for measuring a delay difference of a second delay, comprising:
Outputting a first logic signal of either positive or negative logic in the first signal and a first output that varies according to either the positive or negative second logic signal of the second signal;
Outputting a third logic signal having a logic opposite to the first logic signal, and a second output changing according to a fourth logic signal having a logic opposite to the second logic signal;
While sweeping the second signal, measure a first change point where the output of the first unit changes and a second change point where the output of the second unit changes,
Obtaining a delay difference between the first signal and the second signal by obtaining an intermediate value between the measured first change point and the second change point;
A method of detecting a delay difference of a semiconductor device.

1 Semiconductor device (chip)
2 Macro 3 Delay difference detection circuit 3a 1st unit 3b 2nd unit 30, 31, 32 Inverter 33-38 NAND gate

Claims (6)

A delay difference detection circuit for measuring a delay difference between a first signal and a second signal,
A first output that changes in accordance with either a first logic signal of positive or negative logic in the first signal and a second logic signal of either positive or negative in the second signal. Unit,
A second logic unit that outputs a third logic signal opposite in logic to the first logic signal and a second output that changes in accordance with a fourth logic signal opposite in logic to the second logic signal;
While sweeping the second signal, a first change point where the output of the first unit changes and a second change point where the output of the second unit changes are measured, and the measured first change point and the measured Obtaining an intermediate value of a second change point to obtain a delay difference between the first signal and the second signal;
A delay difference detection circuit characterized by the above. The first unit is:
A first logic gate for detecting a change timing of the first logic signal and the second logic signal;
A first latch circuit for detecting and holding a pulse at the output of the first logic gate;
The second unit is
A second logic gate for detecting a change timing of the third logic signal and the fourth logic signal;
A second latch circuit for detecting and holding a pulse at the output of the second logic gate;
The delay difference detection circuit according to claim 1. A first logic inversion element provided in the first unit receives the second signal and inverts the logic to output the second logic signal;
A second logic inversion element provided in the second unit receives the first signal and inverts the logic to output the third logic signal;
3. The delay difference detection circuit according to claim 1, wherein the delay difference detection circuit is a delay difference detection circuit. The second unit is
The common circuit component;
A first logic inverting element that receives the second signal and logically inverts and outputs the fourth logic signal;
A second logic inverting element that receives the first signal and inverts the logic to output the third logic signal;
3. The delay difference detection circuit according to claim 1, wherein the delay difference detection circuit is a delay difference detection circuit. A semiconductor device provided with a macro,
A first input pad to which a first signal is input;
A second input pad for receiving a second signal;
A first delay that occurs when the first signal is input from the first input pad to the macro, and a second delay that occurs when the second signal is input from the second input pad to the macro. A delay difference detection circuit capable of measuring the delay difference of the delay;
A first output pad for outputting a first output from the delay difference detection circuit;
A second output pad for outputting a second output from the delay difference detection circuit,
The delay difference detection circuit is the delay difference detection circuit according to any one of claims 1 to 4,
The first output is an output of the first unit in the delay difference detection circuit,
The second output is an output of the second unit in the delay difference detection circuit.
A semiconductor device. In the semiconductor device provided with the macro, the first delay until the first signal from the first input pad is input to the macro and the second signal from the second input pad until the second signal is input to the macro. A method for detecting a delay difference of a semiconductor device for measuring a delay difference of a second delay, comprising:
Outputting a first logic signal of either positive or negative logic in the first signal and a first output that varies according to either the positive or negative second logic signal of the second signal;
Outputting a third logic signal having a logic opposite to the first logic signal, and a second output changing according to a fourth logic signal having a logic opposite to the second logic signal;
While sweeping the second signal, measure a first change point where the output of the first unit changes and a second change point where the output of the second unit changes,
Obtaining a delay difference between the first signal and the second signal by obtaining an intermediate value between the measured first change point and the second change point;
A method of detecting a delay difference of a semiconductor device.

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