KR100636920B1 - Circuit for detecting timing margin of semiconductor device - Google Patents

Abstract

A circuit for detecting a timing margin of a semiconductor device is provided to improve the yield when performing a fuse trimming, by checking a timing margin of the inside of chip at a wafer level and to reduce the error analyzing time, by checking the timing margin without performing Decap after the package process. A circuit for detecting a timing margin of a semiconductor device comprises a timing margin detector(200), a free driver(300), an output buffer(400) and output pins(DQ0-DQ3). The timing margin detector(200) detects the timing margin between the data inside chip and a clock, divides the timing margin into the period which has a constant time interval and outputs digital code signals(Q0-Q3) which are assigned as the different code values to the respective period. The free driver(300) drives the digital code signals(Q0-Q3) and outputs the drive signals(PDO0-PDO3) to the output buffer(400). The output buffer(400) buffers the digital code signals(Q0-Q3) and outputs the buffer output signals(QB0-QB3) to the data output pins(DQ0-DQ3). In the digital code signals(Q0-Q3), the upper bit increases step by step when the period of the timing margin increases.

Description

Circuit margin detecting circuit of a semiconductor device {Circuit for detecting timing margin of semiconductor device}

1 is a configuration diagram for explaining a conventional timing margin.

2 and 3 are operation timing diagrams for explaining a conventional timing margin.

4 is a block diagram of a timing margin discrimination circuit of a semiconductor device according to the present invention;

5 is an operation timing diagram relating to a timing margin discrimination circuit of a semiconductor device according to the present invention.

6 is a detailed circuit diagram illustrating a timing margin detector of FIG. 4.

FIG. 7 is an operation timing diagram relating to the timing margin detector of FIG. 6. FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing margin discrimination circuit of a semiconductor device, wherein the timing margin between data detected in the semiconductor device and a clock or a timing margin between an internal signal and a control clock can be determined by a digital code from outside the chip. Technology.

FIG. 1 shows a case where the input data Din and the internal clock Clk are input to the D-flip flop 1 to output the data Dout in the internal circuit of the semiconductor chip.

2 is an operation timing diagram for explaining the timing margin of the prior art.

When the input data Din is input as shown in the timing diagram of FIG. 2, the normal data Dout is performed after the internal delay time tdelay of the D-flip flop (1) when the clock Clk satisfies the setup time tsetup and hold time thold with respect to the input data Din. Output

However, the D-flip-flop 1 according to the related art causes a malfunction when the timing margin tmargin of the clock Clk is smaller than zero, as shown in the timing diagram of FIG. 3.

In this case, when the chip is tested, it turns out to be a bad chip, but it is difficult to determine in which circuit inside the chip the actual defect occurred. In particular, when the chip is in a packaged state, the circuit in which the failure occurs may be determined only by decapping and probing an internal signal or performing an E-beam probing test. Accordingly, in order to perform such a test, additional measurement equipment is required, and a large amount of time and cost for failure analysis are consumed.

The present invention has been made to solve the above problems, and it is possible to determine the timing margin of the internal signals by measuring the internal timing margin between the data and the clock and output it as a digital code through a data pin outside the chip. The purpose is.

The timing margin determination circuit of the semiconductor device of the present invention for achieving the above object, by detecting the timing margin between the data and the clock inside the chip to divide the timing margin into a section having a predetermined time interval and different codes for each section A timing margin detector for outputting a digital code signal assigned as a value; And an output buffer for buffering the digital code signal and outputting the buffer output signal to the data output pin.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a block diagram of a timing margin discrimination circuit of a semiconductor device according to the present invention.

The present invention includes a timing margin detector 200, a pre-driver 300, an output buffer 400, and data output pins DQ0 to DQ3. In the embodiment of the present invention, the device to which the input data Din and the clock Clk are input will be described as the D-flip flop 100.

Here, the timing margin detector 200 detects the timing margin according to the input data Din and the clock Clk input to the D-flip flop 100 and outputs the digital code signals Q0 to Q3. The predriver 300 drives the digital code signals Q0 to Q3 applied from the timing margin detector 200 to output the driving signals PDO0 to PDO3. The output buffer 400 buffers the driving signals PDO0 to PDO3 and outputs the buffer output signals OBO0 to OBO3 to the data output pins DQ0 to DQ3, respectively.

An operation process of the present invention having such a configuration will be described below with reference to the operation timing diagram of FIG. 5.

In the operation timing diagram of FIG. 5, the data Din ′ is data that compensates for the setup time of the input data Din. For this data Din ', the rising edge of the clock Clk is divided into a case where the timing margin tmargin is greater than zero and less than zero.

Here, when the timing margin between the input data Din and the clock Clk is less than zero, each timing margin tmargin is subdivided into constant time intervals tunit. If the time interval of the timing margin is the shortest, set the time interval tunit. If the time interval of the timing margin is the longest, set the time interval 4 x tunit.

As shown in the operation timing diagram of FIG. 5, the time interval tunit is divided into four sections I to IV and allocates a digital code DQi to each section. The digital code DQi is composed of 4 bits, and corresponds to a thermometer code in which the upper bits are sequentially increased one by one as the interval of the timing margin increases.

For example, the time interval section I of the timing margin is assigned to the digital code 0001, the section II to the digital code 0011, the section III to the digital code 0111, and the section IV to the digital code 1111.

The digital code signals Q0 to Q3 according to the digital codes allocated by the timing margin detector 200 are output to the data output pins DQ0 to DQ3 through the pre-driver 300 and the output buffer 400.

6 is a detailed circuit diagram of the timing margin detector 200 of FIG. 4.

The timing margin detector 200 includes a clock generator 210, a delay unit 220, a latch unit 230, and a clock synchronization unit 240.

In detail, the clock generator 210 includes PMOS transistors P1 to P4, NMOS transistors N1 to N2, inverters IV1 to IV11, and NAND gate ND1.

The PMOS transistors P1 and P2 and the NMOS transistor N1 are connected in series between the supply voltage terminal and the ground voltage terminal. The input data Din is applied to the PMOS transistor P1 through the gate terminal, and the clock Clk is applied to the PMOS transistor P2 and the NMOS transistor N1 through the common gate terminal.

The PMOS transistors P3 and P4 and the NMOS transistor N2 are connected in series between the power supply voltage terminal and the ground voltage terminal. The clock Clk is applied to the PMOS transistor P3 through the gate terminal, and the input data Din is applied to the PMOS transistor P4 and the NMOS transistor N5 through the common gate terminal.

The inverters IV1 and IV2 having the latch structure latch the output signal of the PMOS transistor P2 and output the output signal fout1. Inverters IV3 and IV4 having a latch structure latch the output signal of the PMOS transistor P4 to output the output signal fout2.

The NAND gate ND1 performs a NAND operation on the output signals fout1 and fout2. The inverter chains IV5 to IV11 delay the output of the NAND gate ND1 for a predetermined time and output the synchronous clock signal S_CLK.

The delay unit 220 delays the above-described output signals fout1 and fout2, and includes unit time delay units UD1 to UD18 having delay times equal to the same time interval tunit. Here, it is preferable to set the delay time size of the unit time delay units UD1 to UD18 to be equal to or larger than the setup time tsetup in the timing diagram of FIG.

The unit time delay units UD1, UD4, UD8, and UD13 respectively delay the output signal fout2 with a constant delay time. The unit time delay units UD2, UD3, UD5 to UD7, UD9 to UD12, and UD14 to UD18 respectively delay the above-described output signal fout1 with different delay times. That is, since each unit time delay unit UD is increased by one with respect to the digital code signals Q0 to Q3, one bit of the digital code has a timing resolution equal to the unit time interval tunit.

In addition, the latch unit 230 includes NAND gates ND2 to ND9 of the SR latch structure to output the latch signals L0 to L3.

Here, the NAND gates ND2 and ND3 latch the output of the unit time delay units UD1 to UD3 to output the latch signal L0. The NAND gates ND4 and ND5 latch the output of the unit time delay units UD4 to UD7 to output the latch signal L1. The NAND gates ND6 and ND7 latch the output of the unit time delay units UD8 to UD12 to output the latch signal L2. The NAND gates ND8 and ND9 latch the output of the unit time delay units UD13 to UD18 to output the latch signal L3.

In addition, the clock synchronizer 240 samples the latch signals L0 to L3 in synchronization with the synchronous clock signal S_CLK applied from the clock generator 210 to output the digital code signals Q0 to Q3. DF3.

Here, the D-flip-flop DF0 flips the latch signal L0 in synchronization with the rising edge of the synchronous clock signal S_CLK to output the output signal Q0. The D-flip-flop DF1 flip-flops the latch signal L1 in synchronism with the rising edge of the synchronous clock signal S_CLK to output the digital code signal Q1. The D-flip-flop DF2 flips the latch signal L2 in synchronization with the rising edge of the synchronous clock signal S_CLK to output the digital code signal Q2. The D-flip-flop DF3 flips the latch signal L3 in synchronization with the rising edge of the synchronous clock signal S_CLK to output the digital code signal Q3.

The operation of the timing margin detector 200 of the present invention having such a configuration will be described below with reference to the operation timing diagram of FIG. 7.

First, the PMOS transistors P1 to P4, the NMOS transistors N1 and N2, and the inverters IV1 to IV4 of the clock generator 230 are dynamic latch circuits to which input data Din and clock Clk are applied, and loading of input data Din and clock Clk is performed. ) And outputs the output signals fout1 and fout2 symmetrically to have the same value. Here, the output signal fout1 is synchronized with the rising edge of the input data Din, and the output signal fout2 is synchronized with the rising edge of the clock Clk.

Accordingly, the synchronous clock signal S_CLK is a signal generated by the AND combination of the output signals fout1 and fout2, and thus follows the rising edge of the slower of the input data Din or clock Clk.

Thereafter, the inverter chains IV5 to IV11 output the synchronous clock signal S_CLK in the flip-flops DF0 to DF3 of the clock synchronization unit 240 so that the synchronous clock signal S_CLK has sufficient setup time for the latch signals L0 to L3.

In addition, since the plurality of unit time delay units UD1 to UD18 are used for both the output signals fout1 and fout2, the plurality of unit time delay units UD1 to UD18 may have the same fanout. In addition, it is possible to have the same slew rate at the input terminal of the latch unit 230 to enable accurate timing comparison operation.

Subsequently, the latch unit 230 compares the timings of the output signals fout1 and fout2 to determine the logic levels of the latch signals L0 to L3, and is initialized to logic high when the timing comparison ends.

Next, the D-flip flops DF0 to DF3 output the synchronous digital code signals Q0 to Q3 at the rising edge of the synchronous clock signal S_CLK. Therefore, even when the level transition time points of the latch signals L0 to L3 are different in time, the digital code signals Q0 to Q3 can be output at the same timing. As a result, as shown in the operation timing diagram of FIG. 7, different digital code signals Q0 to Q3 are output for respective sections I to IV.

As described above, the present invention provides the following effects.

First, the test mode can be used at the wafer or package level to output the value of the digital code signal through the data output pin so that the digital code can check the timing margin inside the chip.

Secondly, the timing margin inside the chip is checked at the wafer level to improve yield when fuse trimming is performed.

Third, the timing margin can be checked without decap after the package is processed to reduce the defect analysis time.

Fourth, it provides an effect of improving the detection accuracy of the timing margin by correlating or fitting the digital code measured in the equipment and the digital code known in the simulation result of the present invention.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (10)

A timing margin detector for detecting timing margins between data and a clock inside the chip, dividing the timing margins into sections having a predetermined time interval, and outputting digital code signals assigned to different code values for each section; And And an output buffer for buffering the digital code signal and outputting a buffer output signal to a data output pin. 2. The timing margin discrimination circuit of claim 1, further comprising a pre-driver for driving the digital code signal to output a driving signal to the output buffer. The timing margin discrimination circuit of claim 1, wherein the digital code signal is a code signal in which upper bits sequentially increase one by one as the interval of the timing margin increases. The method of claim 1, wherein the timing margin detector A clock generator which outputs a first output signal synchronized with the data and a second output signal synchronized with the clock, and outputs a synchronous clock signal by delaying the first output signal and the second output signal for a predetermined time; A delay unit delaying the first output signal to output a plurality of first delay signals having different unit times, and delaying the second output signal to output a plurality of second delay signals having the same unit time; A latch unit configured to latch the plurality of first delay signals and the plurality of second delay signals, respectively, and output a plurality of latch signals; And And a clock synchronizing unit for sampling the plurality of latch signals and outputting the digital code signal in synchronism with the synchronizing clock signal. The method of claim 4, wherein the clock generator A driving unit for driving the data and the clock to have the same loading value; A latch configured to latch the output of the driver for a predetermined time to output the first output signal and the second output signal; And And a logic calculator configured to AND the first output signal and the second output signal and delay the predetermined time to generate the synchronous clock signal. 5. The timing margin discrimination circuit of claim 4, wherein the unit time is set to be greater than or equal to the setup time of the data. The timing margin discrimination circuit of claim 4, wherein one bit of the digital code signal has a time interval equal to the unit time. The method of claim 4, wherein the delay unit A first unit time delay unit configured to delay the first output signal and output a plurality of first delay signals having different unit times; And And a second unit time delay unit configured to delay the second output signal and output a plurality of second delay signals having the same unit time. 5. The timing margin discrimination circuit of claim 4, wherein the latch unit is an SR latch which latches the plurality of first delay signals and the plurality of second delay signals, respectively, and outputs a plurality of latch signals. The timing margin discrimination circuit of claim 4, wherein the clock synchronizer is a D-flip-flop that samples the plurality of latch signals and outputs the digital code signal at the same timing.

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