JP3911556B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a delay circuit capable of changing a delay time by digital control, and more particularly to a technique that is particularly useful when used in a DLL (Delay Locked Loop) circuit that performs high-frequency output.
[0002]
[Prior art]
As a conventional delay circuit for changing the delay time by digital control, there is a technology described in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.31, NO.7, JULY 1996, PP.958-965.
[0003]
As shown in FIG. 5 and FIG. 6, this delay circuit has a plurality of delay stages A1, A2,..., An connected in series, and the coarse adjustment is configured so that the output can be taken out from each stage. The delay line (FIG. 5) and an interpolation delay circuit for fine adjustment (FIG. 6) for adding a further subdivided delay to the signal extracted from the delay line.
[0004]
In the delay line of FIG. 5, two output tristate inverters D1 to Dn and E1 to En are provided at each output node of the delay stages A1 to An in order to extract a delayed output. Among these, the output of one tri-state inverter D1 to Dn is output to the first system drive circuit 21 in FIG. 6, and the output of the other tri-state inverter E1 to En is output to the second system drive circuit 22. It is connected to the.
[0005]
Further, the delay line of FIG. 5 is configured such that the outputs of two successive delay stages are selectively output by selection signals SELECT X and SELECT X + 1 input from the outside. Of these two delayed signals, the preceding stage signal is output to the input terminal A of the first system drive circuit 21 of the interpolation delay circuit, and the subsequent stage signal is output to the input terminal B of the second system drive circuit 22. Selected.
[0006]
The interpolation delay circuit of FIG. 6 includes first and second system drive circuits 21 and 22 in which a plurality of inverters 21a to 21e and 22a to 22e are connected in parallel, and these first and second system drive circuits. And a buffer circuit 23 composed of a CMOS inverter driven by both outputs of 21 and 22. The drive circuit 21 of the first system and the drive circuit 22 of the second system are configured such that the number of inverters 21a to 21e and 22a to 22e connected in parallel and the driving force of each inverter are symmetrical, and each inverter 21a to 21e and 22a to 22e can be controlled to be active or inactive by the control signals COM1 and COM2, and when the same control signal is input to both systems, the inverters corresponding to each other are activated. Yes.
[0007]
In the actual control of the interpolation delay circuit, the control signal SEL2 input from the outside is input to the second system side as it is, inverted and input to the first system side by the inverter 42, and is thereby activated. And the inactivated inverter are set to be opposite to each other on the first system side and the second system side. For example, when the two inverters 21a and 21b from the top are activated on the first system side, the three inverters 22c, 22d and 22e from the bottom are activated on the second system side. That is, by such control, when both the first system and second system drive circuits 21 and 22 operate, the same driving force is always obtained.
[0008]
According to the configuration as described above, of the two delayed signals extracted from the delay line in FIG. 5, the preceding stage signal is input to the input terminal A of the first system drive circuit 21, and the succeeding stage signal is the second system. To the input terminal B of the driving circuit 22.
[0009]
As a result, first, the delay signal from the delay line is input to the first-system drive circuit 21, and the actively controlled inverter of the drive circuit 21 operates. Thereby, the driving of the buffer circuit 23 is started. Even if a signal is input to the terminal A, the output of the buffer circuit 23 does not change immediately due to the parasitic capacitance C1 of the input terminal.
[0010]
Next, the delayed signal in the subsequent stage is input to the second-system drive circuit 22, and the inverter activated on the second-system side operates. Here, the driving power of the inverters operating in the first and second drive circuits 21 and 22, that is, the sum of the current values for charging and discharging the parasitic capacitance C1, is always constant regardless of the control signal SEL2. By this operation, the driving of the buffer circuit 23 is accelerated, and an inverted signal is output from the buffer circuit 23.
[0011]
As described above, in the interpolation delay circuit of FIG. 6, the driving power of the inverter to be operated is changed by the control signal SEL2 between the input of the first delay signal and the input of the second delay signal. The operation delay time of the buffer circuit 23 changes, and the delay amount can be finely adjusted.
[0012]
The large adjustment of the delay amount in the delay line of FIG. 5 and the fine adjustment of the interpolation delay circuit of FIG. 6 are combined, and the delay amount can be adjusted with a relatively large range and high resolution. Yes.
[0013]
[Problems to be solved by the invention]
In order to use the delay circuit as described above for a clock generation circuit such as a ring oscillator having a wide frequency range, for example, the number of delay stages provided in the delay line is increased or the delay time adjustable by the interpolation delay circuit is set. It is necessary to further subdivide the resolution.
[0014]
However, in the conventional delay circuit, since it is necessary to provide two tristate inverters at each output node of the plurality of delay stages provided on the delay line, the parasitic capacitance of the output node of each delay stage is increased. In addition, if the number of delay stages is increased, the parasitic capacitance of the circuit increases in proportion to that. For this reason, there is a problem that the fixed delay inherent to the circuit becomes large, which becomes an obstacle when a high-frequency signal is generated.
[0015]
An object of the present invention is to reduce a fixed delay inherent in a circuit in a delay circuit including a delay line formed by connecting a plurality of delay stages in series and an interpolation delay circuit capable of further adjusting a delay amount by subdividing the delay amount. Therefore, when a delay circuit is used as a clock generation circuit, it is possible to operate at a higher frequency than in the prior art.
[0016]
Another object of the present invention is to provide a semiconductor integrated circuit including a DLL circuit capable of generating a high frequency clock using a delay circuit having a small fixed delay.
[0017]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0018]
[Means for Solving the Problems]
Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, a first delay means in which a plurality of delay stages are connected in series, a signal extracting means capable of branching and outputting the outputs of the plurality of delay stages, and a plurality of drive circuits connected in parallel. A second delay unit having a drive unit and a second drive unit, the output delay of which is changed by controlling each of these drive circuits to be active or inactive. A delay obtained by adding the delay of the first delay means and the delay of the second delay means by selecting the outputs of the two delay stages and supplying them as the operation timing signals of the first drive means and the second drive means, respectively. In a semiconductor integrated circuit including a delay circuit configured to output a signal from the second delay unit, the signal extraction unit is connected to each output node of the plurality of delay stages. Has been a plurality of tri-state buffer circuit is configured such that the output of each tri-state buffer circuit is fixedly input to one of the first driving means or the second driving means.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
A preferred embodiment of the present invention will be described below with reference to FIGS.
FIG. 1 is a schematic diagram showing a configuration of a ring oscillator using a delay circuit according to an embodiment of the present invention.
This ring oscillator is composed of a delay circuit 100 according to the present invention and a logic gate 2 such as a NAND circuit having the output of the delay circuit 100 as one input and the reset signal as the other input. By inverting the logic gate 2 and feeding it back to the input side, an oscillating operation is performed at a frequency corresponding to the delay amount of the delay circuit 100.
[0020]
The delay circuit 100 includes a delay block 10 for coarse adjustment as first delay means formed by connecting a plurality of delay stages A1 to An in series, and a plurality of drive inverters 21a to 21e and 22a to 22e as drive circuits. Interpolation delay block 20 for fine adjustment as a second delay means comprising a first system drive circuit (first drive means) 21 and a second system drive circuit (second drive means) 22 connected in parallel. It consists of.
[0021]
FIG. 2 shows an example of a detailed circuit diagram of the delay block 10.
Each of the delay stages A1 to An constituting the delay block 10 is formed by connecting, for example, two CMOS inverters in cascade, and is configured to have the same delay amount. In this delay block 10, tristate inverters (tristate buffer circuits) B1 to Bn for taking out outputs of the delay stages A1 to An as signal extracting means are connected to output nodes of the delay stages A1 to An one by one. When any one of these tri-state inverters B1 to Bn is selected, a delay signal is extracted therefrom.
[0022]
Any one of the selection signals SELECT X, SELECT X + 1... Is input to the delay block 10 via a decoding circuit (not shown), and any two consecutive ones of the tri-state inverters B1 to Bn are selected. The delayed signals at the locations are taken out. In addition, the selection signal SEL1 input to the decoding circuit selects the number of successive two delay stages.
[0023]
The selected delay signal is output from the corresponding tristate inverters B1 to Bn and sent to the interpolation delay block 20. The output terminals of the tristate inverters B1 to Bn are, for example, odd-numbered delay stages A1 and A3. , A5... Tristate inverters B1, B3, B5... That take out outputs from the even-numbered delay stages A2, A4, A6. B4, B6... Are fixedly connected to the input terminal B of the second system drive circuit 22, respectively.
[0024]
FIG. 3 shows an example of a detailed circuit diagram of the interpolation delay block 20.
The interpolation delay block 20 controls the states of the drive circuits 21 and 22 of the first system and the second system, the buffer circuit 23 composed of a CMOS inverter driven by the drive circuits 21 and 22, and the states of the drive circuits 21 and 22. The control circuit 30 is configured.
[0025]
The drive inverters 21a to 21e and 22a to 22e constituting the drive circuits 21 and 22 are, for example, tristate CMOS inverters configured such that a power supply line can be connected or disconnected by a switch. Active control is possible.
[0026]
The first-system drive circuit 21 is formed by, for example, connecting in parallel five sets of drive inverters 21a to 21e that are switch-controlled by respective bit signals of a 5-bit control signal COM1. These five sets of drive inverters 21a to 21e are formed so as to increase the driving force twice in order from the first set to the fifth set by forming the device constants of the MOSFETs or the number of CMOS inverters differently. Has been.
[0027]
The second system drive circuit 22 is configured symmetrically with the first system drive circuit 21. That is, the five sets of drive inverters 22a to 22e of the drive circuit 22 and the five sets of drive inverters 21a to 21e of the drive circuit 21 corresponding thereto are formed with the same drive force, and each drive circuit The control signals COM1 and COM2 respectively input to 21 and 22 are such that the same bit signal acts in the same way on two sets of driving inverters formed with the same driving force in the first system and the second system. It is configured.
[0028]
The buffer circuit 23 is driven by the first and second system drive circuits 21 and 22 and outputs a delay signal from the interpolation delay block 20. Since the buffer circuit 23 has an input load such as a parasitic capacitance C1, the operation delay varies depending on the driving force of the input terminal.
[0029]
The control circuit 30 externally inputs a selection signal SEL2 indicating a selection pattern of a drive inverter to be activated and an inversion control signal REV, and controls to activate or deactivate the states of the drive inverters 21a to 21e and 22a to 22e. Signals COM1 and COM2 are generated. Specifically, the exclusive OR circuit 31 that inputs the selection signal SEL2 and the inverted control signal REV and the control signals that are input to the first system side and the second system side are in opposite phase to each other. And an inverter 32 for inverting the selection signal.
[0030]
Here, the inversion control signal REV is a binary signal indicating whether or not the selection signal SEL2 is inverted, and is uniquely determined based on the selection signal SEL1 input to the delay block 10 for coarse adjustment. Is. That is, when the output destinations of the two delay signals selected by the delay block 10 are in the order of the input terminals A and B in the output order, the inversion control signal REV is set to “0” (not inverted). In the order of the input terminals B and A, the inversion control signal REV is set to be “1” (inverted).
[0031]
According to the delay circuit 100 configured as described above, when a signal is input to the delay block 10 in a state where the selection signals SEL1 and SEL2 are input, first, the selection signal from the plurality of delay stages A1 to An is selected. The outputs of two consecutive delay stages in the selected state are extracted by SEL 1 and output to the interpolation delay block 20. Here, by selecting which delay stage output from the delay block 10 is taken out, first, a relatively large delay amount is adjusted.
[0032]
Next, the following processing is performed in the interpolation delay block 20. That is, first, among the drive inverters 21a to 21e and 22a to 22e of the first system and the second system, the drive inverter selected by the selection signal SEL2 and the inversion control signal REV is controlled to be active, and the others are controlled to be inactive. Is done. Here, on the first system side and the second system side, the control signals COM1 and COM2 are inverted with each other by the inverter 32, so that the drive inverter that is activated and the drive signal that is deactivated Control is performed so that the inverter is opposite to that of the inverter.
[0033]
In this state, the two delay outputs extracted from the delay block 10 and having different output timings are sent to the first series drive circuit 21 and the second series drive circuit 22 of the interpolation delay block 20 with a predetermined delay time. Each is input separately.
[0034]
For example, when the first and second delay outputs of the delay block 10 are selected by the select signal X in FIG. 2, first, the first delay output is input to the first-system drive circuit 21. Thereafter, the delay output of the second stage is input to the second-system drive circuit 22 with a predetermined delay time. When the second and third delay outputs of the delay block 10 are selected by the select signal X + 1 in FIG. 2, first, the second delay output is input to the second-system drive circuit 22. Thereafter, the delay output of the third stage is input to the first-system drive circuit 21 with a predetermined delay time.
[0035]
As described above, the one in which the delay output is input first among the drive circuits 21 and 22 in the first system and the second system is switched depending on the selection position of the delay signal in the delay block 10. When the signal is first input to the first system side, first, among the first system drive inverters 21a to 21e, the one that is actively selected by the control signal is operated, and the interpolation delay block 20 is operated. The buffer circuit 23 is started to be driven. The buffer circuit 23 has an input load such as a parasitic capacitance C1, and the driving power of the drive circuits 21 and 22 is set to be relatively small. Therefore, the input potential of the buffer circuit 23 does not exceed the threshold value Vth. Displaced as far as possible.
[0036]
Next, the second delay output is input to the second-system drive circuit 22, whereby the one of the second-system drive inverters 22 a to 22 e that has been selected is activated to operate the buffer circuit. 23 is accelerated. Here, the total driving force of the driving circuits of the first system and the second system to be operated is constant regardless of the selection signal SEL2. Accordingly, the buffer circuit 23 outputs a signal when the input potential of the buffer circuit 23 exceeds the threshold value Vth.
[0037]
When the delay signal is first input to the second system side, the operation sequence of the first system drive circuit 21 and the second system drive circuit 22 is simply switched, and the other operations are performed in the same manner.
[0038]
In this manner, the interpolation delay block 20 changes the driving force of the driving circuit 21 or 22 that operates between the time when the first delay signal is input and the time when the second delay signal is input. The signal delay can be finely adjusted by changing the operation delay of the buffer circuit 23 at substantially constant intervals.
[0039]
As described above, according to the delay circuit 100 of this embodiment, the relatively large delay amount adjustment in the coarse adjustment delay block 10 and the fine adjustment of the delay amount in the interpolation delay block 20 are combined, The delay amount can be adjusted with a large range and high resolution. Further, since the number of tri-state inverters B1 to Bn for extracting a delay signal from the coarse adjustment delay block 10 is reduced by half compared to the conventional example of FIG. The capacitance can be reduced, and the fixed delay of the circuit can be reduced. In addition, the chip occupation area and power consumption can be reduced.
[0040]
Next, the relationship between the delay amount of the delay circuit 100 and the selection signals SEL1 and SEL2 will be described.
As described above, the delay amount of the delay circuit 100 includes the selection signal SEL1 supplied to the coarse adjustment delay block 10, the selection signal SEL2 and the inverted control signal input to the control circuit 30 of the interpolation delay block 20. Determined by REV.
[0041]
The selection signals SEL1 and SEL2 are expressed by, for example, a binary code of predetermined bits. Among these, the upper several bits are applied to the selection signal SEL1, and the remaining lower several bits (5 bits in the case of FIG. 3) are applied to the selection signal SEL2. It is done. The delay amount of the delay circuit 100 is increased in proportion to the size of the binary code.
[0042]
Specifically, the selection signal SEL1 is converted into a signal for actually selecting the tristate inverters B1 to Bn through a decoding circuit (not shown). The configuration of this decoding circuit is represented by the selection signal SEL1. As the value increases by one, the selected portion of the delay signal is set to shift to the previous stage by one stage.
[0043]
The selection signal SEL2 activates or deactivates each of the five sets of drive inverters 21a to 21e and 22a to 22e provided in the drive circuits 21 and 22 of the first system and the second system. It is a signal to control. Of the control signals COM1 and COM2 derived from the selection signal SEL2, the upper 1-bit signal is the drive inverter 21e, 22e having the largest driving force, and the upper 2-bit signal is the second driving force. Each bit signal is associated with each set of drive inverters, such as corresponding to the large drive inverters 21d and 22di. Then, the control signals COM1 and COM2 are inverted by the inverter 32, and further, the select signal SEL2 and the control signal COM2 are controlled to be the same or inverted by the inversion control signal REV.
[0044]
The inversion control signal REV can be, for example, the same signal as the lower 1 bit signal of the selection signal SEL1. As a result, when the preceding one of the two delay stages selected by the selection signal SEL1 is the odd-numbered delay stages A1, A3,..., The inversion control signal REV is set to “0” (not inverted). .., The inversion control signal REV is set to “1” (inverted).
[0045]
In such a configuration of the control signal, gradually increasing the delay amount of the delay circuit 100 is achieved by increasing the numerical values represented by the selection signals SEL1 and SEL2 by one. That is, the upper multiple bit selection signal SEL1 is fixed, and the lower multiple bit selection signal SEL2 is incremented by “1” from “00000”. When the value of the selection signal SEL2 becomes “11111”, next, the value of the selection signal SEL1 is incremented by “1” and the value of the selection signal SEL1 is returned to “00000” again. Thereafter, the amount of delay gradually increases by repeating this.
[0046]
When the delay amount is gradually increased in this way, the value of the selection signal SEL2 may change from “11111” to “00000”. At this time, in the delay circuit 100 of this embodiment, the value of the selection signal SEL1 is incremented by “1”, so that the inversion control signal REV changes from “0” (not inverted) to “1” (inverted). Therefore, even when the selection signal SEL2 changes as described above, the signal that has passed through the exclusive OR circuit 31 becomes “11111” both before and after the change.
[0047]
That is, in the delay circuit 100 of this embodiment, the state of the drive inverters 21a to 21e and 22a to 22e of the interpolation delay block 20 does not change before and after the selection signal SEL2 changes from “11111” to “00000”. .
[0048]
On the other hand, in the conventional example of FIG. 6, when the selection signal SEL1 changes from “11111” to “00000”, the change in the signal is directly transmitted to the drive circuits 21 and 22 of the first system and the second system. The first system drive inverters 21a to 22e all change from the inactive state to the active state, and the second system drive inverters 22a to 22e all change from the active state to the inactive state. In order to change such many circuit states at the same time, the amount of current required also increases, so that the time required for the state transition becomes longer than in other cases. For this reason, in the conventional delay circuit, when the selection signal SEL1 changes from “00000” to “11111”, there is a risk that the transition of the state is not in time for the signal passing timing, and the amount of delay may be distorted. It was.
[0049]
However, in the delay circuit 100 of the present embodiment, since the drive inverters 21a to 21e and 22a to 22e are not suddenly changed even in the above-described case, the delay amount is increased when the delay amount is smoothly increased or decreased. The effect is that there is no fear of the amount of flying.
[0050]
FIG. 4 shows a block diagram of a DLL circuit using the ring oscillator of this embodiment as a variable frequency oscillator.
In this figure, 70 is a ring oscillator formed by connecting a delay circuit 100 having a delay block 10 and an interpolation delay block 20 and a logic gate 2 for inverting the signal, and 71 is a multiplication clock φn from the ring oscillator 80. An n-ary counter that counts and detects the n-th multiplication clock and outputs the count signal n times. A frequency comparator 72 compares the time difference between the count signal and the reference clock φr and outputs the comparison result signal. A delay control counter 73 in which a value obtained by converting the delay time of the delay circuit 100 into a digital signal is stored; 73 is a delay control counter 75 based on the comparison result signal so that the comparison result in the frequency comparator 72 becomes “0”. Addition value control logic 74 as a control circuit for determining the addition / subtraction value, 74 is the value of delay control counter 75 based on the control of addition value control logic 73. A y-value adder 76 for adding and subtracting is a decoding circuit that decodes the selection signal SEL1 and generates selection signals for the tri-state inverters B1 to Bn of the delay block 10.
[0051]
According to such a DLL circuit, it is possible to stably generate a high-frequency clock φn obtained by multiplying the reference clock φr by n while synchronizing with the reference clock φr. Further, since the clock signal is generated by digital control, there is an effect that a stable result can be obtained with respect to temperature characteristics and voltage characteristics as compared with an analog control PLL (Phase locked loop) circuit or the like. Further, by using the delay circuit 100 of this embodiment, it is possible to cope with a higher frequency clock signal because the fixed delay is small, and further, when the delay amount of the delay circuit 100 is changed gently. In this case, there is no fear that a delay amount will occur, and there is an effect that stable high-frequency operation is possible.
[0052]
The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.
For example, in the above embodiment, the control circuit 30 of the interpolation delay block 20 is provided with the inverter 32 that inverts the control signals COM1 and COM2, but the control circuit 30 and the control terminals of the drive inverters 21a to 21e By changing the wiring form of the control lines connecting the two so that the on / off state is reversed, the same effect can be obtained without providing the inverter 32.
[0053]
In the embodiment, the interpolation delay block 20 is provided with an exclusive OR circuit that inputs the inverted control signal REV and the selection signal SEL2. However, the value of the lower 5 bits of the delay control counter is lower 6 bits. If count control is performed so as to be inverted in accordance with the eye signal, the configuration of the exclusive OR circuit can be eliminated.
[0054]
In the DLL circuit of the above-described embodiment, the output clock is generated by the oscillation operation of the ring oscillator using the delay circuit 100. However, in the DLL circuit of the present invention, the reference clock is passed through the delay circuit 100. And a DLL circuit configured to control the delay amount of the delay circuit 100 based on the comparison result by generating an output clock, feeding back the output clock and comparing it with a reference clock.
[0055]
In the above description, an example in which the invention made by the present inventor is mainly applied to a DLL circuit which is a field of use as a background has been described. However, the present invention is not limited to this example. It can be used widely.
[0056]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, the adjustment of the delay amount with a relatively large range and high resolution can be achieved by combining the adjustment of the relatively large delay amount in the first delay unit and the fine adjustment of the delay amount in the second delay unit. In addition, the number of tri-state buffers for extracting two delayed signals from the first delay means can be halved compared to the conventional one, so that the circuit area and power consumption can be reduced accordingly. In addition, since the fixed delay of the circuit is reduced, there is an effect that the circuit can be adapted to an operation at a higher frequency.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit configuration of a ring oscillator using a delay circuit according to an embodiment of the present invention.
2 is a circuit diagram showing details of a coarse adjustment delay block in the delay circuit of FIG. 1; FIG.
FIG. 3 is a circuit diagram illustrating details of an interpolation delay block for fine adjustment in the delay circuit of FIG. 1;
FIG. 4 is a block diagram illustrating a configuration example of a DLL circuit using the delay circuit according to the embodiment.
FIG. 5 is a circuit diagram showing a delay line for coarse adjustment of a conventional delay circuit that performs delay control with a digital signal;
FIG. 6 is a circuit diagram showing an interpolation delay circuit for fine adjustment of the conventional delay circuit.
[Explanation of symbols]
10 delay block (first delay means)
A1-An delay stage
B1-Bn Tri-state inverter
20 Interpolation delay block (second delay means)
21 First-system drive circuit (first drive means)
22 Second-system drive circuit (second drive means)
21a-21e Drive inverter
22a-22e Drive inverter
23 Buffer circuit
30 Control circuit
70 ring oscillator
71 n-ary counter
72 Frequency comparator
73 Addition value control logic
74 y value adder
75 Delay control counter
76 Decode circuit
100 delay circuit
SEL1, SEL2 selection signal
REV Inversion control signal

Claims (4)

First delay means comprising a plurality of delay stages connected in series;
A signal extracting means capable of branching the outputs of the plurality of delay stages, a first driving means in which a plurality of driving circuits are connected in parallel, and a plurality of driving circuits connected in parallel to the first driving means. The output nodes of the first driving means and the second driving means are made common and the plurality of driving circuits are controlled to be active or inactive, respectively, thereby changing the output delay. Second delay means,
Those things and inactive active and along with is controlled to be opposite between the first driving means and second driving means of the drive circuit of the second delay means, continuously from said first delay means the outputs of the two delay stages is selected by being supplied as an operating timing signal of the first driving means and second driving means for the delay and the addition of the delay and the second delay means of said first delay means A semiconductor integrated circuit comprising a delay circuit configured to output the delayed signal from the second delay means,
The signal extracting means is a plurality of tristate buffer circuits connected to each of the output nodes of the plurality of delay stages, and the output of each tristate buffer circuit is the first driving means or the second driving means. is configured to be input to either fixedly,
The delay circuit includes
A selection signal including selection information of a driving circuit to be activated among the driving circuits of the second delay circuit, and an instruction to supply the selection signal to the first driving means side or the second driving means side An exclusive OR circuit to which an inversion control signal is input;
A semiconductor integrated circuit , comprising: an inverter that causes the control signals supplied to the first driving means and the second driving means to be in opposite phases to each other . 2. The semiconductor according to claim 1, wherein the second delay means is provided with a buffer circuit that is driven by the first drive means and the second drive means and changes an output delay by the driving force. Integrated circuit. 3. The semiconductor integrated circuit according to claim 2, wherein each drive circuit of the second delay means and the buffer circuit are each constituted by a CMOS inverter. And said delay circuit, said counter binary code is stored which determines the delay amount of the delay circuit, the reference clock frequency and the frequency comparator for comparing the frequency of the signal based on the output output clock from the delay circuit When the semiconductor integrated circuit according to any one of claims 1 to 3, characterized in that the DLL circuit and a control circuit for controlling the value of the counter based on the comparison result of the frequency comparator is provided.

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