JP5707813B2 - Semiconductor integrated circuit for device evaluation - Google Patents

Description

  The present invention relates to an element evaluation semiconductor integrated circuit suitable as an element evaluation TEG (Test Element Group) for highly accurately evaluating the characteristic variation of elements of a large-scale semiconductor integrated circuit manufactured by a miniaturization process.

  With the progress of semiconductor microfabrication, there is an increasing demand for large-scale circuits, low voltages, and power savings of circuits mounted on semiconductor chips. In particular, regarding power saving, the current target of 1/10 is presented in terms of power. However, the degree of variation in transistor characteristics has increased due to miniaturization, and the influence of transistor characteristic variations on circuit operation has increased due to lower voltage. It has become difficult to manufacture at a high yield. Therefore, as means for acquiring information used for semiconductor process optimization control, means for manufacturing an element evaluation semiconductor integrated circuit having a large number of elements and performing the evaluation is used. As an example of this kind of element evaluation semiconductor integrated circuit, a circuit having a large-scale inverter chain, specifically, a circuit having a ring oscillator in which a large number of inverters are connected in multiple stages as illustrated in FIG. Alternatively, as illustrated in FIG. 13, there are some in which a large number of inverters are arranged in a matrix over the entire surface of the semiconductor chip.

Presentation material of STARC Forum / Symposium held on August 25, 2009 "Trump card for greening: ultra-low power circuit / system technology", Speaker: The University of Tokyo, Takayasu Sakurai, Semiconductor Science and Engineering Research Center, Shinohara History

  According to the conventional semiconductor integrated circuit for element evaluation described above, the inverter chain is operated under various operating conditions such as the power supply voltage, and the operation of the inverter chain is confirmed. It is possible to make a global evaluation from the viewpoint of whether or not the electrical characteristics are appropriate as a whole. However, as reported in Non-Patent Document 1, for example, even in a logic circuit having a relatively wide operation margin, under extremely low voltage conditions, due to local variations in transistor characteristics, etc. Part of the circuit (inverter or the like) becomes inoperable, which makes the entire chip defective. Therefore, in order to investigate the cause of the failure of the entire chip, it is necessary to specify a circuit such as an inoperable inverter and evaluate the electrical characteristics of the circuit in detail. However, in the above-described conventional semiconductor integrated circuit for element evaluation, for example, when the power supply voltage of the ring oscillator in FIG. 12 is lowered, the fourth inverter from the left becomes inoperable and the oscillation of the ring oscillator stops. In this case, even though the fact that the oscillation has stopped can be confirmed, it cannot be determined that the fourth inverter is inoperable. The same applies to the element evaluation semiconductor integrated circuit of FIG. As described above, the conventional device evaluation semiconductor integrated circuit can perform an operation analysis using a large-scale inverter chain. However, since there are a large number of inverters, it is possible to identify the inverter causing the failure. The transistor characteristics of the inverter could not be investigated.

  The present invention has been made in view of the above-described circumstances, and has a large-scale gate chain composed of logic gates such as inverters, and identifies a logic gate causing a defect in the gate chain. An object of the present invention is to provide a semiconductor integrated circuit for device evaluation that is easy to implement.

  The present invention relates to a monitor unit comprising a gate chain composed of a plurality of logic gates connected in multiple stages, a monitor signal line, an output node of each logic gate in the gate chain, and the monitor signal line. When a control signal instructing is given, a plurality of monitor units for generating a signal depending on the voltage of the output node on the monitor signal line, and output nodes of a plurality of logic gates in the gate chain are sequentially monitored. There is provided a semiconductor integrated circuit for element evaluation, comprising: monitor unit selecting means for generating a control signal indicating a monitor unit connected to an output node of a logic gate to be monitored.

  According to this invention, each monitor unit connected to the output node of each logic gate is sequentially selected, and each monitor unit generates a signal depending on the voltage of the output node of each logic gate on the monitor signal line. Therefore, by monitoring the signal generated on the monitor signal line, it is possible to determine which of the plurality of logic gates constituting the gate chain is inoperable.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a partial configuration of a device evaluation semiconductor integrated circuit according to a first embodiment of the present invention; It is a circuit diagram which shows the circuit structural example of the inverter chain in the same embodiment. It is a circuit diagram which shows the structure of the semiconductor integrated circuit for element evaluation which is 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the monitor unit of the semiconductor integrated circuit for element evaluation which is 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the monitor unit of the semiconductor integrated circuit for element evaluation which is 4th Embodiment of this invention. It is a figure explaining the specific example of the monitoring method of the output voltage of the inverter using the monitor unit by the embodiment. It is a circuit diagram which shows the structure of the semiconductor integrated circuit for element evaluation which is 5th Embodiment of this invention. It is a circuit diagram which shows the structure of a part of the semiconductor integrated circuit for the same element evaluation in detail. FIG. 4 is a diagram illustrating a method for measuring input / output transfer characteristics of a desired inverter in the ring oscillator and a method for measuring electrical characteristics of an N-channel transistor and a P-channel transistor in the inverter in the embodiment. It is sectional drawing which shows the structural example of the semiconductor chip of the double WELL structure suitable for the semiconductor integrated circuit for element evaluation by this invention. It is sectional drawing which shows the other structural example of the semiconductor chip of the double WELL structure suitable for the semiconductor integrated circuit for element evaluation by this invention. It is a circuit diagram which shows the structural example of the ring oscillator used for the semiconductor integrated circuit for element evaluation. It is a circuit diagram which shows the structural example of the inverter chain used for the semiconductor integrated circuit for element evaluation.

  Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing a partial configuration of a device evaluation semiconductor integrated circuit according to a first embodiment of the present invention. This element evaluation semiconductor integrated circuit has an inverter chain which is one form of a gate chain, and also has a monitor means for individually detecting the voltage at the output node of each inverter constituting the inverter chain.

  In FIG. 1, the monitor signal line MON is wired so as to pass through the vicinity of each inverter constituting the inverter chain on the semiconductor chip. The monitor signal line MON is connected to a bonding pad provided on the semiconductor chip (not shown in FIG. 1). Therefore, the voltage of the monitor signal line MON can be confirmed from the outside of the semiconductor integrated circuit.

  FIG. 1 also shows two inverters INV1 and INV2 that are arranged in succession as a part of the inverter chain. In the example shown in FIG. 1, a monitor unit MUa is interposed between the output node of the inverter INV1 and the monitor signal line MON. The monitor unit MUa is a circuit that generates a signal depending on the voltage of the output node (in this example, the output node of the inverter INV1) on the monitor signal line MON when a signal instructing the monitor unit MUa is given. . Although not shown, a similar monitor unit MUa is connected to each output node of other inverters constituting the inverter chain.

  As shown in FIG. 1, the monitor unit MUa includes a switch SW and an address match detection unit ADET. Here, the switch SW is a CMOS analog switch composed of a P-channel MOS field effect transistor (hereinafter simply referred to as a P-channel transistor) and an N-channel MOS field effect transistor (hereinafter simply referred to as an N-channel transistor). It is inserted between the output node and the monitor signal line MON.

  Address match signals AX and AY are given to the address match detection unit ADET. Here, the address match signals AX and AY will be described. In the present embodiment, the inverters constituting the inverter chain are arranged in a matrix along the X direction, which is a direction along one side of the semiconductor chip, and the Y direction perpendicular thereto. In the present embodiment, the output node of each inverter indicates the X address indicating the position of the output node along the X direction and the position of the output node along the Y direction. The output node of the inverter to be monitored is specified by the X address and the Y address. In the example shown in FIG. 1, the address match signal AX becomes an active level when the X address of the output node of the inverter to be monitored matches the X address of the output node of the inverter INV1, and the address match signal AY is The active level is obtained when the Y address of the output node of the inverter to be monitored matches the Y address of the output node of the inverter INV1. The address coincidence detection unit ADET is composed of a NAND gate and an inverter in the illustrated example, and is provided with an address coincidence signal indicating the monitor unit MUa, more specifically, the address coincidence signals AX and AY. When both become active levels, a signal for turning on the switch SW is output.

  In the present embodiment, the power supply system that supplies the power supply voltage to the inverter chain and the power supply system that supplies the power supply voltage to circuits (including the monitor unit MUa) other than the inverter chain are separate. In this embodiment, the high-potential power supply voltage VDDC and the low-potential power supply voltage VSSC applied to the inverter chain can be changed independently of the power supply voltages for circuits other than the inverter chain. Therefore, according to this embodiment, it is possible to perform the following characteristic evaluation on the inverter chain.

  That is, the power supply voltage VDDC-VSSC for the inverter chain is lowered in a state where the power supply voltage for the circuits other than the inverter chain is kept sufficiently high. The output node of each inverter constituting the chain is sequentially selected and connected to the monitor signal line MON, and the voltage of the output node of each inverter is confirmed from the outside of the semiconductor integrated circuit via the monitor signal line MON.

  By performing this confirmation, the inverter that causes the operation of the inverter chain to be stopped is found. Specifically, an inverter that does not output an H level when the input signal is at an L level, an inverter that does not output an L level when the input signal is at an H level, or an H level that is not an L level. There is no intermediate level output inverter. If the inverter that causes the operation stop is found, then the electrical cause of the inverter can be examined in detail to investigate the cause of the process that causes the malfunction.

  In order to accurately measure the voltage at the output node of the inverter applied to the monitor signal line MON outside the semiconductor integrated circuit, it is desirable that the ON resistance of the switch SW of the monitor unit MUa is sufficiently small. For this purpose, a circuit other than the inverter chain such as the monitor unit MUa is constituted by a high breakdown voltage transistor, and a circuit other than the inverter chain is operated with a sufficiently high power supply voltage, thereby forming a P-channel transistor constituting the switch SW. It is preferable to apply a sufficiently large gate voltage to the N-channel transistor.

  Various aspects are conceivable regarding the circuit configuration of the inverter chain. FIGS. 2A to 2E show examples thereof. In the example shown in FIG. 2A, the inverter chain is a ring oscillator in which a large number of inverters are connected in a closed loop. In this example, there is no output buffer or bonding pad for extracting a signal from a node in the middle of the ring oscillator to the outside of the semiconductor integrated circuit. Accordingly, the switch SW of one of the monitor units MUa is turned on to output the signal of the node in the middle of the ring oscillator to the monitor signal line MON, and the signal waveform of the monitor signal line MON is observed from outside the semiconductor integrated circuit, It will be confirmed whether or not the ring oscillator is oscillating.

  In the example shown in FIG. 2B, an output buffer OB and a bonding pad for taking out a signal at a node in the middle of the ring oscillator to the outside of the semiconductor integrated circuit are provided. In this case, in order to obtain the operating limit of the ring oscillator, the power supply voltage of the ring oscillator is lowered while the power supply voltage of the circuit other than the ring oscillator (including the output buffer OB) is kept high. The one with level shift function is used.

  In the example shown in FIG. 2C, an input signal IN from the outside of the semiconductor integrated circuit is input to the inverter chain via the bonding pad and the input buffer IB, and the output signal of the inverter chain is input via the output buffer OB and the bonding pad. So that it is output to the outside of the semiconductor integrated circuit. In this configuration, the expected value of the voltage at the output node of each inverter constituting the inverter chain can be changed by changing the external input signal IN. Therefore, there is an advantage that a more detailed investigation can be performed regarding the operation limit of the inverter chain. As in the case of FIG. 2B, the output buffer OB having a level shift function is also used in the configuration of FIG.

  In the example of FIG. 2D, a NAND gate is inserted in the middle of the ring oscillator, and the ring oscillator can be oscillated or stopped by an enable signal EN given from the outside. In this case, the NAND gate includes two N-channel transistors connected in series between the output node and the low potential power supply line. Therefore, it is preferable that the two N-channel transistors of the NAND gate have a sufficiently large transistor size so that the NAND gate does not cause the ring oscillator to stop operating.

  In the example shown in FIG. 2 (e), the input signal to the head inverter is used as the output signal of the last inverter at the head of the inverter chain in which the inverters are connected in multiple stages, or the input signal is given from the outside of the semiconductor integrated circuit. A switch is provided for switching between IN and IN based on a selection signal SEL given from the outside. This switch is constituted by, for example, a CMOS analog switch. The input buffer IB that drives the switch based on the selection signal SEL is supplied with a sufficiently high power supply voltage independent of the power supply voltage of the inverter chain. According to this configuration, it is possible to switch between operating the inverter chain as a ring oscillator or responding to the input signal IN. Therefore, there is an advantage that a more detailed investigation can be performed regarding the operation limit of the inverter chain. Also, with this configuration, a sufficiently large gate voltage is applied to the P-channel transistor and N-channel transistor that constitute the switch, so that the switch can be prevented from causing the inverter chain to stop operating. The output buffer OB in FIGS. 2B and 2C is configured by level shift in this example, but it is necessary to set so that the operation margin is not determined by this level shift. When a highly accurate evaluation device is used, it may be replaced with a general output buffer.

Second Embodiment
FIG. 3 is a circuit diagram showing a configuration of an element evaluation semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 3, the inverter chain 100 has L pieces arranged in a matrix along the X direction (the direction from the top to the bottom in FIG. 3) and the Y direction (the direction from the left to the right in FIG. 3) of the semiconductor chip. (L is an odd number) inverters. Here, each inverter in the inverter chain 100 is connected to the output terminal and the input terminal of the inverters adjacent to each other so as to form one closed loop as a whole, thereby forming a ring oscillator. All inverters in the inverter chain 100 are supplied with the high potential power supply voltage VDDC and the low potential power supply voltage VSSSC through dedicated electrodes (bonding pads) and power supply lines.

  The monitor signal line MON is wired on the semiconductor chip along each inverter constituting the inverter chain 100, and is connected to a bonding pad as a monitor electrode. A monitor unit MU is interposed between the output node of each inverter of the inverter chain 100 and the monitor signal line MON. The monitor unit MU is a circuit that generates a signal depending on the voltage of the output node of the inverter to be monitored on the monitor signal line MON, and may be the monitor unit MUa of the first embodiment described above, which is a third embodiment described later. The monitor unit MUb of the embodiment or the monitor unit MUc of the fourth embodiment may be used.

  In the region occupied by the inverter chain 100, the output nodes of the inverters arranged in the X direction and the Y direction have an X address indicating which output node the output node is along the X direction, and the output node. Has a Y address indicating the number of the output node along the Y direction. In the region occupied by the inverter chain 100, n Y address match lines AY (j) (j = 0 to n−1), which are arranged apart from each other in the Y direction and extend in the X direction, and X M X address coincidence lines AX (i) (i = 0 to m−1) arranged in the direction away from each other and extending in the Y direction are wired. Here, each Y address match line AY (j) (j = 0 to n−1) is connected to each monitor unit MU connected to each output node of a maximum of m inverters whose Y address is j. And serves as the Y address match line AY of FIG. Each X address match line AX (i) (i = 0 to m−1) is connected to each monitor unit MU connected to each output node of a maximum of n inverters whose X address is i. Thus, it plays the role of the X address match line AX in FIG.

  The monitor address generation unit MAGA is a circuit that generates the X address and the Y address of the output node of the inverter to be monitored among the inverters of the inverter chain 100. The monitor address generator MAGA is connected to a bonding pad that is a mode electrode and a bonding pad that is a clock electrode. The monitor address generation unit MAGA is supplied with a mode designation signal via a mode electrode and a clock via a clock electrode.

  When the mode designation signal is “0”, the monitor address generator MAGA does not count the clock and sets both the X address and the Y address to 0. On the other hand, when the mode designation signal is “1”, the monitor address generator MAGA counts the clock and updates the X address and the Y address based on the count value.

  Y decoder YDECj (j = 0 to n−1) is arranged along the Y direction and is connected to Y address match line AY (j) (j = 0 to n−1), respectively. A decoding circuit is configured. The Y address is supplied from the monitor address generator MAGA to each Y decoder YDECj (j = 0 to n−1). Each of the Y decoders YDECj (j = 0 to n−1) sets the Y address match line AY (j) to the active level when the Y address is j. The X decoder XDECi (i = 0 to m−1) is arranged along the X direction and is connected to the X address coincidence line AX (i) (i = 0 to m−1), respectively. A decoding circuit is configured. Each X decoder XDECi (i = 0 to m−1) is supplied with an X address from the monitor address generator MAGA. Each of the X decoders XDECi (i = 0 to m−1) sets the X address matching line AX (i) to an active level when the X address is i.

  Various aspects are conceivable regarding the configuration of the monitor address generator MAGA. In a preferred embodiment, the monitor address generator MAGA includes an n-ary counter that repeatedly counts from 0 to n-1 in synchronization with the clock, and a count value of the n-ary counter when the count value returns from n-1 to 0. An m-ary counter that repeatedly counts from 0 to m−1 in synchronization with the clock is provided. Here, the n-ary counter and the m-ary counter are in a reset state when the mode designation signal is “0”, and count the clock when the mode designation signal is “1”. Then, the count value of the n-ary counter is output as it is as the Y address, and the count value of the m-ary counter is output as it is as the X address.

  In the inverter chain 100, consecutive n inverters forming a part of the ring oscillator are sequentially arranged from left to right in the top row, and the next consecutive n inverters are sequentially arranged from left to right in the second row. When the inverters are arranged in the raster scan order, such a monitor address generator MAGA is convenient. In this case, when the X address and the Y address sequentially output by the monitor address generation unit MAGA are used, the output node of the first inverter, the output node of the second inverter, the output node of the third inverter in the ring oscillator,. In other words, the output nodes of the inverters are sequentially connected to the monitor signal line MON in accordance with the signal propagation order in the ring oscillator. Accordingly, the voltage at the output node of each inverter is confirmed outside the semiconductor integrated circuit in accordance with the signal propagation order in the ring oscillator, and the output signal of each inverter is regularly leveled such as H level, L level, H level,. It is possible to easily confirm whether the operation is reversed or the operation abnormality deviates from such regularity.

  However, as shown in FIG. 3, when the inverters constituting the ring oscillator are not arranged in the raster scan order, if the monitor address generation unit MAGA as described above is used, what is the signal propagation order in the ring oscillator? In a different order, the output node of each inverter is selected and connected to the monitor signal line MON. For example, in the example of FIG. 3, in the ring oscillator, the inverter at the next stage of the rightmost inverter in the uppermost row is the rightmost inverter in the lower row. However, when connection control to the monitor signal line MON of the output node of the inverter is performed according to the X address and Y address generated by the monitor address generator MAGA, the output node of the rightmost inverter on the uppermost row is connected to the monitor signal line MON. After that, the output node of the leftmost inverter in the lower row is connected to the monitor signal line MON.

  Accordingly, when it is necessary to check the voltage of the output node of each inverter in accordance with the signal propagation order in the ring oscillator, the output node of each inverter that is output to the outside of the semiconductor integrated circuit via the monitor signal line MON. It is necessary to rearrange the voltages so that they are in the order of signal propagation in the ring oscillator.

  In another preferred embodiment, the monitor address generation unit MAGA includes an L-ary counter and an address conversion circuit that counts from 0 to L-1 in synchronization with the clock. Here, when the predetermined inverter in the ring oscillator is the 0th inverter, the count value of the L-ary counter is the inverter number of the inverter to be monitored along the signal propagation direction in the ring oscillator. Indicates whether or not The address conversion circuit converts the count value indicating the rank of the inverter to be monitored into a set of X address and Y address of the output node of the inverter. Such an address conversion circuit can be constituted by a ROM, for example.

  According to this aspect, even when the inverters constituting the ring oscillator are not arranged in the raster scan order, the voltage of the output node of each inverter is output to the outside of the semiconductor integrated circuit according to the signal propagation order in the ring oscillator. Can do.

  In the above configuration, the monitor address generation unit MAGA, the Y decoder YDECj (j = 0 to n−1), and the X decoder XDECi (i = 0 to m−1) are connected to the output node of the logic gate to be monitored. Monitor unit selection means for generating a control signal for instructing the monitor unit MU. Then, a control circuit other than the inverter chain 100, specifically, each circuit constituting the monitor unit selection means and m × n monitor units MU are provided with bonding pads and power lines different from those for the inverter chain 100. The high-potential power supply voltage VDD and the low-potential power supply voltage VSS are supplied through the vias. Therefore, according to this embodiment, it is possible to perform the following characteristic evaluation on the inverter chain 100.

  First, the mode designation signal is set to “0”. Then, the power supply voltage VDDC-VSSC for the inverter chain 100 is gradually lowered in a state where the power supply voltage VDD-VSS for the circuits other than the inverter chain 100 is maintained sufficiently high. During this time, the oscillation operation of the inverter chain 100 which is a ring oscillator is confirmed. Specifically, the voltage at the output node of the first inverter of the ring oscillator output to the outside of the semiconductor integrated circuit via the monitor signal line MON is observed.

  When it is confirmed from the output signal waveform of the monitor electrode that the oscillation of the ring oscillator has stopped, the power supply voltage VDDC-VSSC for the ring oscillator is fixed, and the mode designation signal is set to “1”. As a result, the output nodes of the inverters constituting the ring oscillator are sequentially selected and connected to the monitor signal line MON, and the voltage of the output node of each inverter is output to the outside of the semiconductor integrated circuit. By checking the voltage of each output node, the inverter that causes the ring oscillator to stop is obtained. By examining the electrical characteristics of the inverter in detail, the cause of the process causing the malfunction is investigated.

<Third Embodiment>
In the present embodiment, the monitor unit MUb shown in FIG. 4 is used as the monitor unit MU in the second embodiment (FIG. 3). As shown in the figure, the monitor unit MUb is composed of two N-channel transistors NTY and NTX inserted in series between the output node of each inverter constituting the inverter chain and the monitor signal line MON.

  Here, the gate of the N channel transistor NTY is connected to the address match line AY which is one of the address match lines AYj (j = 0 to n−1) in FIG. 3, and the gate of the N channel transistor NTX is the address in FIG. It is connected to an address match line AX which is one of the match lines AXi (i = 0 to m−1).

  In the monitor unit MUb, when both the address match lines AY and AX are at the active level, both the N-channel transistors NTY and NTX are turned on, and the output node of the inverter (inverter INV1 in the example of FIG. 4) is N-channel. Transistors NTY and NTX are connected in series to monitor signal line MON. Therefore, the voltage at the output node of the inverter designated by the X address and the Y address can be confirmed from the monitor electrode in FIG.

  Here, in the state where the voltage VDD which is the active level is output to the address match lines AY and AX and the N-channel transistors NTY and NTX are ON, the upper limit of the level of the mode signal line MON is N-channel from the voltage VDD. The voltage VDD−Vthn is obtained by subtracting the threshold voltage Vthn of the transistor. This is because when the voltage of the mode signal line MON becomes equal to or higher than the voltage VDD-Vthn, the gate-source voltages of the N-channel transistors NTY and NTX become Vthn or lower and the N-channel transistors NTY and NTX are turned off. Therefore, when the voltage range that can be taken by the output node of the inverter is 0V to VDDC, the gates of the N-channel transistors NTY and NTX are used so that the voltage of the output node of the inverter can be accurately measured in this entire range. The power supply voltage VDD as a voltage is required to be higher than the inverter chain power supply voltage VDDC by a threshold Vthn or more.

  Further, since a high voltage is applied to the N-channel transistors NTY and NTX and the peripheral circuit for controlling the gate voltage thereto, for example, a 1.8V high voltage transistor is used rather than a 0.5V low voltage transistor. Is preferred.

<Fourth embodiment>
The monitor unit MUa in FIG. 1 and the monitor unit MUb in FIG. 4 connect the output node of the inverter to be monitored to the monitor signal line MON and directly output the output voltage of the inverter to the monitor signal line MON. It was. Since the monitoring method using these monitor units MUa and MUb outputs the output voltage of the inverter to the monitor electrode, the output voltage of the inverter to be monitored can be measured with high accuracy. However, when the monitor unit MUa or MUb connects the monitor signal line MON to the output node of the inverter, the wiring parasitic capacitance of the monitor signal line MON becomes a load on the inverter, which may affect the measurement of the ring oscillator. is there. For example, when the output node of one inverter of the ring oscillator is connected to the monitor signal line MON by the monitor unit MUa or MUb and the output waveform of the inverter during the oscillation of the ring oscillator is observed via the monitor signal line, the monitor In some cases, the wiring parasitic capacitance interposed in the signal line MON affects the oscillation operation of the ring oscillator. In addition, in the state where the oscillation of the ring oscillator is stopped due to the decrease of the power supply voltage VDDC, when monitoring by switching the output node of each inverter of the ring oscillator sequentially, the monitor signal line MON is disconnected from the output node of a certain inverter each time the switching is performed. As a result, the monitor signal line MON is connected to the output node of another inverter. At that time, noise is given to the output node of the inverter, and the voltage of the output node of each inverter may change. The present embodiment addresses this problem.

  In the present embodiment, the monitor unit MUc shown in FIG. 5 is used as the monitor unit MU in the second embodiment (FIG. 3). As shown in FIG. 5, the monitor unit MUc in the present embodiment includes an N-channel transistor MONT and a decode switch DSW.

  Here, the N-channel transistor MONT has a gate connected to the output node of the inverter to be monitored (inverter INV1 in the example of FIG. 5), and a source connected to the power supply line VSN. The power supply line VSN is connected to a bonding pad for supplying the low potential power supply voltage VSS to a circuit other than the inverter chain, for example.

  The decode switch DSW is interposed between the drain of the N-channel transistor MONT and the monitor signal line MON. The decode switch DSW is constituted by a circuit including, for example, the address match detection unit ADET and the switch SW shown in FIG. More specifically, the decode switch DSW of the monitor unit MUc has a switch SW interposed between the drain of the N-channel transistor MONT and the monitor signal line MON, and an address match detection unit ADET. Here, the address match detection unit ADET turns on the switch SW and connects the drain of the N-channel transistor MONT to the monitor signal line MON when both of the address match signals AY and AX become active levels.

  In a state where the monitor signal line MON is connected to the drain of the N channel transistor MONT, a drain current can be supplied from the monitor electrode to the N channel transistor MONT via the monitor signal line MON. At that time, the conductance of the N-channel transistor MONT increases depending on the voltage of the output node of the inverter to be monitored. Therefore, for example, when an output node of one inverter in a ring oscillator is to be monitored and the ring oscillator is operated, by applying a predetermined voltage to the monitor electrode and monitoring a change in current flowing from the monitor electrode, the ring oscillator Whether or not the oscillation is normal can be monitored from the outside of the semiconductor integrated circuit. In this state, since only the N-channel transistor MONT is connected to the output node of the inverter to be monitored in addition to the subsequent inverter, the load on the inverter is light and the influence on the operation of the ring oscillator is small. Therefore, the lower limit value of the power supply voltage VDDC that becomes the oscillation limit of the ring oscillator can be obtained without greatly affecting the operation of the ring oscillator.

  When the power supply voltage VDDC is lowered and the oscillation of the ring oscillator is stopped, the voltage applied to the monitor electrode (≈drain voltage of the N-channel transistor MONT) and the monitor electrode are switched for each inverter while switching the inverter to be monitored. The current flowing into the transistor (= drain current of the N-channel transistor MONT) may be measured. Here, if the characteristics (for example, VG-ID characteristics) of a transistor having the same size as the transistor MONT prepared separately are measured, the voltage at the output node of the inverter to be monitored can be estimated from the measurement result. it can. Here, even if the output node of the inverter to be monitored is switched, the load state of each inverter of the ring oscillator does not change. Therefore, switching of the monitoring target does not adversely affect the state of the ring oscillator.

  Next, a specific example of a method for monitoring the output voltage of the inverter using the monitor unit MUc according to the present embodiment will be described with reference to FIG. FIG. 6A is a diagram illustrating the relationship between the gate voltage VCG and the drain current Id when the back gate bias is 0 V in the N-channel transistor MONT. In the monitoring method shown in FIG. 6B, the voltage VD = 0.05 V is applied to the drain of the N channel transistor MONT via the monitor electrode and the decode switch DSW, and the N channel transistor MONT is supplied via the power line VSN. A voltage VS = 0 V is applied to the source. Here, the voltage VD applied through the monitor electrode is set to a low voltage of 0.05 V because the coupling capacitance between the drain and the gate of the N-channel transistor MONT when the ON / OFF of the decode switch DSW is switched. This is to minimize switching noise propagating to the output node of the inverter in the inverter chain.

  In the example shown in FIGS. 6A and 6B, when the VCG-Id characteristic shown in FIG. 6A is known, the current Id1 flowing through the monitor electrode as shown in FIG. 6A is shown as an example. Can be estimated from the current Id1 that the output voltage VCG of the monitored inverter is 0.3V.

  By the way, in the region where the output voltage VCG of the inverter to be monitored is equal to or lower than the threshold voltage Vthn of the N-channel transistor MONT, the drain current Id of the N-channel transistor MONT is 0 as shown in FIG. Therefore, in this region, the output voltage VCG of the inverter cannot be estimated based on the current flowing from the monitor electrode.

  Therefore, in order to accurately measure the output voltage of the inverter to be monitored over a wide range, a negative back gate bias is applied to the N-channel transistor MONT so that the effective threshold voltage of the N-channel transistor MONT is 0 V or less. give. In the example shown in FIG. 6D, while the substrate voltage VB is 0V, the source voltage VSN of the N-channel transistor MONT is set to −0.2V, and a back gate voltage VSB of −0.2V is generated. The effective threshold voltage of the N channel transistor MONT is lowered to 0V or less. Further, as the source voltage VSN of the N-channel transistor MONT is set to −0.2V, the drain voltage VD applied from the monitor electrode is set to −0.15V. By doing so, as illustrated in FIG. 6C, the drain current Id flows to the N-channel transistor MONT even when the output voltage VCG of the inverter is 0V, and the output voltage VCG of the inverter is 0V or more. In a wide range, the drain current Id increases linearly as the output voltage VCG increases. Therefore, the output voltage VCG of the inverter can be accurately estimated from the drain current Id in a wide range. In the example shown in FIG. 6C, the weak drain current Id2 flowing through the monitor electrode is measured, and the output voltage VCG of the inverter to be monitored is estimated to be 0.05 V from this drain current Id2.

  Since the forward voltage VF between the n + diffusion layer forming the source of the N channel transistor MONT and the substrate is about 0.6 V, the back gate voltage applied to the N channel transistor MONT is equal to or less than this forward voltage. It is preferable.

<Fifth Embodiment>
FIG. 7 is a circuit diagram showing a configuration of an element evaluation semiconductor integrated circuit according to a fifth embodiment of the present invention. FIG. 8 is a circuit diagram showing in detail the configuration of a part of the element evaluation semiconductor integrated circuit. In the present embodiment, the input / output transmission characteristics of each inverter constituting the inverter chain 100 and the electrical characteristics of the N-channel transistor and the P-channel transistor constituting each inverter can be individually measured. This is a modification of the embodiment.

  In the present embodiment, as a power supply system for supplying a power supply voltage to the inverter chain 100, each electrode (bonding pad) for supplying a high potential power supply voltage VD1 and a low potential power supply voltage VS1 and a power supply line connected thereto. And a second power supply system consisting of electrodes (bonding pads) for supplying the high potential power supply voltage VD2 and the low potential power supply voltage VS2 and a power supply line connected to these electrodes. Is provided. Each power supply line for supplying power supply voltages VD1, VD2, VS1, and VS2 is wired along each row of inverters constituting inverter chain 100. In the present embodiment, two monitor electrodes are provided, and monitor signal lines MON1 and MON2 connected to the monitor electrodes are wired along each row of the inverters constituting the inverter chain 100.

  As in the second embodiment, each inverter in the inverter chain 100 constitutes a ring oscillator. Each inverter constituting the ring oscillator has a serial number along the signal propagation direction in the ring oscillator. In the example shown in FIG. 7, the upper left inverter is the first inverter in the ring oscillator. When each inverter is counted in order from the first inverter along the signal propagation direction of the ring oscillator, the odd-numbered inverter monitors between the output node of the inverter and the mode signal line MON1. The unit MU is inserted, and in the even-numbered inverter, the monitor unit MU is inserted between the output node of the inverter and the mode signal line MON2. Here, the monitor unit MU is, for example, the monitor unit MUa shown in FIG. 1 or the monitor unit MUb shown in FIG. The odd-numbered inverter is supplied with the high-potential power supply voltage VD1 and the low-potential power-supply voltage VS1 through the first power supply system, and the even-numbered inverter is supplied with the high potential power supply voltage VS1 through the second power supply system. Potential power supply voltage VD2 and low potential power supply voltage VS2 are applied.

  In the region occupied by the inverter chain 100, n Y address match line pairs AYo (j) (j = 0 to n−1) and AYe (j) (j = 0) are separated from each other along the Y direction. To n-1) are wired. In the region occupied by the inverter chain 100, m sets of X address matching line pairs AXo (i) (i = 0 to m−1) and AXe (i) (i) are separated from each other along the X direction. = 0 to m-1) are wired. Here, the Y address match line pairs AYo (j) and AYe (j) of each set are wired so as to sew the vicinity of each output node of each inverter whose Y address is j. Among these inverters whose Y address is j, the monitor unit MU connected to the output node of the ring oscillator which is an odd-numbered inverter is connected to the Y-address matching line AYo (j), and even-numbered The Y address match line AYe (j) is connected to the monitor unit MU connected to the output node of the inverter. Each pair of X address match line pairs AXo (i) and AXe (i) is wired so as to sew the vicinity of each output node of each inverter whose X address is i. Among these inverters whose X address is i, which is an odd numbered inverter in the ring oscillator, an X address match line AXo (i) is connected to the monitor unit MU connected to the output node, and even numbered An X address match line AXe (i) is connected to the monitor unit MU connected to the output node of the inverter.

  In the present embodiment, for one type of Y address j, two Y address match lines AYo (j) and AYe (j) are provided, for example, for the leftmost inverter in the top row of the inverter chain of FIG. This is because it is possible to simultaneously monitor two output nodes having the same Y address, such as a set of output nodes and the output node of the leftmost inverter in the lower row. In addition, for one type of X address i, two X address match lines AXo (i) and AXe (i) are provided, for example, with the output node of the leftmost inverter in the top row of the inverter chain of FIG. This is because it is possible to simultaneously monitor two output nodes having the same X address, such as a set of output nodes of the inverter on the right side. A circuit for selecting the monitoring target will be described later.

  FIG. 8 shows the connection state between the individual inverters in the inverter chain 100, the monitor unit MU, and the monitor signal lines MON1 and MON2, the relationship between the inverters and the power supply voltages VD1, VD2, VS1, and VS2 supplied thereto, The connection state between the monitor unit MU and the address match lines AYo (j), AYe (j), AXo (i), and AXe (i) is illustrated in detail. In FIG. 8, INV1 to INV4 are four inverters arranged from the left end of the uppermost row in FIG. The X addresses i of the output nodes of these inverters INV1 to INV4 are all “0”. The Y address j of each output node of the inverters INV1 to INV4 is “0” to “3”, respectively.

  Here, inverters INV1 and INV3 are odd-numbered inverters in the ring oscillator. Accordingly, the monitor unit MU1 is interposed between the output node of the inverter INV1 and the monitor signal line MON1, and the monitor unit MU3 is interposed between the output node of the inverter INV3 and the monitor signal line MON1. The monitor unit MU1 is connected with address match lines AYo (0) and AXo (0), and the monitor unit MU3 is connected with address match lines AYo (2) and AXo (0). The inverters INV1 and INV3 are supplied with a high potential power supply voltage VD1 and a low potential power supply voltage VS1.

  On the other hand, inverters INV2 and INV4 are even-numbered inverters in the ring oscillator. Accordingly, the monitor unit MU2 is interposed between the output node of the inverter INV2 and the monitor signal line MON2, and the monitor unit MU4 is interposed between the output node of the inverter INV4 and the monitor signal line MON2. The address match lines AYe (1) and AXe (0) are connected to the monitor unit MU2, and the address match lines AYe (3) and AXe (0) are connected to the monitor unit MU4. The inverters INV2 and INV4 are supplied with a high potential power supply voltage VD2 and a low potential power supply voltage VS2.

  In FIG. 7, the monitor address generation unit MAGB is a circuit that generates one or two sets of X and Y addresses of the output node of the inverter to be monitored among the inverters of the inverter chain 100. Two mode electrodes, a clock electrode, and a preset electrode are connected to the monitor address generator MAGB. The monitor address generation unit MAGB is supplied with a mode designation signal via a mode electrode and a clock via a clock electrode.

  When the mode designation signal is “00”, the monitor address generator MAGB does not count the clock, sets the count value of the counter to “0”, and the rank corresponding to this count value = “0” in the ring oscillator ( X address and Y address of the output node of the inverter having No. 1) are generated and output as odd number address data. When the mode designation signal is “01”, the monitor address generator MAGB counts the clock and generates the X address and Y address of the output node of the inverter having the order indicated by the count value in the ring oscillator. When the rank indicated by the count value is an odd number, the generated X address and Y address are output as odd number address data. When the rank is an even number, the generated X address and Y address are even numbers. Output as address data. That is, when the count value is “0”, the X address and Y address of the output node of the first inverter are output as odd-numbered address data in the ring oscillator, and when the count value is “1”, the second inverter The X address and Y address of the output node are output as even-numbered address data, and so on, and so on. The odd-numbered address data or even-numbered address is synchronized with the clock of the X address and Y address of the output node of each inverter in the ring oscillator. It is output sequentially as data.

  When the mode designation signal is “10”, the monitor address generator MAGB receives preset data from the preset electrode, presets it as a count value in a counter that counts the clock, and an inverter having the order indicated by the count value X address and Y address of the output node are generated. When the rank indicated by the count value is an odd number, the generated X address and Y address are output as odd number address data. When the rank is an even number, the generated X address and Y address are even numbers. Output as address data.

  When the mode designation signal is “11”, the monitor address generation unit MAGB receives preset data from the preset electrode, presets it as a count value in a counter that counts the clock, and outputs the inverter of the rank indicated by the count value. The X address and Y address of the node are generated, and the X address and Y address of the output node of the previous inverter are generated. Then, each of the generated two sets of X address and Y address is output as odd number address data or even number address data.

  Y decoders YDECj (j = 0 to n−1) are arranged along the Y direction, and Y address match lines AYo (j) (j = 0 to n−1) and AYe (j) (j = 0 to n). -1) are connected to each other to constitute a Y address decoding circuit as a whole. Each of the Y decoders YDECj (j = 0 to n−1) outputs the Y address when the odd address data is output from the monitor address generator MAGB and the Y address in the odd address data is j. The match line AYo (j) is set to the active level. Each of the Y decoders YDECj (j = 0 to n−1) outputs the even-numbered address data from the monitor address generation unit MAGB and the Y-address in the even-numbered address data is j. The Y address match line AYe (j) is set to the active level.

  The X decoder XDECi (i = 0 to m−1) is arranged along the X direction, and the X address match line pair AXo (i) (i = 0 to m−1) and AXe (i) (i = 0 to 0). m-1) are connected to each other to constitute an X address decoding circuit as a whole. Each of the X decoders XDECi (i = 0 to m−1) outputs an X address when the odd address data is output from the monitor address generation unit MAGB and the X address in the odd address data is i. The match line AXo (i) is set to the active level. Each of the X decoders XDECi (i = 0 to m−1) outputs the even-numbered address data from the monitor address generating unit MAGB and the X-address in the even-numbered address data is i. The X address match line AXe (i) is set to the active level.

The feature of this embodiment is the selection operation of the monitor unit when the mode designation signal is “11”. Here, a specific example is given and the selection operation of this monitor unit is demonstrated. First, it is assumed that preset data “0” is supplied to the monitor address generation unit MAGB in a state where the mode designation signal “11” is supplied. In this case, the monitoring target is the output node of the leftmost inverter in the uppermost row of the inverter chain of FIG. 7 and the output node of the leftmost inverter in the lower row. Therefore, the monitor address generator MAGB outputs both the next odd number address data and even number address data.
Odd number address data: X address i = 0, Y address j = 0
Even number address data: X address i = 1, Y address j = 0
As a result, the Y decoder YDEC0 sets the Y address match line AYo (0) to the active level, the X decoder XDEC0 sets the X address match line AXo (0) to the active level, and the output node of the inverter at the left end of the uppermost row is monitored. Connected to signal line MON1. Further, the Y address match line AYe (0) is set to the active level by the Y decoder YDEC0, the X address match line AXe (1) is set to the active level by the X decoder XDEC1, and the output node of the inverter at the left end of the second row is monitored. Connected to signal line MON2.

Next, it is assumed that preset data “1” is supplied to the monitor address generation unit MAGB in a state where the mode designation signal “11” is supplied. In this case, the monitoring target is the output node of the leftmost inverter in the uppermost row of the inverter chain of FIG. 7 and the output node of the inverter on the right side thereof. Therefore, the monitor address generator MAGB outputs both the next odd number address data and even number address data.
Odd number address data: X address i = 0, Y address j = 0
Even number address data: X address i = 0, Y address j = 1
As a result, the Y decoder YDEC0 sets the Y address match line AYo (0) to the active level, the X decoder XDEC0 sets the X address match line AXo (0) to the active level, and the output node of the inverter at the left end of the uppermost row is monitored. Connected to signal line MON1. The Y address match line AYe (1) is set to the active level by the Y decoder YDEC1, and the X address match line AXe (0) is set to the active level by the X decoder XDEC0. The output node of the second inverter from the leftmost row Is connected to the monitor signal line MON2.

  In the above configuration, the control circuit other than the inverter chain 100 is supplied with the high potential power supply voltage VDD and the low potential power supply voltage VSS via a bonding pad and a power supply line different from those for the inverter chain 100.

  Next, an example of an evaluation method for the device evaluation semiconductor integrated circuit according to the present embodiment will be described. First, the mode designation signal is set to “00”. Then, the power supply voltages VD1-VS1 and VD2-VS2 for the inverter chain 100 are gradually lowered while maintaining the power supply voltage VDD-VSS for the circuits other than the inverter chain 100 sufficiently high. During this time, the oscillation operation of the inverter chain 100 which is a ring oscillator is confirmed. Specifically, the voltage of the output node of the first inverter of the ring oscillator output to the outside of the semiconductor integrated circuit via the monitor signal line MON1 is observed.

  When it is confirmed from the output signal waveform of the monitor electrode that the oscillation of the ring oscillator has stopped, the power supply voltages VD1-VS1 and VD2-VS2 for the ring oscillator are fixed, and the mode designation signal is set to “01”. As a result, the output nodes of the inverters constituting the ring oscillator are sequentially selected, the output nodes of the odd-numbered inverters are connected to the monitor signal line MON1, and the output nodes of the even-numbered inverters are connected to the monitor signal line MON2. The voltage at the output node of each inverter is output outside the circuit. By checking the voltage of each output node, the rank of the inverter which is in an inoperable state and causes the ring oscillator to stop is obtained.

  If the rank of the inverter that is inoperable in the ring oscillator is found, if you want to check the output voltage of the inverter just in case, set the mode designation signal to “10” and count that indicates the rank of the inverter. A value (data obtained by subtracting 1 from the rank) is given as preset data from the preset electrode to the monitor address generator MAGB. As a result, the output node of the inverter is connected to the monitor signal line MON1 or MON2. Therefore, the output voltage of the inverter can be confirmed.

  Next, a method for measuring input / output transfer characteristics of a desired inverter in a ring oscillator and a method for measuring electrical characteristics of N-channel transistors and P-channel transistors in the inverter will be described with reference to FIG.

  When the inverter to be measured is, for example, the inverter INV2 in FIG. 8, since this inverter INV2 is an even-numbered inverter, the power supply voltages VD2 and VS2 are given, and the power supply voltage VD1 and the inverters before and after that are supplied. VS1 is given. Therefore, the power supply voltages VD1 and VS1 are turned off to open the power supply lines for supplying the power supply voltages VD1 and VS1. Then, the mode designation signal is set to “11”, and the count value “1” corresponding to the rank of the inverter INV2 is given as preset data to the monitor address generator MAGB. As a result, the X address and Y address of the output node of the inverter INV1 are output as odd-numbered address data from the monitor address generator MAGB, and the X address and Y address of the output node of the inverter INV2 are output as even-numbered address data. As a result, the output node of the inverter INV1 (that is, the input node of the inverter INV2 to be measured) is connected to the monitor signal line MON1 via the monitor unit MU1, and the output node of the inverter INV2 to be measured is connected to the monitor unit MU2. To the monitor signal line MON2. In this state, the output voltage VOUT (that is, the output voltage of the inverter INV2) that is output to the monitor output line MON2 is changed while the input voltage VIN (that is, the input voltage of the inverter INV2) that is externally applied to the monitor signal line MON1 is changed. If observed from the outside, the input / output transfer characteristics of the inverter INV2 can be obtained.

  When the inverter to be measured is, for example, the inverter INV3 in FIG. 8, since this inverter INV3 is an odd-numbered inverter, the power supply voltages VD1 and VS1 are given. VS2 is given. Therefore, the power supply voltages VD2 and VS2 are turned off, and the power supply lines for supplying the power supply voltages VD2 and VS2 are opened. Then, the mode designation signal is set to “11”, and the count value “2” corresponding to the rank of the inverter INV3 is given as preset data to the monitor address generating unit MAGB. As a result, the X address and Y address of the output node of the inverter INV3 are output as odd number address data from the monitor address generator MAGB, and the X address and Y address of the output node of the inverter INV2 are output as even number address data. As a result, the output node of the inverter INV2 (that is, the input node of the inverter INV3 to be measured) is connected to the monitor signal line MON2 via the monitor unit MU2, and the output node of the inverter INV3 to be measured is connected to the monitor unit MU3. To the monitor signal line MON1. In this state, the output voltage VOUT (that is, the output voltage of the inverter INV3) that is output to the monitor output line MON1 is changed while the input voltage VIN (that is, the input voltage of the inverter INV3) that is externally applied to the monitor signal line MON2 is changed. If observed from the outside, the input / output transfer characteristics of the inverter INV3 can be obtained.

  Next, a method for measuring the electrical characteristics of the transistor will be described. When the measurement target is the P-channel transistor TP2 of the inverter INV2, the power supply voltages VD1 and VS1 are turned off and the output node of the inverter INV1 is connected via the monitor unit MU1 as in the case of measuring the input / output transfer characteristics of the inverter INV2. Connected to the monitor signal line MON1, the output node of the inverter INV2 is connected to the monitor signal line MON2 via the monitor unit MU2. Further, the power supply voltage VS2 is turned off to open the drain current flow path of the N-channel transistor TN2. In this state, the gate voltage Vg is applied to the P channel transistor TP2 from the outside via the monitor signal line MON1, and the drain voltage Vd is applied to the P channel transistor TP2 via the monitor signal line MON2. Then, the drain current flowing from the outside to the P-channel transistor TP2 via the monitor signal line MON2 is measured.

  On the other hand, when the measurement target is the N-channel transistor TN2 of the inverter INV2, as in the case of the P-channel transistor TP2, the power supply voltages VD1 and VS1 are turned off, and the output node of the inverter INV1 is monitored via the monitor unit MU1. The output node of the inverter INV2 is connected to the monitor signal line MON2 via the monitor unit MU2. Further, the power supply voltage VD2 is turned off to open the drain current flow path of the P-channel transistor TP2. In this state, a gate voltage Vg is applied from the outside to the N channel transistor TN2 via the monitor signal line MON1, and a drain voltage Vd is applied to the N channel transistor TN2 via the monitor signal line MON2. Then, the drain current flowing from the outside to the N-channel transistor TN2 via the monitor signal line MON2 is measured.

  As described above, according to the present embodiment, when the oscillation of the ring oscillator stops as a result of reducing the power supply voltage to the ring oscillator, it is possible to easily determine the inverter that is inoperable in the ring oscillator. In addition, the input / output transfer characteristics of the inverter and the electrical characteristics of the P-channel transistor and the N-channel transistor constituting the inverter can be easily measured.

<Sixth Embodiment>
FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor chip having a double-WELL structure suitable for an element evaluation semiconductor integrated circuit according to the present invention.

  In this example, an n-type first well DEEP-NWELL is formed on a p-type semiconductor substrate P-Sub. The inner region of the first well DEEP-NWELL is a 0.5V MOS region in which a 0.5V transistor is formed. The region outside the first well DEEP-NWELL is a 1.8V MOS region in which a 1.8V transistor is formed. A p-type second well PWELL shallower than the first well DEEP-NWELL is formed in the first well DEEP-NWELL. On the other hand, in the region where the first well DEEP-NWELL is not formed in the semiconductor substrate P-Sub, the n-type third well NWELL is formed.

  And each transistor which comprises the inverter chain in the said 1st-5th embodiment is formed in the 0.5V type | system | group MOS area | region shown in the right half of FIG. More specifically, the P-channel transistor in the inverter chain is formed in a region where the second well PWELL is not formed in the first well DEEP-NWELL, and the N-channel transistor constituting the inverter chain is the second channel. It is formed in the well PWELL.

  In the first to fifth embodiments, each transistor constituting the control circuit other than the inverter chain is formed in the 1.8 V system MOS region shown in the left half of FIG. More specifically, the P channel transistor constituting the control circuit is formed in the third well NWELL, and the N channel transistor constituting the control circuit is formed in the first well DEEP-NWELL and the semiconductor substrate P-Sub. It is formed in a region where none of the third well NWELL is formed.

  According to such a structure, the transistor in the 1.8V system MOS region and the transistor in the 0.5V system MOS region can be electrically separated, so that the inverter chain can be measured satisfactorily. For example, when this structure is employed in the element evaluation semiconductor integrated circuit of the fourth embodiment (FIG. 5), VSub = VSS = VSN = −0.3V, VDD = 1.8V, VD = −0.25V, VSSC Good measurement can be performed by setting = 0V and VDDC = 0.5V.

  In this example, the N-channel transistor in the 1.8V system MOS region is formed directly on the semiconductor substrate P-Sub. However, for concentration adjustment, another p-type well PWELL is used as shown by a broken line in FIG. And an N-channel transistor may be formed in the p-type well. In this example, a 0.5V P-channel transistor is formed directly in the first well DEEP-NWELL. However, for the purpose of concentration adjustment, as shown by a broken line in FIG. 10, the first well DEEP- Another n-type well NWELL may be formed in the NWELL, and a 0.5 V P-channel transistor may be formed in the well.

<Seventh embodiment>
FIG. 11 is a cross-sectional view showing another configuration example of a semiconductor chip having a double-WELL structure suitable for a device integrated semiconductor integrated circuit according to the present invention. In the sixth embodiment, the p-type substrate P-Sub is used as the semiconductor substrate. On the other hand, in this embodiment, an n-type semiconductor substrate N-Sub is used.

  In this example, a p-type first well DEEP-PWELL is formed in an n-type semiconductor substrate N-Sub. The region inside the first well DEEP-PWELL is a 1.8V MOS region in which a 1.8V transistor is formed. Further, the region outside the first well DEEP-PWELL is a 0.5V MOS region in which a 0.5V transistor is formed. In the first well DEEP-PWELL, an n-type second well NWELL shallower than the first well DEEP-PWELL is formed. On the other hand, a p-type third well PWELL is formed in a region where the first well DEEP-PWELL is not formed in the semiconductor substrate N-Sub.

In the first to fifth embodiments, in the 1.8V N-channel transistor constituting the control circuit other than the inverter chain, the second well NWELL in the first well DEEP-PWELL is not formed. A 1.8V P-channel transistor formed in the region and constituting a control circuit other than the inverter chain is formed in the second well NWELL. The 0.5V N-channel transistor constituting the inverter chain is formed in the third well PWELL, and the 0.5V P-channel transistor constituting the inverter chain is the first in the semiconductor substrate N-Sub. It is formed in a region where neither the well DEEP-PWELL nor the third well PWELL is formed.
Also in this embodiment, the same effect as the sixth embodiment can be obtained.

  In this example, the P-channel transistor in the 0.5V system MOS region is formed directly on the semiconductor substrate N-Sub. However, for concentration adjustment, another n-type well NWELL is used as shown by a broken line in FIG. And a P-channel transistor may be formed in the n-type well. Further, in this example, a 1.8V N-channel transistor is formed directly in the first well DEEP-PWELL. However, in order to adjust the concentration, the first well DEEP- Another p-type well PWELL may be formed in the PWELL, and a 1.8V N-channel transistor may be formed in the well.

Although the first to seventh embodiments of the present invention have been described above, other embodiments are conceivable for the present invention. For example:
(1) As a means for selecting the monitor unit, a shift register having the same number of stages as the number of inverter stages of the inverter chain may be provided. In this aspect, the output signal of each stage of the shift register is supplied to each monitor unit provided at the output node of each inverter of the inverter chain, and the switch of each monitor unit is turned ON / OFF by the output signal of each stage of the shift register. To control. Specifically, after all the stages of the shift register are reset, bit “1” is sequentially shifted to the shift register, and among the output nodes of each inverter, the output nodes connected to the monitor signal line are sequentially switched.
(2) The number of types of combinations of the X address and the Y address may not match the number of inverter stages constituting the inverter chain.
(3) In each of the above embodiments, an inverter chain is used as an example of a gate chain. However, an element evaluation semiconductor integrated circuit is formed using a gate chain in which logic gates other than inverters such as NAND gates and NOR gates are connected in multiple stages. It may be configured.

MUa, MUb, MUc, MU, MU1 to MU4 ... monitor unit, MON, MON1, MON2 ... monitor signal line, SW ... switch, ADET ... address match detector, IB ... input buffer, OB ... output Buffer, 100... Inverter chain, MAGA, MAGB... Monitor address generator, YDECj (j = 0 to n-1)... Y decoder, XDECi (i = 0 to m-1). j) (j = 0 to n-1)... Y address coincidence line, AX (i) (i = 0 to m-1)... X address coincidence line, NTX, NTY, MON... N channel transistor, DSW ...... Decode switch.

Claims (3)

A first high-potential power supply electrode provided on a semiconductor chip and a first high-potential power supply line connected to the first high-potential power supply electrode;
A second high potential power supply electrode provided on the semiconductor chip and a second high potential power supply line connected to the second high potential power supply electrode;
A first low potential power supply electrode provided on the semiconductor chip and a first low potential power supply line connected to the first low potential power supply electrode;
A second low potential power supply electrode provided on the semiconductor chip and a second low potential power supply line connected to the second low potential power supply electrode;
A first monitor electrode provided on the semiconductor chip and a first monitor signal line connected to the first monitor electrode;
A second monitor electrode provided on the semiconductor chip and a second monitor signal line connected to the second monitor electrode;
A plurality of logic gates formed on the semiconductor chip and connected in multiple stages, each logic gate being in one of the extending directions of each side of the semiconductor chip in an X direction and a Y direction orthogonal to the X direction Each of the logic gates is grouped so that one of the two logic gates arranged before and after each other belongs to the first group and the other belongs to the second group. Each logic gate belonging to the first group is supplied with a power supply voltage via the first high-potential power line and the first low-potential power line, and each logic gate belonging to the second group is supplied to the second group. A gate chain that receives supply of power supply voltage via a high potential power supply line and a second low potential power supply line;
A plurality of first switches interposed between each of the output nodes of each logic gate belonging to the first group and the first monitor signal line;
A plurality of second switches interposed between the output nodes of the logic gates belonging to the second group and the second monitor signal line;
A set of a first X address match line corresponding to the first switch and a second X address match line corresponding to the second switch, and a plurality of X address match line pairs arranged in the X direction;
A set of a first Y address match line corresponding to the first switch and a second Y address match line corresponding to the second switch, and a plurality of Y address match line pairs arranged in the Y direction;
Each of the logic gates belonging to the first group is provided in association with an output node of each logic gate, and is connected to one of the plurality of first X address match lines and one of the plurality of first Y address match lines, respectively. A plurality of first address coincidence detections that turn on the first switch connected to the output node by setting both the first X address coincidence line and the first Y address coincidence line to the active level. And
Each of the logic gates belonging to the second group is provided in association with an output node of each logic gate, and is connected to one of the plurality of second X address match lines and one of the plurality of second Y address match lines, respectively. A plurality of second address coincidence detections that turn on the second switch connected to the output node by setting both the second X address coincidence line and the second Y address coincidence line to the active level. And
Monitor address generating means for generating X and Y addresses of output nodes of one or two logic gates to be monitored;
When the logic gate to be monitored belongs to the first group, the logic gate to be monitored is set to the active level of the first X address match line specified by the X address among the plurality of first X address match lines. X address decoding means for setting the second X address match line designated by the X address among the plurality of second X address match lines as an active level,
When the logic gate to be monitored belongs to the first group, the first Y address match line designated by the Y address among the plurality of first Y address match lines is set to the active level, and the logic gate to be monitored Are in the second group, Y address decoding means for setting the second Y address match line designated by the Y address among the plurality of second Y address match lines as an active level;
A semiconductor integrated circuit for device evaluation, comprising: An n-type first well is formed in a p-type semiconductor substrate, a p-type second well shallower than the first well is formed in the first well, and the first well in the semiconductor substrate is formed. An n-type third well is formed in a region where no well is formed,
The P-channel MOS field effect transistor constituting the gate chain is formed in a region of the first well where the second well is not formed, and the N-channel MOS field effect transistor constituting the gate chain is the Formed in the second well,
A P-channel MOS field effect transistor that constitutes a circuit other than the gate chain is formed in the third well, and an N-channel MOS field effect transistor that constitutes a circuit other than the gate chain is formed in the first semiconductor substrate. 2. The element evaluation semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is formed in a region where neither the well nor the third well is formed. A p-type first well is formed in an n-type semiconductor substrate, an n-type second well shallower than the first well is formed in the first well, and the first well in the semiconductor substrate is formed. A p-type third well is formed in a region where no well is formed,
An N channel MOS field effect transistor constituting a circuit other than the gate chain is formed in a region of the first well where the second well is not formed, and a P channel constituting a circuit other than the gate chain. A MOS field effect transistor is formed in the second well;
The N-channel MOS field effect transistor constituting the gate chain is formed in the third well, and the P-channel MOS field effect transistor constituting the gate chain is formed in the first well and the third well in the semiconductor substrate. 2. The semiconductor integrated circuit for element evaluation according to claim 1, wherein the well is formed in a region where none of the wells is formed.

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