JPH0627205A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain the integrated circuit device in which accuracy is enhanced in the operational test of incorporated memory, accuracy is enhanced in the measurement of address access time of the memory, measurement accuracy is prevented from deteriorating due to delay of input signal, and decision of output can be made independently from the accuracy of tester or the delay due to internal wiring. CONSTITUTION:In the semiconductor integrated circuit, a memory 4 is provided on a chip 9 and operational test of the memory 4 is carried out based on an input signal WE to terminal Ti dedicated for test on the chip 9. A memory test circuit 11 outputs a signal CK for activating a latch circuit 7, connected with an output port Po of the memory 4, upon elapse of a predetermined time after provision of a multibit address signal AD to an input port Pi of the memory 4 from the terminal Ti dedicated for test. Output signal from the latch circuit 7 is delivered through an output terminal To of the chip 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory operation test in a semiconductor integrated circuit device having a memory and a logic circuit on the same chip, and configured to control the operation of the memory by the logic circuit in a normal operation. Is.

In recent years, semiconductor integrated circuit devices have become larger in scale, more multifunctional, and faster, so that CPUs and RAs can be mounted on the same chip.
It is common to have a built-in memory such as M or ROM. Also, due to the increase in the size of the chip, the internal wiring is lengthened to increase the wiring capacitance and wiring resistance, and as the wiring capacitance and wiring resistance increase, the operation delay time tends to increase.

In such a semiconductor integrated circuit device, the operation delay time may vary greatly due to process variations due to miniaturization. Therefore, it is required to prevent the deterioration of the accuracy of the operation test due to the variation of the operation delay time.

Further, the variation in the operation delay time is a great impediment factor to guaranteeing the AC characteristics of the built-in memory. Furthermore, it has become difficult for the test circuit of the memory to have the accuracy for guaranteeing the AC characteristic due to the increase in the speed of the memory. Therefore, the development of a measurement method that is not affected by the factors that obstruct the guarantee of the AC characteristic of the memory. Is desired.

[0005]

2. Description of the Related Art In a conventional semiconductor integrated circuit device having a memory on the same chip, a test-dedicated terminal is provided as an external terminal, and an external test device is connected to the test-dedicated terminal to perform a memory operation test. .

That is, an address signal and a write control signal are directly input from an external test device to a memory through a test-dedicated terminal, the same data is written to, for example, a large number of memory cells, and then the data written in the memory is written to the external test device. It is directly read to determine whether each memory cell is operating properly.

During such an operation test, the delay time due to the wiring capacity from the test dedicated input terminal to the memory input port and the delay time due to the wiring capacity from the memory output port to the chip test dedicated output terminal are estimated in advance,
The address signal and write control signal input from the test equipment are added to the memory by adding the estimated delay time, and the external test equipment determines whether the data written in the read operation following the write operation is correct. Has been determined.

[0008]

However, in the semiconductor integrated circuit device as described above, due to its large scale and high integration, wiring from the test-dedicated input terminal to the memory input port and the test from the memory output port to the chip are performed. The wiring to the dedicated output terminal is lengthened, and the variation in wiring capacitance and wiring resistance due to the variation in process is also increasing.

Therefore, it becomes difficult to accurately estimate the delay time due to the wiring from the test-dedicated terminal to the input port of the memory, and between the address signals input from the test apparatus, the data input signal, and the write control signal. There may be a deviation in the input timing to the memory input port.

Similarly, with respect to the output as well, the output timing of the output data output from the test-dedicated output terminal to the external tester is deviated due to the variation in the delay time due to the wiring from the output port of the memory to the test-dedicated output terminal. Sometimes.

Further, the speed of the memory is faster than the accuracy of the test apparatus, and the timing error between the input signals of the test apparatus and the error of the comparator for judging the output cannot be ignored.

Therefore, the output data output from the normal memory is determined as erroneous data by the external test device,
Alternatively, erroneous data may be determined as normal output data, which reduces the reliability.

An object of the present invention is to improve the accuracy of the operation test of the memory built in the semiconductor integrated circuit device. Another object of the present invention is to improve the measurement accuracy of the memory address access time, the write recovery time, and the write recovery time, to prevent the decrease of the measurement accuracy due to the delay of the input signal, and the determination of the output. Is to be irrelevant to the accuracy of the test equipment and internal wiring delay.

[0014]

FIG. 1 is a diagram illustrating the principle of a semiconductor integrated circuit device having the first, second and third features of the present invention. That is, the memory 4 is provided on the chip 9, and the address signal A input from the test exclusive terminal Ti of the chip 9 is input.
In a semiconductor integrated circuit for testing the operation of the memory 4 based on D, a predetermined time has elapsed since the address signal AD was input to the input port Pi of the memory 4 based on the multi-bit address signal AD input from the test dedicated terminal Ti. A memory test circuit 11 that outputs an activation signal CK that activates the latch circuit 7 connected to the output port Po of the memory 4 later is provided, and the output signal of the latch circuit 7 is the output terminal To of the chip 9.
Is output from.

Further, as shown in FIG. 2, the memory test circuit 11 supplies the address signals C1 to C3 to the input port Pi of the memory 4 based on the multi-bit address signals AD1 to AD3.
Is composed of a delay circuit 2d that outputs an output signal after a predetermined delay time from the input of, and pulse generation circuits 2e and 6a that generate an activation signal CK to the latch circuit 7 based on the output signal of the delay circuit 2d. Has been done.

Further, as shown in FIG. 10, the memory test circuit 11 latches the multi-bit address signals AD1 to AD3 inputted from the external tester on the basis of the clock signal CLK, and inputs it to the input port Pi of the memory 4. Latch circuit 7b which outputs as address signals ADD1 to ADD3
7d, a latch circuit 7e that latches and outputs the signal I input from the external test apparatus based on the clock signal CLK, and outputs an output signal after a predetermined delay time after inputting the output signal of the latch circuit 7e Delay circuit 2d for
Pulse generation circuits 2e and 6a for generating an activation signal CK to the latch circuit 7 based on the output signal of the delay circuit 2d,
A latch circuit 7a which is activated based on the activation signal CK and latches and outputs the output signal of the output port Po of the memory 4.
It consists of and.

Next, FIG. 12 is an explanatory view of the principle of the semiconductor integrated circuit device of the fourth feature of the present invention. Further, in the semiconductor integrated circuit according to the fourth aspect of the present invention, as shown in FIG. 13, the memory test circuit 11 ′ has a write enable signal WE in which the signal change of the write enable signal WE A delay circuit 2d which outputs an output signal after a predetermined delay time has passed since it was determined at the terminal WEi,
Pulse generation circuits 2e and 6a for generating the activation signal CK to the latch circuit 7 based on the output signal of the delay circuit 2d.
And is configured.

[0018]

In the semiconductor integrated circuit device having the first, second and third characteristics of the present invention, as shown in FIG.
Is input to the input port Pi of the memory 4, a activating signal CK is input to the latch circuit 7 by the memory test circuit 11 after a predetermined time, and the latch circuit 7 outputs the activation signal CK to the output port Po of the memory 4 based on the activation signal. The data output from Latch is latched and output to the output terminal To of the chip 9.
Therefore, the accuracy of the output signal output from the output terminal To is improved, and the write recovery time and the write delay time can be measured without considering the delay of the input wiring. .

Further, in the semiconductor integrated circuit device of the fourth and fifth features of the present invention, as shown in FIG. 12, a predetermined delay is made based on the signal change of the write enable signal WE at the write enable terminal WEi of the memory 4. The data output from the output port Po is latched after a certain time and is output to the output terminal To of the chip 9. Therefore, the accuracy of the output signal output from the output terminal To is improved, and the write recovery time and the write delay time can be measured without considering the delay of the input wiring.

The output value (DOtest) is held after a predetermined delay time, and the timing of measuring the output depends on the magnitude of the address access time TAA write delay time TWS and the write recovery time TWR. Since it can be measured at a loose timing, AC of external test equipment
It is not necessary to consider the accuracy and the output wiring delay time.
The factor that determines the measurement accuracy is determined only by the accuracy of the delay circuit 2d and the delay of the gate circuit that constitutes the circuit.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A memory test circuit embodying the present invention will be described below.
An embodiment will be described with reference to the drawings. First embodiment FIG. 2 is a circuit diagram of a memory test circuit according to the first embodiment of the present invention.
Is.

As shown in the figure, address signals AD1 ...
AD3 is input from an external test device to a test-dedicated input terminal (not shown) provided on the chip, and internal wirings L1 to L
Delay circuits 1a to 1c and an inverter circuit 2a
To 2c, and the output signals B1 to B3 of the delay circuits 1a to 1c are input to one input terminals of the EOR circuits 3a to 3c.

Output signal A1 of the inverter circuits 2a-2c
To A3 are input to the other input terminals of the EOR circuits 3a to 3c. Output signals B1 to 1 of the delay circuits 1a to 1c
B3 is input as input address signals C1 to C3 to the input port Pi of the memory 4 built in the semiconductor integrated circuit device, and output signals D1 to D3 of the EOR circuits 3a to 3c are input to the AND circuit 5a.

The output signal E of the AND circuit 5a is input to one input terminal of the NOR circuit 6a as an output signal F from the odd-numbered inverter circuit 2d, and the output signal F of the inverter circuit 2d is further increased by one stage or. It is input to the other input terminal of the NOR circuit 6a via the odd-numbered inverter circuits 2e.

The delay time of the inverter circuit 2d is set to an arbitrary time, in particular, an address access time to be guaranteed. The output signal G of the NOR circuit 6a is input to the latch circuit 7 as a clock signal CK. The input terminal of the latch circuit 7 is connected to the output port Po of the memory 4, and when the clock signal CK is input, the latch circuit 7 latches the output data X of the memory 4 and outputs it as the output signal H as a test-dedicated output terminal. (Not shown).

Since one such latch circuit 7 is provided for each output port of the memory 4, a large number of latch circuits are provided in the memory 4 which outputs multi-bit output data in parallel from a large number of output ports. It is installed side by side.

Next, the operation of the memory test circuit configured as described above will be described with reference to FIGS. When the address signals AD1 to AD3 are input from the external tester via the test dedicated terminal and the wirings L1 to L3, the address signal AD1 is delayed by the delay circuit 1a as shown in FIG. 3, and the EOR circuit is output as the output signal B1. The output signal A1 is output to the EOR circuit 3a as an output signal A1.

Therefore, the input signal B1 obtained by delaying the address signal AD1 in the EOR circuit 3a by the delay circuit 1a and the inverter circuit 2a and the same signal B1 in the opposite phase to the signal B1.
The input signal A1 that changes at an earlier timing is input.

Then, based on the input signals A1 and B1,
The EOR circuit 3a outputs the output signal D1 which becomes L level when both the input signals A1 and B1 are H level. In addition, the delay circuit 1b, the inverter circuit 2b and the EOR circuit 3
b, the delay circuit 1c, the inverter circuit 2c, and the EOR circuit 3c operate similarly.

As shown in FIG. 4, each of the EOR circuits 3a to 3a.
The input signals A1 to A3 input to c are shifted in their rising timings due to variations in the wiring capacitance from the test-dedicated terminals to the respective inverter circuits 2a to 2c.
The input signals B1 to B3 input to the OR circuits 3a to 3c have fall timings due to variations in wiring capacitance from the test-dedicated terminals to the delay circuits 1a to 1c.

As a result, the timings of the output signals D1 to D3 output from the EOR circuits 3a to 3c are also deviated, and when the output signals D1 to D3 are input to the AND circuit 5a, the output of the AND circuit 5a is output. The signal E is the output signal D
If any of 1 to D3 is L level, it becomes L level.

Therefore, among the output signals D1 to D3, the address signal C1 to C which is input to the memory 4 after the output signal D3 having the latest timing is returned to the H level.
AND until the address signal C3 input at the latest timing out of 3 is input to the input port of the memory 4.
The output signal E of the circuit 5a is maintained at L level.

When the output signal E of the AND circuit 5a rises from the L level to the H level, the output signal F of the inverter circuit 2d falls from the H level to the L level after the delay time of the inverter circuit 2D. Then, the input signals of the NOR circuit 6a both become L level, the output signal G thereof rises, and the output signal G returns to L level after the delay time by the inverter circuit 2e. Then, the output signal G is input to the latch circuit 7 as a clock signal CK.

The output signal X of the memory 4 is sent to the latch circuit 7.
When the output signal G of the NOR circuit 6a is input to the latch circuit 7 as the clock signal CK in the state where the clock signal CK is input, the latch circuit 7 latches the output signal X of the memory 4 and raises the clock signal CK. After falling, it outputs as an output signal H.

As described above, in this memory test circuit, the address signals AD1 to AD3 input from the external tester are input.
Is input to the input port of the memory 4 as the address signals C1 to C3, and after a delay time t1 set by the inverter circuit 2d, the latch circuit 7 is activated and the output signal X of the memory 4 outputs the latch signal 7. And is output as the output signal H.

Therefore, the output signal H output from the latch circuit 7 is delayed by the delay time t1 set by the inverter circuit 2d.
Since the output signal X at the time of is held, variations in the signal transmission delay time from the test dedicated input terminal to the input port of the memory 4 or the signal transmission delay from the output terminal of the latch circuit 7 to the test dedicated output terminal of the chip Since the output signal X of the memory 4 can be stably output to the external test apparatus regardless of the time variation, the accuracy of the operation test of the memory 4 can be improved. Modification of First Embodiment FIG. 5 shows another embodiment of a delay circuit corresponding to the inverter circuit 2d of the above embodiment. That is, the odd-numbered inverter circuit group 2g and the AND circuits 5b, 5c and O
A delay circuit is configured with the R circuit 8a.

Then, the output signal E of the AND circuit 5a
Is input to the OR circuit 8a through the odd-numbered inverter circuit group 2g, and the odd-numbered terminal N1 from the input terminal of the inverter circuit group 2g is connected to one input terminal of the AND circuit 5b. To the even-numbered terminal N2
Is connected to one input terminal of the AND circuit 5c.
The other input terminal of the AND circuit 5b receives the input signal b
And the input signal a is input to the other input terminal of the AND circuit 5c.

In such a delay circuit, when the input signal E falling from the H level to the L level is input with the input signals a and b set to the L level as shown in FIG. 6, the delay is caused by the inverter circuit group 2g. After a lapse of time, the output signal F of the OR circuit 8a falls from the L level to the H level.

The input signal a is at H level and the input signal b is
Is set to the L level, the terminal N2 of the inverter circuit group 2g is
The delay time by the inverter circuit in the subsequent stage is invalidated and the delay time of this delay circuit is shortened. Further, when the input signal b is set to the H level, the delay time by the inverter circuit in the subsequent stage from the terminal N1 of the inverter circuit group 2g is reduced. It is invalidated and the delay time of this delay circuit is further shortened.

In such a delay circuit, the delay time can be selected by appropriately inputting the input signals a and b from the outside, so that the address signal C1 is applied to the memory 4.
~ C3 is input, the NOR circuit 6a is input to the latch circuit 7.
The time until the output signal G of is input can be selected.

FIG. 7 shows an embodiment in which the inverter circuit group 2d shown in FIG. 2 is composed of bipolar transistors. That is, the inverter circuit group 2d is an NPN
The transistors Tr1 to Tr4 form an inverter circuit of one stage, and such inverter circuits are connected in series in odd stages.

Then, in each inverter circuit, when the transistor Tr3 is turned on based on the bias signal Vcs, the transistors Tr1 and Tr2 forming the differential circuit are activated,
A signal obtained by inverting the input signal E is output from the emitter of the transistor Tr4 to the inverter circuit in the subsequent stage.

Output transistor Tr4 of each inverter circuit
The emitters of are connected to the power supply VT via resistors. By varying the voltage level of the power supply VT, the delay time of each inverter circuit can be varied.

When the input signal E is input by such a configuration, the output signal F is output after a delay time based on the sum of the delay times of the respective inverter circuits, and the delay time changes the voltage level of the power supply VT. Can be adjusted appropriately.

FIG. 8 shows the inverter circuit group 2 shown in FIG.
It shows an embodiment in which d is a MOS transistor. That is, the inverter circuit group 2d is a P channel M
The odd-numbered inverter circuits configured by connecting the OS transistor Trp and the N-channel MOS transistor Trn in series between the power supply Vccx and the ground GND are connected in series, and the input signal E is input to the input terminal of the first-stage inverter circuit. Input signal and output signal F from the final stage inverter circuit
Is being output. The voltage level of the high-potential-side power supply Vccx of each inverter circuit can be changed independently of the power supply Vcc of other circuits.

When the input signal E shifts from the H level to the L level or from the L level to the H level with such a configuration, the output signal F changes from the L level to the H level after a delay time that is the sum of the operating time of each inverter circuit. Alternatively, the H level is shifted to the L level. Then, by changing the voltage level of the power supply Vccx of each inverter circuit, the delay time can be adjusted appropriately.

FIG. 9 shows an inverter circuit group 2d shown in FIG.
It is a circuit configuration for monitoring the set delay time, and outputs an input signal E of the inverter circuit group 2d to an external measuring device and an output signal F of the inverter circuit group 2d.
Is output as an output signal M to the external measuring device through the inverter circuit group 2h having a larger number of stages.

With such a configuration, the delay time of the output signal M with respect to the input signal E is measured by an external measuring device, and the number of inverter circuits in the inverter circuit group 2d and the number of inverter circuits 2h added as described above are calculated. It is possible to monitor the delay time of the inverter circuit group 2d by calculating and obtaining the delay time of the inverter circuit group 2d based on the ratio and the measured delay time.

The multistage inverter circuit 2h connected to the final stage inverter circuit of the inverter circuit group 2d has a relative delay time for directly outputting the input signal E of the inverter circuit group 2d to the external measuring device. It is added in order to calculate as a small value that can be ignored, so long as the delay time for outputting the input signal E to the outside is a time that can be ignored with respect to the delay time by the inverter circuit group 2d. Not necessary. Second Embodiment FIG. 10 is a circuit diagram of a memory test circuit according to a second embodiment of the present invention.

That is, the address signals AD1, AD2 input from the external test equipment through the test dedicated terminals of the chip.
AD3 is input to the latch circuits 7b to 7d, and the signal I which is also input from the external test apparatus via the test dedicated terminal of the chip is input to the latch circuit 7e.

Each of the latch circuits 7b to 7d latches an input signal on the basis of the clock signal CLK and outputs it to the input port Pi of the memory 4, and the latch circuit 7e latches the signal I to the inverter circuit 2d of odd stages. Output.

The latch circuits 7b to 7d are connected to the memory 4
Signal transmission time t to the input port Pi and signal transmission delay time t from the latch circuit 7e to the inverter circuit 2d
Are almost the same and almost negligible.

In such a test circuit, as shown in FIG. 11, AD1, AD2, AD input from an external test apparatus are used.
3 and the signal I are input to the latch circuits 7b to 7e, the clock signal CL is input to the latch circuits 7b to 7e.
When K is input, each of the latch circuits 7b to 7e latches and outputs the address signals ADD1, ADD2, ADD3, and the signal I, respectively.

Then, the address signals ADD1 and ADD2
, ADD3 are input to the input port Pi of the memory 4,
The signal I is input to the inverter circuit 2d. The output signal F of the inverter circuit 2d is the output signal J of the latch circuit 7e.
Rises from L level to H level, it falls from H level to L level after a delay time by the inverter circuit 2d.

Then, the input signals of the NOR circuit 6a both become L level, the output signal G rises, and the output signal G returns to L level after the delay time by the inverter circuit 2e.

The output signal G is output to the latch circuit 7a.
Is input as a clock signal CK. With the output signal X of the memory 4 being input to the latch circuit 7a,
When the output signal G of the NOR circuit 6a is input to the latch circuit 7a as the clock signal CK, the latch circuit 7a is also provided.
Latches the output signal X of the memory 4 and outputs the clock signal CK
After the fall of, the output signal H is output.

Therefore, in this test circuit, the signal transmission time T1 from the test-dedicated terminal to each of the latch circuits 7b to 7e is T1.
Even if T4 varies, the address signals ADD1, ADD2, ADD3 and the output signal J of the latch circuit 7e are synchronized by the clock signal CLK, so that they are not affected by the variations in the signal transmission delay times T1 to T4. The test accuracy of the memory 4 can be improved. Third Embodiment FIG. 13 is a circuit diagram of a memory test circuit according to a third embodiment of the present invention. The memory test circuit 11 'of this embodiment is similar to that shown in FIG.
It is constructed in a semiconductor integrated circuit chip as shown in FIG.

As shown in FIG. 12, as the write enable signal WE input to the write enable terminal WEi of the memory 4, the test dedicated input terminal T provided in the chip is used.
A test write enable input signal WEtest is input to i from an external test apparatus. The write enable signal WE is also supplied to the memory test circuit 11 ', and the latch circuit 7 connected to the output port Po of the memory 4 is also provided.
Is used as a reference signal for generating a clock signal (activation signal) CK for activating.

The memory test circuit 11 ', as shown in FIG. 13, has a predetermined delay time after the signal change of the write enable signal WE is determined at the write enable terminal WEi of the memory 4 based on the write enable signal WE. The delay circuit 2d outputs an output signal, and pulse generation circuits 2e and 6a which generate a clock signal CK to the latch circuit 7 based on the output signal of the delay circuit 2d. The delay circuit 2d includes an odd number of inverters. Circuit, and the pulse generation circuit includes an inverter circuit 2e of one stage or an odd number stage and an N stage.
It is composed of an OR circuit 6a.

The delay circuit 2d has a write enable signal W.
E (signal E ′) is input to output an output signal F ′ delayed by the delay time of the odd-numbered inverter circuits. In the pulse generation circuit, the output signal F ′ of this delay circuit 2d is NORed.
It is input to one input terminal of the circuit 6a and also input to the inverter circuit 2e of one stage or an odd number of stages, and the output of the inverter circuit 2e is input to the other input terminal of the NOR circuit 6a.

Therefore, according to this structure, the delay circuit 2d has L
By inputting the signal E ′ that changes from the level to the H level, the clock signal CK to the latch circuit 7 is delayed from the pulse generation circuit by the delay time of the odd-numbered inverter circuits of the delay circuit 2d, and 1 The pulse width (t
A pulse with p) is output. Thus, by changing the number of stages of the inverter circuit of the delay circuit 2d, it is possible to obtain an arbitrary delay time. In this case, the accuracy depends on the unit delay time of the inverter circuit. In this embodiment, the delay time of the delay circuit 2d is set to the write delay time TWS that should be guaranteed.

The output signal G'of the NOR circuit 6a is input to the latch circuit 7 as the clock signal CK. The input terminal of the latch circuit 7 is connected to the output port Po of the memory 4, and when the clock signal CK is input, the latch circuit 7 latches the output data X of the memory 4 and outputs it as an output signal H for the test-dedicated output terminal To. To the test output signal DOte
It becomes st.

Since one such latch circuit 7 is provided for each output port of the memory 4, a large number of latch circuits are provided in the memory 4 which outputs multi-bit output data in parallel from a large number of output ports. It is installed side by side.

Next, the operation of the memory test circuit configured as described above will be described with reference to FIG. When the test write enable input signal WEtest is input to the test dedicated input terminal Ti from the external test apparatus, the write enable signal WE (signal E ′) delayed by the input delay time tDi is input to the write enable terminal WEi of the memory 4. Transmitted.
The write enable signal WE is supplied to the pulse generating circuits 2e and 6a as a signal F'delayed by the delay time (write delay time to be guaranteed) of the odd-numbered inverter circuits of the delay circuit 2d.

Here, assuming that the delays of the pulse generation circuits 2e and 6a have no problem in measurement, the latch circuit 7 is delayed by the write delay time TWS to be guaranteed (in the figure,
The output X at the timing At) can be held. Further, as the test output signal DOtest, the data held in the latch circuit 7 is output with a delay of the pulse width tp of the pulse generating circuits 2e and 6a + the output delay time tDo.

As described above, in the memory test circuit of the present embodiment, the test output signal DOtest output from the test-dedicated output terminal To maintains the output delayed by the delay time of the delay circuit 2d, and the internal wiring is used. It can be made independent of delay and the like. Further, since the output signal X of the memory 4 is held until the next clock signal CK is given to the latch circuit 7, it is possible to carry out the measurement according to the accuracy of the external test apparatus. That is,
It can be independent of the accuracy of the external test equipment.

In the above description, the write delay time TWS
As described above, the delay time of the delay circuit 2d is set to the write recovery time TWR to be guaranteed,
By making the delay circuit an even number of inverter circuits,
The write recovery time TWR can be similarly guaranteed.

The modified example developed for the first embodiment can be similarly applied to this embodiment.

[0069]

As described above in detail, the present invention exerts an excellent effect of improving the accuracy of the operation test of the memory built in the semiconductor integrated circuit device.

That is, according to the semiconductor integrated circuit device of the first, second, and third features of the present invention, the memory test circuit causes the latch circuit to operate in a predetermined time after the address signal is input to the input port of the memory. The activation signal is input, and based on the activation signal, the latch circuit latches the data output from the memory output port and outputs it to the output terminal of the chip, so it is output from the output terminal in the memory operation test. It is possible to provide a semiconductor integrated circuit in which the accuracy of the output signal obtained is improved and, as a result, the reliability is improved.

Further, according to the semiconductor integrated circuit device of the fourth and fifth aspects of the present invention, a predetermined delay time is set with a predetermined delay time from the output port with reference to the signal change of the write enable signal at the write enable terminal of the memory. Since the output data is latched and output to the output terminal of the chip, it is possible to measure without taking delay of input wiring into consideration, and the output value is held at a point after a predetermined delay time. The output measurement timing can be measured at a loose timing regardless of the write delay time (TWS) and write recovery time (TWR). Irrespective of the above, it is possible to perform a measurement in which the write delay time (TWS) and the write recovery time (TWR) are guaranteed with an accurate guaranteed value for the memory. , It is possible to provide a semiconductor integrated circuit with improved reliability as a result.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a test circuit according to a first embodiment of the present invention.

FIG. 3 is a waveform diagram showing the operation of the first embodiment.

FIG. 4 is a waveform diagram showing the operation of the first embodiment.

FIG. 5 is a circuit diagram showing a modification of the delay circuit of the first embodiment.

6 is a waveform chart showing an operation of the delay circuit shown in FIG.

FIG. 7 is a circuit diagram showing a specific configuration of the delay circuit of the first embodiment.

FIG. 8 is a circuit diagram showing a specific configuration of the delay circuit according to the first embodiment.

FIG. 9 is a circuit diagram showing a modification of the delay circuit of the first embodiment.

FIG. 10 is a circuit diagram showing a second embodiment of the present invention.

FIG. 11 is a waveform chart showing the operation of the second embodiment.

FIG. 12 is a diagram illustrating the principle of the present invention.

FIG. 13 is a circuit diagram showing a test circuit of a third embodiment of the present invention.

FIG. 14 is a waveform chart showing the operation of the third embodiment.

[Explanation of symbols]

 1a to 1c ... Delay circuit 2d ... Delay circuit 2e, 6a ... Pulse generating circuit 2a to 2c, 2d, 2e, 2g, 2h ... Inverter circuit 3a to 3c ... EOR circuit 4 ... Memory 5a, 5b, 5c ... AND circuit 6a ... NOR circuit 7 ... Latch circuit 7b to 7d, 7e ... Latch circuit 8a ... OR circuit 9, 9 '... Chip 10 ... Logic circuit 11, 11' ... Memory test circuit A1 to A3 ... Inverter circuits 2a to 2c output signals AD, AD1 to AD3 ... Address signals ADD1, ADD2, ADD3 ... Address signal At ... Timing B1 to B3 ... Output signals of delay circuits 1a to 1c C1 to C3 ... Input address signal CLK ... Clock signal CK ... Clock signal (activation signal) D1 -D3 ... Output signal of EOR circuits 3a-3c DOtest ... Test output signal E ... Output signal of AND circuit 5a F ... output signal of the inverter circuit 2d G ... output signal of the NOR circuit 6a GND ... ground I ... input signal from an external test device J ... output signal of the latch circuit 7e L1 to L3 ... internal wiring M ... output signal of the inverter circuit group 2h Pi ... Input port Po ... Output port TWS ... Write delay time TWR ... Write recovery time Ti ... Test dedicated input terminal To ... Test dedicated output terminal Tr1 to Tr4 ... NPN transistor Trp ... P channel MOS transistor Trn ... N channel MOS transistor VT ... Power supply Vcs ... Bias signal Vccx ... Power supply WEi ... Write enable terminal WE ... Write enable signal WEtest ... Test write enable input signal X ... Memory 4 output signal tp ... Inverter circuit 2e delay time pulse width tDi ... Input delay Time tDo ... Output delay time

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location // H01L 21/66 W 7352-4M

Claims (4)

[Claims] 1. A memory (4) is provided on a chip (9),
A semiconductor integrated circuit for performing an operation test of the memory (4) based on an input signal (WE) to a test dedicated terminal (Ti) of the chip (9), the input signal to the test dedicated terminal (Ti) An activation signal (7) for activating the latch circuit (7) connected to the output port (Po) of the memory (4) after a predetermined time has passed since (WE) was input to the input port (Pi) of the memory (4). CK)
A semiconductor integrated circuit device, comprising: a memory test circuit (11) for outputting the signal, and outputting the output signal of the latch circuit (7) from an output terminal (To) of the chip. 2. The memory test circuit (11) supplies address signals (C1 to C1) to an input port (Pi) of the memory (4) based on multi-bit address signals (AD1 to AD3).
A delay circuit (2d) that outputs an output signal after a predetermined delay time from the input of C3), and an activation signal (CK) to the latch circuit (7) based on the output signal of the delay circuit (2d). 2. A semiconductor integrated circuit device according to claim 1, further comprising a pulse generation circuit (2e, 6a) for generating the. 3. The memory test circuit (11) latches multi-bit address signals (AD1 to AD3) input from an external tester based on a clock signal (CLK) to input the input port of the memory (4). Latch circuits (7b to 7d) which output to (Pi) as address signals (ADD1 to ADD3), and a latch which latches and outputs a signal (I) input from an external test device based on the clock signal (CLK). A circuit (7e) and a delay circuit (2d) for outputting an output signal after a predetermined delay time from the input of the output signal of the latch circuit (7e)
A pulse generation circuit (2e, 6a) for generating an activation signal (CK) to the latch circuit (7) based on the output signal of the delay circuit (2d), and based on the activation signal (CK) 2. The semiconductor integrated circuit device according to claim 1, further comprising a latch circuit (7a) which is activated to latch and output an output signal of the output port (Po) of the memory (4). 4. The memory test circuit (11 ′) determines the signal change of the write enable signal (WE) at a write enable terminal (WEi) of the memory (4) based on the write enable signal (WE). Delay circuit (2d) that outputs an output signal after a predetermined delay time, and pulse generation that generates an activation signal (CK) to the latch circuit (7) based on the output signal of the delay circuit (2d) The semiconductor integrated circuit device according to claim 4, further comprising a circuit (2e, 6a).