JPH05264675A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the precision of the operation test of a memory built in a semiconductor integrated circuit device. CONSTITUTION:A memory 4 and a logical circuit 12 are formed on the same chip 11, and the operation test of the memory 4 is conducted on the basis of an address signal AD inputted from the terminal Ti exclusive for text of the chip 11. Further, this device has a memory test circuit 13 for outputting a write control signal WE having a determined pulse width on the basis of the address signal AD after the address signal AD is inputted to the input port Pi of the memory 4 on the basis of the multi-bit address signal AD inputted from the terminal Ti exclusive for test.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the operation of the memory in a semiconductor integrated circuit device which is provided with a memory and a logic circuit on the same chip and is configured to control the operation of the memory by the logic circuit in a normal operation. It is about the test.

In recent years, semiconductor integrated circuit devices have become larger, more multifunctional, and faster, and a CPU and RA in the same chip.
The one with built-in M or ROM is generalized. Also, due to the increase in the size of the chip, the internal wiring becomes large and the wiring capacitance and the wiring resistance increase. As the wiring capacitance and the wiring resistance increase, the operation delay time tends to increase.

In such a semiconductor integrated circuit device, the operation delay time may vary greatly due to process variations due to miniaturization. Therefore, it is required to prevent the accuracy of the operation test from decreasing due to the variation in the operation delay time.

[0004]

2. Description of the Related Art In a conventional semiconductor integrated circuit device having a memory and a logic circuit on the same chip, an external terminal is provided with a test-dedicated terminal, and the test-dedicated terminal is connected to an external tester to perform a memory operation test. It is carried out.

That is, an operation test of the memory is conducted by directly inputting an address signal and a write control signal from an external test device to the memory via a test dedicated terminal. When performing such an operation test, estimate the delay time due to the wiring capacitance from the test-dedicated terminal to the memory input port in advance,
The address signal and write control signal input from the test equipment are added to the memory with the estimated delay time added, and based on the write operation, the external test equipment determines whether the written data is correct or not. ing.

[0006]

However, in the semiconductor integrated circuit device as described above, the wiring from the test-dedicated terminal to the input port of the memory becomes large due to the large scale and high integration, and the wiring capacitance due to the process variation. Also, the variation in wiring resistance is large.

For this reason, it is difficult to accurately estimate the delay time due to the wiring from the test-dedicated terminal to the input port of the memory, and the setup time and hold time for writing the address signal and data input from the test apparatus can be calculated. The input timing to the memory input port may deviate from the write control signal to be set.

Therefore, there is a case where erroneous writing is performed even in a normal memory, or normal writing data is output even in a defective memory, so that an accurate operation test cannot be performed and the yield is lowered. There is.

Further, with the speeding up of the operation of the memory, it has become impossible to speed up the address signal and the write signal output from the test device with sufficient accuracy for performing the operation test of the memory.

An object of the present invention is to improve the accuracy of the operation test of the memory built in the semiconductor integrated circuit device.

[0011]

FIG. 1 illustrates the principle of the present invention. That is, the memory 4 and the logic circuit 12 are formed on the same chip 11, and the operation test of the memory 4 is performed based on the address signal AD input from the test dedicated terminal Ti of the chip 11. Then, based on the multi-bit address signal AD input from the test-dedicated terminal Ti, the address signal AD is sent to the input port P of the memory 4.
A memory test circuit 13 is provided which outputs a write control signal WE having a predetermined pulse width to the memory based on the address signal AD after being input to i.

Further, as shown in FIG. 2, the memory test circuit 4 receives the address signals B1 to B input to the input port Pi based on the multi-bit address signals AD1 to AD3.
3 and the address signals B1 to B3 are paired with early timing signals A1 to A3, and the changes between the signals A1 to A3 and the address signals B1 to B3 are EOR circuits 3a to 3a.
output signal D of the EOR circuits 3a to 3c
1 to D3 are input to the AND circuit 5a, and the write signal H is generated based on the output signal of the AND circuit 5a.

[0013]

Since the multi-bit address signal AD is input to the input port Pi of the memory 4, the write control signal WE having a predetermined pulse width is input from the memory test circuit 13 to the memory 4 based on the address signal AD. , The address signal AD, which is input at the latest timing among the multi-bit address signals AD, is input to the memory 4 even if the timing at which the address signal AD is input from the test-dedicated terminal Ti to the input port Pi of the memory 4 varies. After being input, the write control signal WE is input to the memory 4.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a memory test circuit embodying the present invention will be described below with reference to the drawings. As shown in FIG. 2, the address signals AD1 to AD3 are input from an external test apparatus to a test-dedicated terminal (not shown) provided on the chip, and the delay circuits 1a to 1c and the inverter circuits 2a to are connected via internal wirings L1 to L3. 2d, and the output signals B1 to B3 of the delay circuits 1a to 1c are input to the EOR circuits 3a to 3c.
It is input to one input terminal of c. Inverter circuit 2a
The output signals A1 to A3 of .about.2c are input to the other input terminals of the EOR circuits 3a to 3c.

Output signals B1 to 1 of the delay circuits 1a to 1c
B3 is input as input address signals C1 to C3 to the input port Pi of the memory 4 built in the semiconductor integrated circuit device, and output signals D1 to D3 of the EOR circuits 3a to 3c are input to the AND circuit 5a.

The output signal E of the AND circuit 5a is NAN.
The write enable signal WE is input to one input terminal of the D circuit 6a, and the other input terminal of the NAND circuit 6a is input from the external test apparatus via the test dedicated terminal.

The output signal F of the NAND circuit 6a is input to the delay circuit 1d, and the output signal G of the delay circuit 1d is input to the write pulse generation circuit 7. And
The output signal H of the write pulse generation circuit 7 is the memory 4
Has been entered in.

The specific structure of the delay circuit 1d and the write pulse generating circuit 7 will be described with reference to FIG. 5. The delay circuit 1d is composed of inverter circuits of even stages connected in series. In the write pulse generation circuit 7, the output signal G of the delay circuit 1d is input to one input terminal of the NOR circuit 8a, and N is output through an odd number of inverter circuits.
It is input to the other input terminal of the OR circuit 8a.

With such a configuration, the delay circuit 1d can set the delay time based on the operating time of the even-numbered inverter circuits, and the write pulse generating circuit 7 changes the output signal G of the delay circuit 1d from the H level to the L level. At the time of falling, an H level write pulse having a pulse width based on the operation delay time of the odd-numbered inverter circuits is output as the output signal H.

Next, the operation of the memory test circuit configured as described above will be described with reference to FIGS. When the address signals AD1 to AD3 are input from the external test circuit through the test dedicated terminal and the wirings L1 to L3, the address signal AD1 is delayed by the delay circuit 1a as shown in FIG. 3, and the EOR circuit is output as the output signal B1. The output signal A1 is output to the EOR circuit 3a as an output signal A1. Therefore,
The input signal B1 obtained by delaying the address signal AD1 is supplied to the EOR circuit 3a by the delay circuit 1a and the inverter circuit 2a.
And an input signal A1 that is in anti-phase with the signal B1 and changes at a timing earlier than the same B1.

Then, based on the input signals A1 and B1, E
The OR circuit 3a outputs the output signal D1 which becomes L level when both the input signals A1 and B1 are H level. In addition, the delay circuit 1b, the inverter circuit 2b, and the EOR circuit 3
b, the delay circuit 1c, the inverter circuit 2c, and the EOR circuit 3c operate similarly.

As shown in FIG. 4, each of the EOR circuits 3a to 3a.
The input signals A1 to A3 input to c are shifted in their rising timings due to variations in wiring capacitance from the test-dedicated terminals to the respective inverter circuits 2a to 2c, and each E
The input signals B1 to B3 input to the OR circuits 3a to 3c have their falling timings deviated due to variations in wiring capacitance and wiring resistance from the test-dedicated terminals to the delay circuits 1a to 1c.

As a result, the timings of the output signals D1 to D3 output from the EOR circuits 3a to 3c are also deviated, and when the output signals D1 to D3 are input to the AND circuit 5a, the output of the AND circuit 5a is output. The signal E is the output signal D
If any of 1 to D3 is L level, it becomes L level.

Therefore, among the output signals D1 to D3, the address signal C1 to be input to the memory 4 after the output signal D3 having the latest timing is returned to the H level, that is,
AND until the address signal C3 input at the latest timing of C3 is input to the input port of the memory 4.
The output signal E of the circuit 5a is maintained at L level.

With the H-level write enable signal WE being input to the NAND circuit 6a, the AND circuit 5a
When the output signal E of the NAND circuit 6a rises to the H level, the output signal F of the NAND circuit 6a falls from the H level to the L level, and the delay circuit 1d outputs the output signal G obtained by delaying the output signal F of the NAND circuit 6a. The write pulse generation circuit 7 outputs a write pulse having a predetermined pulse width to the memory 4 as an output signal H based on the output signal G of the delay circuit 1d.

Therefore, the address signals C1 to C1 are stored in the memory 4.
After the input of C3 is completed, the write signal H having a predetermined pulse width t2 is input after a setup time t1 set by the delay circuit 1d.

As described above, in this memory test circuit, after the address signals AD1 to AD3 input from the external tester are input to the input ports of the memory 4 as the address signals C1 to C3, a predetermined setup time t1 is passed and a predetermined time is passed. The write pulse signal H having the pulse width t2 is input.

Therefore, the write signal H having the predetermined setup time t1 and the predetermined pulse width t2 can be input to the memory 4 regardless of the variation in the signal transmission delay time from the test-dedicated terminal to the input port of the memory 4. ,
The accuracy of the operation test of the memory 4 can be improved.

FIG. 6 shows another embodiment of the delay circuit 1d and the write pulse generating circuit 7 of the above embodiment.
That is, the delay circuit 1d is configured by the odd-numbered inverter circuit group 2d, the NOR circuit 8b, and the AND circuits 5b, 5c, and the write pulse is similarly formed by the odd-numbered inverter circuit group 2e, the NOR circuit 8c, and the AND circuits 5d, 5e. The generation circuit 7 is configured.

The output signal F of the NAND circuit 6a is NORed through the odd-numbered inverter circuit group 2d.
It is input to the circuit 8b, the terminal N1 of the odd-numbered stages from the input terminal of the inverter circuit group 2d is connected to one input terminal of the AND circuit 5b, and the terminal N2 of the even-numbered stage from the terminal N1 is one of the AND circuits 5c. Connected to the input terminal of. The input signal b is input to the other input terminal of the AND circuit 5b, and the input signal a is input to the other input terminal of the AND circuit 5c.

With such a configuration of the delay circuit 1d, when the input signal F falling from H level to L level is input while the input signals a and b are at L level, the NOR circuit is delayed by the inverter circuit group 2d. The output signal G of 8b falls from H level to L level.

Input signal a is at H level and input signal b is
Is set to the L level, the terminal N2 of the inverter circuit group 2d is
The delay time of the inverter circuit in the subsequent stage is invalidated and the delay time of the delay circuit 1d is shortened. Further, when the input signal b is set to the H level, the delay time of the inverter circuit in the subsequent stage from the terminal N1 of the inverter circuit group 2d becomes It is invalidated and the delay time of the delay circuit 1d is further shortened.

The write pulse generating circuit 7 shown in FIG. 6 has the same structure as the delay circuit 1d except that the output signal G of the delay circuit 1d is directly input to the NOR circuit 8c. Then, when the input signal G falling from the H level to the L level is input while the input signals a and b are at the L level, the write pulse signal H having the pulse width defined by the delay time by the inverter circuit group 2e is output. To be done.

The input signal c is at H level and the input signal d is
Is set to the L level, the terminal N4 of the inverter circuit group 2e is
When the delay time due to the inverter circuit at the subsequent stage is invalidated and the pulse width of the write pulse signal H is shortened, and when the input signal d is set to the H level, the inverter circuit group 2e
The delay time due to the inverter circuit at the stage subsequent to the terminal N3 is invalidated, and the pulse width of the write pulse signal H is further shortened.

In such a delay circuit 1d and the write pulse generating circuit 7, by appropriately inputting the input signals a to d from the outside, the delay time of the delay circuit 1d and the pulse width of the output signal H of the write pulse generating circuit 7 are set. Since it can be selected, the setup time of the write pulse signal H and the pulse width of the write signal input to the memory 4 can be selected and input.

Therefore, by changing the setup time and the pulse width of the write signal appropriately and performing the operation test of the memory 4, it is possible to easily and surely evaluate the limit operation characteristics of the memory 4.

FIG. 7 shows another embodiment of the write pulse generating circuit 7. That is, the write pulse generating circuit 7 has three NPN transistors Tr1 to Tr12.
Inverter circuits 2f to 2h are formed, and NPN transistors Tr13 to Tr16 form a NOR circuit 8d.

The respective inverter circuits 2f to 2h are connected in series, and the output signal of the final stage inverter circuit 2h is input to one input terminal of the NOR circuit 8d and the other input terminal of the NOR circuit 8d. The input signal G is input.

For example, in the inverter circuit 2f, when the transistor Tr3 is turned on based on the bias signal Vcs, the transistors Tr1 and Tr2 forming the differential circuit are activated,
A signal obtained by inverting the input signal G is output from the emitter of the transistor Tr4 to the subsequent inverter circuit 2g. The inverter circuits 2g and 2h also operate in the same manner.

The emitters of the output transistors Tr4, Tr8, Tr12 of the respective inverter circuits 2f to 2h are connected to the power supply VT via resistors. By making the voltage level of the power supply VT variable, each inverter circuit 2f ...
The delay time of 2h can be made variable.

When the input signal G falling from the H level to the L level is input by such a configuration, the writing pulse signal H having the pulse width based on the delay time of the inverter circuits 2f to 2h is output from the NOR circuit 8d, The pulse width can be appropriately adjusted by changing the voltage level of the power supply VT.

Further, the write pulse generating circuit 7 is provided with a delay circuit in which the inverter circuit 2f is connected in series in an even number of stages.
A delay circuit capable of changing the setup time can be configured by connecting the delay circuit to the preceding stage.

FIG. 8 shows the write pulse generation circuit 7 with M
It is an example configured by using an OS transistor. That is, the P-channel MOS transistor Trp and the N-channel MOS transistor Trn are connected to the power source Vcc1 and the ground G.
The five-stage inverter circuits 2i to 2m configured by connecting in series with the ND are connected in series, the input signal G is input to the input terminal of the first-stage inverter circuit 2i, and the final-stage inverter circuit 2m is connected. The output signal is input to the NOR circuit 8e.

The voltage level of the high-potential-side power source Vcc1 of each inverter circuit 2i to 2m can be changed independently of the power source Vcc of the NOR circuit 8e. With this configuration, when the input signal G falls from the H level to the L level, the write pulse signal H having the pulse width based on the delay time of the inverter circuits 2i to 2m is output to the NOR circuit 8e.
Is output from.

The pulse width of the write pulse signal H can be appropriately adjusted by changing the voltage level of the power source Vcc1 of each of the inverter circuits 2i to 2m.
Further, by connecting a delay circuit in which the above-mentioned inverter circuit 2i is connected in series in an even number stage to the preceding stage of this write pulse generation circuit, a delay circuit capable of changing the setup time can be configured.

FIG. 9 shows a circuit configuration for monitoring the setup time t1 set by the delay circuit 1d and the write pulse generation circuit 7 and the pulse width t2 of the write signal H shown in FIG. In addition to outputting F to the outside, the output signal of the final stage inverter circuit constituting the write pulse generating circuit 7 is output to the outside as the output signal M via the multiple stages of inverter circuits 2n.

With such a configuration, the delay time of the output signal M with respect to the input signal F is measured by an external measuring device, and the number of stages of the inverter circuit of the delay circuit 1d, the number of stages of the inverter circuit constituting the write pulse generating circuit 7 and the above-mentioned. The setup time t1 and the pulse width t2 of the write signal by the delay circuit 1d can be calculated and calculated based on the ratio of the added number of stages of the inverter circuit 2n and the measured delay time.

The multistage inverter circuit 2n connected to the final stage inverter circuit constituting the write pulse generating circuit 7 can relatively ignore the delay time for outputting the input signal F of the delay circuit 1d to the outside. The delay time for outputting the input signal F to the outside is such that it can be ignored with respect to the setup time t1 and the pulse width t2 of the write signal. It is not absolutely necessary.

FIG. 10 shows the memory 4 shown in FIG. 2 based on the address signal input from the external test apparatus to the test-dedicated terminal.
2 is a circuit for generating an address signal C input to the AND circuit and an input signal D of the AND circuit 5a, which is another embodiment of a circuit corresponding to the delay circuit 1a, the inverter circuit 2a, and the EOR circuit 3a shown in FIG.

That is, the address signal AD input from the test-dedicated terminal is input as an input signal b2 to one input terminal of the NOR circuit 8f via the even-numbered inverter circuits 2p forming a delay circuit, and is also input to the memory 4. And the address signal AD is output to the other input terminal of the NOR circuit 8f via the first-stage inverter circuit of the even-stage inverter circuit 2p.
Has been entered as.

The address signal AD is the NOR circuit 8g.
Input signal a1 to one of the input terminals
The input signal of the final-stage inverter circuit of the even-numbered inverter circuit 2p is input as the input signal b1 to the other input terminal of the OR circuit 8g.

The output signals d1 and d2 of the NOR circuits 8f and 8g are input to the NOR circuit 8h, and the signal D output from the NOR circuit 8h is the AND circuit 5 shown in FIG.
is output to a.

The operation of the circuit configured as described above is shown in FIG.
1, the address signal AD input from the test-dedicated terminal is input to the NOR circuit 8g as the input signal a1, and the input signal a2 of the NOR circuit 8f inverts the address signal AD after a delay time t1 of one inverter circuit. It will be what was made.

The input signal b1 of the NOR circuit 8g is obtained by delaying and inverting the address signal AD, and the input signal b2 of the NOR circuit 8f is obtained by inverting the input signal b1 after a delay time t1 of one stage of the inverter circuit. Will be things.

The output signal d1 of the NOR circuit 8g rises after the operation delay time t2 of the NOR circuit 8g based on the fall of the input signal a1 and falls based on the rise of the input signal b1.

The output signal d2 of the NOR circuit 8f rises after the operation delay time t2 of the NOR circuit 8f based on the fall of the input signal a2, and falls based on the rise of the input signal b2.

Then, by the output signals d1 and d2, N
The output signal D of the OR circuit 8h rises based on the rising edge of the address signal C input to the memory 4, and becomes a signal for detecting that the address change is transmitted to the memory 4.

FIG. 12 shows another embodiment of the present invention. That is, the address signals AD1 and AD2 and the write data D, which are input from the external test device via the test dedicated terminal of the chip, are input to the latch circuits 9a to 9c, and also from the external test device via the test dedicated terminal of the chip. The write enable signal WE is input to the latch circuit 9d.

Each of the latch circuits 9a-9c has a clock signal C.
The input signal is latched based on LK and output to the memory 4, and the latch circuit 9d latches the write enable signal WE and outputs it to the write pulse generator 10.

This write pulse generator 10 is, for example, a circuit similar to the delay circuit 1d and the write pulse generator 7 of the above-mentioned embodiment. The latch circuits 9a to 9c
To the input port of the memory 4 and the signal transmission delay time t from the latch circuit 9d to the write pulse generating device 10 are almost the same and almost negligible.

In such a test circuit, as shown in FIG. 13, the address signals AD1 and A input from the external test device are input.
D2, write data D and write enable signal WE
When the clock signal CLK is input to each of the latch circuits 9a to 9d while being input to each of the latch circuits 9a to 9d, each of the latch circuits 9a to 9d causes the address signals ADD1 and ADD1.
DD2, write data Din, write enable signal WE
Are each latched and output.

Then, the address signals ADD1, ADD2 and the write data Din are input to the memory 4, and the write enable signal WE is input to the write pulse generator 10. The write pulse generator 10 inputs a write signal having a predetermined pulse width t2 to the memory 4 as a write enable signal WEn after a predetermined setup time t1 has elapsed based on the input write enable signal WE.

Therefore, in this test circuit, the signal transmission delay time T1 from the test dedicated terminal to each of the latch circuits 9a to 9d is set.
Even if T4 varies, the address signals ADD1, ADD2 and the write data Din are input to the memory 4 in synchronization with the clock signal CLK.
, ADD2 and write data Din and the write enable signal WEn output from the write pulse generator 10.
Since the write operation is performed based on, the test accuracy of the memory 4 can be improved without being affected by the variations in the signal transmission delay times T1 to T4.

In the above embodiment, the synchronized clock signal CLK is input to each of the latch circuits 9a to 9d. However, if the clock signal CLK is input to the latch circuits 9a and 9b via the delay circuit, the setup time t1 is set. It is also possible to shift the output timing of each of the latch circuits 9a to 9d, for example, by setting the minus value.

[0065]

As described above in detail, the present invention exhibits an excellent effect of improving the accuracy of the operation test of the memory built in the semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a test circuit according to a first embodiment of the present invention.

FIG. 3 is a waveform diagram showing the operation of the first embodiment.

FIG. 4 is a waveform diagram showing the operation of the first embodiment.

FIG. 5 is a circuit diagram showing a specific configuration of a delay circuit and a write pulse generation circuit of the first embodiment.

FIG. 6 is a circuit diagram showing a specific configuration of a delay circuit and a write pulse generation circuit of the first embodiment.

FIG. 7 is a circuit diagram showing a specific configuration of a write pulse generation circuit of the first embodiment.

FIG. 8 is a circuit diagram showing a specific configuration of a write pulse generation circuit of the first embodiment.

FIG. 9 is a circuit diagram showing a modified example of the delay circuit and the write pulse generation circuit of the first embodiment.

FIG. 10 is a circuit diagram showing a modification of the first embodiment.

11 is a circuit diagram showing an operation of the modified example shown in FIG.

FIG. 12 is a block diagram showing a second embodiment of the present invention.

FIG. 13 is a waveform chart showing the operation of the second embodiment of the present invention.

[Explanation of symbols]

 4 memory 11 chip 12 logic circuit 13 memory test circuit AD address signal Ti test dedicated terminal Pi input port WE write control signal

Claims (2)

[Claims] 1. A memory (4) and a logic circuit (12) are formed on the same chip (11), and an address signal (A) inputted from a test exclusive terminal (Ti) of the chip (11) is formed.
A semiconductor integrated circuit for performing an operation test of the memory (4) based on D), the address signal (AD) based on a multi-bit address signal (AD) input from the test dedicated terminal (Ti).
A memory test circuit (13) for outputting a write control signal (WE) having a predetermined pulse width to the memory based on the address signal (AD) after being input to the input port (Pi) of the memory (4). A semiconductor integrated circuit device characterized by the above. 2. The memory test circuit (4) receives an address signal (B1 to B3) input to the input port (Pi) based on a multi-bit address signal (AD1 to AD3) and the address signal (B1 to B3). ) To generate signals (A1 to A3) at early timing, and
3) and the change of the address signals (B1 to B3) are detected by the EOR circuits (3a to 3c), and the EOR circuits (3a to 3) are detected.
The output signal (D1 to D3) of c) is input to an AND circuit (5a), and a write signal (H) is generated based on the output signal of the AND circuit (5a). Semiconductor integrated circuit device.