JP5697382B2 - Constant voltage circuit - Google Patents

Description

  The present invention relates to a phase compensation technique for a constant voltage circuit.

  A series regulator in which a voltage control element is connected in series to a load is used as a constant voltage DC power supply circuit. Series regulators have the advantages of less power ripple and noise and higher stability than switching regulators. FIG. 1 is a schematic configuration diagram of a series regulator circuit.

  The series regulator circuit 100 includes a first transistor Q1, a voltage dividing circuit including a series connection of resistors R1 and R2, a differential unit 1, a reference voltage generation unit 2, an amplification unit 3, a bypass capacitor C1, and a phase A compensation capacitor C2 is provided.

  The first transistor Q1 is connected in series between the input voltage VIN and the load L, and supplies the output voltage VOUT to the load L. The emitter electrode of the first transistor Q1 is connected to the load L, and the collector electrode of the first transistor Q1 is connected to the input voltage VIN.

  In order to stabilize the output voltage VOUT, a bypass capacitor C1 is connected in parallel to the load L. A voltage dividing circuit including a series connection of resistors R1 and R2 is connected between the output voltage VOUT of the first transistor Q1 and the ground, and generates a divided voltage Vdv proportional to the output voltage VOUT.

  The differential unit 1 receives the reference voltage Vref and the divided voltage Vdv generated by the reference voltage generation unit 2 and outputs a differential voltage corresponding to the difference between the reference voltage Vref and the divided voltage Vdv to the amplification unit 3. A phase compensation capacitor C2 is connected between the output of the differential unit 1 and the input voltage VIN.

  The output of the amplifier 3 is connected to the base electrode of the first transistor Q1. The amplifier 3 amplifies the differential voltage and inputs it to the base electrode of the first transistor Q1.

  Patent Document 1 listed below describes a series regulator power supply circuit including an amplification stage having a variable resistance portion whose resistance value decreases in response to an increase in load. This series regulator power supply circuit further includes a MOS switch that is a phase compensation canceling means, thereby generating zero at heavy load and ensuring optimum frequency characteristics at both light load and heavy load.

JP 2006-318204 A

  The frequency characteristics of the transfer function are taken into account when phase compensation of the series regulator. When the series regulator circuit 100 includes the phase compensation capacitor C2, the transfer function is determined by the first pole determined by the resistance of the load L and the capacitance of the bypass capacitor C1, the output impedance of the differential unit 1, and the capacitance of the phase compensation capacitor C2. It has a second pole.

When the resistance value of the load L is RL and the capacitance value of the bypass capacitor C1 is Co, the frequency fp1 of the first pole is given by the following equation (1).
fp1 = 1 / (2π × RL × Co) (1)

When the value of the output impedance of the differential section 1 is Z and the value of the phase compensation capacitor C2 is Cp, the frequency fp2 of the second pole is given by the following equation (2).
fp2 = 1 / (2π × Z × Cp) (2)

  In order for the series regulator circuit 100 to operate stably, it is desirable that the phase margin is large. The phase margin is determined by how many smaller than 180 degrees the phase shift amount due to the pole at the frequency at which the gain reaches zero.

  An object of the present invention is to increase the phase margin of a series regulator circuit.

  A constant voltage circuit according to an aspect of the present invention includes a first transistor that is connected between an input voltage and a load and supplies an output voltage to the load, a voltage detection unit that outputs a voltage signal corresponding to the output voltage, and a reference voltage A differential unit that outputs a differential voltage corresponding to a difference between the differential signal and the voltage signal; an amplifier unit that amplifies the differential voltage and inputs the differential voltage to the control electrode of the first transistor; and at least one of the differential unit and the amplifier unit A feedback path for negatively feeding back a current corresponding to the output current of the first transistor to the output of the first transistor.

  According to the present invention, the feedback current corresponding to the output current of the first transistor is negatively fed back to the output of at least one of the differential unit and the amplification unit, so that the differential unit and / or the amplification unit to which the feedback current is fed back. The output impedance can be reduced. As a result, the gain of the series regulator circuit is reduced, so that the phase margin of the series regulator circuit can be increased.

  In addition, according to the present invention, the output impedance of the differential section can be reduced by negatively feeding back the feedback current to the output of the differential section. As a result, the frequency fp2 of the second pole can be moved to the high frequency side, and the phase margin of the series regulator circuit can be increased.

  In the present invention, in order to reduce the output impedance of the differential unit and / or the amplifier unit, the feedback current corresponding to the output current of the first transistor is negatively fed back. As another method of reducing the output impedance of the differential unit and / or the amplification unit, it is conceivable to reduce the output impedance by adjusting constants of circuit elements constituting the differential unit and the amplification unit. However, according to the present invention, it is easy to increase the amount of decrease in output impedance as compared with the method of adjusting the constants of circuit elements. Further, according to the present invention, the output impedance can be easily adjusted, so that the output impedance value can be set with higher accuracy.

It is a schematic block diagram of a series regulator circuit. It is a block diagram of the series regulator circuit by 1st Example. It is a block diagram of the series regulator circuit by 2nd Example. (A) And (B) is a Bode diagram explaining the increase in the phase margin by the reduction of the gain. (A) And (B) is a board figure explaining the increase in a phase margin by reduction of output impedance. It is a block diagram of the series regulator circuit by 3rd Example. It is a block diagram of the series regulator circuit by 4th Example. It is a block diagram of the series regulator circuit by 5th Example.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 2 is a configuration diagram of the series regulator circuit according to the first embodiment. The series regulator circuit 10 includes a first transistor Q1, a differential unit 1, a reference voltage generation unit 2, an amplification unit 3, a voltage detection unit 4, a current signal generation unit 5, a bypass capacitor C1, and phase compensation. A capacitor C2 is provided.

  The first transistor Q1 is an NPN-type bipolar transistor, and an emitter electrode and a collector electrode are used as a conductive electrode, and a base electrode is used as a control electrode. An input voltage VIN is connected to the collector electrode of the first transistor Q1, and a load L is connected to the emitter electrode. The first transistor Q1 outputs the output voltage VOUT and the output current I1 to the load L.

  The phase of the value of the output voltage VOUT and the value of the output current I1 is in phase with the phase of the value of the voltage applied to the base electrode. That is, when the voltage applied to the base electrode increases, the output voltage VOUT and the output current I1 increase, and when the voltage applied to the base electrode decreases, the output voltage VOUT and the output current I1 decrease.

  The bypass capacitor C1 is connected to the load L in parallel. The voltage detector 4 outputs a voltage signal V1 corresponding to the output voltage VOUT of the first transistor Q1. The voltage detector 4 may be, for example, a voltage dividing circuit having a series connection of a plurality of resistors connected between the output voltage VOUT and the ground.

  The differential unit 1 includes a reference voltage generation unit 2 that generates a reference voltage Vref and a differential amplifier connected to the output of the voltage detection unit 4. A voltage signal V1 and a reference voltage Vref are applied to the positive input and the negative input of the differential amplifier, respectively.

  The output of the differential unit 1 is connected to the input of the amplification unit 3. The differential unit 1 outputs a differential voltage V2 corresponding to the difference between the reference voltage Vref and the voltage signal V1 to the differential unit 3. When the divided voltage V1 becomes larger than the reference voltage Vref, the differential voltage V2 becomes large, and when the divided voltage V1 becomes smaller than the reference voltage Vref, the differential voltage V2 becomes small. The phase compensation capacitor C2 is connected between the output of the differential unit 1 and the input voltage VIN.

  The amplification unit 3 includes an inverting amplifier. The input of the inverting amplifier is connected to the output of the differential unit 1, and the output is connected to the base electrode of the first transistor Q1. The amplifying unit 3 inverts and amplifies the differential voltage V2 output from the differential unit 1 and inputs it to the base electrode of the first transistor Q1.

  Accordingly, when the divided voltage V1 becomes larger than the reference voltage Vref, the voltage applied to the base electrode of the first transistor Q1 is reduced, and the first transistor Q1 is controlled so that the output voltage VOUT is reduced. Further, when the divided voltage V1 becomes smaller than the reference voltage Vref, the voltage applied to the base electrode of the first transistor Q1 is increased, and the first transistor Q1 is controlled so that the output voltage VOUT is increased.

  The current signal generator 5 generates a current signal I2 corresponding to the output current I1 of the first transistor Q1. The current signal generated by the current signal generator 5 may be referred to as “feedback current”.

  As will be described later, the current signal generator 5 may be realized by an input voltage VIN, a shunt resistor connected in series with the first transistor Q1 and the load L, and a sense amplifier that detects a voltage drop caused by the shunt resistor. In addition, the current signal generation unit 5 may be realized by a transistor element controlled by a control signal common to the first transistor Q1. In addition, the current signal generation unit 5 may be realized by a transistor element controlled by a common control signal with a transistor element provided in the amplification unit 3 to drive the first transistor Q1.

  In the embodiment shown in FIG. 2, the current signal generator 5 may generate a feedback current I2 that is in phase with the phase of the output current I1. The current signal generator 5 inputs the feedback current I2 to the output line 7 of the differential unit 1 via the line 6. The current signal generator 5 and the line 6 are examples of feedback paths described in the claims.

  Next, the operation of the feedback current input to the output line 7 of the differential unit 1 will be described. The amplifying unit 3 inverts and amplifies the output voltage V2 of the differential unit 1. For this reason, a signal having a phase opposite to that of the output voltage V2 is applied to the base electrode of the transistor Q1. Therefore, the direction of change of the output voltage V2 of the differential unit 1 is opposite to the direction of change of the output current I1 of the transistor Q1.

  For this reason, when the feedback current I2 having the same phase as the output current I1 is fed back to the output of the differential section 1, the feedback current I2 acts in a direction that hinders the change of the output voltage V2 of the differential section 1. Therefore, the feedback of the feedback current I2 is negative feedback. As a result, the change in the output voltage V2 with respect to the change in output current in the differential unit 1 is reduced, and the output impedance of the differential unit 1 is reduced.

  In another embodiment, the feedback current output from the current signal generator 5 may be input to the output line 8 of the amplifier 3 as shown in FIG. FIG. 3 is a configuration diagram of a series regulator circuit according to the second embodiment. By inputting the feedback current to the output line 8 of the amplifying unit 3, the output impedance of the amplifying unit 3 is lowered.

  In this case, the current signal generator 5 generates the feedback current so that the feedback current becomes negative feedback, that is, the direction of change of the feedback current is opposite to the direction of change of the output voltage of the amplifier 3. The current signal generator 5 generates a feedback current having a phase opposite to that of the output current I1 of the transistor Q1.

  In another embodiment, negative feedback of feedback current to the output of the differential unit 1 and negative feedback of feedback current to the output of the amplification unit 3 may be combined.

  By reducing the output impedance of the differential unit 1 and / or the output impedance of the amplification unit 3, the gain of the series regulator circuit 10 is reduced. As a result, the phase margin of the series regulator circuit 10 increases. FIG. 4A and FIG. 4B are Bode diagrams illustrating an increase in phase margin due to a decrease in gain.

  4A and 4B are a gain diagram and a phase diagram of a series regulator having a first pole fp1 and a second pole fp2, respectively. In the gain diagram, a dotted line and a solid line indicate characteristics when the gain is not reduced and when the gain is reduced, respectively.

  In the example of FIGS. 4A and 4B, when the gain is not reduced, the phase shift amount reaches 180 degrees before the gain becomes zero at the frequency fa. For this reason, the phase margin is zero. On the other hand, when the gain is reduced, the phase shift amount does not yet reach 180 degrees even when the gain becomes zero at the frequency fb. For this reason, there is a phase margin Pm. In this way, the phase margin of the series regulator is improved by reducing the gain.

  Next, the effect of increasing the phase margin by reducing the output impedance of the differential section 1 will be described. When the phase compensation capacitor C2 is provided between the differential unit 1 and the amplification unit 3, the transfer function of the series regulator circuit 10 has a second pole given by the frequency of the above equation (2). When the phase compensation of the regulator is performed, it is desirable that the distance between the first pole and the second pole be as wide as possible.

  When the phase compensation capacitor C2 is built in an integrated circuit (IC), there is a limit to the capacity of the phase compensation capacitor C2. For this reason, in a normal case, the second pole is generated on the higher frequency side than the first pole.

  The frequency of the first pole is determined by the capacitance of the bypass capacitor C1 and the resistance value of the load L. For this reason, when the load increases, the first pole moves to the high frequency side, so that the phase margin is deteriorated. As a method for improving the phase margin, it is conceivable to increase the capacity of the bypass capacitor C1, but increasing the capacity of the bypass capacitor C1 causes an increase in cost.

  Therefore, in this embodiment, the phase margin is increased by reducing the output impedance. When the impedance Z of the differential section 1 is reduced by the above equation (2), the frequency of the second pole is increased. The influence on the phase margin due to the increase in the frequency of the second pole will be described with reference to FIGS. FIG. 5A and FIG. 5B are board diagrams for explaining an increase in phase margin due to a reduction in output impedance.

  In FIG. 5A and FIG. 5B, the dotted line and the solid line indicate the characteristics when the output impedance is not reduced and when the output impedance is reduced, respectively. Further, fp1 is the frequency of the first pole, fp21 is the frequency of the second pole when the output impedance is not reduced, and fp22 is the frequency of the second pole when the output impedance is reduced. As the output impedance is reduced, the frequency of the second pole moves from fp21 to a higher speed fp22.

  In the examples of FIGS. 5A and 5B, when the output impedance is not reduced, the phase shift amount reaches 180 degrees before the gain becomes zero at the frequency fa. For this reason, the phase margin is zero. On the other hand, in a state where the output impedance is reduced, the phase margin Pm exists because the phase shift amount does not reach 180 degrees when the gain becomes zero at the frequency fb. Thus, the phase margin of the series regulator increases due to the output impedance reduction.

  Next, another embodiment of the series regulator circuit will be described. FIG. 6 is a block diagram of a series regulator circuit according to the third embodiment. The series regulator circuit 10 includes a first transistor Q1, a differential unit 1, a reference voltage generation unit 2, an amplification unit 3, a voltage detection unit 4, a current signal generation unit 5, a bypass capacitor C1, a differential A phase compensation capacitor C2 provided between the unit 1 and the amplification unit 3 is provided.

  The first transistor Q1 is an NPN-type bipolar transistor, and an emitter electrode and a collector electrode are used as a conductive electrode, and a base electrode is used as a control electrode. An input voltage VIN is connected to the collector electrode of the first transistor Q1, and a load L is connected to the emitter electrode. The bypass capacitor C1 is connected to the load L in parallel.

  The voltage detection unit 4 includes a voltage dividing circuit having a series connection of resistors R1 and R2. The resistors R1 and R2 are connected between the output voltage VOUT of the first transistor Q1 and the ground. The voltage detector 4 outputs a divided voltage V1 obtained by dividing the output voltage VOUT of the first transistor Q1 by the ratio of the resistors R1 and R2.

  The differential unit 1 includes a differential pair formed by NPN transistors Q2 and Q3, a constant current source 20 commonly connected to the emitter electrodes of the transistors Q2 and Q3, and a current mirror circuit including PNP transistors Q4 and Q5. And comprising. The differential section 1 includes a series connection of a constant current source 21 and a PNP transistor Q6 that form a level shift circuit, and a series connection of a constant current source 22 and a PNP transistor Q7 that form a level shift circuit.

  The emitter electrodes of the transistors Q4 and Q5 are connected to the input voltage VIN, and the collector electrodes are connected to the collector electrodes of the transistors Q2 and Q3, respectively. The base electrodes of transistors Q4 and Q5 are connected to the collector electrode of transistor Q5. Thus, the current mirror circuit formed by the transistors Q4 and Q5 is connected as an active load to the differential pair formed by the transistors Q2 and Q3. The output line 7 of the differential section 1 is taken out from the collector electrode of the transistor Q2.

  The constant current source 21 is connected between the input voltage VIN and the emitter electrode of the transistor Q6, and the collector electrode of the transistor Q6 is connected to the ground. The constant current source 21 and the transistor Q6 form a level shift circuit that shifts the voltage level of the reference voltage Vref applied to the base electrode. The emitter electrode of the transistor Q6 is connected to the base electrode of the transistor Q2, and the reference voltage Vref after the voltage level is shifted is input to the base electrode of the transistor Q2.

  The constant current source 22 is connected between the input voltage VIN and the emitter electrode of the transistor Q7, and the collector electrode of the transistor Q7 is connected to the ground. The constant current source 22 and the transistor Q7 form a level shift circuit that shifts the voltage level of the divided voltage V1 applied to the base electrode. The emitter electrode of the transistor Q7 is connected to the base electrode of the transistor Q3, and the divided voltage V1 after the voltage level is shifted is input to the base electrode of the transistor Q3.

  The reference voltage Vref and the divided voltage V1 are input to the transistors Q2 and Q3 forming the differential pair, respectively, and a differential voltage corresponding to the difference between the reference voltage Vref and the divided voltage V1 is output from the output line 7 of the differential section 1. V2 is output.

  The amplifying unit 3 includes a series connection of a constant current source 23 and a PNP transistor Q8 forming a level shift circuit, a second transistor Q9 which is a PNP transistor, and a resistor R4.

  The constant current source 23 is connected between the input voltage VIN and the emitter electrode of the transistor Q8, and the collector electrode of the transistor Q8 is connected to the ground. The base electrode of the transistor Q8 is connected to the output line 7 of the differential unit 1. The constant current source 23 and the transistor Q8 are provided for the purpose of amplifying the output current from the differential unit 1. The emitter electrode of the transistor Q8 is connected to the base electrode of the second transistor Q9, and the differential voltage V2 after the voltage level is shifted is input to the base electrode of the second transistor Q9.

  The emitter electrode, which is the first conduction electrode of the second transistor Q9, which is a PNP transistor, is connected to the input voltage VIN. A resistor R4 is connected between the collector electrode, which is the second conductive electrode, and the load L, and the collector current of the second transistor Q9 flows through the resistor R4. Since the phase of the collector current of the second transistor Q9 is opposite to the phase of the differential voltage V2 applied to the base electrode, a voltage drop having a phase opposite to the phase of the differential voltage V2 appears across the resistor R4.

  Both ends of the resistor R4 are connected to the base electrode and the emitter electrode of the first transistor Q1. Therefore, the output voltage VOUT and the output current V1 of the first transistor Q1 are controlled by the collector current of the second transistor Q9.

  When the divided voltage V1 is larger than the reference voltage Vref, the output voltage V2 of the differential unit 1 is increased, and as a result, the output voltage VOUT and the output current V1 of the first transistor Q1 are decreased. Further, when the divided voltage V1 becomes smaller than the reference voltage Vref, the output voltage V2 of the differential unit 1 becomes small, and as a result, the output voltage VOUT and the output current V1 of the first transistor Q1 become large.

  The current signal generator 5 includes a third transistor Q10, which is a PNP transistor, and a resistor R5. The base electrode of the third transistor Q10 is connected to the base electrode of the second transistor Q9, and the emitter electrode of the third transistor Q10 is connected to the input voltage VIN via the resistor R5. That is, the emitter electrode of the third transistor Q10 is connected to the emitter electrode of the second transistor Q9 via the resistor R5.

  The collector current of the third transistor Q10 becomes an in-phase signal with the collector current of the second transistor Q9. The ratio of the collector current of the second transistor Q9 and the collector current of the third transistor Q10 can be set by the area of the junction surface of the PN junction of the second transistor Q9 and the third transistor Q10 and the resistor R5. The collector current of the third transistor Q10 may be 1/2000 of the collector current of the second transistor Q9, for example.

  The collector electrode of the third transistor Q10 is connected to the output line 7 of the differential section 1 via the line 6. Since the collector current of the third transistor Q10 having the same phase as that of the collector current of the second transistor Q9 is opposite in phase to the differential voltage V2, the collector current of the third transistor Q10 is input to the output line 7 of the differential section 1. Is negative feedback. Therefore, the output impedance of the differential section 1 can be reduced as in the first embodiment. As a result, the gain of the series regulator circuit 10 is reduced.

  According to this embodiment, the gain of the series regulator circuit 10 is reduced and the phase margin of the series regulator circuit 10 is increased. Further, the output impedance of the differential unit 1 is reduced, so that the frequency of the second pole becomes faster and the phase margin of the series regulator circuit 10 increases.

  According to this embodiment, in order to reduce the output impedance of the differential section 1, the feedback current corresponding to the output current I1 of the first transistor is negatively fed back. As a method for reducing the output impedance of the differential unit 1, it is conceivable to change the constants of the circuit elements forming the differential unit 1. However, it is actually difficult to greatly reduce the output impedance of the differential section 1 by changing the constants of the circuit elements due to design constraints. It is also difficult to adjust the output impedance to a desired value.

  According to the present embodiment, it is easy to arbitrarily set the magnitude of the feedback current. For this reason, the amount of reduction in output impedance can be increased as compared with the method of changing the constant of the circuit element. . Since the value of the output impedance can be adjusted by the value of the feedback current, it is difficult to adjust the output impedance to a desired value.

  Next, another embodiment of the series regulator circuit will be described. FIG. 7 is a configuration diagram of a series regulator circuit according to the fourth embodiment. Constituent elements that are the same as those shown in FIG. The operation of the components denoted by the same reference numerals is the same unless otherwise described.

  The current signal generator 5 includes a shunt resistor R6 connected in series to the input voltage VIN, the load L, and the first transistor Q1, and a sense amplifier that detects a potential difference generated at both ends of the shunt resistor R6 and outputs a current corresponding to the potential difference. 24.

  In this embodiment, the shunt resistor R6 is connected between the input voltage VIN and the collector electrode of the first transistor Q1. The sense amplifier 24 outputs a signal corresponding to the collector current of the first transistor Q1 flowing through the shunt resistor R6, so that a current signal corresponding to the output current I1 output from the first transistor Q1 to the load L is used as a feedback current. Generate. The feedback current output from the sense amplifier 24 is input to the output line 7 of the differential unit 1 via the line 6.

  In another embodiment, the shunt resistor R6 may be connected between the emitter electrode of the first transistor Q1 and the load L. Alternatively, the logic of the feedback current output from the sense amplifier 24 may be inverted and then input to the output line 8 of the amplifying unit 3 via the line 6.

  According to the present embodiment, by using the sense amplifier for detecting the output current of the first transistor Q1, it is possible to increase the accuracy of the feedback current as compared with the second embodiment.

  Next, another embodiment of the series regulator circuit will be described. FIG. 8 is a block diagram of a series regulator circuit according to the fifth embodiment. The series regulator circuit 10 includes a first transistor Q11, a differential unit 1, a reference voltage generation unit 2, an amplification unit 3, a voltage detection unit 4, a current signal generation unit 5, a bypass capacitor C1, a differential A phase compensation capacitor C2 provided between the unit 1 and the amplification unit 3 is provided.

  The first transistor Q11 is a PNP-type bipolar transistor, and an emitter electrode and a collector electrode are used as a conductive electrode, and a base electrode is used as a control electrode. The emitter electrode of the first transistor Q11 is connected to the input voltage VIN, and the load L is connected to the collector electrode. The phase of the control voltage applied to the base electrode of the first transistor Q11 is opposite to the phase of the output voltage VOUT.

  The bypass capacitor C1 is connected to the load L in parallel. The voltage detection unit 4 includes a voltage dividing circuit having a series connection of resistors R1 and R2. The resistors R1 and R2 are connected between the output voltage VOUT of the first transistor Q1 and the ground. The voltage detector 4 outputs a divided voltage V1 of the output voltage VOUT.

  The differential unit 1 includes a differential amplifier. The differential amplifier is connected to the outputs of the reference voltage generator 2 and the voltage detector 4 that generate the reference voltage Vref, and receives the reference voltage Vref and the voltage signal V1. A reference voltage Vref and a voltage signal V1 are applied to the positive input and the negative input of the differential amplifier, respectively.

  The output of the differential unit 1 is connected to the input of the amplification unit 3. The differential unit 1 outputs a differential voltage V2 corresponding to the difference between the reference voltage Vref and the voltage signal V1 to the differential unit 3. When the divided voltage V1 becomes larger than the reference voltage Vref, the differential voltage V2 becomes small. When the divided voltage V1 becomes smaller than the reference voltage Vref, the differential voltage V2 becomes large. The phase compensation capacitor C2 is connected between the output of the differential unit 1 and the input voltage VIN.

  The amplifying unit 3 includes a second transistor Q19 and a constant current source 25 connected between the input voltage VIN and the second transistor Q19. The second transistor Q19 is an NPN-type bipolar transistor, and the output of the differential unit 1 is connected to the base electrode. The emitter electrode is connected to the ground, and the collector electrode is connected to the constant current source 25. The output line 8 of the amplifying unit 3 is taken out from the collector electrode of the second transistor Q19 and connected to the base electrode of the first transistor Q11. The phase of the output voltage of the second transistor Q19 is opposite to the phase of the original differential voltage V2.

  Therefore, when the divided voltage V1 is larger than the reference voltage Vref, the voltage applied to the base electrode of the first transistor Q11 is increased, and the output voltage VOUT is controlled to be smaller. Further, when the divided voltage V1 becomes smaller than the reference voltage Vref, the voltage applied to the base electrode of the first transistor Q1 is reduced, and the output voltage VOUT is controlled to be larger.

  The current signal generator 5 includes a third transistor Q20, which is a PNP transistor, and a resistor R15. The base electrode of the third transistor Q20 is connected to the base electrode of the first transistor Q11, and the emitter electrode of the third transistor Q20 is connected to the input voltage VIN via the resistor R15. That is, the emitter electrode of the third transistor Q20 is connected to the emitter electrode of the first transistor Q11 via the resistor R15.

  As a result, the collector current of the third transistor Q20 becomes an in-phase signal with the collector current of the first transistor Q11. The ratio between the collector current of the first transistor Q11 and the collector current of the third transistor Q20 is set by the area of the junction surface of the PN junction of the first transistor Q11 and the third transistor Q20 and the resistor R15.

  The collector electrode of the third transistor Q20 is connected to the collector electrode of the second transistor Q19 to which the output line 8 of the amplifying unit 3 is connected. Since the collector current of the third transistor Q20 is in reverse phase to the potential of the collector electrode of the second transistor Q19, the feedback of the collector current of the third transistor Q20 is negative feedback. Therefore, the output impedance of the amplifying unit 3 is reduced, and the gain of the series regulator circuit 10 is reduced.

  According to the present embodiment, in order to generate a feedback current that reduces the output impedance of the amplifying unit 3 using another transistor controlled by a common control signal with the first transistor 11 connected in series to the load. The current flowing through the first transistor 11 used for the above can be detected.

  In another embodiment, the current flowing through the output transistor is detected using another transistor controlled by a common control signal with the output transistor connected in series with the load, and the feedback current according to the current flowing through the output transistor is Negative feedback may be provided to the output of the amplifying unit 1.

  For example, in the circuit configuration shown in FIG. 8, the divided voltage V1 and the reference voltage Vref are used as the positive input and the negative input of the differential section 1, and a PNP bipolar transistor is used as the second transistor Q19. Then, the collector current of the third transistor Q20 may be fed back to the output line of the differential unit 1.

DESCRIPTION OF SYMBOLS 1 Differential part 3 Amplifying part 4 Voltage detection part 5 Current signal generation part 10 Series regulator circuit C1 Bypass capacitor C2 Phase compensation capacitor L Load Q1 1st transistor

Claims (6)

A first transistor connected between the input voltage and the load to supply an output voltage to the load;
A voltage detector that outputs a voltage signal corresponding to the output voltage;
A differential unit that outputs a differential voltage corresponding to a difference between a reference voltage and the voltage signal;
An amplifier for amplifying the differential voltage and inputting the amplified voltage to the control electrode of the first transistor;
A phase compensation capacitor connected between the output of the differential section and the input voltage;
A feedback path that is arranged in parallel with the phase compensation capacitor and negatively feeds back a feedback current corresponding to the output current of the first transistor to at least one of the output of the differential unit and the amplification unit;
A constant voltage circuit comprising: The amplifying unit includes a second transistor that drives the first transistor according to a control signal according to the differential voltage,
2. The constant voltage circuit according to claim 1, wherein the feedback path includes a third transistor that controls the feedback current to be negatively fed back to the output of the amplifier according to the control signal. The second transistor includes a base electrode to which a control signal corresponding to the differential voltage is applied and an emitter electrode connected to the input voltage, and controls a collector current that drives the first transistor,
The third transistor includes a base electrode and an emitter electrode respectively connected to a base electrode and an emitter electrode of the second transistor, and controls a collector current as the feedback current to be negatively fed back to the output of the amplifying unit. 2. The constant voltage circuit according to 2.   The constant voltage circuit according to claim 1, wherein the feedback path includes a third transistor that controls the feedback current in accordance with a control signal common to the first transistor. The first transistor includes a base electrode and an emitter electrode connected to the output of the differential unit and the input voltage, respectively, and controls a collector current output to the load;
5. The constant voltage circuit according to claim 4, wherein the third transistor includes a base electrode and an emitter electrode connected to the base electrode and the emitter electrode of the first transistor, respectively, and controls a collector current as the feedback current. The feedback path is
A resistor connected in series to the input voltage, the load and the first transistor;
A sense amplifier that detects a potential difference generated at both ends of the resistor and applies a current corresponding to the potential difference to the at least one output;
A constant voltage circuit according to claim 1.

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