JP5687078B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a technique for forming a termination structure of a semiconductor element.

  Semiconductor elements using silicon carbide (SiC) are promising as next-generation switching elements that can achieve high withstand voltage, low loss, and high heat resistance, and are expected to be applied to power semiconductor devices such as inverters. . However, many problems to be solved remain in the SiC semiconductor device. One of them is a semiconductor device due to electric field concentration at a terminal portion of a semiconductor element (for example, an end portion of a Schottky electrode of a Schottky barrier diode or an end portion of a pn diode or a pn junction of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)). This is a problem that the withstand voltage characteristics of the above deteriorate.

  Typical examples of the termination structure for reducing the electric field generated at the termination portion of the semiconductor element include a guard ring structure, a JTE (Junction Termination Extension) structure, and an FLR (Field Limiting Ring) structure. These are impurity regions formed so as to surround the semiconductor element. In general, the JTE structure is provided for the purpose of reducing the surface electric field, and has a structure in which the impurity concentration gradually decreases from the terminal portion of the semiconductor element to the outside. On the other hand, the FLR structure is composed of a plurality of impurity regions having the same concentration.

  For example, Patent Document 1 below discloses a termination structure that combines a guard ring and JTE. The termination structure of Patent Document 1 is a structure in which a JTE having a lower impurity concentration than the guard ring is disposed outside the guard ring. Further, in Patent Document 1, the guard ring and the JTE are formed under the recess provided on the surface of the semiconductor layer, thereby increasing the distance between the bottom end of the guard ring and the JTE where the electric field concentration is likely to occur and the surface of the semiconductor layer. A technique for further relaxing the electric field on the surface of the semiconductor layer has been proposed.

International Publication No. 2009/116444

  In general, the guard ring is formed with a relatively high impurity concentration in order to ensure the withstand voltage performance of the semiconductor element. For this reason, when a high voltage is applied to the semiconductor element, the depletion layer does not grow much in the impurity region of the guard ring, and a strong electric field is likely to be generated. When the guard ring is formed under the recess as in Patent Document 1, a strong electric field is likely to be generated at the bottom end of the recess.

  Furthermore, the present inventors have found that in the etching for forming the recess, when a sharp notch (notch) is formed at the bottom end of the recess, the electric field at that portion becomes particularly strong. Various etching conditions were examined to prevent the formation of a notch at the bottom of the recess. As a result of investigation, if the etching rate was lowered, the notch tended to become smaller. However, since SiC has a higher hardness than Si, the notch is generated while maintaining a practical etching rate in the formation of the SiC semiconductor element. It was difficult to suppress.

  The present invention has been made to solve the above-described problems, and in forming a termination structure including an impurity region formed at the bottom of the recess, the notch generated at the bottom end of the recess is removed or a gentle shape is formed. It is an object of the present invention to provide a method for manufacturing a silicon carbide semiconductor device that can be made.

A method for manufacturing a silicon carbide semiconductor device according to a first aspect of the present invention includes a step of forming a recess in a silicon carbide semiconductor layer by reactive ion etching in a termination region of a silicon carbide semiconductor element; A step of ion-implanting the region including the recess to form an impurity region , and thermally oxidizing the surface of the semiconductor layer including the impurity region formed by the ion implantation inside the recess, The method includes a step of forming an oxide layer having a thickness of 0.05 μm or more and 10 μm or less on the surface and a step of removing the oxide layer.

A method for manufacturing a silicon carbide semiconductor device according to a second aspect of the present invention includes: forming a recess in a silicon carbide semiconductor layer by reactive ion etching in a termination region of a silicon carbide semiconductor element; and A photoresist is formed on the surface of the semiconductor layer including the interior of the recess by ion implantation into the region including the recess, and the photoresist is thickened at the notch portion formed in the recess forming step. and curing the coating to the surface of the photoresist is the semiconductor layer which is formed, while removing the photoresist, in which and a step you reactive ion etching.

  According to the method for manufacturing a silicon carbide semiconductor device according to the first and second aspects of the present invention, even if a notch is generated at the bottom end of the recess in the step of forming the recess, the notch is formed in the subsequent step. It can be removed or reduced in curvature. Therefore, generation of a strong electric field at the bottom end of the recess can be suppressed, and the withstand voltage performance of the silicon carbide semiconductor device can be improved.

  According to the silicon carbide semiconductor device of the third aspect of the present invention, since the impurity region is locally deeply formed under the bottom end portion of the recess, electric field concentration in the portion can be reduced, and the silicon carbide semiconductor The withstand voltage performance of the device is improved.

It is a block diagram of the termination area | region of the semiconductor device which concerns on embodiment of this invention. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor device according to the third embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a diagram showing a configuration of a termination structure of a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram showing a configuration of a termination structure of a semiconductor device according to a fifth embodiment.

<Embodiment 1>
FIG. 1 is a configuration diagram of a termination region of the semiconductor device according to the first embodiment. Here, as an example, a configuration is shown in which a guard ring is provided as a termination structure at the end of a Schottky barrier diode formed using a silicon carbide (SiC) semiconductor.

  The semiconductor device is formed using an epitaxial substrate including an n-type SiC substrate 1 and an n-type SiC drift layer 2 epitaxially grown thereon. On the upper surface of the SiC drift layer 2, an anode electrode 3 that is in Schottky connection with the SiC drift layer 2 is disposed. On the anode electrode 3, the pad electrode 4 for connecting wiring is formed.

  A cathode electrode 4 that is in ohmic contact with the SiC substrate 1 is disposed on the lower surface of the SiC substrate 1. A protective film 8 (for example, polyimide) having an opening on the pad electrode 4 is formed on the upper surface of the semiconductor device.

  As shown in FIG. 1, the region including the region below the end portion of the anode electrode 3 in the surface portion of the SiC drift layer 2 is a guard that is a p-type impurity region for suppressing electric field concentration under the end portion of the anode electrode 3. A ring 6 is formed. The guard ring 6 is formed at the bottom of the recess 7 formed in the SiC drift layer 2, and the end of the anode electrode 3 extends into the recess 7. With this structure, the distance between the bottom end portion of guard ring 6 and the surface of SiC drift layer 2 is increased, so that the electric field at the surface portion of SiC drift layer 2 is relaxed.

  The guard ring 6 is formed not only on the bottom portion of the recess 7 but also on the inner wall portion thereof. Thereby, the longitudinal cross-sectional area of the guard ring 6 becomes large, and the electric field concentration at the bottom end portion of the guard ring 6 is further alleviated.

  Hereinafter, a method for manufacturing the semiconductor device according to the present embodiment will be described. As described above, the present invention relates to a notch generated at the bottom end of the recess 7, and therefore, in this specification, a method for forming the recess 7 will be mainly described. In each process diagram, a dotted line in FIG. The portion of the enclosed recess end 10 is shown enlarged.

First, an n-type (n ⁺ -type) SiC substrate 1 having a relatively high impurity concentration is prepared, and an n-type SiC drift layer 2 is formed thereon by epitaxial growth. Here, as the SiC substrate 1, a 4H polytype having a plane orientation of (0001) was used.

  Subsequently, a recess 7 is formed on the upper surface of the SiC drift layer 2 by the following procedure. FIG. 2 is a process chart of forming the recess 7.

First, a photoresist 9 patterned so as to open the formation region of the guard ring 6 is formed on the SiC drift layer 2 (FIG. 2A). Then, using the photoresist 9 as a mask, reactive ion etching (RIE) using SF ₆ as a reactive gas is performed to form a recess 7 on the upper surface of the SiC drift layer 2 (FIG. 2B). At this time, a notch 11 appears at the bottom end of the recess 7. It is presumed that RIE etching ions tend to concentrate on the corner portion of the recess 7 and an electrical bias accompanying RIE is added to this portion.

  In the present embodiment, the depth of the recess 7 is 0.3 μm from the surface of the SiC drift layer 2. The depth of the recess 7 formed in this step is not limited to 0.3 μm, but is preferably 0.5 μm or less. If it is deeper than 0.5 μm, the reproducibility of the shape of the notch 11 becomes unstable.

  In order to reduce the number of necessary mask patterns, the alignment mark pattern may be formed in the SiC drift layer 2 by RIE forming the recess 7 by including the alignment mark pattern in the photoresist 9. In that case, the depth of the recess 7 is preferably 0.03 μm or more. This is because if it is shallower than this, the visibility of the alignment mark is poor and it is difficult to align the mask pattern.

  Subsequently, ion implantation of a p-type impurity such as aluminum (Al) is performed using the photoresist 9 as a mask to form a guard ring 6 which is a p-type impurity region (FIG. 2C). Then, the photoresist 9 is removed (FIG. 2D).

  In the present embodiment, a photoresist 9 having an angle formed by the side wall of the photoresist 9 and the surface of the SiC drift layer 2 of 45 degrees or more and less than 80 degrees is used. In addition, the DC bias voltage of RIE was set to 0 V or more and less than 300 V, and the etching rate of RIE for forming the recess 7 was slowed within a range that can maintain a practical speed so as to make the notch 11 as shallow as possible. When the cross-sectional shape of the recess 7 is observed using an electron microscope, the depth of the notch 11 appearing at the bottom end of the recess 7 is 0.01 μm, and the radius of curvature of the tip is sharp, about 0.03 μm. It was. Such a sharp tip of the notch 11 generates a high electric field at the bottom end of the recess 7 and causes a reduction in withstand voltage of the semiconductor device.

  Next, the following processing is performed on the recess 7. FIG. 3 is a process diagram thereof.

  The surface of the SiC drift layer 2 including the inside of the recess 7 is thermally oxidized to form an oxide layer 12 having a thickness of about 0.1 μm (FIG. 3A). The temperature of the thermal oxidation treatment was 1150 ° C. The dotted lines shown in FIG. 3A indicate the shapes of the recess 7 and the notch 11 before the oxide layer 12 is formed. Since the volume of the SiC drift layer 2 expands when oxidized, the oxide layer 12 is formed so as to fill the notch 11, and the bottom surface of the oxide layer 12 formed in the notch 11 has a notch immediately after the recess 7 is formed. The shape is gentler than the tip of 11 (dotted line).

  Subsequently, the oxide layer 12 is removed by wet etching using hydrofluoric acid or the like. Then, the notch 11 having the gentle shape as described above remains at the bottom end of the recess 7 (FIG. 3B). When the cross-sectional shape of the notch 11 after the oxide layer 12 was removed was observed using an electron microscope, it was a depression having a radius of curvature of 0.13 μm.

  Although illustration is omitted, thereafter, the anode electrode 3, the pad electrode 4, and the protective film 8 are formed on the upper surface of the SiC drift layer 2, and the cathode electrode 5 is formed on the bottom surface of the SiC substrate 1. Thereby, the configuration of the Schottky barrier diode shown in FIG. 1 is obtained.

  The inventors of the present invention have formed the conventional diode (notch 11 is sharp as shown in FIG. 2D) formed without performing the thermal oxidation process of FIG. 3 and the present invention formed by performing the thermal oxidation process of FIG. The withstand voltage test of each of the diodes (notch 11 has a gentle shape as shown in FIG. 3B) was performed, and the withstand voltage performances of the two were compared. As a result, the withstand voltage value of the conventional diode is 450V, whereas the withstand voltage value of the diode according to the present invention is 730V, and the withstand voltage is increased by increasing the radius of curvature of the notch 11 (that is, decreasing the curvature). It was confirmed that the performance was greatly improved.

  Thus, according to the present embodiment, since the shape of the notch 11 at the bottom end of the recess 7 can be made gentle, the strength of the electric field generated at that portion can be suppressed, and the withstand voltage of the semiconductor device can be improved. it can.

  Note that the thickness of the oxide layer 12 formed in the step of FIG. 3A is preferably 0.05 μm or more and 10 μm or less. Further, the curvature of the bottom end of the recess 7 after removal of the oxide layer 12 (the curvature of the notch 11) can be adjusted by the thickness of the oxide layer 12 to be formed, but the curvature radius is preferably 0.05 μm or more and 10 μm or less. .

<Embodiment 2>
In the first embodiment, a technique for reducing the curvature of the notch 11 is shown. In the second embodiment, a technique for removing the notch 11 is shown. Hereinafter, a method for manufacturing the semiconductor device according to the present embodiment will be described.

  First, recess 7 and guard ring 6 are formed in SiC drift layer 2 by the same procedure as in the first embodiment. In this state, a sharp notch 11 appears at the bottom end of the recess 7 as shown in FIG. Further, as in the first embodiment, the surface of SiC drift layer 2 including the inside of recess 7 is thermally oxidized to form oxide layer 12 (FIG. 4A). The dotted lines shown in FIG. 4A indicate the shapes of the recess 7 and the notch 11 before the oxide layer 12 is formed.

Thereafter, wet etching is performed to remove the oxide layer 12 in the first embodiment, but dry etching is performed in the present embodiment. Here, reactive ion etching (RIE) using SF ₆ gas was performed as dry etching. Since the SiC drift layer 2 expands in volume when oxidized, the oxide layer 12 is formed so as to fill the notch 11, and the oxide layer 12 is thicker in the portion than the other portions. Therefore, when RIE is advanced, the bottom surface of the recess 7 and the top surface of the SiC drift layer 2 are exposed first from the oxide layer 12 as shown in FIG. 4B, and the oxide layer 12 remains only in the notch 11. .

Although the etching rate by RIE varies depending on the amount of material to be etched, in SiC RIE using SF ₆ gas, the SiC drift layer 2 that is n-type SiC and the guard ring 6 that is p-type SiC have substantially the same etching rate. On the other hand, the etching rate of oxide layer 12 containing SiO ₂ as a main component is slower than the etching rate of SiC drift layer 2 and guard ring 6.

  Therefore, when RIE is further advanced from the state of FIG. 4B, the bottom surface of the recess 7 and the top surface of the SiC drift layer 2 are etched faster than the oxide layer 12 in the notch 11. Therefore, when the oxide layer 12 in the notch 11 is removed, the notch 11 disappears from the bottom end of the recess 7 as shown in FIG. 4C, and the bottom end of the recess 7 has a smooth curved surface.

  According to the present embodiment, since the notch 11 at the bottom end portion of the recess 7 is removed, the strength of the electric field generated at that portion can be further suppressed than in the first embodiment, and the withstand voltage of the semiconductor device is improved. Can be made.

In RIE using CF ₄ gas, CHF ₃ gas, or the like, the etching rate of SiO ₂ is higher than that of SiC. Therefore, a mixed gas of these gases and SF ₆ is used for RIE of the oxide layer 12, and the difference in etching rate between SiC and SiO ₂ can be adjusted by the mixing ratio. By utilizing this, it is possible to control the shape and curvature of the bottom end portion of the recess 7 after the RIE process (FIG. 4C).

  Further, the thickness of the oxide layer 12 formed in the step of FIG. 4A is preferably 0.05 μm or more and 10 μm or less. The radius of curvature of the bottom end of the recess 7 after the oxide layer 12 is removed is preferably 0.05 μm or more and 10 μm or less.

<Embodiment 3>
Embodiment 3 shows another method for removing the notch 11. Hereinafter, a method for manufacturing the semiconductor device according to the present embodiment will be described.

  First, recess 7 and guard ring 6 are formed in SiC drift layer 2 by the same procedure as in the first embodiment. In this state, a sharp notch 11 appears at the bottom end of the recess 7 as shown in FIG.

  Subsequently, a photoresist 13 is applied to the surface of the SiC drift layer 2 including the inside of the recess 7 (FIG. 5A). Here, a photoresist 13 having a thickness of 0.3 μm was applied. At this time, the photoresist 13 is filled in the recess 7, but the surface of the photoresist 13 above the recess 7 becomes a smooth curved surface due to surface tension. Therefore, the photoresist 13 is thicker on the notch 11 than on other portions.

Then, the photoresist 13 is cured and the surface thereof is dry etched. Here, as dry etching, RIE was performed using a mixed gas of SF ₆ and CHF ₃ as an etching gas. Since the photoresist 13 is thick at the notch 11 as described above, when the RIE is advanced, the bottom surface of the recess 7 and the top surface of the SiC drift layer 2 are first exposed from the photoresist 13 as shown in FIG. The photoresist 13 is left exposed only in the notch 11.

  Therefore, when RIE is further advanced from the state of FIG. 5B, the bottom surface of the recess 7 and the top surface of the SiC drift layer 2 are etched while the inner wall of the notch 11 is protected by the photoresist 13. Therefore, when the photoresist 13 in the notch 11 is removed, the notch 11 disappears from the bottom end of the recess 7 as shown in FIG. 5C, and the bottom end of the recess 7 has a smooth curved surface. 5A shows the shapes of the notch 11 and the photoresist 13 in the state shown in FIG.

  According to the present embodiment, since the notch 11 at the bottom end portion of the recess 7 is removed, the strength of the electric field generated at that portion can be further suppressed than in the first embodiment, and the withstand voltage of the semiconductor device is improved. Can be made.

  Note that the thickness of the photoresist 13 applied in the step of FIG. 5A is preferably 0.05 μm or more and 10 μm or less. The radius of curvature of the bottom end of the recess 7 after the removal of the photoresist 13 is preferably 0.05 μm or more and 10 μm or less.

<Embodiment 4>
In the first embodiment, the etching rate of RIE for forming the recess 7 is slowed within a practical range, the depth of the notch 11 is suppressed to about 0.01 μm, and the notch 11 can be easily reduced in curvature. I was able to do it. On the contrary, the fourth embodiment proposes a technique for improving the breakdown voltage of the semiconductor device by forming a deep notch 11 at the bottom end of the recess 7.

  FIG. 6 is a process chart of forming the recess 7 in the present embodiment. First, a photoresist 9 patterned so as to open the formation region of the guard ring 6 is formed on the SiC drift layer 2 (FIG. 6A). In the present embodiment, as the photoresist 9, a photoresist having higher sidewall verticality than that in the first embodiment is used. Specifically, a photoresist 9 having an angle between the side wall of the photoresist 9 and the upper surface of the SiC drift layer 2 of 80 degrees or more and less than 90 degrees is used.

Then, using the photoresist 9 as a mask, reactive ion etching (RIE) using SF ₆ as a reactive gas is performed to form a recess 7 on the upper surface of the SiC drift layer 2 (FIG. 6B). In this embodiment, the DC bias voltage when performing RIE is increased. The CD bias voltage is preferably 300 V or more, but if it exceeds 1000 V, the surface of the SiC drift layer 2 is roughened.

  As a result, the etching ions are concentrated in the corner portion of the recess 7, so that the notch 11 appearing at the bottom end portion of the recess 7 becomes deeper and the shape of the tip becomes sharper. When observed using an electron microscope, the depth of the notch 11 was 0.07 μm. In addition, SiC crystal defects (not shown) are generated in the vicinity of the tip of the notch 11 due to concentration of etching ions. In the present embodiment, the notch 11 formed at this time has a depth of 0.02 μm or more and 10 μm or less, and a curvature radius of the tip is 0.001 μm or more and less than 0.03 μm.

  Subsequently, p-type impurities such as Al are ion-implanted using the photoresist 9 as a mask to form the guard ring 6 (FIG. 6C). In the present embodiment, the notch 11 is deeply formed, and a crystal defect is generated in the vicinity of the tip portion thereof, so that the p-type impurity is implanted deeper in the vicinity of the notch 11 than in other portions. Accordingly, as shown in FIG. 6C, the guard ring 6 is locally thick (deep) below the end of the recess 7.

  Then, after removing the photoresist 9 (FIG. 6D), the curvature of the notch 11 is reduced by the method described with reference to FIG. 3 in the first embodiment. As a result, as shown in FIG. 7, it is possible to obtain a termination structure in which the end of the guard ring 6 is thick (deep) and the notch 11 at the bottom end of the recess 7 has a gentle shape.

  In general, a strong electric field is likely to be generated at the bottom end portion of the guard ring 6, but by forming that portion thick, an effect of relaxing the electric field at that portion can be obtained. Therefore, in the present embodiment, the electric field generated at the bottom end of the recess 7 can be reduced as compared with the first embodiment, and the withstand voltage characteristics of the semiconductor device can be further improved.

<Embodiment 5>
In the fourth embodiment, the notch 11 is formed deep, and then the curvature is reduced by the method of the first embodiment. However, the fourth embodiment can be applied to the second and third embodiments. It is. That is, after forming the notch 11 deeply, it may be removed by the method of the second or third embodiment.

  As a result, as shown in FIG. 8, a terminal structure is obtained in which the end of the guard ring 6 is thick (deep) and the bottom end of the recess 7 is a smooth curved surface. Thereby, the electric field generated at the bottom end of the recess 7 is reduced as compared with the second and third embodiments, and the withstand voltage characteristic of the semiconductor device can be further improved.

<Embodiment 6>
In each of the above embodiments, the Schottky barrier diode is exemplified as the semiconductor element, but the present invention can also be applied to a termination structure such as a MOSFET. Further, although the guard ring is illustrated as the termination structure, it can be widely applied to a termination structure including an impurity region formed at the bottom of the recess, for example, a JTE structure, an FLR structure, or a combined structure of JTE and a guard ring.

  In each embodiment, it has been described that the guard ring 6 is formed before the processing (reducing or removing the curvature) of the notch 11. However, in the first to third embodiments, after the processing of the notch 11 is performed. A guard ring 6 may be formed.

  1 SiC substrate, 2 SiC drift layer, 3 anode electrode, 4 pad electrode, 5 cathode electrode, 6 guard ring, 7 recess, 8 protective film, 9 photoresist, 10 recess end, 11 notch, 12 oxide layer, 13 photo Resist.

Claims (6)

Forming a recess in the terminal region of the silicon carbide semiconductor element by reactive ion etching in the silicon carbide semiconductor layer;
Forming an impurity region by performing ion implantation in a region including the recess of the semiconductor layer;
By thermally oxidizing the surface of the semiconductor layer including the impurity region formed by the ion implantation inside the recess, an oxide layer having a thickness of 0.05 μm or more and 10 μm or less is formed on the surface of the semiconductor layer. And a process of
And a step of removing the oxide layer. A method for manufacturing a silicon carbide semiconductor device, comprising: The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of removing the oxide layer is performed by performing wet etching on a surface of the semiconductor layer on which the oxide layer is formed. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of removing the oxide layer is performed by dry etching a surface of the semiconductor layer on which the oxide layer is formed. Forming a recess in the terminal region of the silicon carbide semiconductor element by reactive ion etching in the silicon carbide semiconductor layer;
Forming an impurity region by performing ion implantation in a region including the recess of the semiconductor layer;
Applying and curing a photoresist on the surface of the semiconductor layer including the inside of the recess so as to be thick at a notch portion formed in the step of forming the recess; and
The surface of the semiconductor layer where the photoresist has been formed, while removing the photoresist, the method for manufacturing the silicon carbide semiconductor device, characterized in that it comprises a you reactive ion etching process. The step of forming the recess includes
Forming a resist pattern having an opening in the recess formation region on the semiconductor layer;
Forming the recess by reactive ion etching using the resist pattern as a mask,
The angle formed between the sidewall of the resist pattern and the surface of the semiconductor layer is 80 degrees to 90 degrees,
5. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein a DC bias voltage of the reactive ion etching is 300 V or more. 6. The notch having a depth of 0.02 μm or more and a curvature radius of the tip of less than 0.03 μ is formed at the bottom end of the recess in the step of forming the recess. A method for manufacturing a silicon carbide semiconductor device according to one item.

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