JP5680696B2 - シンボルの再グループ化による復号化処理のためのシステム及び方法 - Google Patents
シンボルの再グループ化による復号化処理のためのシステム及び方法 Download PDFInfo
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- JP5680696B2 JP5680696B2 JP2013086719A JP2013086719A JP5680696B2 JP 5680696 B2 JP5680696 B2 JP 5680696B2 JP 2013086719 A JP2013086719 A JP 2013086719A JP 2013086719 A JP2013086719 A JP 2013086719A JP 5680696 B2 JP5680696 B2 JP 5680696B2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1128—Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/1171—Parity-check or generator matrices with non-binary elements, e.g. for non-binary LDPC codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6331—Error control coding in combination with equalisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6343—Error control coding in combination with techniques for partial response channels, e.g. recording
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- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Error Detection And Correction (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/474,668 US8736998B2 (en) | 2012-05-17 | 2012-05-17 | Systems and methods for symbol re-grouping decoding processing |
| US13/474,668 | 2012-05-17 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013243653A JP2013243653A (ja) | 2013-12-05 |
| JP2013243653A5 JP2013243653A5 (enExample) | 2014-07-31 |
| JP5680696B2 true JP5680696B2 (ja) | 2015-03-04 |
Family
ID=48128150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013086719A Expired - Fee Related JP5680696B2 (ja) | 2012-05-17 | 2013-04-17 | シンボルの再グループ化による復号化処理のためのシステム及び方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8736998B2 (enExample) |
| EP (1) | EP2665190B1 (enExample) |
| JP (1) | JP5680696B2 (enExample) |
| KR (1) | KR101547858B1 (enExample) |
| CN (1) | CN103427849B (enExample) |
| TW (1) | TW201412028A (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170288697A1 (en) * | 2016-03-31 | 2017-10-05 | Silicon Motion Inc. | Ldpc shuffle decoder with initialization circuit comprising ordered set memory |
| US10756846B2 (en) * | 2017-03-16 | 2020-08-25 | Qualcomm Incorporated | Distributed feedback architecture for polar decoding |
| JP7234098B2 (ja) * | 2019-11-12 | 2023-03-07 | 株式会社東芝 | 磁気ディスク装置及びリオーダリング処理の方法 |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3328093B2 (ja) | 1994-07-12 | 2002-09-24 | 三菱電機株式会社 | エラー訂正装置 |
| US5701314A (en) | 1995-12-21 | 1997-12-23 | Cirrus Logic, Inc. | On-the-fly error correction using thermal asperity erasure pointers from a sampled amplitude read channel in a magnetic disk drive |
| GB2350531B (en) | 1999-05-26 | 2001-07-11 | 3Com Corp | High speed parallel bit error rate tester |
| WO2001039188A2 (en) | 1999-11-22 | 2001-05-31 | Seagate Technology Llc | Method and apparatus for data error recovery using defect threshold detector and viterbi gain |
| US7136244B1 (en) | 2002-02-22 | 2006-11-14 | Western Digital Technologies, Inc. | Disk drive employing data averaging techniques during retry operations to facilitate data recovery |
| KR100698613B1 (ko) * | 2004-05-13 | 2007-03-22 | 삼성전자주식회사 | 수신 성능이 향상된 디지털 방송 송수신기 및 그의신호처리방법 |
| JP2006115145A (ja) * | 2004-10-14 | 2006-04-27 | Nec Electronics Corp | 復号装置及び復号方法 |
| US7730384B2 (en) | 2005-02-28 | 2010-06-01 | Agere Systems Inc. | Method and apparatus for evaluating performance of a read channel |
| JP2007087529A (ja) * | 2005-09-22 | 2007-04-05 | Rohm Co Ltd | 信号復号装置、信号復号方法、および記憶システム |
| US7925965B2 (en) * | 2006-02-02 | 2011-04-12 | Samsung Electronics Co., Ltd | Method for transmitting/receiving signals in a communications system and an apparatus therefor |
| US7738201B2 (en) | 2006-08-18 | 2010-06-15 | Seagate Technology Llc | Read error recovery using soft information |
| US7702989B2 (en) | 2006-09-27 | 2010-04-20 | Agere Systems Inc. | Systems and methods for generating erasure flags |
| US7971125B2 (en) | 2007-01-08 | 2011-06-28 | Agere Systems Inc. | Systems and methods for prioritizing error correction data |
| WO2008087042A1 (en) | 2007-01-19 | 2008-07-24 | Friedrich-Alexander-Universität Erlangen-Nürnberg | Multiple-bases belief-propagation and permutation decoding for block codes |
| KR101418467B1 (ko) * | 2008-08-15 | 2014-07-10 | 엘에스아이 코포레이션 | 니어 코드워드들의 ram 리스트-디코딩 |
| JP2012509549A (ja) | 2008-11-20 | 2012-04-19 | エルエスアイ コーポレーション | 雑音低減型データ検出のシステムおよび方法 |
| US8347155B2 (en) | 2009-04-17 | 2013-01-01 | Lsi Corporation | Systems and methods for predicting failure of a storage medium |
| US7990642B2 (en) | 2009-04-17 | 2011-08-02 | Lsi Corporation | Systems and methods for storage channel testing |
| US8176404B2 (en) | 2009-09-09 | 2012-05-08 | Lsi Corporation | Systems and methods for stepped data retry in a storage system |
| US8688873B2 (en) | 2009-12-31 | 2014-04-01 | Lsi Corporation | Systems and methods for monitoring out of order data decoding |
| US8732564B2 (en) | 2010-01-27 | 2014-05-20 | Telefonaktiebolaget L M Ericsson (Publ) | Error floor reduction in iteratively decoded FEC codes |
| US8527831B2 (en) * | 2010-04-26 | 2013-09-03 | Lsi Corporation | Systems and methods for low density parity check data decoding |
| US8810940B2 (en) | 2011-02-07 | 2014-08-19 | Lsi Corporation | Systems and methods for off track error recovery |
| US8693120B2 (en) | 2011-03-17 | 2014-04-08 | Lsi Corporation | Systems and methods for sample averaging in data processing |
-
2012
- 2012-05-17 US US13/474,668 patent/US8736998B2/en active Active
-
2013
- 2013-04-16 EP EP13163872.8A patent/EP2665190B1/en not_active Not-in-force
- 2013-04-16 CN CN201310130059.8A patent/CN103427849B/zh active Active
- 2013-04-17 JP JP2013086719A patent/JP5680696B2/ja not_active Expired - Fee Related
- 2013-04-17 KR KR1020130042546A patent/KR101547858B1/ko not_active Expired - Fee Related
- 2013-04-17 TW TW102113630A patent/TW201412028A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| CN103427849B (zh) | 2018-01-09 |
| TW201412028A (zh) | 2014-03-16 |
| US8736998B2 (en) | 2014-05-27 |
| US20130308221A1 (en) | 2013-11-21 |
| CN103427849A (zh) | 2013-12-04 |
| EP2665190A1 (en) | 2013-11-20 |
| EP2665190B1 (en) | 2016-07-06 |
| JP2013243653A (ja) | 2013-12-05 |
| KR20130129094A (ko) | 2013-11-27 |
| KR101547858B1 (ko) | 2015-08-27 |
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