JP5670119B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a circuit board and a manufacturing method thereof, a semiconductor device to which the circuit board is applied, a manufacturing method and a system thereof. Furthermore, the present invention relates to a wafer level package structure and a manufacturing method thereof.

  In recent years, there has been a great demand for miniaturization of circuit systems using semiconductor chips such as computers and mobile communication devices. In order to satisfy such requirements, a semiconductor chip may be mounted in a chip size package (CSP) close to the chip size.

  As one method for realizing CSP, a packaging method called a wafer level package (WLP) is known (see Patent Documents 1 and 2). WLP is a method of forming an external terminal electrode or the like on a silicon wafer before being diced by dicing, and singulation by dicing is performed after WLP. If WLP is used, it is expected that productivity can be improved because external terminal electrodes and the like can be simultaneously formed on a large number of semiconductor chips.

JP 2004-319792 A JP 2007-157879 A

  However, WLP is a process after the pre-process for manufacturing a substrate having an internal terminal electrode. Unlike a general packaging method using a bonding wire, WLP is generally used in a post-process for finishing a final product including a substrate. Since a photolithography process (resist application, exposure, development, resist stripping) is included, there is a problem that the manufacturing cost is high. For example, in FIG. 9 of Patent Document 1, a method of forming an external terminal electrode (31) after patterning a wiring layer (12) by photolithography and further patterning an insulating layer (21) by photolithography. Is described. 3 to 4 of Patent Document 2, the wiring layer (13) is patterned by the photolithography method, and further, the insulating layer (15) is patterned by the photolithography method, and then the external terminal electrode (16) is formed. A method of forming is described.

  Such a problem is not limited to the WLP of the semiconductor chip, but also occurs in other cases where external terminal electrodes are formed on various circuit boards on which fine internal circuits are formed.

  Therefore, there is a demand for a cheaper method for forming external terminal electrodes and the like on a circuit board on which fine internal circuits are formed, particularly a silicon wafer, at the wafer level.

  Furthermore, the present inventors have also noticed the following. For example, when considering a system-in-package (SIP) semiconductor device in which a circuit board and other functional chips are mixedly mounted, the package size of the semiconductor device is a package (CSP) close to the size of the semiconductor chip included in the package. It is desirable to implement. For example, a first chip included in a circuit board and a second chip that communicates with the first chip have different chip sizes, and mounting technology at a chip level is required to make the chips have a stacked structure. is there. Preferably, there is a need to package a plurality of chips together at the wafer level for further miniaturization and cost reduction.

  In addition, for example, when a plurality of second chips corresponding to each other are stacked on a wafer constituted by a plurality of first chips and connected by bonding wires, for example, rewiring to be connected to the bonding wires on the wafer (Rewiring layer) needs to be created, but Cu wiring generated by additive (damascene) plating after sputtering of the commonly used base metal, such as wettability to connect with bonding wire Because of the problem, it is not a suitable metal, and it is required to further apply Au plating on the Cu wiring layer which is a rewiring. Therefore, the rewiring layer has a multilayer structure and a high manufacturing cost.

  As a result of intensive studies on an inexpensive method for forming an external terminal electrode on a circuit board, the present inventors have found that at least one of the above problems can be solved. First, if a method of ion plating a metal material on a circuit board through a metal mask and then peeling (lifting off) the metal mask is used, it is possible to connect to an external terminal electrode without using a photolithography process. It was found that a wiring layer can be formed. The ion plating method itself is a well-known metal film forming method, but by combining the ion plating method and the lift-off method, a method of directly forming a wiring layer without using a photolithography method (ion printing) There is no proposed example at least in WLP of semiconductor chips. The reason for this is that, as a method for forming a thin wiring layer in WLP, a photolithography method and a method using physical deposition by non-ion species such as vapor deposition and sputtering have been established. This is probably because a method using a photolithography method and a plating method has been established as a method for forming a thick wiring layer. However, according to the studies by the present inventors, the above-described method, that is, forming a wiring layer on a circuit board by ion printing is not only lower in manufacturing cost than the current process using a photolithography method. It was also found that the characteristics of the formed wiring layer are good. Next, it has been found that the manufacturing cost is further reduced by applying the bonding wire technique to the wiring layer having the characteristics and connecting the plurality of chips.

  The present invention has been made on the basis of such technical knowledge, and a circuit board according to the present invention and a method of manufacturing a semiconductor device including the circuit board are provided on a first substrate having an internal terminal electrode. A circuit board for forming a wiring for electrically connecting a terminal electrode and the outside of the first substrate, and a manufacturing method of a semiconductor device including the circuit board, wherein the manufacturing process of the circuit board includes the internal terminal A mask step of covering the substrate with a metallic metal mask having an opening that exposes a part of the surface of the first substrate including the electrode and connected to the cathode side; and By applying a predetermined potential and applying a deposition energy of 0.01 eV to 250 eV to a deposition metal ionized to a potential different from the predetermined potential, a part of the surface of the substrate and the metal mask are provided. Io A film forming step of forming a metallic conductor from particles of positively charged ions by a plating method; and the internal terminal electrode formed on a part of the surface of the substrate by peeling the metal mask A lift-off process for leaving a wiring layer of the wiring made of a metallic conductor to be electrically connected, and the manufacturing process of the semiconductor device includes a second substrate having an internal terminal electrode, A first laminating step of laminating on a surface on the wiring side; and a first connecting step of connecting the internal terminal electrode of the second substrate and the wiring on the circuit board. .

  In the semiconductor device according to one aspect of the present invention, the first electronic circuit is drawn on the main surface, and the first electronic circuit communicates with the outside of the first electronic circuit, respectively. A first substrate having an internal terminal electrode and a second electronic circuit are drawn on the main surface, and the second electronic circuit communicates with the outside of the second electronic circuit, respectively. A wiring layer having a terminal electrode, formed on a part of the surface of the first substrate, a second substrate stacked on the first substrate, and each having a first node and a second node; A first wiring layer connecting a wiring layer including a first wiring and a second wiring, the third and fourth internal terminal electrodes, and a first node of the corresponding first and second wirings, respectively. 1 and a second bonding wire, the first and second bonding wires being The cross-section is circular, and the wiring layer includes an edge portion viewed from a direction perpendicular to the surface of the first substrate, and the first wiring layer at the edge portion in contact with the first substrate is the first wiring layer. The angle of the cross section perpendicular to the surface of the substrate is 55 ° or less.

  In a preferred embodiment of the present invention, a metal is patterned on the extraction electrode part (internal terminal electrode) 2 of a preprocess completed wafer (substrate) 1 on which a plurality of semiconductor circuits are formed and a surface connected thereto through a metal mask. A wafer level package characterized by a structure in which different chips are stacked on the wafer, the lead-out electrode portions of the different chips and the rewiring pattern are connected by bonding wires, and a basic circuit chip is formed by dicing. In this semiconductor device, the metal film formed by ion plating is formed in a columnar crystal or a polycrystal.

  Metal pattern deposition uses a high-frequency high electric field plasma (ion energy to be deposited 0.1 to 1000 eV) or thermal electrons to ionize the ion plating, and the main part of the deposition energy of the ionized deposition metal. It is preferable to substantially suppress the distribution to 25 ± 10 eV and the range of 0.01 eV to 250 eV (5% or less rounded down). The metal is preferably a material mainly composed of aluminum.

  According to one effect of the present invention, since the wiring layer is directly formed on the substrate by a combination of the ion plating method using a metal mask and the lift-off method (ion printing), it is necessary to use a photolithography process. Disappear. Furthermore, the connection between the wiring layer (rewiring) and the internal terminal electrode of the chip laminated on the circuit board or the wiring on the insulating board on which the circuit board is mounted is carried out by bonding wires, so that manufacturing in WLP in particular. Costs can be greatly reduced.

  In addition, since the edge portion of the wiring layer formed by ion printing has an angle of 55 ° or less, the stress at the edge portion is relaxed, and the adhesion between the wiring layer and the protective insulating film is also improved. Reliability is improved. Furthermore, since the wiring layer is composed of aggregates of columnar crystals, deposition strain is reduced, and adhesion between the substrate and the wiring layer is improved.

  This makes it possible to supply a highly reliable circuit board at a low cost.

It is typical sectional drawing which shows the structure of the circuit board (silicon wafer) by preferable embodiment of this invention. 1 is an enlarged cross-sectional view showing a main part of a silicon wafer 10. FIG. (A) is a plan view showing an example of the planar shape of the wiring layer 21, and (b) is a plan view showing an example of the planar shape of the wiring layer 22. It is an expanded sectional view along the straight line B shown in FIG.3 (b). It is a schematic diagram for demonstrating the width | variety of the edge part 22a. It is an expanded sectional view along the straight line C shown to Fig.3 (a). 5 is a process diagram for explaining a method for manufacturing the silicon wafer 10. FIG. 5 is a process diagram for explaining a method for manufacturing the silicon wafer 10. FIG. It is a schematic diagram for demonstrating the principle which the side surface 21s becomes diagonal with respect to a board | substrate. It is a related figure for demonstrating the shape of the wiring layer 21 formed using the additive method. It is a related figure for demonstrating the shape of the wiring layer 21 formed using the subtractive method. It is a related figure for demonstrating the shape of the wiring layer 22 formed using the additive method. It is a related figure for demonstrating the shape of the wiring layer 22 formed using the subtractive method. It is a figure which shows the cross section of Cu formed by the ion plating method. It is a figure for demonstrating the mechanism in which the aggregate | assembly of the columnar lump 30 grows. It is a graph which shows the result of the X-ray-diffraction measurement of Cu film | membrane formed by the ion plating method. It is a figure which shows the modification of this invention. It is another figure which shows the modification of this invention. It is the figure seen from the upper surface which shows the example of the semiconductor device concerning this invention. It is a figure which shows the example of a connection of the controller which controls CPU, NAND flash memory, and NAND flash memory which are contained in the semiconductor device and electronic system concerning this invention. It is a figure which shows the 1st cross-section concerning the 1st chip | tip and 2nd chip | tip contained in the semiconductor device and electronic system concerning this invention. It is a figure which shows the 2nd cross-sectional structure which concerns on the 1st chip | tip and 2nd chip | tip contained in the semiconductor device and electronic system concerning this invention. It is a figure which shows the 3rd cross-section which concerns on the 1st chip | tip and 2nd chip | tip contained in the semiconductor device and electronic system concerning this invention. It is the figure seen from the upper surface which shows the rewiring on the 1st chip | tip concerning this invention. It is the figure seen from the upper surface which shows the rewiring on the 1st wafer comprised with the some 1st chip | tip concerning this invention. It is the figure seen from the upper surface which shows the rewiring on the 3rd chip | tip concerning this invention. It is the figure seen from the upper surface which shows the rewiring on the 4th chip | tip concerning this invention. It is the figure seen from the upper surface which shows the structure which laminated | stacked the 5th chip | tip on the rewiring on the 2nd wafer comprised with the some 3rd chip | tip concerning the 1st manufacturing method of this invention. It is the figure seen from the upper surface which shows the structure which laid the bonding wire between the 3rd and 5th chip | tip concerning FIG. It is the figure seen from the upper surface which shows the protective insulating film of the area | region of the bonding wire concerning FIG. It is the figure seen from the upper surface which shows the 1st thru | or 5th chip | tip laminated | stacked concerning FIG. FIG. 3 is a view from above showing bonding wires between first to fifth chips stacked on an insulating substrate 50 and wirings 51 on the insulating substrate. FIG. 6 is a view from above showing a protective film in regions of first to seventh chips arranged on an insulating substrate 50. It is the figure seen from the upper surface which shows the structure which laminated | stacked several 1st thru | or 5th chip | tip concerning the 2nd manufacturing method of this invention. It is the figure seen from the upper surface which shows the semiconductor device concerning the 2nd manufacturing method of this invention. It is the figure seen from the upper surface which shows the 1st thru | or 5th chip | tip laminated | stacked concerning the 3rd manufacturing method of this invention. It is sectional drawing which shows the example of the semiconductor device concerning this invention, and an electronic system. It is sectional drawing which shows the manufacture flow of the semiconductor device concerning this invention, and an electronic system. FIG. 35 is a cross-sectional view showing a manufacturing flow of the semiconductor device and the electronic system according to FIG. 34. FIG. 37 is a cross-sectional view showing a manufacturing flow of the semiconductor device and the electronic system according to FIG. 36. It is a schematic diagram which shows the example which performs a part electrical connection between chips | tips by flip chip connection. It is a schematic diagram for demonstrating the connection between the several chip | tips which are not laminated | stacked. It is a graph which shows energy distribution of the metal ion to be deposited at the time of ion plating of this embodiment. It is the graph which displayed FIG. 43 logarithmically. It is a graph which compares the distribution of the deposition energy of a general ion plating and the ion plating in this embodiment. It is the graph which displayed FIG. 45 logarithmically. It is an experimental result which shows the relationship between the deposition energy of the deposition metal (Cu) at the time of ion plating, and the structure of the formed Cu crystal. 7 is an experimental result illustrating the cross-sectional shape of the wiring layer described with reference to FIGS. 5 and 6.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 to 18 describe the structure and manufacturing method of the circuit board, and FIGS. 19 to 42 explain the structure and manufacturing method of the semiconductor device and electronic system related to the circuit board. It is a thing.

  FIG. 1 is a schematic cross-sectional view (third direction (Z)) showing the structure of a circuit board (including a silicon wafer) according to a preferred embodiment of the present invention.

  As shown in FIG. 1, the silicon wafer 10 according to the present embodiment is electrically connected to a substrate 1 as a wafer body, a chip extraction electrode (internal terminal electrode) 2 formed on the surface of the substrate 1, and a chip extraction electrode 2. And solder balls (external terminal electrodes) 9 connected to each other. The substrate 1 is a collective substrate composed of a plurality of semiconductor chips that are then separated. The circuits formed on these semiconductor chips are the same.

  The surface of the substrate 1 is almost entirely covered with an insulating passivation film 3 (second insulating film) other than the region where the chip extraction electrode 2 is provided. Although not particularly limited, the chip extraction electrode 2 is generally made of Al, and the passivation film 3 is generally made of polyimide having a thickness of about 5 μm. The chip extraction electrode 2 may be plated (for example, Ni + Au) in advance on the surface in contact with the wiring layer described later. In this specification, the term “substrate 1” may include the chip extraction electrode 2 and the passivation film 3. Therefore, the “surface of the substrate 1” may also refer to the surface of the chip extraction electrode 2 and the surface of the passivation film 3.

  The portion composed of the substrate 1, the chip extraction electrode 2, and the passivation film 3 is a portion manufactured in a so-called pre-process (diffusion process). In the pre-process, extremely fine internal wiring and the like are formed on the substrate by an extremely high-precision photolithography method using a stepper or the like. A portion serving as a terminal of these internal wirings is a chip extraction electrode 2. The silicon wafer 10 according to this embodiment forms the wiring layers 21 and 22 and the solder balls 9 shown in FIG. 1 by processing the surface thereof at the wafer level. A broken line A shown in FIG. 1 is a scribe line. After the processing (WLP process) at the wafer level for the silicon wafer 10 is completed, the silicon wafer 10 is diced along the scribe line, so that individual semiconductor chips are separated. It is separated.

  FIG. 2 is an enlarged cross-sectional view showing the main part of the silicon wafer 10. In FIG. 2, the surface on which the solder balls 9 are formed is shown on the lower side.

  As shown in FIG. 2, a chip extraction electrode 2 and a passivation film 3 are provided on the surface of the substrate 1. As described above, the passivation film 3 covers almost the entire surface of the substrate 1 other than the region where the chip extraction electrode 2 is provided. The extraction electrode 2 is connected to a first wiring layer 21 in which a barrier metal wiring 4 and a copper wiring 5 are laminated. Although not particularly limited, the thickness of the barrier metal wiring 4 may be about 0.3 μm, and the thickness of the copper wiring 5 may be about 5 μm.

  The first wiring layer 21 extends along the surface of the substrate 1 and connects the end 21a and the end 21b with the first end 21a, the second end 21b, which covers the chip extraction electrode 2. And a rewiring portion 21c. An example of the planar shape of the wiring layer 21 (which is indicated by the first direction (X) and the second direction (Y)) is shown in FIG. 3A and is not particularly limited. The width of the rewiring portion 21c is designed to be narrower than the diameters of the end portions 21a and 21b. Further, the end 21 a is designed to be slightly larger than the diameter of the chip extraction electrode 2 so as to cover the entire surface of the chip extraction electrode 2. All of the upper surface of the wiring layer 21 except the portion covered with the wiring layer 22 is covered with the protective insulating film 8. In the present specification, a portion of the upper surface of the wiring layers 21 and 22 that is not covered with the protective insulating film 8 is referred to as a “first portion”, and a portion covered with the protective insulating film 8 is referred to as a “second portion”. Sometimes called “part”. Therefore, the wiring layer 21 does not have the first portion.

  Further, as shown in FIG. 2, the end portion 21 b of the wiring layer 21 is connected to the second wiring layer 22 in which the barrier metal wiring 6 and the copper wiring 7 are laminated. Although not particularly limited, the thickness of the barrier metal wiring 6 may be about 0.3 μm, and the thickness of the copper wiring 7 may be about 10 μm. The second wiring layer 22 is a wiring layer that functions as a post electrode serving as a base of the solder ball 9, and is provided perpendicular to the surface of the substrate 1. In other words, it does not have a portion extending along the surface of the substrate 1 like the rewiring portion 21c. An example of the planar shape of the wiring layer 22 is shown in FIG. 3B, and has a diameter slightly smaller than the end portion 21 b of the wiring layer 21. On the other hand, as shown in FIG. 3B, the wiring layer 22 is designed to be slightly larger than the bottom surface 9 a of the solder ball 9 so as to cover the entire bottom surface 9 a of the solder ball 9. These can be understood in detail in the description using FIG. 5 described later. Although not particularly limited, if the diameter of the solder ball 9 is about 500 μm, the diameter of the wiring layer 22 may be about 400 μm.

  As the barrier metal wirings 4 and 6, a single layer film made of Ti, Cr, Ta, or Pd, or a laminated film of Ti and Ni can be used. Although it is not essential to provide the barrier metal wirings 4 and 6 in the present invention, in general, when the copper wiring 5 is directly formed on the surface of the passivation film 3, the adhesiveness between the two is insufficient, and the copper wiring 5 once exposed to the atmosphere. If the copper wiring 7 is directly formed on the surface, the adhesion between the two is insufficient, and it is preferable to provide these. However, since the copper wirings 5 and 7 are formed by the ion plating method in the present invention, it is possible to adjust the adhesion and the deposition stress by controlling the deposition energy. Therefore, in the present invention, it is less necessary to provide the barrier metal wirings 4 and 6 than the conventional WLP.

  As shown in FIG. 2, the entire surface of the surface of the substrate 1 excluding the region where the solder balls 9 are formed is covered with a protective insulating film 8. The material of the protective insulating film 8 is not particularly limited, but it is preferable to use a material obtained by solidifying a liquid organic insulating material with a cure or the like.

  With this structure, all of the surface of the wiring layer 21 other than the portion covered with the wiring layer 22 is covered with the protective insulating film 8. Similarly, all of the surface of the wiring layer 22 other than the portion (first portion) covered by the bottom surface 9a of the solder ball 9 is covered by the protective insulating film 8 (second portion). As shown in FIG. 3B, the portion of the surface of the wiring layer 22 that is covered with the bottom surface 9 a of the solder ball 9 is the central portion of the wiring layer 22. The edge 22 a is covered with the protective insulating film 8. This state is also shown in FIG. 4 which is an enlarged cross-sectional view along the straight line B shown in FIG. 3B, and the surface of the edge 22 a of the wiring layer 22 is covered with the protective insulating film 8. I understand.

  With this structure, since the edge 22a including the edge of the wiring layer 22 is protected by the protective insulating film 8, it is possible to prevent the occurrence of peeling. An edge refers to an end portion viewed from a direction perpendicular to the surface of the substrate 1. Further, since the edge 22a of the wiring layer 22 is covered with the protective insulating film 8, the wiring layer 22 is not dropped off. As a result, the reliability of the package can be improved.

  Here, the width L of the edge 22a of the wiring layer 22 (see FIG. 3B), that is, the width covered with the protective insulating film 8 is not particularly limited, but is set to 1 μm or more. Is preferred. This is because if the width L of the edge portion 22a is less than 1 μm, the above effects may not be sufficiently obtained. The upper limit of the width L of the edge 22a is not particularly limited, but is preferably 30 μm or less. This is because, even if the width L of the edge 22a exceeds 30 μm, the above effect is not further improved, but the contact area with the solder ball 9 becomes smaller than necessary. In order to sufficiently obtain the above effect while ensuring a sufficient contact area with the solder ball 9, it is preferable to set the width L of the edge 22a to about 15 μm. As shown in FIG. 5, the width L of the edge portion 22a refers to the protective insulation from the intersection P between the average tangent line D1 of the side surface 22s of the wiring layer 22 and the virtual line D2 along the upper surface 22u of the wiring layer 22. Defined by the distance to the end 8a of the membrane 8. Further, as shown in FIG. 5, the height of the protective insulating film 8 from the substrate 1 is higher than the height of the upper surface 22 u of the wiring layer 22 from the substrate 1. As shown in FIG. 5, the side surface 22s of the wiring layer 22 is not vertical but is slanted. The same applies to the wiring layer 21, and the cross-sectional structure of the wiring layer 21 will be described below as an example.

  FIG. 6 is an enlarged cross-sectional view along the straight line C shown in FIG.

  As shown in FIG. 6, the cross-sectional shape of the wiring layer 21 is such that the upper surface 21 u is substantially parallel to the surface of the substrate 1, while the side surface 21 s has an oblique angle with respect to the surface of the substrate 1. Yes. That is, the edge portion 21e of the wiring layer 21 has an acute angle. The angle θ is 55 ° or less, preferably 20 ° or more and 40 ° or less, and particularly preferably 25 ° or more and 35 ° or less. In this embodiment, since the edge part 21e of the wiring layer 21 has such an angle, the stress in the edge part 21e is relieved. In addition, since the contact area between the wiring layer 21 and the protective insulating film 8 is increased, the adhesion between them is also improved. Furthermore, since the edge portion 21e is covered with the protective insulating film 8 from above, the adhesion between the wiring layer 21 and the passivation film 3 is also improved. As a result, the reliability of the package can be improved. As shown in FIG. 5, since the edge portion 21e having the angle θ is covered with the protective insulating film 8, the first portion (the portion not covered with the protective insulating film 8) is a wiring. This is an inclusion region excluding a portion constituting an edge portion having an angle θ from the pattern shape of the surface of the layers 21 and 22. As shown in FIG. 5, the side surface 21 s of the wiring layer 21 may not be a straight section, but may be a curve whose angle gradually changes. The angle θ in such a case is defined by the angles at the edge portions 21e and 22e shown in FIG. The edge portion 21 e is a starting point where the wiring layer 21 is in contact with the passivation film 3, and the edge portion 22 e is a starting point where the wiring layer 22 is in contact with the wiring layer 21.

  Next, the method for manufacturing the silicon wafer 10 according to the present embodiment will be described.

  7 to 8 are process diagrams for explaining the method for manufacturing the silicon wafer 10 according to the present embodiment.

  First, the substrate 1 in which the previous process (diffusion process) is completed is prepared, and the surface thereof is covered with a metal mask 100 as shown in FIG. 7A (mask process). The metal mask 100 (first metal mask) is provided with a plurality of openings 101 corresponding to the planar shape of the wiring layer 21, and a region in the surface of the substrate 1 where the wiring layer 21 is to be formed is an opening. A metal mask 100 is placed so as to be exposed through 101. The region where the wiring layer 21 is to be formed is a region including the chip extraction electrode 2 as shown in FIG. The metal mask 100 is aligned using a fixture and then brought into close contact with the substrate 1 and connected to the cathode side of the ion plating apparatus. The metal mask 100 is fixed so that some tension is applied to the periphery at the fixing portion of the fixture so that warpage due to temperature and distortion due to the deposited metal does not occur.

  The material of the metal mask 100 is not particularly limited, but is metallic, and it is preferable to use stainless steel or the like. The metal mask 100 is a rigid mask that is different from a photoresist patterned by a photolithography method. The metal mask 100 can cover the substrate 1 as it is and is in a state as it is. Can be peeled off from the substrate 1. In this respect, it is clearly distinguished from an organic mask such as a photoresist.

  Next, as shown in FIG. 7B, with the metal mask 100 covered, the barrier metal material 4a and Cu 5a are deposited in this order by the ion plating method (film formation step). The ion plating method evaporates or sublimates a metal material to be deposited in vacuum, and applies a positive charge to the metal vapor and a negative charge to the deposition substrate, thereby depositing the metal material on the deposition substrate. It is a method to do. Therefore, the process shown in FIG. 7B is performed by storing the substrate 1 in a vacuum chamber and applying a positive charge to the gaseous barrier metal material and Cu and a negative charge to the substrate 1.

  As a result, the barrier metal material 4 a and Cu 5 a are deposited on the surface of the substrate exposed through the opening 101 of the metal mask 100 and the upper surface of the metal mask 100. At this time, the barrier metal material 4a and Cu 5a formed in the portion exposed through the opening 101 have the upper surface 21u substantially parallel to the surface of the substrate 1 as shown in FIG. The side surface 21 s is inclined with respect to the surface of the substrate 1. This is a characteristic when ion plating is performed through a metal mask having a certain thickness. Of the region exposed through the opening 101, a portion near the side surface 100s of the metal mask 100 is per unit time. This is because the amount of deposition decreases.

  The reason for this is that the component of the metal vapor that is attracted to the substrate 1 that is slightly inclined in the traveling direction adheres to the substrate 1 without being obstructed by the metal mask 100 in the center of the opening 101 (see arrow 31). This is because the end of the opening 101 is blocked by the metal mask 100 and does not reach the substrate 1 (see arrow 32). Further, as shown in FIG. 9, since the metal material is deposited on the side surface 100s of the metal mask 100 in an overhang shape, this serves as a mask and the deposition amount at the end of the opening 101 is reduced. Due to such a principle, the upper surface 21 u is substantially parallel to the substrate 1, while the side surface 21 s is oblique to the substrate 1. The effects obtained by such a structure are as already described.

  On the other hand, when a plating method (additive method), which is a general method for forming a wiring layer in WLP, is used, as shown in FIG. 10, the wiring is formed in the opening of the photoresist 41 patterned by the photolithography method. Layer 42 is selectively formed. In this case, the inner wall 41s of the opening portion of the photoresist 41 is substantially perpendicular to the surface of the substrate 1 as a result of patterning by the photolithography method, and therefore, the side surface of the wiring layer 42 formed in the opening portion. Is also substantially vertical.

  Although not a general method for forming a wiring layer in WLP, when a subtractive method is used, a photolithography method is applied to the surface of the metal conductor 51 formed on the entire surface of the substrate as shown in FIG. As a result, a patterned photoresist 52 is formed. Then, as shown in FIG. 11B, when the metal conductor 51 is patterned using the photoresist 52 as a mask, the side surface of the formed wiring layer 53 is substantially perpendicular to the surface of the substrate 1.

  Thus, when the photolithography method is used, the side surface of the formed wiring layer is substantially vertical, and thus the above-described effect cannot be obtained.

  Returning to the description of the features of the present application, the barrier metal material 4a and the Cu 5a are thus deposited in this order, and then the metal mask 100 is peeled from the substrate 1 as shown in FIG. 7C (lift-off process). . Thereby, since the barrier metal material 4a and Cu 5a in the opening 101 remain, the first wiring layer 21 including the barrier metal wiring 4 and the copper wiring 5 is patterned by the lift-off method without using the photolithography method. Will be. Thus, in the present invention, the wiring layer 21 can be directly formed by ion plating and a lift-off process without using a photolithography method. In this specification, such a method may be referred to as ion printing.

  After the first wiring layer 21 is formed, the second wiring layer 22 is subsequently formed. The method of forming the second wiring layer 22 is the same as the method of forming the first wiring layer 21, and an opening 201 corresponding to the planar shape of the wiring layer 22 is provided as shown in FIG. A metal mask 200 (second metal mask) is prepared, and the metal mask 200 is put on the surface of the substrate 1 so that a region where the wiring layer 22 is to be formed is exposed through the opening 201 (mask process). The region where the wiring layer 22 is to be formed is a region including the end portion 21b of the first wiring layer 21 as shown in FIG. As for the material of the metal mask 200, the same material as that of the metal mask 100 may be used.

  Next, with the metal mask 200 covered, the barrier metal material 6a and Cu 7a are deposited in this order by the ion plating method (film forming step). As a result, the barrier metal material 6 a and Cu 7 a were deposited on the surface of the substrate 1 exposed through the opening 201 of the metal mask 200 (more precisely, the surface of the copper wiring 5) and the upper surface of the metal mask 200. It becomes a state. Also in this case, the barrier metal material 6a and Cu 7a formed in the portion exposed through the opening 201 have the upper surface 22u substantially parallel to the substrate as shown in FIG. 22s is inclined with respect to the substrate.

  Then, as shown in FIG. 8B, if the metal mask 200 is peeled from the substrate 1 (lift-off process), the second wiring layer composed of the barrier metal wiring 6 and the copper wiring 7 is used without using a photolithography method. 22 is formed.

  Next, as shown in FIG. 8C, the insulating material having fluidity is selectively supplied to the surface of the substrate 1 excluding the portion where the solder balls 9 are to be formed, and solidified by curing (see FIG. 8C). Protective insulating film forming step). It is preferable to use a screen printing method for the selective supply of the insulating material. When the insulating material is selectively supplied, the entire surface of the wiring layer 21 and the side surface 22s of the wiring layer 22 are covered with the protective insulating film 8. In the stage before supplying the insulating material, since the wiring layer 22 protrudes most from the substrate, if the insulating material is selectively supplied so as to avoid the wiring layer 22, the insulating material is dammed by the side surface of the wiring layer 22. Therefore, the entire upper surface of the wiring layer 22 is not covered with the insulating material. However, the upper surface of the wiring layer 22 is not completely covered with the insulating material, and the edge 22a of the wiring layer 22 is covered with the surface tension as shown in FIG. 5 which is an enlarged view. The effects obtained by such a structure are as already described.

  On the other hand, when a plating method (additive method) which is a general method for forming a wiring layer in WLP is used, as shown in FIG. 12, the inside of the opening 61 of the protective insulating film 60 patterned by the photolithography method is used. In addition, a wiring layer 62 to be a post electrode is selectively formed. In this case, since the wiring layer 62 is formed after the protective insulating film 60, the edge 62 a of the wiring layer 62 is not covered with the protective insulating film 60.

  Also, when the subtractive method is used, the metal conductor formed on the entire surface of the protective insulating film 70 is patterned as shown in FIG. Also in this case, since the wiring layer 71 is formed after the protective insulating film 70, the edge 71 a of the wiring layer 71 is not covered with the protective insulating film 70.

  Thus, when the photolithography method is used, the edge portions 62a and 71a of the wiring layers 62 and 71 are not covered with the protective insulating films 60 and 70, and thus the above-described effect cannot be obtained.

  Returning to the description of the features of the present application, after that, if solder is supplied to the exposed portion of the wiring layer 22 and melted, solder balls 9 are formed as shown in FIG. 1 (electrode formation step). Thus, a series of WLP processes are completed. Thereafter, if the substrate 1 is diced along the scribe line, it can be divided into individual semiconductor chips (cutting step). The dicing of the substrate 1 may be performed after the protective insulating film 8 is formed and before the solder balls 9 are formed.

  As described above, according to the method for manufacturing the silicon wafer 10 according to the present embodiment, the photolithography process (a series of processes including resist coating, exposure, development, and resist stripping) is performed by ion printing twice. The wiring layers 21 and 22 are directly formed without passing through. For this reason, compared with the case where the conventional general method is used, the number of processes reduces to 1/3-1/4. In addition, the metal mask 100 can be mass-produced at low cost, and if the deposited metal is removed by etching, the cleaned metal mask and the etched metal material can be used repeatedly. According to the experiments by the present inventors, no deterioration in quality was observed in the formed wiring layers 21 and 22 even after repeated use about 5 times. Accordingly, it is possible to provide the silicon wafer 10 with high productivity and low cost.

  The copper wirings 5 and 7 included in the wiring layers 21 and 22 are relatively thick (in the above example, 5 μm and 10 μm, respectively), which causes stress. However, as described above, the edges of the wiring layers 21 and 22 have an acute angle, and the angle θ is 55 ° or less, so that stress at the edge portion is relieved. In order to further relax the stress, it is preferable to control the film formation conditions with less strain by lowering the temperature of the substrate 1 during ion plating and lowering the deposited atom energy.

  More specifically, it is preferable to set the deposited atom energy during ion plating in the range of 5 to 100 eV. This is because if the deposited atomic energy is too high, interface breakdown occurs. On the other hand, when the deposition atomic energy is set in the above range, secondary migration becomes active, and as a result, the deposited metal becomes an aggregate of columnar crystals extending in the growth direction.

  FIG. 14 is a view showing a cross section of Cu formed by the ion plating method.

  As shown in FIG. 14, when Cu is formed by an ion plating method, Cu becomes an aggregate of columnar lumps 30 extending in the growth direction. The columnar lump 30 is typically a crystal of a metal material (Cu) that constitutes a wiring layer. In this case, a boundary portion between two adjacent lumps 30 is a crystal interface. Further, at least some of these columnar chunks 30 may have different crystal orientations. The growth direction of the columnar mass 30 is a direction different from the surface direction of the substrate 1, and is typically a direction substantially perpendicular to the surface of the substrate. Therefore, the wiring layers 21 and 22 formed by the ion plating method are typically constituted by aggregates of columnar crystals that extend substantially perpendicular to the surface of the substrate 1. For this reason, since the grains are subdivided with respect to the surface direction, it is possible to obtain a strong adhesive force at the interface with little deposition strain.

  FIG. 15 is a diagram for explaining a mechanism by which an aggregate of columnar lumps 30 grows.

  First, the species 32 ionized in a vacuum move toward the substrate 31 by the Coulomb force and adhere to the substrate 31 (FIG. 15A). The species 32a adhering to the substrate 31 move on the surface of the substrate 31 by secondary migration, and the species 32b moved thereby are united (FIG. 15B). By repeating this, species cores 32c are formed on the surface of the substrate 31 (FIG. 15C). FIG. 15D is a view of the species core 32c as seen from the plane direction. As ion plating proceeds, the nucleus 32c grows in the planar direction and the height direction, and becomes an island-shaped lump 32d (FIG. 15E). The island-shaped lump 32d further grows as ion plating progresses, and after the surface of the substrate 31 is completely covered with the island-shaped lump 32d, the growth proceeds in the height direction. (FIG. 15 (f)). Since the aggregate of the columnar chunks 30 is grown by such a mechanism, the height of the columnar chunks 30 is increased in the places where the island-like chunks 32d are formed at an early stage, and the columnar chunks 30 are formed in other places. The height of the lump 30 is slightly lowered. For this reason, the height of the columnar block 30 from the substrate 31 is slightly different from each other. As a result, fine irregularities appear on the surfaces of the wiring layers 21 and 22.

  As the ion plating apparatus to be used, a commercially available ion plating apparatus can be used. By controlling the energy of the deposited metal ions, the film forming conditions are set so as to prevent the occurrence of distortion while ensuring the adhesion. be able to. The ion source is evaporated by an electron beam method, and the evaporated metal atoms are infiltrated into Ar plasma generated in a high frequency coil to be ionized. The ionized metal atoms are attracted to the wafer placed on the negative electrode by Coulomb force and deposited.

The deposition energy is related to the ion mean free path and voltage. When the effective area of ions is σ2, the mean free path λ [m] is determined by the Ar gas temperature T [K] and the gas pressure P [Pa] and can be expressed by the following equation.

If the ion mass is m [g], the accelerated speed v can be expressed by the following equation.

Therefore, the ion acceleration energy U can be expressed by the following equation.

  Naturally, since the mean free path λ has a Boltzmann distribution, it has a spread from 0 to 1000 times or more, but the properties of the deposited layer differ in the mean free path.

  As is clear from the above equation, the ion acceleration energy U has the same dimension as the mean free path λ, and thus has a Boltzmann distribution. FIG. 43 is a graph showing the energy distribution of deposited metal ions during ion plating according to the present embodiment. FIG. 44 is a graph logarithmically representing FIG. Referring to FIG. 44 where the energy distribution is easy to visually recognize, the ion plating of this embodiment gives a deposition energy of 0.01 eV to 250 eV with the main part being 25 ± 10 eV.

  Here, the “main part” means a peak of deposition energy having a Boltzmann distribution. As shown in FIG. 43, in this embodiment, the peak of the deposition energy may be in the range of 25 ± 10 eV, that is, in the range of 15 eV to 35 eV. FIG. 43 illustrates three types of energy distributions f1 (u), f2 (u), and f3 (u) having peaks of 15 eV, 25 eV, and 35 eV, respectively.

  Next, the reason why the range (upper and lower limits) of the deposition energy centered on the peak is determined from 0.01 eV to 250 eV will be described. Originally, there is no upper and lower limit for the deposition energy distributed in Boltzmann. However, in order to differentiate the deposition energy of this embodiment from that of general ion plating, an energy value that is hardly used and whose frequency is 5% (value 0.05) or less shown on the vertical axis of FIG. Rounded down as a guide. Then, an energy range of 0.8 to 250 eV is obtained. However, in the present embodiment, the lower limit value is made smaller, and the deposition energy range is 0.01 to 250 eV. This is because molecules and atoms with low deposition energy are likely to collide with space during the flight, and this is considered to reduce energy.

  FIG. 45 is a graph comparing the distribution of deposition energy of a general ion plating and the ion plating in this embodiment. FIG. 46 is a graph showing the logarithm of FIG. The feature of ion plating in the present embodiment is that the peak of deposition energy (peak 15 eV of energy distribution f1 (u) shown in FIG. 46 as a representative) is the peak of deposition energy of general ion plating (FIG. 46). The energy distribution f0 (u) has a peak which is much smaller than the peak 1 keV), and has a difference of two digits.

  Although there is such a clear difference in the peaks, as described above, because the Boltzmann distributions have no upper and lower limits, the distribution curves of the deposition energy of the ion plating and the general ion plating in this embodiment are as follows: It overlaps at the base part (0.05 = 5% or less) that is hardly used. Therefore, also in general ion plating, the energy value having a frequency of 5% or less is rounded down as a temporary guide as in the present embodiment. As a result, the deposition energy range of 0.01 to 250 eV in this embodiment does not overlap with the deposition energy range of a general ion plating. Therefore, the two can be clearly differentiated.

  As described above, it is preferable to further limit the deposition atomic energy range of the ion plating from the above 0.01 to 250 eV and to 5 to 100 eV.

  The structure in which the angles of the edge portions 21e and 22e of the wiring layers 21 and 22 shown in FIGS. 5 and 6 are 55 ° or less, and the structure in which Cu is an aggregate of columnar chunks 30 shown in FIG. Is a structure peculiar to this embodiment. That is, by using a metal mask having a certain thickness and performing ion plating with a deposition energy of 0.01 eV to 250 eV in which the main portion is 25 ± 10 eV, a wiring layer having such a structure can be obtained.

If the average value of the particle energy of Cu ²⁺ ions is 15.5 eV from the Boltzmann distribution, the distribution will be approximately 200 eV (0.01% or less rounded down). This value is about 5 to 10 times the atomic bond energy, and has the energy to rearrange after deposition, but is not a value that disturbs the deposited state. It is. The measurement result which compared the peak by X-ray diffraction of the Cu film | membrane deposited on these conditions with rolled copper foil is shown in FIG. FIG. 16 is a diagram comparing the Cu film 80 deposited in the above case and the standard Cu plate 81. The maximum peak (2θ = 69 °) and the peak of 2θ = 33 ° are peaks that are attached to the SUS plate and represent SUS. It is necessary to exclude this, but it is standard that the strength is strong overall Since it is the Cu plate 81 and the peak values coincide with the same place, it can be seen that the Cu crystal has no distortion.

  As is clear from the above description, a thick Cu wiring with little distortion can be formed without using a photolithography method.

  FIG. 47 shows the experimental results showing the relationship between the deposition energy of the deposited metal (Cu) during ion plating and the structure of the deposited Cu crystal. This figure is a cross section of the crystal cut by FIB (Focused Ion Beam). The bias voltage and Cu ion energy are changed in four ways. 47 (a), the bias is 10V, the Cu ion energy is 1.825 eV + α (condition 1), the bias is 55V in FIG. 47 (b), the Cu ion energy is 10.038 eV + α (condition 2), and the bias is in FIG. 47 (c). 200 V, Cu ion energy 36.503 eV + α (condition 3), and in FIG. 47D, the bias is 300 V and the Cu ion energy 54.754 eV + α (condition 4). The reason why each deposition energy is set to “+ α” is that the kinetic energy (1 to 5 eV) of ion beam heating to the raw material substrate should be added to these deposition energy values.

  Conditions 1 to 4 are all within the range of deposition energy recommended by the present invention from 0.01 eV to 250 eV. Therefore, most of Cu is a columnar crystal, which seems to be a good result of the secondary migration described in FIG. The difference in the growth of columnar crystals under conditions 1 to 4 will be considered below.

  It can be seen that Condition 2 shown in FIG. 47B, that is, the case where the deposition energy is 10.038 eV + α = 11 to 15 eV, is the most fine and clean columnar crystal over the whole of the four conditions. The deposition energy in condition 2 is the closest value to 25 ± 10 eV particularly recommended by the present invention as the main part in the range of 0.01 eV to 250 eV.

  In the case of condition 1 shown in FIG. 47A, that is, low deposition energy of 1.825 eV + α = 2.8 to 6.8 eV, there is a region that has become a coarse crystal as shown in region A1. This is thought to be because the columnar crystals that are not stably grown due to the lack of secondary migration described with reference to FIG. 15 have been eroded from the columnar crystals that are growing adjacently. Therefore, it does not have a columnar shape but can be expanded laterally, and a coarse crystal as described above is formed. In addition, as seen in the other three regions A2, A3, and A4, such erosion also occurs in the middle of the columnar crystal. When the energy is made lower than that in the condition 1, such coarsening becomes remarkable, and when the energy is made lower, the crystal is considered to approach amorphous.

  In the condition 3 shown in FIG. 47 (c), that is, 36.503 eV + α = 37 to 41 eV in which the deposition energy is increased, a tendency of fine columnar crystals is observed at the beginning of deposition (approximately the layer below the line L1). However, after the middle stage above the line L1, the crystal already generated at the time of species collision is disturbed, and the secondary saddle migration tends to hinder the continuity of the columnar crystals, and the grains gradually grow and grow. I will do it.

  In the case of condition 4 shown in FIG. 47 (d), that is, 54.754 eV + α = 55 to 60 eV in which the deposition energy is further increased, in the layer approximately above line L2, along with the coarse growth similar to condition 3, the columnar crystal The continuity of is lost, and the disturbance is increasing. The reason for this can be judged from the fact that there are many branches due to the disturbance of the existing crystals. Further, within the range not included in the results of this experiment, it is suggested that when the deposition energy is set to a level of 100 eV, not a columnar crystal but a granular crystal may be generated.

  When the comparison of the above conditions 1 to 4 is summarized, the order of condition 2> condition 3> condition 1> condition 4 is given in order from the most ideal columnar crystal growth. In general, good columnar crystals are formed in order from the ones subjected to ion plating at a value close to the deposition energy of 25 ± 10 eV particularly recommended by the present invention.

  Note that it is considered that the difference in crystal growth appears more significantly when experiments are performed using a wider range of deposition energies, such as deposition energy lower than condition 1 and energy higher than condition 4.

  In ultra-fine columnar crystals (approximately 50 nm in diameter) with about 500 to 800 atoms, the number of grain boundaries is extremely large. Therefore, the film-forming strain is reduced due to the high displacement ability of the grain boundaries, and the deposition thickness is reduced. Even if it is thick, a stable film with small residual stress is formed.

  Since the metal deposited by ion plating is deposited with energy several times the normal metal binding energy, the interfacial adhesion strength is large and the strain is small, so columnar crystals are the optimum film forming conditions.

  FIG. 48 shows experimental results illustrating the cross-sectional shape of the wiring layer 21 described with reference to FIGS. 5 and 6. FIG. 48A shows the crystal structure of the formed wiring layer 21. FIG. 48B is a diagram schematically showing the positional relationship between the wiring layer 21 and the metal mask 100 when the wiring layer 21 is formed. FIG. 48C is a diagram exemplifying experimental results when the wiring layer 42 is formed by the plating method shown in FIG. 10, which is a comparison object with FIG. In FIG. 48A, a wiring layer (Cu) is formed by ion plating using a metal mask, and its deposition energy is 18.25 eV (bias 100 v).

  In FIG. 48A, although there is a region A5 where energy is weak and columnar crystals are not well formed due to the influence of the metal mask 100 whose positional relationship is schematically shown in FIG. 48B, the angle of the edge portion is small. A wiring layer 21 that is 55 ° or less is formed.

  On the other hand, when the wiring layer is formed by the plating method shown in FIG. 48C as a comparative example, the shape of the edge portion A6 is substantially 90 ° with respect to the substrate 1, and the stress of the edge portion A6 is The adhesion between the wiring layer 42 and the protective insulating film cannot be improved, and the reliability of the package cannot be improved.

  As mentioned above, although the embodiment regarding the preferable circuit board of this invention was described, this invention is not limited to said embodiment, A various change is possible in the range which does not deviate from the main point of this invention, and they are also It goes without saying that these are included in the scope of the present invention.

  For example, in the present invention, it is not essential to provide the two wiring layers 21 and 22 on the substrate, and the wiring layer 22 is directly formed on the chip extraction electrode 2 as shown in FIG. It doesn't matter. That is, it is possible to omit the wiring layer 21 having the rewiring portion. Such a structure is suitable in the case where the electrode pitch of the chip extraction electrode 2 is sufficiently wide and rewiring is not required. In this case, as shown in FIG. 18, the side surface 22 s of the wiring layer 22 is oblique (55 ° or less), and the edge 22 a along the outer periphery of the upper surface 22 u of the wiring layer 22 is covered with the protective insulating film 8.

  In the above embodiment, the wiring layers 21 and 22 have a two-layer structure of barrier metal wiring and copper wiring, but the present invention is not limited to this. Therefore, the barrier metal wiring may be omitted, or a wiring made of another metal material may be used instead of the copper wiring mainly composed of copper. Examples of the main component of other preferable metal material (main metal) other than Cu include Al, Ti, Cr, and Ni. Preferably, the main component is 50 percent or more. The other component (secondary metal) has a minor component of 10% or less. In particular, Al is a metal material that cannot be formed by a plating method used in general WLP, but can be formed by an ion plating method regardless of the type of metal. Moreover, when Al wiring is used instead of copper wiring, barrier metal wiring is unnecessary. Furthermore, instead of the copper wiring, a wiring including a multi-component alloy made of a plurality of metal materials may be used. Depending on the type of the multi-component alloy, it is difficult to form by a plating method. However, according to the ion plating method, any type of metal can be mixed in an arbitrary ratio. The manufacturing cost can be further reduced by the ion plating method using a multi-component alloy.

  In the above embodiment, a plurality of wiring layers of barrier metal wiring (first metallic conductor) and copper wiring (second metallic conductor) are continuously formed using the same metal mask. (A series of steps consisting of one mask step, a plurality of successive film formation steps, and one lift-off step corresponding to the one mask step), but the present invention is limited to this. Instead, the barrier metal wiring may be formed using a metal mask, and then the metal mask may be peeled off and the copper wiring may be formed using another metal mask.

  Furthermore, the subject of the present invention is not limited to silicon wafers, and can be applied to various circuit boards.

  Furthermore, the circuit board that is the subject of the present application is not limited to a silicon wafer and a semiconductor chip, but an electronic device (single semiconductor chip or a plurality of semiconductors) as a final product encapsulating the silicon wafer and the semiconductor chip. As a system included in a semiconductor device in which a chip is sealed by molding or the like, a card including a single or a plurality of semiconductor devices, a card including a single or a plurality of semiconductor chips, and an electronic device such as a computer or a mobile communication device For example, a motherboard). In this case, the external terminal electrode of the circuit board is an external terminal electrode included in the final product. One technical idea of the present application (a mask process in which a metal mask is applied to a substrate created through a photolithography process without using a photolithography process, and a film forming process in which a metallic conductor is formed by an ion plating method) And a lift-off process for peeling the metal mask, and an electrode forming process for forming the external terminal electrode).

  It should be noted that the technical idea so far does not exclude the laying of bonding wires in the subsequent process, and does not restrict the circuit board or the final product from containing bonding wires. Therefore, instead of the solder ball 9 in the embodiment, a bonding wire or TAB (tape automated bonding) may be included in the external terminal electrode.

  Next, the structure of the semiconductor device and the electronic system according to the present embodiment and the manufacturing method thereof will be described. 19 to 42 illustrate the structure and manufacturing method of the semiconductor device and electronic system related to the circuit board.

  FIG. 19 is a top view of a schematic structural diagram showing the structure of a semiconductor device (including a plurality of chips) according to a preferred embodiment of the present invention.

  As shown in FIG. 19, in the semiconductor device according to the present embodiment, a plurality of semiconductor chips (first to seventh chips) as a plurality of functional elements are mounted on an insulating substrate 50 (fourth substrate). The insulating substrate 50 is made of a known material and manufacturing method. A plurality of wirings each including a plurality of wiring layers 51 (insulating substrate wirings) are included on the insulating substrate. The wiring layer 51 is made of a known material and manufacturing method. The semiconductor device has external terminal groups 1 and 2 that communicate with the outside. The external terminal group has the same structure as the wiring layer 51. The external terminal groups 1 and 2 do not have to be formed on the upper surface of the insulating substrate 50 (the surface on which the first to seventh chips are mounted), and may be formed on the rear surface of the insulating substrate 50. Absent. In FIG. 19, the external terminal groups 1 and 2 are indicated by broken lines, which means that the external terminal groups 1 and 2 are formed on the back surface of the insulating substrate 50. This also applies to FIGS. 32, 33, 35, and 37.

  The semiconductor device according to the present embodiment has a first system composed of first, second and sixth chips, and a second system composed of third, fourth, fifth and seventh chips. The first chip (first substrate) and the second chip (second substrate) are stacked. The third, fourth and fifth chips are stacked. The first chip, the third chip (first substrate), and the fourth chip (fifth substrate) are the circuit boards described above. The third chip and the fourth chip are semiconductor chips having the same function. The sixth chip (third substrate) communicates with the outside of the semiconductor device via the first and second chips and the external terminal group 1, respectively. The seventh chip (third substrate) communicates with the outside of the semiconductor device via the third to fifth chips and the external terminal group 2, respectively. The electrical connection configuration of the second system composed of the third, fourth, fifth and seventh chips is shown in FIG. The electrical connection configuration of the first system including the first, second, and sixth chips is not shown, but is the same as that of the second system. Therefore, this semiconductor device is an example having two systems.

As shown in FIG. 20, the second system according to the present embodiment is a control circuit for converting an instruction signal of a CPU (processor: seventh chip) into an operation signal of a NAND flash memory (third and fourth chips). It is an example which showed the connection state with a chip | tip (5th chip | tip). Each symbol is as shown in Table 1. Other-a and -b are undisclosed special signals (not shown).

  The CPU includes control pins such as general-purpose I / O control signal (GPIO) pins, address specification pins A0 to An, and read / write pins RD / _WR. However, since the NAND flash memory sequentially executes reading and writing, it must be executed in steps different from the CPU instruction, and a control circuit (fifth chip) is required. In order to access the memory, first a predetermined command is input, and then the memory address is input for a necessary cycle. In addition, necessary data can be read and written. The control circuit properly executes the NAND flash memory and executes the NAND memory task according to the CPU instruction. This shows that the connection wiring a between the CPU and the NAND flash memory, the connection wiring b between the CPU and the control circuit, the connection wiring c between the control circuit and the NAND flash memory, and the CPU, control circuit, and NAND flash memory. There is a connection wiring d shared between the three parties.

  Returning to FIG. 19, the connection wiring a, the connection wiring b, and the connection wiring d are each represented by a plurality of wiring layers 51 (a, b-1 to b-3, d−1, d−2, e−1). . The connection wiring c (c-1 to c-7) is indicated by the above-described wiring layer 21 or bonding wire, or a combination thereof. Note that the number of wirings is reduced on the drawing paper. Therefore, the number of chip take-out electrodes (internal terminal electrodes) 2 included in each corresponding chip is also shown smaller than the actual number of products. The plurality of internal terminal electrodes 2 are indicated by D1 to D10, E1 to E10, and F1 to F12 indicated by white frames in FIG. The wiring layer 21 includes a first end portion 21a, a second end portion 21b, and a rewiring portion 21c. In FIG. 19, the first end portion 21a and the second end portion 21b are indicated by symbols G and H indicated by gray frames, and the rewiring portion 21c is indicated by a dotted line or a one-dot chain line. The rewiring part 21c connects the first end 21a and the second end 21b, or the first ends 21a, or the second ends 21b. The wiring layer 21 formed on the surface of each of the third chip and the fourth chip has the same pattern. As for the bonding wires, the bonding wires connecting between the internal terminal electrodes 2 or connecting the internal terminal electrode 2 and the first end portion 21a and the second end portion 21b are shown by either a thin line or a thick line. It is.

  The connection between the first chip and the second chip and the connection between them and the wiring layer 51 will be described in detail. The first chip has a plurality of chip take-out electrodes (internal terminal electrodes) 2. They are indicated by A1 to A5 indicated by white frames. The surface of the first chip includes a first end portion 21a (second node), a second end portion 21b (first node), and a rewiring portion 21c (first or second wiring). A rewiring is formed. The second chip has a plurality of chip take-out electrodes (internal terminal electrodes) 2. They are indicated by B1 to B6 indicated by white frames. The extraction electrode (internal terminal electrode) 2 (A1) is connected to the first end 21a (C2) as shown in FIG. For the convenience of the drawing, the white frame and the gray frame are slightly shifted. As a first structure type, the extraction electrode (internal terminal electrode) 2 (B1) is connected to the second end 21b (C1; first node) by a bonding wire (first bonding wire). Hereinafter, in the drawings, a solid line symbol drawn by a curve indicates a bonding wire. There are a thin solid line and a thick solid line, the meaning of which will be described later. The extraction electrode (internal terminal electrode) 2 (A1) is connected to the first end 21a (C2; second node). The extraction electrode (internal terminal electrode) 2 (A5) is connected to the first end portion 21a (C12). The extraction electrode (internal terminal electrode) 2 (B6) is connected to the second end 21b (C11). FIG. 21 shows a cross-sectional view of these components expressed by lines X-1 to X-2. The bonding wire 40 is formed by a known material, structure (circular and circular in cross section) and technique. An adhesive 42 is formed between the first and second chips. The insulating film 43 protects the bonding wire 40. This is a protective film necessary for the process of dicing the first wafer constituted by the first chip later along the scline line 41. The protective insulating film 8 is not shown. The rewiring is formed by the above-described metal mask, ion plating, and metal mask lift-off, and has a special structure. They include an edge portion viewed from a direction perpendicular to the surface of the first chip, and an angle of a cross section perpendicular to the surface of the first chip of the wiring layer, which is a rewiring in the edge portion in contact with the first chip, is provided. It is 55 degrees or less. For example, it is shown by the shape of the end of the wiring layer 21 on the scribe line 41 side. Further, the wiring layer 21 is constituted by an aggregate of columnar chunks extending in a direction different from the surface direction of the first chip. The wiring layer 21 is preferably a metal mainly composed of aluminum Al, and a small amount of sub-metal such as Si, Ti, and Cu is mixed therein to increase the adhesion to the passivation film and to resist electromigration due to a large current. Increased corrosion resistance. This is the range in which secondary metals are mixed in a range where the metallicity of Al is ensured. In particular, Al is a metal material that cannot be formed by a plating method used in general WLP, but can be formed by an ion plating method regardless of the type of metal. As an example, the thickness of the wiring layer 21 is 0.5 to 2 micrometers, but may be 0.2 to 10 micrometers as described above. The adhesive is, for example, an epoxy mixed with metal powder or the like, which is a die bonding agent (paste), or a silicone resin. In the present invention, the “main component” refers to a material having the largest weight ratio, and preferably refers to a material having a weight ratio of 50% or more.

  Returning to FIG. 19, as a second structure type, the extraction electrode (internal terminal electrode) 2 (B2) is connected to the second end 21b (C3) by a bonding wire (second bonding wire). The first wiring layer 51 (insulating substrate wiring; f) is connected to the second end 21b (C4) by a bonding wire (third bonding wire). FIG. 22 shows a cross-sectional view of these, which is expressed by lines X-3 to X-4.

  As a third structure type, the extraction electrode (internal terminal electrode) 2 (A3) is connected to the first end 21a (C9). The second wiring layer 51 (insulating substrate wiring; f) is connected to the second end portion 21b (C6). FIG. 23 shows a cross-sectional view of these expressed by lines X-5 to X-6. The wiring layer 21 is disposed between the first chip and the second chip, and is connected to the first end 21a (C9) and the second end 21b (C6). FIG. 23 shows a cross-sectional view of these expressed by lines X-5 to X-6.

  As a fourth structure type, the third wiring layer 51 (insulating substrate wiring; f) includes an extraction electrode (internal terminal electrode) 2 (A2), a second end 21b (C7), and a second end 21b. The lead electrode (internal terminal electrode) 2 (B3) is connected via (C8).

  As a fifth structure type, the fourth wiring layer 51 (insulating substrate wiring; f) is connected to the second end portion 21b (C5). The extraction electrode (internal terminal electrode) 2 (B4) is connected to the second end 21b (C5) via the second end 21b (C10). This is an application of the second and third structural types.

  The connection between the third chip, the fourth chip, and the fifth chip, and the connection between them and the wiring layer 51 will be described in detail. Basically, it is the same as the connection between the first and second chips, but the parts not disclosed in them will be described in detail.

  As a sixth structure type, the fifth wiring layer 51 (insulating substrate wiring; d-1) is connected to the second end 21b (G5) and the extraction electrode (internal terminal electrode) 2 (E1). The extraction electrode (internal terminal electrode) 2 (D1) is connected to the second end 21b (G5) via the first end 21a (G6). The extraction electrode (internal terminal electrode) 2 (F2) is connected to the second end 21b (G5) via the second end 21b (G2). Although the fourth chip has the wiring layer 21 and the two second end portions 21b (G2) and (G5) as in the third chip, they are not used. The extraction electrode (internal terminal electrode) 2 (E1) of the fourth chip is substantially connected to the second end portion 21b (G6; not shown) of the fourth chip.

  As the seventh structure type, the sixth wiring layer 51 (insulating substrate wiring; d-2) includes the second end 21b (G7), the extraction electrode (internal terminal electrode) 2 (D2), and the extraction electrode (internal Terminal electrode) 2 (E2). The extraction electrode (internal terminal electrode) 2 (F3) is connected to the second end 21b (G7) via the second end 21b (G3). Like the third chip, the fourth chip includes the wiring layer 21 and the two second end portions 21b (G3 (H3)) (G7 (H7)), but they are not used. The same applies hereinafter.

  As an eighth structure type, the two extraction electrodes (internal terminal electrodes) 2 (D5) (E4) are connected to the extraction electrodes (via the second end portion 21b (G10) and the second end portion 21b (G9)). Internal terminal electrode) 2 (F4). These are indicated by a connection wiring c (c-1).

  As a ninth structure type, the two extraction electrodes (internal terminal electrodes) 2 (F5) (E5) are connected via the second end 21b (G11) and the second end 21b (G12). . These are indicated by the connection wiring c (c-2). F5 and G11 are connected by a bonding wire (fifth bonding wire). E5 and D5 are connected by a bonding wire (sixth bonding wire).

  As a tenth structure type, the two extraction electrodes (internal terminal electrodes) 2 (F6) (D6) are connected via the second end 21b (G13) and the second end 21b (G14). . These are indicated by a connection wiring c (c-3).

  As the eleventh structure type, the two extraction electrodes (internal terminal electrodes) 2 (E10) and (D10) are respectively corresponding to the first end 21a (H16) (G16) and the first end 21a (H15). It connects to the extraction electrode (internal terminal electrode) 2 (F11) via (G15). The two extraction electrodes (internal terminal electrodes) 2 (E9) and (D9) are connected to the extraction electrodes (internal terminal electrodes) 2 (F11) via the corresponding first end portions 21a (H15) (G15), respectively. . These are indicated by a connection wiring c (c-7). The two first end portions 21a (H15) and (H16) are connected by a rewiring portion 21c (one-dot chain line) formed on the surface of the fourth chip. The rewiring part 21c (dashed line) is arranged between the third chip and the fourth chip. The two first end portions 21a (G15) and (G16) are connected by a rewiring portion 21c (dotted line) formed on the surface of the third chip. The rewiring portion 21c (dotted line) is disposed between the third chip and the fifth chip. As another structural form, the wiring layer 51 (insulating substrate wiring; a) is connected to the extraction electrode (internal terminal electrode) 2 (E3) with a bonding wire (seventh bonding wire), and the wiring layer 51 (insulation) The substrate wiring; a) is connected to the extraction electrode (internal terminal electrode) 2 (D3) by a bonding wire. The wiring layer 51 (insulating substrate wiring; b-3) is connected to the extraction electrode (internal terminal electrode) 2 (F10) by a bonding wire (fourth bonding wire).

  The first chip will be described in detail with reference to FIGS. FIG. 24 is a top view of the rewiring including the first end 21a, the second end 21b, and the rewiring portion 21c formed on the surface of the first chip. FIG. 25 is a top view of a wafer (first wafer) state formed of a plurality of first chips each having a rewiring formed thereon. The characteristics of these structures and manufacturing methods are as described above. Therefore, one first chip shown in FIG. 24 is an enlarged view of one first chip in the state of the first wafer.

  The third and fourth chips will be described in detail with reference to FIGS. 26 and 27 are top views of rewiring including the first end 21a, the second end 21b, and the rewiring portion 21c formed on the surfaces of the third chip and the fourth chip, respectively. . In this embodiment, since the chips have the same function, the rewirings have the same layout pattern, and only the signs are different. The third chip (fourth chip) shown in FIG. 26 is a wafer (second wafer) composed of a plurality of third chips on which rewirings are formed in the same manner as the first wafer (FIG. 25). Yes, it is an enlargement of one third chip. The same applies to FIG. Chips diced from one second wafer in the dicing step may be defined as third and fourth chips.

  The third and fifth chips relating to the first manufacturing method will be described in detail with reference to FIG. 28, FIG. 29 and FIG. FIG. 28 is a top view in which the fifth chip is laminated on the third chip with an adhesive. Precisely, the fifth chip is laminated on the rewiring formed on the surface of the third chip via an adhesive. In FIGS. 28, 29 and 30, it should be noted that the third chip is an enlargement of one third chip in the state of the second wafer. FIG. 29 is a top view in which the third chip and the fifth chip are connected by a bonding wire. Bonding wiring is performed at 8 locations. In the description of this embodiment, the bonding wire is treated as a single noun as a name. The bonding wire may be referred to as wire bonding. FIG. 30 is a top view in which eight bonding wires are protected by insulating films (shaded). In the process of dicing the second wafer or the test process, the bonding wire is prevented from being lost. Thereafter, the second wafer on which the plurality of fifth chips are stacked is diced into one stacked individual chip.

  The first to fifth chips will be described in detail with reference to FIG. A third chip is stacked on the fourth chip. A first chip and a fifth chip are stacked on the third chip, respectively. A second chip is stacked on the first chip. Precisely, one first individual chip in which the third chip and the fifth chip are stacked by bonding with a bonding wire is stacked on the fourth chip. One second individual chip in which the first chip and the second chip are stacked by bonding with a bonding wire is stacked on the third chip. The fourth chip is an individual chip obtained by dicing a second wafer on the surface of which a rewiring including a first end 21a, a second end 21b, and a rewiring portion 21c is formed. It is. Further, in the subsequent process, the third and fourth chips are stacked. The third chip is laminated on the fourth chip so that the extraction electrode (internal terminal electrode) 2, the first end 21a, and the second end 21b of at least a part of the fourth chip are exposed. The The significance of the exposure is for connection to at least one of the insulating substrate wiring 51, the extraction electrode (internal terminal electrode) 2 of the other chip, the first end portion 21a, and the second end portion 21b.

  The semiconductor device will be described in detail with reference to FIGS. In FIG. 32, the fourth chip (more precisely, the stacked first chip to fifth chip) is mounted on the insulating substrate 50. Each chip or a plurality of rewirings related to each chip is connected to a plurality of insulating substrate wirings 51 by a plurality of bonding wires (thick solid lines). The fourth chip or the rewiring associated with the fourth chip is connected to the third and fifth chips by a plurality of bonding wires (thick solid lines). In FIG. 33, the first to seventh chips are each protected by an insulating film (shaded).

  The first to fifth chips related to the second manufacturing method will be described in detail with reference to FIGS. In FIG. 34, the first to fifth chips diced from the respective wafers are stacked. Naturally, rewiring is formed on the respective surfaces of the first, third and fourth chips. In the first manufacturing method, different chips are stacked in a wafer state including rewiring, bonding wires are laid, and then dicing is performed. On the other hand, in the second manufacturing method, first, rewiring is included. The wafer is diced to stack different chips.

  In FIG. 35 (semiconductor device), a fourth chip (precisely, stacked first to fifth chips) is mounted on an insulating substrate 50, and a plurality of insulating substrate wirings 51 and Connected with multiple bonding wires. The first chip to the fifth chip are each connected by a plurality of bonding wires. Note that all bonding wires are thick solid lines. This is because all bonding wires are laid in one step. The first chip to the seventh chip are each protected by an insulating film.

  The first to fifth chips relating to the third manufacturing method will be described in detail with reference to FIG. In FIG. 36, first to fifth chips diced from the respective wafers are stacked. Naturally, rewiring is formed on the respective surfaces of the first, third and fourth chips. The first chip and the second chip are connected by a bonding wire (thin solid line). Further, the third chip and the fifth chip are connected by a bonding wire (thin solid line). These bonding wires are protected by an insulating film (shaded). In the second manufacturing method, the fourth chip (more precisely, the stacked first chip to fifth chip) is mounted on the insulating substrate 50, and a plurality of insulating substrate wirings 51 and a plurality of bondings are respectively mounted. In contrast to the connection by wires, in the third manufacturing method, the fourth chip (precisely, the stacked first chip to fifth chip) is one before being mounted on the insulating substrate 50. Bonding wires are laid and a protective film is provided. In a state where a part of the bonding wires is laid, after testing the fourth chip (more precisely, the first to fifth chips stacked), only the non-defective product is mounted on the insulating substrate 50.

  FIG. 37 is a top view of a schematic structural diagram showing the structure of a plurality of semiconductor devices (each including a plurality of chips) and an electronic system according to a preferred embodiment of the present invention. The electronic system includes first to third semiconductor devices (semiconductor devices 1, 2, 3 respectively). The first semiconductor device communicates with the semiconductor devices 2 and 3 via the external terminal groups 1 and 2 laid on the insulating substrate 52, respectively. The semiconductor devices 2 and 3 communicate with the outside through external terminal groups 3 and 4 laid on the insulating substrate 50, respectively. A part of the external terminal groups 1 and 2 may be laid on the back surface of the insulating substrate 52. The semiconductor device shown in FIG. 19 is provided to the customer as one component, whereas the first semiconductor device shown in FIG. 37 is provided to the customer as one component. For example, a customer manufactures first to third semiconductor devices purchased from different suppliers as one system, and provides them to end users as final products of electronic components. The features of the present application similar to those of the first semiconductor device can be applied to the second and third semiconductor devices. Thus, even in an electronic system, it includes the features of the present application.

  Next, the semiconductor device and electronic system manufacturing method according to the present embodiment will be explained. FIG. 38 shows the first manufacturing method, FIG. 39 shows the second manufacturing method, and FIG. 40 shows the third manufacturing method. In the first to third manufacturing methods, FIGS. 24 to 27 are common.

  The first manufacturing method (FIG. 38) corresponds to FIGS. In step 201, an electronic circuit is formed on the wafer. This step is formed by photolithography (resist application, exposure, development, resist stripping) as described above. This may be purchased from a different vendor. In step 202, rewiring and the like are formed on the wafer, which is the feature of the present application described above. In step 203, different chips are stacked with an adhesive or the like on a wafer (circuit board) on which rewiring is formed. After an epoxy or silicone resin mixed with metal powder or the like as a die bonding agent (paste) is formed on the wafer by a printing method, a different chip is mounted and the resin is cured. In step 204 (first bonding wire process), the stacked chips and the wafer are connected by bonding wires (wire bonding). In step 205 (first bonding wire protective film forming step), the bonding wire region is covered with a protective film. The protective film is cured by applying an organic coating material by potting or the like. In step 206, the wafer is diced and separated into a plurality of stacked chips. In step 207, the insulating substrate 50 of the semiconductor device is connected with an adhesive or the like. The adhesive is, for example, an epoxy mixed with metal powder or the like, which is a die bonding agent (paste), or a silicone resin. In step 208 (second bonding wire process), the wiring 51 on the insulating substrate and the stacked chip are connected by a bonding wire. In step 209 (second bonding wire protective film forming step), at least the bonding wire region is covered with a protective film. The protective film is cured by applying an organic coating material by potting or the like. Preferably, a region including the stacked chips is covered with a protective film. In step 210, visual inspection and the like are performed to complete the semiconductor device (semiconductor circuit). It should be noted that there are two bonding wire processes and two insulating films covering the bonding wires. In the test process, it is preferable to apply three test processes. In the first test process (Test 1), an electronic circuit drawn on the wafer is tested. The first test process may be performed after step 202. Alternatively, a test may be performed after step 201 and a test may be performed after step 202. According to this, it is possible to determine whether or not the rewiring formed in step 202 has a defect. In the second test step (Test 2), a plurality of stacked electronic circuits are tested. The second test process may be performed after step 204. This is because the bonding wire may be corrected (repaired) or a redundant bonding wire (not shown) may be laid depending on the test result. In the third test step (Test 3), the entire semiconductor device is tested. The third test process may be performed after step 208. This is because the bonding wire may be corrected (repaired) or a redundant bonding wire (not shown) may be laid depending on the test result. In these series of steps, the significance of the bonding wire can be adjusted by the length of the bonding wire even if the coordinates of the extraction electrodes (internal terminal electrodes) 2 of the first to fifth chips differ due to design changes or the like. Flexible connection can be realized.

  The second manufacturing method (FIG. 39) corresponds to FIGS. Only the point of the first manufacturing method will be described in detail. After step 202, step 206 is applied. After step 206, step 211 is applied. After step 211, step 212 and step 213 are applied sequentially. That is, after step 202, step 203 to step 205 are eliminated and step 206 is applied. In step 211, all the chips are stacked on the insulating substrate 50 as shown in FIG. In step 212 (third bonding wire process), all the chips stacked with the wiring 51 on the insulating substrate and the chips are connected to each other in a single bonding wire process. Step 213 (third bonding wire protective film forming step) covers at least the bonding wire region with a protective film. With these multiple steps, a semiconductor device can be realized with a smaller number of steps than the number of steps of the first manufacturing method. Note that with regard to the test process, the second manufacturing method is reduced to two test processes. However, also in this example, a test may be performed after step 201 and a test may be performed after step 202. According to this, it is possible to determine whether or not the rewiring formed in step 202 has a defect. Further, it is not essential to form all the bonding wires in step 212, and the bonding wires may be formed in a plurality of steps. For example, a bonding wire for connecting chips to each other may be formed first, and then a bonding wire for connecting the wiring 51 on the insulating substrate and the chip may be formed in another process.

  The third manufacturing method (FIG. 40) corresponds to FIG. Only differences from the first manufacturing method will be described in detail. After step 202, step 206 is applied. After step 206, step 214 and step 215 are sequentially applied. That is, the process of step 206 for dicing the wafer is shifted to a process before the first manufacturing method. This makes it possible to use an inexpensive and small bonder device corresponding to the chip size as compared with an expensive and large bonder device corresponding to the wafer size. In step 214, a plurality of chips diced from the respective wafers are stacked. Step 215 connects the chips with bonding wires. Further, the first test process (Test 1) may be performed after Step 206.

  The first to third manufacturing methods have different advantages. A semiconductor device manufacturer does not manufacture all of the first to seventh chips. In addition, re-wiring may be performed by different vendors. The first to third manufacturing methods provide various manufacturing methods related to the plurality of manufacturers. For example, each of Test 1 to Test 3 can be understood as a delivery responsibility associated with a different vendor.

  The preferred embodiments of the semiconductor device and electronic system of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, these are also included in the scope of the present invention.

  For example, the second end 21b may include a wiring layer 22 (second wiring layer) as shown in FIGS. 2 and 3B. In some cases, the manufacturing conditions of the bonding wire that changes to the solder ball 9 can be relaxed.

  Further, the structure in which the sixth chip and the seventh chip are connected to the wiring layer 51 is not limited. The structure shown in FIG. 2 is connected to the insulating substrate 50 as a flip chip. Further, the structure excluding the wirings 6 and 7 and the solder balls 9 in FIG. 2 can be included in the manufacturing process (bonding process, bonding wire process) of the semiconductor device of the present application.

  In addition, the power supply lines supplied from the insulating substrate 50 to the first to seventh chips can be applied by applying the rewiring characteristics disclosed in the present application.

  The semiconductor device may be only the first system configured by the first, second, and sixth chips, and the second system configured by the third, fourth, fifth, and seventh chips, or the first system. Of course, only the second system composed of 3, 5 and the seventh chip may be used. The appearance, shape, and function of the semiconductor device are not limited. Therefore, in the first system, the system related to the NAND flash memory is exemplified, but the system is not limited to the nonvolatile memory, but is not limited to the volatile memory, a combination thereof, or the memory function.

  The semiconductor device may have a function of performing data processing related to each other between the first system and the second system. For example, a rewiring connected to the first and second chips with a bonding wire via a rewiring formed on the surface of the third chip, or a rewiring formed on the surface of the first chip; Various structures such as rewiring formed on the surface of the chip, and the third, fourth, and fifth chips are connected by bonding wires are conceivable.

  In the above embodiment, all electrical connections between chips are performed by bonding wires. However, the present invention is not limited to this, and some electrical connections between chips are performed by flip chip connection. You can go. FIG. 41 shows an example in which a part of electrical connection between chips is performed by flip chip connection. In the example shown in FIG. 41, a chip Chip-B is mounted on the chip Chip-A, and a chip Chip-C is mounted on the chip Chip-B. Among these, the chip Chip-A and the chip Chip-B are mounted by the face-up method so that the upper side becomes the main surface, and the chip Chip-C is mounted by the face-down method so that the lower side becomes the main surface. The bonding wires 40 are electrically connected between the chip Chip-A and the wiring 51, between the chip Chip-B and the wiring 51, and between the chip Chip-A and the chip Chip-B. Yes. On the other hand, the chip Chip-B and the chip Chip-C are electrically connected by flip chip connection using the solder balls 9. The present invention can also include such an embodiment. At least one of the chip Chip-B and the chip Chip-C has a redistribution layer that is a feature of the present application and is formed on the surface of the chip. The structure of chip Chip-C is shown in FIG. The structure of the chip Chip-B is, for example, a wiring 42 laid on the surface of the first chip shown in FIG. The solder ball 9 is connected to the wiring 42. By applying the feature of the present application to at least one of the chips, a significant cost reduction can be realized.

  Furthermore, in the above-described embodiment, the connection between a plurality of stacked chips has been described. However, the technical idea of the present invention can also be applied to a connection between a plurality of chips that are not stacked. For example, as shown in FIG. 42, the chip Chip-D and the chip Chip-E are mounted on the upper surface of the insulating substrate 50, and between the chip Chip-D and the wiring 51, between the chip Chip-E and the wiring 51, In addition, the chip Chip-D and the chip Chip-E can be electrically connected by the bonding wire 40. The present invention can also include such an embodiment. The chip Chip-D and the chip Chip-E have a redistribution layer that is a feature of the present application and is formed on the surface of at least one of the chips. The bonding wire 40 is connected to at least one of the chips Chip-D and Chip-E.

  Furthermore, in the above embodiment, an example in which a plurality of semiconductor chips are mounted on the insulating substrate 50 has been described. However, the substrate on which the semiconductor chip is mounted is not limited to an insulating substrate, and a conductive material such as a lead frame. It may be a substrate. The present invention can also include such an embodiment.

1 Substrate 2 Chip extraction electrode (internal terminal electrode)
3 Passivation films 4 and 6 Barrier metal wirings 4a and 6a Barrier metal material 5 and 7 Copper wiring 8 Protective insulating film 8a Protective insulating film end 9 Solder ball 9a Bottom surface of solder ball 10 Silicon wafer 21 Wiring layer (first wiring layer)
22 Wiring layer (second wiring layer)
21a First end portion 21b Second end portion 21c Redistribution portion 21e, 22e Edge portion 21s, 22s Side surface 21u, 22u Upper surface 22a Edge portion 30 Columnar substrate 31 Substrate 32, 32a, 32b Species 32c Species core 32d Island -Like lump 40 Bonding wire 41 Scribe line 42 Adhesive 43, 44 Insulating film 50, 52 Insulating substrate (substrate of semiconductor device, system substrate)
51, a, b, d, e, f, g Insulating substrate wiring 100, 200 Metal mask 101, 201 Opening

Claims (54)

A first substrate having a first electronic circuit drawn on a main surface, the first electronic circuit having first and second internal terminal electrodes each communicating with the outside of the first electronic circuit;
A second electronic circuit is drawn on the main surface, and the second electronic circuit has third and fourth internal terminal electrodes that communicate with the outside of the second electronic circuit, respectively, on the first substrate A laminated second substrate;
Is formed on a part of a surface of said first substrate, each viewing including the first and second lines having first and second node, extending in a direction different from the surface direction of the first substrate A wiring layer constituted by an aggregate of columnar chunks ;
First and second bonding wires connecting the third and fourth internal terminal electrodes and the corresponding first nodes of the first and second wirings, respectively.
The first and second bonding wires have a circular cross section,
The wiring layer includes an edge portion viewed from a direction perpendicular to the surface of the first substrate, and a cross section perpendicular to the surface of the first substrate of the wiring layer at the edge portion in contact with the first substrate. An angle of the semiconductor device is 55 ° or less. Wherein at least a portion of the plurality of columnar mass contained in the aggregate, the semiconductor device according to claim 1, the height from the surface of the first substrate are different from each other, it is characterized. A plurality of columnar chunk included in the aggregate is a crystal of a metal material constituting the wiring layer, the semiconductor device according to claim 1 or 2, characterized in that. The semiconductor device according to claim 3 , wherein at least some of the plurality of columnar chunks included in the aggregate have different crystal orientations. And a first insulating film covering at least the wiring layer excluding the region of the first node.
The height of the surface of the first insulating film from the first substrate is higher than the height of the surface of the wiring layer in contact with the first and second bonding wires from the first substrate, the semiconductor device according to any one of claims 1 to 4, characterized in that. The wiring layers, Cu, Al, Ti, as main components Cr and a metal selected from the group consisting of Ni, the semiconductor device according to any one of claims 1 to 5, characterized in that. The semiconductor device according to claim 6 , wherein a main component of the wiring layer is Al. The wiring layers, a semiconductor device according to any one of claims 1 to 7 comprising a multiple alloy comprising a plurality of metallic materials, characterized in that. The first to fourth internal terminal electrodes, the semiconductor device according to any one of claims 1 to 8, characterized in that includes a layer that is plated on its surface. At least the first and second internal terminal electrodes are made of Al,
The wiring layers, a semiconductor device according to any one of claims 1 to 8 containing Al as a main component, it is characterized. The first substrate includes a semiconductor substrate and a second insulating film that is in contact with the surface of the semiconductor substrate and covers the semiconductor substrate excluding at least the regions of the first and second internal terminal electrodes. the semiconductor device according to any one of claims 1 to 10, characterized in that. The semiconductor device according to claim 11 , wherein the wiring layer is in contact with a surface of the second insulating film and covers a part of the second insulating film. The first substrate is a semiconductor wafer having the same circuit is repeatedly formed, the semiconductor device according to any one of claims 1 to 12, characterized in that. The second node of the first wiring covers the first internal terminal electrode, thereby connecting the second node of the first wiring and the first internal terminal electrode. The semiconductor device according to any one of claims 1 to 13 . The semiconductor device according to claim 14 , wherein a part of the first wiring is disposed between the first and second substrates. 1 to 15 , further comprising a third bonding wire for connecting the second node of the second wiring and the tenth node in the semiconductor device other than the first substrate. The semiconductor device as described in any one. A third substrate having fifth, sixth, and seventh internal terminal electrodes on which a third electronic circuit is drawn and wherein the third electronic circuit communicates with the outside of the third electronic circuit;
A fourth substrate on which the first substrate and the third substrate are mounted;
A second wiring layer formed on a part of the surface of the fourth substrate and including third and fourth wirings each having a third and a fourth node;
A third node of the third wiring, which is a tenth node in the semiconductor device, is electrically connected to the fifth internal terminal electrode via a fourth node of the third wiring; The semiconductor device according to claim 16 . The second internal terminal electrode is connected to a third node of the fourth wiring;
The semiconductor device according to claim 17 , wherein a fourth node of the fourth wiring is electrically connected to the sixth internal terminal electrode. Furthermore, the semiconductor device has an external terminal for communicating with the outside,
The semiconductor device according to claim 18 , wherein the seventh internal terminal electrode is electrically connected to the external terminal. The semiconductor device according to any one of claims 1 to 19 comprising an adhesive that connects the first substrate and the second substrate, it is characterized. And a third insulating film covering at least one of the first and second bonding wires,
The third insulating film, the second does not cover the wiring area of the second node, the semiconductor device according to any one of claims 17 to 19, characterized in that. Furthermore, the second substrate has an eighth internal terminal electrode,
Further, the semiconductor device includes a fourth interface for directly connecting the eighth internal terminal electrode and a node in the semiconductor device other than the first substrate without passing through the first and second wirings. the semiconductor device according to any one of claims 1 to 21 wherein the bonding comprises a wire, it is characterized. And a third insulating film covering at least one of the first and second bonding wires,
The semiconductor device according to claim 22 , wherein the third insulating film does not cover a region of the eighth internal terminal electrode. A fifth substrate disposed between the fourth substrate and the first substrate, on which a fourth electronic circuit is drawn, and having ninth and tenth internal terminal electrodes;
An eleventh internal terminal electrode included in the second substrate, wherein the second electronic circuit communicates with the outside of the second electronic circuit;
A fifth wiring that is formed on a part of the surface of the first substrate and that is the wiring layer having fifth and sixth nodes;
A fifth bonding wire connecting the eleventh internal terminal electrode and a fifth node of the fifth wiring;
18. The semiconductor device according to claim 17 , comprising: the ninth internal terminal electrode; and the sixth bonding wire that connects the sixth node of the fifth wiring. And a third insulating film covering at least one of the first and second bonding wires,
25. The semiconductor device according to claim 24 , wherein the third insulating film does not cover a region of the eleventh internal terminal electrode. Further comprising a seventh said bonding wire for connecting the first 11 node of said tenth the semiconductor device and the internal terminal electrodes other than the first and second substrate of claim 24 or, characterized in that 25. The semiconductor device according to 25 . Furthermore, a twelfth internal terminal electrode included in the third substrate, the third electronic circuit communicating with the outside of the semiconductor device,
A sixth wiring formed on a part of the surface of the fourth substrate and being a wiring layer having seventh and eighth nodes;
A seventh node of the sixth wiring that is an eleventh node in the semiconductor device is electrically connected to the twelfth internal terminal electrode through an eighth node of the sixth wiring; 27. The semiconductor device according to claim 26 . Said first substrate, said fifth the ninth substrate and so as not to cover the first 10 internal terminal electrode, laminated on the fifth substrate, according to claim 24 or 27, characterized in that The semiconductor device as described in any one. A circuit board for forming a wiring for electrically connecting the internal terminal electrode and the outside of the first board on a first board having an internal terminal electrode, and a method of manufacturing a semiconductor device including the circuit board And
The manufacturing process of the circuit board includes:
A mask step of covering the substrate with a metallic metal mask having an opening that exposes a part of the surface of the first substrate including the internal terminal electrode and connected to the cathode side;
By applying a predetermined potential to the first substrate and applying a deposition energy of 0.01 eV to 250 eV to a deposition metal ionized to a potential different from the predetermined potential, a part of the surface of the substrate and On the metal mask, a film forming step of forming a metallic conductor from ion particles having a positive charge by an ion plating method;
A lift-off step of leaving the wiring layer of the wiring made of a metallic conductor electrically connected to the internal terminal electrode formed on a part of the surface of the substrate by peeling the metal mask. ,
The manufacturing process of the semiconductor device includes:
A first laminating step of laminating a second substrate having internal terminal electrodes on a surface of the circuit board on the wiring side;
A first connection step of connecting the internal terminal electrode of the second substrate and the wiring on the circuit board,
A method for manufacturing a semiconductor device. 30. The method of manufacturing a semiconductor device according to claim 29 , wherein a deposition energy of 5 to 100 eV is applied to the ionized deposition metal. 30. The method of manufacturing a semiconductor device according to claim 29 , wherein the first substrate has an internal wiring formed by a photolithography method and electrically connected to the internal terminal electrode. The first substrate is a collective substrate in which the same circuit is repeatedly formed,
32. The method of manufacturing a semiconductor device according to claim 31 , further comprising a cutting step of taking out individual unit substrates by cutting the aggregate substrate after performing at least the lift-off step. 33. The method of manufacturing a semiconductor device according to claim 32 , wherein the cutting step is performed after the first connection step. 34. The method of manufacturing a semiconductor device according to claim 32, wherein the collective substrate is a semiconductor wafer, and the unit substrate is a semiconductor chip. An insulating film forming step of selectively supplying a fluid insulating material to the surface of the substrate excluding the internal terminal electrodes of the circuit substrate after performing the lift-off step and before performing the first stacking step. the method of manufacturing a semiconductor device according to any one of claims 29 to 34, characterized in that it further comprises. 36. The method of manufacturing a semiconductor device according to claim 35 , wherein, in the insulating film forming step, a peripheral portion of an upper surface of the wiring layer is covered with the insulating material. A plurality of wiring layers are formed by a series of process groups including one mask process, a plurality of successive film formation processes, and one lift-off process corresponding to the one mask process. 37. A method of manufacturing a semiconductor device according to any one of claims 29 to 36 . The plurality of successive film forming steps include the first film forming step for forming the first metallic conductor and the second film forming step for forming the second metallic conductor. 38. The method of manufacturing a semiconductor device according to claim 37 , further comprising: A first process group comprising the mask process using the first metal mask, the film forming process at least once, and the lift-off process corresponding to the mask process;
A second mask step of covering the substrate with a metallic second metal mask having an opening that exposes a first region to be electrically connected to the outside of the circuit substrate on the circuit substrate;
At least one second film forming step for forming the metallic conductor by ion plating on the first region and the second metal mask, and peeling the second metal mask. A second process group consisting of a second lift-off process for leaving the second wiring layer made of the metallic conductor formed in the first region,
Wherein the first and second process group, the manufacturing method of a plurality of forming the wiring layer, semiconductor device according to any one of claims 29 to 36, characterized in. The plurality of wiring layers are:
A first end that covers the internal terminal electrode of the circuit board; a second end that is an area to be electrically connected to the outside of the circuit board; and the first end that extends along the surface of the board. A first wiring layer having a rewiring portion that connects one end portion and the second end portion;
The first covers the second end of the wiring layers, according to any one of the first claims 37 to 39 and the second wiring layer in contact with the wiring layer, characterized in that it comprises a for Semiconductor device manufacturing method. In connection with the formation of the wiring layer, the resist coating, exposure, development, and does not include the steps of peeling of the resist, it semiconductor device according to any one of claims 29 to 40, characterized in Manufacturing method. The said film-forming process forms the said metallic conductor by using as a main component the metal selected from the group which consists of Cu, Al, Ti, Cr, and Ni, The any one of Claim 29 thru | or 41 characterized by the above-mentioned. A method for manufacturing the semiconductor device according to the item. 43. The method of manufacturing a semiconductor device according to claim 42 , wherein the film forming step forms the metallic conductor with Al as a main component. Said first connecting step is a step of connecting the bonding wires, the method of manufacturing a semiconductor device according to any one of claims 29 to 43, characterized in that. Furthermore, after the said 1st connection process, except the one part area | region of the wiring on the said circuit board, the 1st insulation process of forming the insulating film which covers the said bonding wire is provided, It is characterized by the above-mentioned. 44. A method for manufacturing a semiconductor device according to 44 . The first substrate is a collective substrate in which the same circuit is repeatedly formed,
Further, after the first insulating step, each of the plurality of substrate includes the second substrate by cutting the collective substrate including the second substrate stacked on the circuit substrate by the first stacking step. 46. The method of manufacturing a semiconductor device according to claim 45 , further comprising a cutting step of taking out the unit substrate. Furthermore, after the cutting step, a second stacking step of mounting the unit substrate on a fourth substrate;
47. The method of manufacturing a semiconductor device according to claim 46 , further comprising a second connection step of connecting the wiring of the fourth substrate and the wiring of the unit substrate. The first substrate is a collective substrate in which the same circuit is repeatedly formed,
48. The method according to claim 47 , further comprising a cutting step of taking out individual unit substrates by cutting the collective substrate between the circuit board manufacturing step and the first stacking step. A method for manufacturing a semiconductor device. The first stacking step includes a step of mounting the unit substrate on a fourth substrate,
The first connection step further includes a connection between the internal terminal electrode of the first substrate and the wiring of the fourth substrate, and the wiring of the internal terminal electrode of the second substrate and the fourth substrate. A connection between the wiring of the circuit board and the wiring of the fourth board, a connection between the internal terminal electrode of the first board and the internal terminal electrode of the second board, Connecting at least one of the wiring of the circuit board and the internal terminal electrode of the first board by the bonding wire,
The first insulating step further includes covering the partial area of the wiring of the circuit board and the bonding wire related to the at least one connection with the insulating film. 48. A method for manufacturing a semiconductor device according to 48 . The first connection step further includes a connection between the internal terminal electrode of the first substrate and the internal terminal electrode of the second substrate, and the wiring of the circuit board and the internal terminal of the first substrate. Connecting at least one of connections between electrodes by the bonding wire,
49. The method of manufacturing a semiconductor device according to claim 48 , wherein the first insulating step further covers the bonding wire related to the at least one connection with the insulating film. Furthermore, after the first insulating step, a second stacking step of mounting the unit substrate on a fourth substrate;
51. The method of manufacturing a semiconductor device according to claim 50 , further comprising a second connection step of connecting the wiring of the fourth substrate and the wiring of the unit substrate. Furthermore, at least any of the internal terminal electrodes of the first substrate, the wiring of the circuit board, and the internal terminal electrodes of the second substrate that are not related to the first connecting step after the first connecting step. via one or the first and comprising a test step of testing the second substrate, according to claim 29 or 48, characterized in that, 50, the manufacturing method of the 51 semiconductor device according to any one of . 53. The method of manufacturing a semiconductor device according to any one of claims 29 to 52 , wherein at least the first substrate is a semiconductor substrate. The deposition energy, a method of manufacturing a semiconductor device according to any one of claims 29 to 53 the main portion and 25 ± 10 eV, it is characterized.