JP5665495B2 - Data phase synchronization apparatus and data phase synchronization method - Google Patents

Description

  The present invention relates to a data phase synchronization apparatus in parallel signal communication applied to a digital transmission system such as an optical communication system.

  Conventionally, in order to perform high-speed data transfer, it is generally performed to increase the amount of transfer data per clock cycle by increasing the clock frequency of a signal and further parallelizing it with a plurality of signals. When the speed is increased by such parallel communication, the data phase shift (skew) due to the data propagation time difference between the signal lines and the demultiplexing phase (tributary) synchronization of the data expanded in parallel become problems. A circuit that aligns the phases is required.

  As a method of synchronizing the data phase, in Patent Documents 1 and 2 below, a reception pattern determination circuit having a large circuit scale is provided, and the length synchronization is proportional to the maximum data phase difference assumed for determining the data phase. A technique for detecting a pattern is disclosed. For example, the following Patent Document 1 uses a method based on MLD (Multi Lane Distribution), SFI-5 (Serdes Framer Interface Level 5), and VSR 5 (Very Short Reach Interface Level 5). A data phase synchronization circuit for obtaining a delay value in which the start point and end point of data match the rising edge of the clock is described.

JP 2010-016791 A JP 2004-127147 A

  However, according to the above-described conventional technology, in order to detect a long synchronization pattern corresponding to more than twice the maximum data phase difference assumed for determining the data phase, a large-capacity received data holding circuit, or A reception pattern determination circuit such as a high-speed pipeline processing circuit that divides a long pattern into multiple stages without accumulating reception data and processes it as needed is required. Therefore, there is a problem that the circuit scale becomes large and complicated.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a data phase synchronization device that can synchronize data phases with a simple configuration with a small circuit scale.

In order to solve the above-described problems and achieve the object, the present invention is a data phase synchronization device that synchronizes data phases between lanes in parallel signal communication in which data communication is performed in parallel using a plurality of lanes. Te, delimiter value indicating a boundary of a training pattern frame, and the training pattern frame synthesizing means for generating a training pattern frame including a counter value corresponding to the training pattern frame number, the data sent to preparative rate training pattern frame into a plurality of lanes determining a selection means to insert, detects the delimiter value from the inserted training pattern frame data received are transmitted by a plurality of lanes, a frame phase of the received data indicated by the position of the detected delimiter value a delimiter detecting means for, based on the frame phase, received Uptake counter value included in the training pattern frame inserted in the data, a counter reproducing means for reproducing the training pattern frame number corresponding to the counter value taken, the frame phase and regenerated training pattern frame number based on the skew estimation means for estimating the amount of skew between a plurality of lanes, based on the amount of skew between a plurality of lanes that is estimated by the skew estimation means, deskew control means for controlling to cancel the skew between a plurality of lanes When, under the control of the deskew controller, characterized in that it comprises a phase adjusting means for processing for canceling the skew in multiple lanes.

  According to the present invention, there is an effect that the data phase can be synchronized with a simple configuration with a small circuit scale.

FIG. 1 is a diagram illustrating a configuration example of a digital transmission system. FIG. 2 is a diagram illustrating a configuration example of a digital transmission system to which the data phase synchronization device is applied. FIG. 3 is a flowchart showing the data phase synchronization processing. FIG. 4 is a diagram illustrating a configuration example of a training pattern frame. FIG. 5 is a diagram illustrating an example of received capture data of a training pattern frame. FIG. 6 is a diagram illustrating a method for detecting a delimiter value. FIG. 7 is a diagram illustrating a configuration example of a digital transmission system.

  Embodiments of a data phase synchronization apparatus according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration example of a digital transmission system according to the present embodiment. The digital transmission system includes a separation unit 1, a FIFO (First In First Out) unit 2, a serializer unit 3, a deserializer unit 4, and a multiplexing unit 5.

  In FIG. 1, a demultiplexer 1 outputs a number of relatively low-speed signals obtained by performing various data processing such as transmission frame demapping processing and error correction decoding on a high-speed electric signal having a total bandwidth of 40 Gbps. . The serializer unit 3 converts these signals into higher-speed 16-lane transmission electrical signals. Then, the deserializer unit 4 converts the signal transmitted through each of these lanes into a lower speed signal suitable for modulation data processing. Finally, the multiplexing unit 5 outputs as a high-speed serial electric signal.

  This serial electrical signal is electro-optically converted into a transmission optical signal (not shown) and transmitted through an optical fiber. Here, the data demultiplexing phase (tributary) at the time of the parallel-serial conversion in the serializer unit 3 and the serial-parallel conversion in the deserializer unit 4 is usually different for each lane and parallel development signal, and further, the serializer unit 3 or It changes irregularly every time the deserializer unit 4 is powered on or reset. As a result, the arrangement of the data bits on the parallel side of the serializer unit 3 and the relative arrangement of the data bits between the lanes on the parallel side of the deserializer unit 4 change with each lane activation and initialization. Thus, the plurality of factors are added together to generate a skew that is a data phase difference between lanes.

  On the other hand, in the digital transmission system, the setup and hold times are satisfied by the FIFO unit 2 that can change the delay time difference between lanes of transmission or reception data, and a clock phase adjustment circuit such as a delay circuit or PLL (not shown), The bit value transmitted every clock cycle is configured not to be double fetched or missed.

  Next, a digital transmission system to which the data phase synchronization apparatus is applied will be described. FIG. 2 is a diagram illustrating a configuration example of a digital transmission system to which the data phase synchronization device is applied. The digital transmission system to which the data phase synchronization device is applied includes a separation unit 1, a serializer unit 3, a deserializer unit 4, a multiplexing unit 5, a delimiter generation unit 11, a bit inversion unit 12, a counter generation unit 13, Training pattern frame synthesis unit 14, selection unit 15, FIFO unit 16, storage unit 17, delimiter detection unit 18, counter reproduction unit 19, skew estimation unit 20, deskew control unit 21, and barrel shifter unit 22 And comprising.

  Next, data phase synchronization processing in a digital transmission system to which the data phase synchronization device is applied will be described. FIG. 3 is a flowchart showing the data phase synchronization processing. First, the delimiter generation unit 11 generates a 2-byte delimiter value indicating the boundary of the training pattern frame. The counter generation unit 13 generates a 1-byte counter value (bit non-inverted counter value) corresponding to the training pattern frame number. The bit inversion unit 12 generates a 1-byte bit inversion counter value of the counter value generated by the counter generation unit 13. Then, the training pattern frame synthesizing unit 14 synthesizes the delimiter value, the bit non-inversion counter value, and the bit inversion counter value to generate a training pattern frame (step S1).

  The training pattern frame synthesis unit 14 outputs the generated training pattern frame to the selection unit 15, and the selection unit 15 inserts the training pattern frame into the transmission side parallel signal (data) of each lane (step S2). The data in which the training pattern frame is inserted is received via the FIFO unit 16, the serializer unit 3, and the deserializer unit 4 after being multiplied by the aforementioned skew, and the storage unit 17 is synchronized with each lane. The received data is stored as received capture data (step S3).

  For this received capture data stored in the storage unit 17, the delimiter detection unit 18 detects a delimiter value in the training pattern frame, and determines the frame phase based on the position of the detected delimiter value (step S4). ). Next, the counter reproducing unit 19 reproduces the corresponding training pattern frame number from the counter values (bit non-inverted counter value, bit inverted counter value) taken in a divided manner based on the frame phase (step S5). Next, the skew estimation unit 20 estimates the skew amount for each lane based on the frame phase and the regenerated training pattern frame number (step S6). Then, the deskew control unit 21 performs control (deskew) to cancel the skew between the lanes based on the skew amount for each lane (step S7). Thereby, the deskew control unit 21 cancels the influence of the skew in the adjustment circuit such as the FIFO unit 16 and the barrel shifter unit 22 that can shift the data demultiplexing phase on the parallel side of the serializer unit 3 and the deserializer unit 4. It can be set appropriately. As a result, the data phase between the lanes can be synchronized.

  Next, a training pattern frame used in the present embodiment will be described. FIG. 4 is a diagram illustrating a configuration example of a training pattern frame in the present embodiment. In the training pattern frame, the 2-byte values 0xF6 and 0x28 are placed as delimiter values indicating the head, followed by the 1-byte bit inversion counter value and the 1-byte bit non-inversion counter value corresponding to the frame number (i). Yes. The training pattern frame with the frame number (i) is followed by the training pattern frame with the frame number (i + 1). After the frame number reaches the final value, it returns to the initial value, and is incremented cyclically thereafter.

  Here, as a series of non-inverted counter values, an arbitrary series of 1-byte values can be selected, which may be a simple binary sequence from 0x00 to 0xFF, a short binary sequence from 0x01 to 0x0A, or gray Any code can be selected as long as it is a sequence in which the corresponding frame numbers (i) are determined for all counter values. The bit inversion counter value is usually sufficient by simply inverting the bit non-inversion counter value literally in bit units. However, the bit order may be changed, and the bit inversion counter value and the bit non-inversion counter may be reversed. The arrangement of values may be exchanged. The delimiter value is not limited to 0xF6 and 0x28, and an appropriate value can be selected. The bit lengths of the delimiter value, the bit inversion counter value, and the bit non-inversion counter value are also required such as an assumed skew amount. It is possible to design with an appropriate value according to the requirement.

  FIG. 5 is a diagram illustrating an example of received capture data of a training pattern frame. For each lane, the fact that a 4 byte long training pattern frame sequence is captured at an arbitrary data phase is divided into the following three cases with respect to the received capture data length of 4 bytes.

  (1) Case 1 is a case where the bit inversion counter value and the non-inversion counter value of the target training pattern frame (i) are captured without being divided, but the delimiter value is divided and captured with respect to the received capture data. is there.

  (2) As Case 2, although the bit non-inversion counter value of the target training pattern frame (i) and the delimiter value of the subsequent training pattern frame (i + 1) are captured without being divided with respect to the received capture data, bit inversion The counter value is divided and taken in.

  (3) As Case 3, although the delimiter value and bit inversion counter value of the training pattern frame (i + 1) subsequent to the training pattern frame (i) of interest are captured without being divided with respect to the received capture data, bit non-inversion The counter value is divided and taken in.

  The case where the delimiter value, the bit inversion counter value, and the bit non-inversion counter value of the subsequent training pattern frame (i + 1) are captured without being divided (Case 3 ') is the same as in Case 3.

  FIG. 6 is a diagram illustrating a delimiter value detection method in the delimiter detection unit 18. When two 4-byte received capture data are arranged side by side for each lane and collated with the 2-byte delimiter value in order from the left side of the figure captured earlier in time, whether or not the delimiter value is divided in the received capture data. It is shown that there is a bit sequence that matches the delimiter value. The delimiter detection unit 18 can determine the frame phase of the training pattern frame sequence captured as received capture data based on the position of the bit sequence that coincides with the first (left side) of the bit sequence.

Thus, although the bit inversion counter value and the non-inverting counter value of the target training pattern frame (i) is incorporated without being interrupted, if the delimiter value captured is divided (Case1) is bit reversal counter value it can correspond to a bit reversed allowed by training pattern frame number of training pattern frame of interest (i).

When the bit non-inverted counter value of the training pattern frame (i) and the delimiter value of the subsequent training pattern frame (i + 1) are captured without being divided, but the bit inverted counter value is captured after being divided (Case 2). ) Can correspond to the training pattern frame number (i) of the training pattern frame in which the bit non-inverting counter value is directly focused.

When the delimiter value and the bit inversion counter value of the training pattern frame (i + 1) following the training pattern frame (i) of interest are captured without being divided, but the bit non-inversion counter value is divided and captured (Case 3) ), by obtaining a training pattern frame (i + 1) bit training pattern frame number before one more belt rate training pattern frame number to correspond to the counter value and the reversal counter value by bit-inversion, and the focused training pattern The frame training pattern frame number (i) can be obtained.

  In the delimiter detection unit 18, in order to simplify the processing circuit, the bit inversion counter value and the non-inversion counter value of the training pattern frame (i) are taken in without being divided, but the delimiter value is taken in by being divided. Also in (Case 1), the bit non-inverted counter value of the target training pattern frame (i) and the delimiter value of the subsequent training pattern frame (i + 1) are captured without being divided, but the bit inverted counter value is divided and captured. As in the case (Case 2), the training pattern frame number (i) of the training pattern frame of interest may be obtained from the bit non-inverting counter value.

  As described above, in the present embodiment, in the received capture data captured in a state in which the training pattern frame structure composed of the delimiter value and the counter value is divided in the preceding and following frames, the delimiter value is detected and the frame phase is determined. The training pattern frame number (i) is reproduced from the frame phase and the skew amount is estimated. Thereby, even in a configuration including only a simple storage unit 17 having a small circuit scale for a long skew amount, the skew amount can be estimated, and a deskew setting for appropriately canceling the skew can be performed. As a result, the data phase between the lanes can be synchronized.

  Further, since the number of bits of the total counter value “0” and “1” becomes equal by the combination of the bit non-inverted counter value and the bit inverted counter value, as shown in the present embodiment, “0” and “1” By selecting a delimiter value with the same number of bits, the number of bits of “0” and “1” becomes equal in each training pattern frame, and the DC balance of the serial transmission signal in each lane is kept at an optimal value. Therefore, it can cope with a serial transmission line using an AC coupling circuit or the like. In the delimiter value, the same effect can be obtained even when the total number of bits of “0” and “1” is different by one.

  In addition, since the detection of the delimiter value can be avoided by combining the bit non-inversion counter value and the bit inversion counter value, a skew amount determination algorithm having a complicated and probabilistic convergence uncertainty including retry control is provided. It is not necessary, and a large skew amount can be uniquely determined with a simple and small circuit.

Embodiment 2. FIG.
FIG. 7 is a diagram illustrating a configuration example of a digital transmission system according to the application of the present embodiment. This corresponds to FIG. 1 in the first embodiment. The digital transmission system includes a separation unit 1, a FIFO unit 2, a serializer unit 3, two deserializer units 4, two barrel shifter units 22 a, and two multiplexing units 5.

  In FIG. 7, a serial transmission path corresponding to one serializer unit 3 is branched, and the serial signal is separately received by a plurality of deserializer units 4. Even in such a case, the skew amount can be estimated by applying the data phase synchronization apparatus by the same method as in the first embodiment. Specifically, as in FIG. 2, the delimiter generation unit 11, the bit inversion unit 12, the counter generation unit 13, the training pattern frame synthesis unit 14, the selection unit 15, the storage unit 17, and the delimiter detection unit 18. A counter reproduction unit 19, a skew estimation unit 20, a deskew control unit 21, a FIFO unit 16 instead of the FIFO unit 2, and two barrel shifter units 22 instead of the two barrel shifter units 22a And

  Here, the effect of the deskew setting in the deskew control unit 21 works in common on the branched lanes in the FIFO unit 16, while the effect of the barrel shifter unit 22 works independently on the branched lanes. Therefore, the circuit scale of the FIFO unit 16 is secured to the extent corresponding to the skew amount derived from the branch source such as the serializer unit 3, and the circuit scale of the barrel shifter unit 22 is suppressed to the extent corresponding to the skew amount after the branch such as the deserializer unit 4. As a result, the circuit scale of the entire system can be reduced.

  As described above, the data phase synchronization apparatus according to the present invention is useful for a digital transmission system, and is particularly suitable when signals are communicated in parallel.

DESCRIPTION OF SYMBOLS 1 Separation part 2 FIFO part 3 Serializer part 4 Deserializer part 5 Multiplex part 11 Delimiter generation part 12 Bit inversion part 13 Counter generation part 14 Training pattern frame synthesis part 15 Selection part 16 FIFO part 17 Storage part 18 Delimiter detection part 19 Counter reproduction part 20 Skew estimation unit 21 Deskew control unit 22, 22a Barrel shifter unit

Claims (10)

In parallel signal communication for data communication in parallel using a plurality of lanes, a data phase synchronization apparatus for synchronizing data phase between the lanes,
Training pattern frame synthesizing means for generating a training pattern frame including a delimiter value indicating a boundary of the training pattern frame and a counter value corresponding to the training pattern frame number;
Selection means to insert the data sent to the training pattern frame to the plurality of lanes,
Detects the delimiter value from the training pattern frame which is inserted into the data received are transmitted by said plurality of lanes, the delimiter determines the received data frame phase indicating the position of the detected delimiter value Detection means;
Based on the frame phase of each of the received data of the plurality of lanes, the counter value included in the training pattern frame inserted into the received data is captured and corresponds to the captured counter value Counter reproduction means for reproducing the training pattern frame number;
Skew estimation means for estimating a skew amount between the plurality of lanes based on the frame phase and the regenerated training pattern frame number;
A deskew control means for performing control to cancel the skew between the plurality of lanes based on the skew amount between the plurality of lanes estimated by the skew estimation means ;
Phase adjusting means for performing processing for canceling skew in the plurality of lanes based on control of the deskew control means;
A data phase synchronization apparatus comprising: The delimiter detection means includes a capture including at least a part of the training pattern frame inserted by the selection means and the training pattern frame inserted after the training pattern frame, which is captured from the received data. Detecting the delimiter value from the data;
  The data phase synchronizer according to claim 1.   The selecting means continuously inserts a plurality of training pattern frames each including the counter value corresponding to the training pattern frame number that changes in units of a predetermined value into the transmitted data.
  3. The data phase synchronization apparatus according to claim 1, wherein the data phase synchronization apparatus is a data phase synchronization apparatus. The training pattern frame synthesis means, delimiter value, the counter value corresponding to the training pattern frame number, and generates a training pattern frame including an anti Utateka counter value which has been subjected to bit inversion with respect to the counter value,
The counter reproducing means reproduces the training pattern frame number from the counter value or the inverted counter value included in the training pattern frame;
The data phase synchronization apparatus according to any one of claims 1 to 3, wherein Said phase adjusting means, arranged in front and rear stage of said plurality of lanes,
The data phase synchronization apparatus according to claim 1 , wherein the data phase synchronization apparatus is a data phase synchronization apparatus. If the previous sharp over emissions is more to the branch,
Comprising the phase adjusting means arranged at the subsequent stage of each of the branched lanes ,
The data phase synchronization apparatus according to claim 1 , wherein the data phase synchronization apparatus is a data phase synchronization apparatus. In parallel signal communication for data communication in parallel using a plurality of lanes, a data phase synchronization method for synchronizing data phase between the lanes,
A training pattern frame synthesizing step for generating a training pattern frame including a delimiter value indicating a boundary of the training pattern frame and a counter value corresponding to the training pattern frame number;
A training pattern frame insertion step to insert the data sent to the training pattern frame to the plurality of lanes,
Detects the delimiter value from the training pattern frame which is inserted into the data received are transmitted by said plurality of lanes, determines the frame phase of the data the reception of each indicated by the position of the detected delimiter value A delimiter value detection step to perform,
A counter value reproduction step of capturing the counter value included in the training pattern frame inserted into the received data based on the frame phase and reproducing the training pattern frame number corresponding to the captured counter value ;
A skew estimation step of estimating a skew amount between the plurality of lanes based on the frame phase and the regenerated training pattern frame number;
A deskew step for performing a process of canceling the skew between the plurality of lanes based on the skew amount between the plurality of lanes estimated in the skew estimation step ;
A data phase synchronization method comprising:   In the delimiter value detection step, a part of the training pattern frame inserted in the training pattern frame insertion step and the training pattern frame inserted after the training pattern frame, captured from the received data, Detecting the delimiter value from capture data including
  The data phase synchronization method according to claim 7, wherein:   In the training pattern frame insertion step, a plurality of training pattern frames each including the counter value corresponding to the training pattern frame number that changes in units of a predetermined value is continuously inserted into the transmitted data.
  9. The data phase synchronization method according to claim 7, wherein the data phase synchronization method is a data phase synchronization method. In the deskew step, it performs processing for canceling the skew with respect to at least one of the data after being received from the data you and the plurality of lanes before being transmitted to the plurality of lanes,
The data phase synchronization method according to any one of claims 7 to 9, wherein the data phase synchronization method is performed.

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