JP5664053B2 - Satellite signal receiver - Google Patents

Description

  The present invention relates to a satellite signal receiving apparatus that receives radio waves from a positioning satellite.

  Mobile phones that use GNSS (Global Navigation Satellite System), such as GPS (Global Positioning System), to acquire time information and position information by receiving radio waves from positioning satellites and decoding satellite signals. There are terminal devices. For example, by acquiring time information transmitted from each positioning satellite (GPS satellite) used in GPS, the current time data of the mobile terminal device can be set or corrected. Also, the current position of the mobile terminal device can be calculated by receiving radio waves from at least four of the GPS satellites and acquiring time information and orbit information of the GPS satellites.

  The frequencies of radio waves transmitted from these GPS satellites are the same. However, the radio waves transmitted from the GPS satellites are received at a frequency deviating from the transmission frequency due to the Doppler effect as each GPS satellite moves at high speed in orbit. The satellite signal from each GPS satellite is determined for each GPS satellite, and is transmitted after being phase-modulated (spread spectrum) with a spreading code (pseudorandom noise code) generated in synchronization with the time of each GPS satellite. Has been. Therefore, when receiving a radio wave from any GPS satellite using a mobile terminal device that does not have GPS satellite orbit information or user position information in advance, first search for a GPS satellite that can receive the radio wave and a reception frequency. Then, it is necessary to perform acquisition processing for phase-synchronizing the despreading code (a pseudo-random noise code identical to the spreading code) for demodulating the satellite signal from the GPS satellite and the spreading code of the received satellite signal.

  In this acquisition process, the amount of change of the reception frequency from the transmission frequency, the pattern of the pseudo random noise code corresponding to the identification number of the GPS satellite, and the reception parameter consisting of the phase of the pseudo random noise code are changed, respectively. The code signal is generated in combination. Then, a satellite radio wave is detected by obtaining a correlation value between the generated code signal and the received radio wave signal. In such processing, the amount of calculation is very large, and therefore a long processing time is required. Therefore, conventionally, a technique has been developed that shortens the search time by using many correlators for obtaining correlation values and performing parallel processing in parallel (for example, Patent Document 1).

JP 2000-266834 A

  However, if many arithmetic processes are performed simultaneously in parallel, a large amount of power is consumed at once in the satellite signal receiving apparatus, and a large current flows. Therefore, in order to operate stably and at high speed, there has been a problem that attention must be paid to the power supply design such as mounting a large battery or capacitor capable of passing a temporary large current in the receiving device.

  An object of the present invention is to provide a satellite signal receiver capable of performing stable and high-speed reception processing without imposing an excessive burden on the power supply.

The present invention
In a satellite signal receiving device that acquires a satellite signal transmitted from a positioning satellite,
Receiving means for receiving radio waves in a frequency band transmitted by the positioning satellite;
Storage means for storing received data for a predetermined period based on radio waves received by the receiving means;
Detecting means for detecting the satellite signal from the received data stored in the storage means;
The data output processing speed from the storage means to the detection means and the detection processing speed by the detection means based on the received data output from the storage means are controlled, and the data output processing speed and the detection processing speed are A clock control means configured to be synchronized and capable of being reduced from a predetermined processing speed;
The received data received with the receiving means in the operating state is stored in the storage means, and then the receiving means is inactivated and the received data stored in the storage means is read and output to the detecting means. Receiving operation control means,
When the satellite signal is detected, the receiving unit is set in an operating state to track the satellite signal. On the other hand, when the satellite signal is not detected, the receiving unit is left in a non-operating state. Control means for terminating the receiving operation;
It is characterized by having.

  According to the present invention, the satellite signal receiving device includes a storage unit that stores a radio signal input from a satellite and a detection unit that detects a satellite signal, and when the detection process is performed by the detection unit, Since it is equipped with clock control means that can reduce the data output processing speed from the storage means to the detection means and the detection processing speed at the detection means to reduce from a predetermined processing speed, it is impossible for the power supply There is an effect that stable and high-speed reception processing can be performed without imposing a burden.

It is a block diagram which shows the internal structure of the electronic timepiece which is embodiment of this invention. It is a figure which shows the structure of the correlator used for a capture circuit. It is a figure which shows the structure of the correlator used for a tracking circuit. It is a flowchart which shows the control procedure of the reception process of a GPS electromagnetic wave. It is a flowchart which shows the control procedure of the capture process of a GPS electromagnetic wave.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an internal configuration of an electronic timepiece when a satellite signal receiving apparatus according to an embodiment of the present invention is applied to the electronic timepiece.

  The electronic timepiece 1 is a timepiece that can receive time information and current position information by receiving radio waves from GPS satellites, and correct current time data based on the acquired time information.

  The electronic timepiece 1 includes an antenna 11, an RF reception unit 12 as a reception unit, a memory unit 13 as a storage unit, a selector 14, a signal detection unit 15, a decoder 18, a clock supply circuit 19, and a reception operation. A CPU (Central Processing Unit) 20, a RAM (Random Access Memory) 21, a ROM (Read Only Memory) 22, a display unit 23, a timer unit 24, a power supply unit 25, and a current value measuring unit The current detection unit 26 is provided. Here, the clock supply circuit 19 and the CPU 20 constitute clock control means.

  The antenna 11 is a small antenna configured to be able to receive a 1.57542 GHz band radio wave transmitted from a GPS satellite, and is, for example, a patch antenna.

  The RF receiving unit 12 is composed of, for example, one integrated circuit, and an amplification circuit (LNA) that amplifies a reception signal related to a radio wave received by the antenna 11 or a signal component other than the frequency band of the satellite signal from the reception signal. A bandpass filter (BPF) to be removed, a mixer circuit that mixes local oscillation signals and converts the received signal into an intermediate frequency band signal, and an analog-to-digital conversion that digitally converts the intermediate frequency analog signal at a predetermined sampling frequency Equipment (ADC) and the like. The BPF has a pass bandwidth of, for example, several MHz, and this pass bandwidth is sufficiently wider than the change width of the reception frequency (about ± 10 KHz) due to the Doppler effect. The converted intermediate frequency is about several MHz. Note that the output voltage can be binarized using, for example, a limiter or a comparator instead of the ADC.

  The RF receiver 12 can be switched based on a power control signal from the CPU 20 such as performing a reception operation when the power is turned on or stopping a reception operation when the power is turned off. . While the power is turned off by the power control signal, the current consumption in the RF receiver 12 can be kept very small. Alternatively, the current consumption may be suppressed by stopping the supply of the amplified voltage to the LNA and the supply of the sample operation clock to the ADC so as to be in a non-operation state.

  The memory unit 13 includes a RAM 13b that stores data, a memory controller 13a that controls the address, speed, and timing of writing and reading data to and from the RAM 13b.

  The RAM 13b temporarily accumulates time-series data of a predetermined time used when executing a capturing process for searching for a satellite signal from received data, and a digital signal output from the RF receiver 12 is, for example, It has a capacity capable of storing 10 milliseconds.

  In response to the operation control signal from the CPU 20, the memory controller 13a takes the digital signal output from the RF receiver 12 and writes it to the RAM 13b in time series order, or reads this data in time series order and outputs it to the selector 14 side. Or

  The memory unit 13 operates in response to an operation clock from the clock supply circuit 19, and the operation of the memory unit 13 is also stopped when the operation clock is stopped. In addition, the speed at which data is read from the RAM 13b can be lowered by lowering the operation clock from the initially set clock frequency. The clock frequency that can be reduced is, for example, 1/2 or 1/4 of the initially set clock frequency. Note that the clock frequency may be initialized so that it can be operated at a higher speed than the initial setting state.

  The selector 14 switches the input source of the signal to be sent to the signal detection unit 15 between the RF reception unit 12 or the memory unit 13 based on the selection control signal from the CPU 20.

  The signal detection unit 15 includes a capture circuit (detection means) 16 that searches and detects satellite signals while changing reception parameters, and a tracking circuit (tracking means) 17 that demodulates while tracking the detected satellite signals. ing. The acquisition circuit 16 obtains a correlation value between a code signal generated using a pseudo random noise code (for example, a C / A code) of each GPS satellite and a reception signal related to the received radio wave, and a correlation value equal to or greater than a certain value is obtained. Obtain the setting of the obtained reception parameter. At this time, the acquisition circuit 16 changes the frequency of the satellite signal to be detected as a reception parameter, the pseudo random noise code used to generate the code signal, and the phase difference between the generated code signal and the reception signal, Correlation values are calculated for all combinations within a predetermined range. The tracking circuit 17 performs despreading processing on the satellite signal detected by the acquisition circuit 16 while appropriately adjusting the frequency and phase difference, and demodulates the satellite signal. The internal configuration of these capture circuit 16 and tracking circuit 17 and the principle of search and tracking will be described in detail later.

  The capture circuit 16 and the tracking circuit 17 operate by receiving an operation clock independently from the clock supply circuit 19, and the operation of the circuit is stopped by stopping the supply of the operation clock.

  The clock supply circuit 19 includes an oscillation circuit that oscillates and outputs a signal having a predetermined frequency, and a frequency dividing circuit that divides the oscillation frequency of the oscillation circuit. The clock supply circuit 19 supplies an operation clock to designated parts of the memory unit 13 and the signal detection unit 15 in accordance with a switching control signal from the CPU 20. Further, the frequency of the operation clock supplied to the memory controller 13a and the capture circuit 16 can be lowered from the initial set frequency by a clock switching control signal from the CPU 20.

  The decoder 18 decodes the navigation message from the satellite signal demodulated by the tracking circuit 17. The decoded navigation message is decoded by the CPU 20 to obtain time data and orbit information.

  The current detection unit 26 measures a current value supplied from the power supply unit 25 when each unit of the electronic timepiece 1 operates, and outputs the measured value to the CPU 20. The current detection unit 26 may calculate power consumption and output it to the CPU 20.

  In the ROM 22, as a control program executed by the CPU 20, a time display process for causing the display unit 23 to display the time corresponding to the time measurement data by updating the display content of the display unit 23 in synchronization with the time measurement data of the time measurement unit 24. Program, a reception control process for receiving a satellite signal from a GPS satellite at a predetermined timing to acquire time information and correcting the time measured by the time measuring unit 24 based on the time information, a program for a time correction process, etc. Is stored.

  The RAM 21 provides a working memory space to the CPU 20 and stores temporary data such as a reception history from a GPS satellite.

  Next, a satellite signal detection and tracking method in the electronic timepiece 1 having the above configuration will be described.

  In a satellite signal transmitted from each GPS satellite, information is represented by a navigation message in which 1-bit code data having a length of 20 ms is arranged in a predetermined format. This navigation message is phase-modulated with a carrier signal having a transmission frequency, and is subjected to spread spectrum (phase modulation) with a pseudo-random noise signal and transmitted. Among the transmission frequencies used by GPS, pseudo-random noise codes used in L1 band transmission radio waves include C / A codes and P (Y) codes. Among these, the publicly available C / A code is 1023 1-bit code data (chips) transmitted at 1023 kHz arranged in a predetermined order, that is, one cycle of the C / A code is 1 ms. This C / A code is repeated 20 cycles for each piece of code data indicating a navigation message. Further, the length of one C / A code chip is 1540 periods of the carrier signal.

  On the other hand, each GPS satellite moves at high speed in orbit. Therefore, the radio wave transmitted at 1.57542 GHz is received at a frequency slightly different from the transmission frequency due to the Doppler effect based on the relative speed with the electronic timepiece 1. Therefore, when the satellite signal is demodulated by the acquisition circuit 16 or the tracking circuit 17, the frequency of the intermediate frequency carrier wave output from the local oscillator in the signal detection unit 15 and mixed with the intermediate frequency signal is finely controlled (for example, The reception frequency is adjusted by a range of ± 15 kHz in 100 Hz steps.

  In the C / A code, a unique code array is set for each GPS satellite. A satellite signal spread by a certain C / A code is demodulated by a waveform signal of the same phase by the same C / A code, while other satellite signals are further spread spectrum, so that no interference occurs. Only the target satellite signal can be acquired. Therefore, by checking whether the satellite signal from the GPS satellite according to the C / A code is detected while changing the reception frequency, the C / A code, and the phase of the C / A code, Searches for radio waves from GPS satellites that can be received when the above conditions match.

  FIG. 2 is a diagram showing the configuration of the matched filter used in the acquisition circuit 16. FIG. 3 is a diagram showing the configuration of the sliding correlator used in the tracking circuit 17.

  As shown in FIG. 2, in the matched filter in the electronic timepiece 1 of the present embodiment, for example, a shift register in which 1023 D flip-flops are connected in series is used. To this shift register, 1023 pieces of received data sampled at 1023 kHz are sequentially input and shifted. On the other hand, the C / A code generator generates 1023 pieces of code data for one C / A code period. Then, the value held by each D flip-flop of the shift register and the value of the in-phase code data generated by the C / A code generator are respectively multiplied by the multiplier. Outputs from these multipliers are accumulated by an adder, and the accumulated value is output as a correlation value. Further, by adding the input signal to the shift register one chip at a time, shifting the phase and calculating the correlation value for each phase, the correlation value for all phases of one C / A code period Is required. A plurality of matched filters may be provided so that detection processing can be simultaneously performed on each C / A code corresponding to a plurality of GPS satellites.

  As shown in FIG. 3, in the sliding correlator, received signals are input in order one chip at a time, and signals are sequentially output from the C / A code generator one chip at a time, and both are sequentially multiplied. The multiplied value is further added to the accumulated value of the previous multiplication results and held. By repeating this operation 1023 times, a correlation value for one phase of one C / A code is calculated. Note that the sliding correlator is provided with, for example, two sliding correlators that can generate and input a C / A code having a phase difference within one chip before and after each sliding correlator. Therefore, it is possible to detect the phase synchronization point more efficiently. Alternatively, more sliding correlators can be provided.

As described above, in the matched filter, the total calculation time for all phases in one C / A code is dramatically shortened. However, by simultaneously operating a plurality of D flip-flops and multipliers, power consumed at a time Increase (eg, 10 ³ to 10 ⁶ ). On the other hand, in the sliding correlator, only one arithmetic unit operates at a time and the power consumed at a time can be kept low, but the number of repetitive calculations increases and the total calculation time becomes long. Therefore, in the electronic timepiece 1 of the present embodiment, the matched filter is used for the acquisition circuit 16 having a large amount of calculation, and the sliding correlator is used for the tracking circuit 17.

  Next, time data acquisition and correction processing using GPS in the electronic timepiece 1 will be described using a flowchart.

  FIG. 4 is a flowchart showing a control procedure by the CPU 20 of the time data acquisition process. FIG. 5 is a flowchart showing a capture processing subroutine called during the time data acquisition processing.

  This time data acquisition process is a process that is automatically started by calling an execution program from the ROM 22 at a predetermined time every day, for example.

  When the time data acquisition process is started, first, as shown in FIG. 4, the CPU 20 sends a power control signal to the RF receiving unit 12 to turn on the power of the RF receiving unit 12 to start radio wave reception. The CPU 20 accumulates and stores received data in the RAM 13b (step S1). Specifically, the CPU 20 sends an output switching control signal to the clock supply circuit 19 to supply an operation clock to the RF receiver 12, and receives received data based on radio waves received in real time by the RF receiver 12 by predetermined sampling. Digitally convert by frequency and output. Further, the CPU 20 causes the clock supply circuit 19 to output to the memory unit 13 an operating frequency clock signal for the RAM 13 b to acquire the digitally converted received data output from the RF receiving unit 12 at the same sampling frequency. Then, the CPU 20 sends an operation control signal to the memory controller 13a, and stores the reception data output from the RF receiver 12 in the RAM 13b. At this stage, the CPU 20 does not operate the signal detection unit 15 by the output switching control signal to the clock supply circuit 19.

  Next, the CPU 20 determines whether or not reception data for a capacity that can be stored in the RAM 13b has been acquired (step S2). If it is determined that the reception data for a predetermined time (for example, 10 ms) has not yet been stored in the RAM 13b and the RAM 13b is not full, the CPU 20 returns to step S1 and continues the reception data acquisition process. To do. When it is determined that the data for 10 ms is accumulated and the RAM 13b is full, the processing of the CPU 20 proceeds to step S3.

  Subsequently, the CPU 20 sends a power control signal to the RF receiver 12 to turn off the power of the RF receiver 12. In addition, the CPU 20 sends a selection control signal to the selector 14 to set the data input source in the memory unit 13. Then, the CPU 20 causes the capturing circuit 16 to perform a capturing process to be described later (step S3). The CPU 20 searches for a radio wave from any of the GPS satellites in this capturing process. Then, the CPU 20 determines whether or not the radio wave from the GPS satellite has been detected in the capturing process, that is, whether or not the GPS satellite has been discovered (step S4). When the radio wave from the GPS satellite is not detected and it is determined that the GPS satellite has not been found, the process of the CPU 20 proceeds to step S9 and stops the GPS reception operation performed in the capture process.

  On the other hand, when the radio wave from the GPS satellite is detected in the discrimination process in step S4 and it is discriminated that the GPS satellite is found, the CPU 20 subsequently sends a power control signal to the RF receiver 12 to receive the RF. The power of the unit 12 is turned on, and radio wave reception is resumed. In addition, the CPU 20 sends a selection control signal to the selector 14 to allow the reception data sent from the RF receiver 12 to pass and input it to the tracking circuit 17.

  The CPU 20 performs a process of identifying the phase synchronization point with the pseudo random noise code from the received signal related to the detected radio wave from the GPS satellite (step S5). At this time, the CPU 20 uses the setting of the satellite number and reception frequency of the GPS satellite from which the radio wave is detected based on the result of the capturing process. When the phase synchronization point with the pseudo-random noise code is detected, the CPU 20 causes the tracking circuit 17 to track the phase synchronization point and input the demodulated data to the decoder 18, and the decoder 18 decodes the navigation message. (Step S6). In addition, the CPU 20 acquires the decoded navigation message data.

  Then, the CPU 20 determines whether or not data necessary for calculating the current time is acquired from the navigation message decoded by the decoder 18 (step S7). If it is determined that necessary data has not yet been acquired, the process returns to step S6, and the CPU 20 continues decoding the navigation message by the decoder 18 to acquire the decoded navigation message data. If it is determined that the data necessary for calculating the current time has been acquired, the CPU 20 calculates the current time based on the acquired data and corrects the time data of the time measuring unit 24 (step S8). Further, the time displayed on the display unit 23 is updated based on the time data of the time measuring unit 24. And the process of CPU20 transfers to step S9. The CPU 20 sends a power control signal to the RF receiver 12 to turn off the power of the RF receiver 12, and also causes the clock supply circuit 19 to stop supplying the operation clock to the tracking circuit 17 so that the GPS reception operation is performed. finish.

  When the GPS reception operation ends in the process of step S9, the CPU 20 waits until the same time on the next day (step S10). Alternatively, if it is determined in step S4 that the radio wave from the GPS satellite cannot be detected, the CPU 20 may restart the time data acquisition process again after one hour, for example.

  Next, details of the capturing process in step S3 will be described.

  As shown in FIG. 5, when proceeding to the acquisition process, first, the CPU 20 initializes the carrier frequency to be detected (step S21). Specifically, the CPU 20 resets a variable indicating the carrier frequency stored in the RAM 21 and obtains an initial value from, for example, a table stored in the ROM 22. Then, the CPU 20 sets the acquired value as a variable (step S22).

  Next, the CPU 20 initializes the satellite number (step S23). Specifically, the CPU 20 resets a variable indicating the satellite number of the detection target stored in the RAM 21 and acquires an initial value from, for example, a table stored in the ROM 22. Then, the CPU 20 sets the acquired initial value as a variable indicating the satellite number, and the C / A code generated by the C / A code generator of the acquisition circuit 16 based on the variable indicating the set satellite number. Is set (step S24).

  The CPU 20 resets the address of the received data read from the memory unit 13 stored in the RAM 21 (step S25). Next, the CPU 20 sets the operation clock frequency for performing the data reading operation from the RAM 13b and the operation of the capturing circuit 16 based on the measurement value of the current detection unit 26 (step S26). Here, the set operation clock frequency is larger than the speed at which reception data is input from the RF receiver 12 in real time in the initial setting state. The operation clock frequency is decelerated as the measurement value by the current detection unit 26 increases, and the current supplied from the power supply unit 25 when the capture circuit 16 is operated can maintain a stable operation of the power supply unit 25. It is set not to exceed the value of.

  Then, the CPU 20 sends a clock switching control signal to the clock supply circuit 19 to perform switching so as to supply the clock signal at the set operation clock frequency. Further, the CPU 20 sends an output switching control signal to the clock supply circuit 19 to supply the operation clock signal of the switched frequency to the memory controller 13a and the capturing circuit 16. Then, the CPU 20 sends a selection control signal to the selector 14 to switch the input source to the memory unit 13 side.

  Further, the CPU 20 sends an operation control signal to the memory controller 13a to output data from the RAM 13b to the selector 14 side. The CPU 20 outputs a read address and a read command to the memory controller 13a, and sequentially stores received data read from the RAM 13b and input to the capture circuit 16 via the selector 14 in the shift register. Each time the received data stored in the shift register is shifted one by one, the CPU 20 generates a C / A code based on the setting and outputs it to each multiplier. And CPU20 acquires the output data from the capture circuit 16 which integrated the output of each multiplier as a correlation value (step S27). During these processes, the CPU 20 can change the operation clock frequency as needed by sending a clock switching control signal to the clock supply circuit 19 while monitoring the measurement data of the current detector 26.

  Then, the CPU 20 determines whether or not the reading of the received data from the RAM 13b has been completed (step S28). If it is determined that the reading of the received data has not been completed, the CPU 20 returns to step S27 to read the next data from the RAM 13b and input it to the capturing circuit 16, and obtains the calculated correlation value. . If it is determined that all data has been read, the CPU 20 advances to step S29.

  When the reading of all data from the RAM 13b is completed, the CPU 20 associates the acquired correlation value data with the satellite number, the carrier frequency, and the phase information of the C / A code, and stores it in the RAM 21, for example (step S29). At this time, all the acquired correlation values can be stored, or only the maximum value can be stored. Further, for example, correlation values for 10 C / A code periods may be acquired, and values obtained by integrating 10 correlation values for the same phase data array may be stored.

  Subsequently, the CPU 20 changes the set satellite number (step S30). For example, the CPU 20 reads a value indicating the next satellite number in the order set in the table of the ROM 22. Then, the CPU 20 determines whether or not all the satellite numbers have been set (step S31). For example, if it is determined that there is a variable that has not been read out among the variables indicating the satellite numbers in the table of the ROM 22 and the process of storing the correlation values for all the satellite numbers has not been completed, The process of the CPU 20 returns to step S24. CPU20 sets the value acquired by the process of step S30 as a variable value which shows a satellite number, and changes the production | generation pattern of the C / A code by a C / A code generator. And the process of step S24-S31 is repeated.

  On the other hand, if, for example, values indicating all satellite numbers have already been read from the table of the ROM 22 and it is determined that the process of storing correlation values for all satellite numbers has been completed, the processing of the CPU 20 Moves to step S32. Then, the CPU 20 acquires the next set value of the carrier frequency to be detected (step S32). Subsequently, the CPU 20 determines whether or not the acquisition process for all carrier frequencies has been completed (step S33). If it is determined that the acquisition process for all carrier frequencies has been completed, for example, if the next carrier frequency cannot be read or is outside the setting range, the acquisition process is terminated and the time data acquisition process is completed. Return. On the other hand, if it is determined that acquisition processing for all carrier frequencies has not yet been completed, the processing of the CPU 20 returns to step S22. And CPU20 repeats the process of step S22-S33.

  Then, all satellite numbers, carrier frequencies, and correlation values at each phase of the C / A code are acquired, and after the necessary values are stored, the process returns to the time acquisition / correction process, and the stored correlation values are By comparing with a predetermined threshold level, whether or not a radio wave from a GPS satellite is received, and the reception frequency and satellite number when received are acquired.

  In the above embodiment, it is determined whether or not the signal has been received after searching for all GPS satellites and reception frequencies. However, in the acquisition process, the correlation value acquisition process (step S27) in each GPS satellite is performed. It is possible to determine whether or not a satellite signal has been detected each time the process is completed, and end the acquisition process when a predetermined number of satellite signals are detected.

  In the above embodiment, the capture processing is controlled using the CPU 20, RAM 21, and ROM 22. However, the capture circuit 16 is provided with a separate data storage area and a calculation unit, and the capture circuit 16 independently performs the capture processing. It is good also as comprising so that can be performed.

  As described above, according to the electronic timepiece 1 of the embodiment of the present invention, the RAM 13b that stores the reception data related to the radio wave received by the RF receiver 12, and the radio wave from the GPS satellite based on the storage data of the RAM 13b. When detecting a radio wave from a GPS satellite using the capture circuit 16 that includes the capture circuit 16 to detect and has a power consumption that is significantly increased compared to the normal time, data output processing from the RAM 13b to the capture circuit 16 The power consumption can be controlled by keeping the detection processing speed in the speed and capture circuit 16 lower than a preset processable speed on the circuit. Therefore, detection processing can be performed at high speed while keeping the power supply circuit stable.

  In particular, when acquiring time information by receiving a radio wave from a GPS satellite with a portable terminal with limited power supply such as an electronic wristwatch, there is no need to arrange a large power source in a small device, Time information can be acquired stably only by software control.

  In addition, a current detection unit 26 is provided, and the current value supplied from the power supply unit 25 measured by the current detection unit 26 is supplied from the RAM 13b to the capture circuit 16 so as to be within a range that does not hinder the stable operation of the electronic timepiece 1. Since the data output processing speed and the detection processing speed in the capture circuit 16 can be reduced as appropriate, stable and high-speed detection processing can be performed without applying an excessive load to the power supply circuit of the electronic timepiece 1.

  In addition, a plurality of correlators are operated simultaneously in the acquisition circuit 16 and the tracking circuit 17 to calculate correlation values for C / A codes of a plurality of GPS satellites and calculation of correlation values for a plurality of phases of C / A codes. Since the clock frequency from the clock supply circuit 19 is not significantly changed, a high-speed and stable operation can be performed.

  Further, by using a matched filter for the acquisition circuit 16, radio waves from GPS satellites can be detected very efficiently, and the operation clock frequency supplied from the clock supply circuit 19 according to the power consumption of the matched filter can be set. By setting it to low speed, it is possible to stably perform high-speed radio wave detection processing. On the other hand, in the tracking circuit 17 that does not require a large amount of calculation at a time, a high-speed operation clock frequency is maintained without consuming an excessive amount of power by using a sliding correlator instead of the matched filter. The radio wave reception process from the GPS satellite can be continued.

  In particular, the power consumption digit changes due to the use of a matched filter, but fine power control with a factor of 2 to 4 becomes possible by controlling the clock frequency, so that efficient peak power control can be performed. .

  Further, while the data is output from the RAM 13b to the capture circuit 16, it is unnecessary because the power of the RF receiver 12 that does not need to receive data can be turned off by the power control signal from the CPU 20. Therefore, stable and high-speed processing can be performed without reducing the operation clock frequency of the capture circuit 16 more than necessary.

  The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the above-described embodiment, the range of decrease in the operation clock frequency is controlled based on the measurement result of the current detection unit 26. However, the measured current value is compared with a preset threshold value, and the threshold value is exceeded. When the current amount is supplied, the control may be performed in two steps such as lowering the operation clock frequency. Alternatively, when an electric power consumed in normal operation and an electric power consumed for capturing a radio wave from a GPS satellite are almost determined each time, such as an electronic timepiece, the current detection unit 26 is provided. Instead, it is also possible to preset the decrease width of the operating clock frequency based on the power consumption that is the reference.

  In the above embodiment, a matched filter is used for the acquisition circuit 16, but a large number of sliding correlators may be arranged in parallel. Alternatively, other correlators can be used.

  In the above-described embodiment, an electronic timepiece has been described as an example. However, a device on which the satellite signal receiving device of the present invention is mounted is not limited thereto. It can be used for various devices such as a PDA (Personal Digital Assistant), a portable communication terminal, a portable photographing device, and a recording device. In addition, the specific configuration and numerical values shown in the above embodiment can be changed as appropriate without departing from the spirit of the invention.

DESCRIPTION OF SYMBOLS 1 Electronic timepiece 11 Antenna 12 RF receiving part 13 Memory part 13a Memory controller 13b, 21 RAM
14 selector 15 signal detector 16 capture circuit 17 tracking circuit 18 decoder 19 clock supply circuit 20 CPU
22 ROM
23 Display Unit 24 Timing Unit 25 Power Supply Unit 26 Current Detection Unit

Claims (5)

In a satellite signal receiving device that acquires a satellite signal transmitted from a positioning satellite,
Receiving means for receiving radio waves in a frequency band transmitted by the positioning satellite;
Storage means for storing received data for a predetermined period based on radio waves received by the receiving means;
Detecting means for detecting the satellite signal from the received data stored in the storage means;
The data output processing speed from the storage means to the detection means and the detection processing speed by the detection means based on the received data output from the storage means are controlled, and the data output processing speed and the detection processing speed are A clock control means configured to be synchronized and capable of being reduced from a predetermined processing speed;
The received data received with the receiving means in the operating state is stored in the storage means, and then the receiving means is inactivated and the received data stored in the storage means is read and output to the detecting means. Receiving operation control means,
When the satellite signal is detected, the receiving unit is set in an operating state to track the satellite signal. On the other hand, when the satellite signal is not detected, the receiving unit is left in a non-operating state. Control means for terminating the receiving operation;
A satellite signal receiving apparatus comprising:   The satellite signal receiving apparatus according to claim 1, further comprising a determination unit configured to execute a control operation by the reception operation control unit and determine whether or not the satellite signal is detected by the detection unit. A power supply for supplying power;
Current value measuring means for measuring a current value supplied from the power supply unit;
With
The said clock control means controls the said data output processing speed and the said detection processing speed so that the electric current value measured by the said electric current value measurement means may be below a predetermined value. The satellite signal receiving device described. The detection means includes
A process of switching a plurality of reception parameters and searching for a combination in which a satellite signal is detected from among a combination of the plurality of reception parameters can be performed simultaneously on the plurality of combinations. The satellite signal receiving device according to any one of claims 1 to 3. Tracking means for continuously tracking the satellite signal detected by the detection means,
The detection means has a matched filter,
The satellite signal receiving apparatus according to claim 1, wherein the tracking unit includes a sliding correlator.

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