JP2001091625A - Gps receiving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption while receiving necessary signals out of navigation messages sent from a GPS satellite and ensuring necessary accuracy in a GPS receiving device suitable for portable use. SOLUTION: This GPS receiving device is provided with a GPS antenna 1; a frequency converting part 2 for converting the frequency of a GPS signal received by the GPS antenna 1; a bit selecting circuit 3 for receiving signals of plural bits outputted from the frequency converting part 2 and outputting signals of plural bits selected channel by channel; a correlator 4 for taking the correlation between the output from the bit selecting circuit 3 and dummy noise codes; and a central control device for computing a position upon receiving a signal from the correlator 4, and giving a command to the bit selecting circuit 3. A clock generating circuit for supplying a clock signal to the correlator 4, and a control circuit for controlling the clock generating circuit, are further provided, and clock frequency can be controlled by the central control device 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GPS receiver for receiving radio waves from a plurality of GPS satellites, measuring a radio wave arrival time between each of the GPS satellites and a receiving device, and obtaining the position and time of a receiving point. It concerns the device.

[0002]

2. Description of the Related Art A signal transmitted by a GPS satellite is phase-modulated with a pseudo noise code having a code different for each satellite.
The pseudo-noise code has a characteristic that when the same code is multiplied by the same phase, there is a correlation, but there is no correlation when a different code or the same code is out of phase by one chip or more. Therefore, if the received signal is multiplied by the pseudo noise code of the satellite to be received and the phase is shifted little by little, there is a correlation only when synchronization is achieved, and the amplitude of the demodulated signal increases. The navigation message included in the demodulated signal contains data such as satellite time and orbit,
Although 1500 bits constitute one frame at a bit rate of 50 bps, not all bits are always required.

[0003]

In recent years, many GPS receivers have been incorporated into application products for portable use. In products for mobile use, unlike GPS used for car navigation, a reduction in size and weight is desired, and a reduction in power consumption is required to enable long-term use. The present invention has been made in view of such circumstances, and has as its object to reduce power consumption by selecting and receiving only necessary bits from navigation messages sent from GPS satellites. Another object is to reduce the power consumption by reducing the clock frequency when accuracy may be low.

[0004]

SUMMARY OF THE INVENTION In the present invention, power consumption is reduced by adjusting the correlation accuracy between a GPS signal and a pseudo-noise code. In general, a GPS receiving system has a plurality of stages such as satellite acquisition and automatic tracking. A circuit called a channel is assigned to each satellite, and different stages of processing are usually performed for each channel. The correlation accuracy in each stage such as satellite acquisition and automatic tracking is different, that is, high accuracy is required in a certain stage, and not so high accuracy in a different stage. Therefore, the accuracy is adjusted for each stage, and the accuracy is lowered at a stage where the accuracy is not so high, and the operation of the circuit is stopped or the operating frequency is reduced to reduce the power consumption.

More specifically, according to the first aspect of the present invention, power consumption is reduced by reducing the number of signals supplied from the bit selection circuit to the channel section with good accuracy and stopping the operation of the corresponding circuit. According to the second aspect of the present invention, the power consumption is reduced by lowering the clock frequency supplied to the channel unit with low accuracy. According to the third aspect of the present invention, the power consumption is further reduced by combining the first and second aspects. Further, in the invention according to claim 4, each step such as satellite acquisition and automatic tracking is not grasped by the CPU, but is grasped by an instruction generation circuit provided separately from the CPU, and is used for bit selection and clock control. Command. As a result, the number of times of communication with the CPU is reduced, and power consumption is reduced.

[0006]

(Embodiment 1) FIG. 1 is a block diagram showing a first embodiment of the present invention. Reference numeral 1 denotes a GPS antenna which receives radio waves from a plurality of GPS satellites. Reference numeral 2 denotes an RF unit, which amplifies GPS signals from a plurality of GPS satellites received by the GPS antenna 1 at high frequencies, mixes local oscillation frequency signals, and outputs downconverted signals. Reference numeral 3 denotes a bit selection circuit that converts an n-bit signal output from the RF unit 2 into m bits for each channel,
Allocate the required number of bits, such as l bits. 4
Is a correlator that multiplies the input signal by the pseudo noise code and outputs a correlation signal. Reference numeral 5 denotes an interface unit, which accumulates a correlation signal output from the correlator 4 in an internal register and outputs it to the CPU 6 as necessary. Reference numeral 6 denotes a central control unit (CPU) which receives a signal from the correlator 4 to calculate a position and gives an instruction to the bit selection circuit 3. The CPU 6 monitors the correlation signal output from the correlator 4 and the code and phase of the pseudo-noise code used by the correlator 4 for the nine channels ch0 to ch8. The operation of the bit selection circuit 3 is controlled so that a signal of a necessary number of bits is supplied to each correlator 4 in accordance with the stage.

(Embodiment 2) FIG. 2 is a second embodiment of the present invention. Reference numeral 1 denotes a GPS antenna which receives radio waves from a plurality of GPS satellites. Reference numeral 2 denotes an RF unit which receives GPS signals from a plurality of GPS satellites received by the GPS antenna 1.
The signal is amplified at a high frequency, the local oscillation frequency signal is mixed and a down-converted signal is output. A correlator 4 multiplies the input signal by the pseudo noise code and outputs a correlation signal. Reference numeral 5 denotes an interface unit, which accumulates a correlation signal output from the correlator 4 in an internal register and outputs it to the CPU 6 as necessary. Reference numeral 7 denotes a clock generation circuit that supplies a clock signal to the correlator 4, and reference numeral 8 denotes a control circuit that controls the clock generation circuit 7. 6 is C
It is a PU that performs position calculation in response to a signal from the correlator 4 and also gives an instruction for clock control to the control circuit 8. The CPU 6 monitors the correlation signal output from the correlator 4 and the code and phase of the pseudo-noise code used by the correlator 4 for the nine channels ch0 to ch8. So that a clock of a required frequency is supplied to each correlator 4 according to the stage of
The operation of the control circuit 8 is controlled.

FIG. 3 shows a third embodiment of the present invention. Reference numeral 1 denotes a GPS antenna which receives radio waves from a plurality of GPS satellites. Reference numeral 2 denotes an RF unit which receives GPS signals from a plurality of GPS satellites received by the GPS antenna 1.
The signal is amplified at a high frequency, the local oscillation frequency signal is mixed and a down-converted signal is output. Reference numeral 3 denotes a bit selection circuit that allocates an n-bit signal output from the RF unit 2 to a required number of bits, such as m bits and 1 bit, for each channel. A correlator 4 multiplies the input signal by the pseudo noise code and outputs a correlation signal.
Reference numeral 5 denotes an interface unit, which accumulates a correlation signal output from the correlator 4 in an internal register.
Output to PU6. Reference numeral 7 denotes a clock generation circuit that supplies a clock signal to the correlator 4, and 8 denotes a clock generation circuit.
Control circuit. Reference numeral 6 denotes a CPU, which receives a signal from the correlator 4 to perform position calculation, gives an instruction for bit selection to the bit selection circuit 3, and gives an instruction for clock control to the control circuit 8. In CPU 6,
The correlation signals output by the correlator 4 and the code and phase of the pseudo-noise code used by the correlator 4 are monitored for the nine channels ch0 to ch8. Accordingly, the operation of the bit selection circuit 3 is controlled so that a signal having a required number of bits is supplied to each correlator 4, and the control circuit 8 is controlled so that a clock having a required frequency is supplied to each correlator 4. It controls the operation.

Since the correlator 4 is a multiplier for multiplying the input signal by the pseudo noise code, the operation speed can be increased by increasing the clock frequency. Therefore, the bit selection circuit 3 fetches n bits of the output signal from the RF unit 2 and stores it in the internal memory, stops the power supply to the RF unit 2, and stores the information of the internal memory for the necessary bits. Only at a high speed, the signals are read out and distributed to the correlators 4 and successively multiplied by different codes and pseudo-noise codes having different phases, whereby the time required for satellite acquisition can be reduced. However, once the satellite is captured and enters the automatic tracking stage, high-speed calculations are no longer necessary.
Therefore, the CPU 6 monitors the level of the correlation signal output from the correlator 4 of each channel, increases the clock frequency in the satellite acquisition stage to increase the speed of the correlation calculation, and in the automatic tracking stage, the clock frequency is increased. To reduce power consumption.

[0010] In the satellite acquisition stage, in the initial stage in which no correlation is obtained at all, the number of bits is reduced until a code or phase in which the level of the correlation signal becomes high is found, and the accuracy is improved. Since it may be low, the calculation time can be reduced, and as a result, the power consumption until the positioning can be performed can be reduced. Also, after the satellite code is determined, in the final stage of satellite acquisition for searching for the phase with the highest correlation, a large number of bits are allocated and highly accurate calculation is performed. After that, if you enter the automatic tracking stage,
The number of bits is allocated again to reduce power consumption. If the satellite is lost due to a break in radio waves during automatic tracking, the number of bits is re-allocated to search for the phase having the highest correlation. By performing such control for each channel, it is possible to perform a correlation operation at high speed and with required accuracy with low power consumption.

(Embodiment 4) FIG. 4 shows an embodiment 4 of the present invention. Reference numeral 1 denotes a GPS antenna which receives radio waves from a plurality of GPS satellites. Reference numeral 2 denotes an RF unit which receives GPS signals from a plurality of GPS satellites received by the GPS antenna 1.
The signal is amplified at a high frequency, the local oscillation frequency signal is mixed and a down-converted signal is output. Reference numeral 3 denotes a bit selection circuit that allocates an n-bit signal output from the RF unit 2 to a required number of bits, such as m bits and 1 bit, for each channel. A correlator 4 multiplies the input signal by the pseudo noise code and outputs a correlation signal.
Reference numeral 9 denotes an instruction generation circuit which monitors a correlation signal output from the correlator 4 of each channel and issues an instruction for bit selection to the bit selection circuit 3 according to the stage of each channel. Further, it issues an instruction for clock control to the control circuit 8. Reference numeral 7 denotes a clock generation circuit that supplies a clock signal to the correlator 4, and reference numeral 8 denotes a control circuit that controls the clock generation circuit 7. In this embodiment, the command generation circuit 9 grasps the stages of satellite acquisition, automatic tracking, and the like, and outputs only information necessary for positioning to the external CPU, so that the number of communications with the CPU having a separate chip configuration is reduced. Power consumption can be reduced.

[0012]

According to the present invention, as compared with the conventional system, unnecessary high precision can be omitted, and power consumption can be reduced by not operating the circuit or reducing the operating frequency.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a second embodiment.

FIG. 3 is a block circuit diagram showing a third embodiment.

FIG. 4 is a block circuit diagram showing a fourth embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 GPS antenna 2 RF part 3 Bit selection circuit 4 Correlator 5 Interface part 6 CPU 7 Clock generation circuit 8 Control circuit 9 Instruction generation circuit

Claims (4)

[Claims] 1. A GPS antenna, a frequency converter for frequency-converting a GPS signal received by the GPS antenna, and a multi-bit signal selected for each channel by using a multi-bit signal output from the frequency converter as an input , A correlator for correlating the output from the bit selection circuit with the pseudo-noise code, and a central controller for receiving the signal from the correlator, performing position calculation, and giving an instruction to the bit selection circuit G characterized by comprising
PS receiver. 2. A GPS antenna, a frequency converter for frequency-converting a GPS signal received by the GPS antenna, a correlator for correlating an output from the frequency converter with a pseudo-noise code, and a clock signal for the correlator. And a control circuit for controlling the clock generation circuit, and a central control unit for receiving a signal from the correlator and performing position calculation and giving a command to the control circuit. apparatus. 3. A GPS antenna, a frequency converter for frequency-converting a GPS signal received by the GPS antenna, and a multi-bit signal output from the frequency converter as an input and outputting a multi-bit signal for each channel. A bit selection circuit, a correlator for correlating the output from the bit selection circuit with the pseudo noise code, a clock generation circuit for supplying a clock signal to the correlator, a control circuit for controlling the clock generation circuit, And a central control unit for performing position calculation in response to the signal of (1) and giving instructions to a bit selection circuit and a control circuit. 4. The GPS receiver according to claim 1, wherein an instruction generation circuit for giving an instruction to the bit selection circuit or the control circuit is provided separately from the central control device.