JP5649867B2 - Semiconductor substrate, method for manufacturing the same, and method for manufacturing a laminated chip package - Google Patents

Description

The present invention relates to a semiconductor substrate for manufacturing a layered chip package including a plurality of stacked chips, a method for manufacturing the same, and a method for manufacturing a layered chip package .

  In recent years, electronic devices such as mobile phones and notebook personal computers are required to be lighter and have higher performance. Accordingly, there is a demand for higher integration of electronic components used in electronic devices. Also, high integration of electronic components is required for increasing the capacity of semiconductor memory devices.

  In recent years, a system in package (hereinafter referred to as “SIP”) has attracted attention as a highly integrated electronic component. SIP is a device in which LSIs are stacked and mounted in a single package. In recent years, SIP using a three-dimensional mounting technique in which a plurality of chips are stacked has attracted attention. As such SIP, a package having a plurality of stacked chips, that is, a stacked chip package is known. In addition to being able to achieve high integration, the layered chip package has the advantage that the circuit length can be shortened and the circuit operation speed can be increased and the stray capacitance of the wiring can be reduced. doing.

  As a three-dimensional mounting technique for manufacturing a layered chip package, a wire bonding method and a through electrode method are known. The wire bonding method is a method in which a plurality of chips are stacked on a substrate, and a plurality of electrodes formed on each chip and an external connection terminal formed on the substrate are connected by wire bonding. The through electrode method is a method in which a plurality of through electrodes are formed on each chip to be stacked, and wiring between the chips is performed by the through electrodes.

The wire bonding method has a problem that it is difficult to narrow the gap between the electrodes so that the wires do not contact each other, a problem that it is difficult to speed up the circuit operation due to the high resistance value of the wire, and it is difficult to reduce the thickness. is there.
The through electrode method solves the above-described problems in the wire bonding method, but has a problem that the cost of the layered chip package is increased because a number of processes are required to form the through electrode in each chip.

  Conventionally, for example, Patent Document 1 and Patent Document 2 are known as a method of manufacturing a layered chip package. Patent Document 1 describes the following manufacturing method. In this manufacturing method, first, a plurality of chips cut out from a wafer are embedded in an embedding resin. Thereafter, a plurality of leads connected to each chip are formed to create a structure called Neo-Wafer. Next, the Neo-Wafer is cut, and a plurality of structures called Neo-chip including a chip, a resin surrounding the chip, and a plurality of leads are created. At this time, the end faces of a plurality of leads connected to the chip are exposed on the side surface of the Neo-chip. Then, a plurality of types of Neo-chips are stacked to create a stacked body. In this laminate, the end faces of a plurality of leads connected to the chips of each layer are exposed on the same side surface of the laminate.

Non-Patent Document 1 describes that a laminated body is manufactured by a method similar to the manufacturing method described in Patent Document 1 and wirings are formed on two side surfaces of the laminated body.
On the other hand, Patent Document 2 discloses a multilayer module configured by laminating a plurality of active layers formed by forming one or more electronic elements and a plurality of conductive traces on a flexible polymer substrate.

US Pat. No. 5,953,588 US Pat. No. 7,127,807 B2

Keith D. Gann, “Neo-StackingTechnology”, HDI Magazine, December 1999

  By the way, the layered chip package is manufactured by the following procedure. First, a wafer (device wafer) in which a plurality of devices are fabricated is created by performing a wafer process. Then, a plurality of grooves along the scribe line are formed on the device wafer. Further, an insulating layer is formed by embedding a resin such as an epoxy resin or a polyimide resin in the groove portion, thereby forming a grooved device wafer. A laminated device wafer is produced by pasting such grooved device wafers with an insulating adhesive. A laminated chip package is manufactured by cutting the laminated device wafer along the groove.

  On the other hand, in the layered chip package, a plurality of device plates are overlapped. When the laminated device wafer is cut along the groove, the grooved device wafer is also cut along the groove. A plate-like member formed by cutting a grooved device wafer along the groove is a device plate.

  Then, when manufacturing the layered chip package, as described above, after forming a plurality of grooves along the scribe line in the device wafer, the insulating layer is formed by embedding a resin in the grooves.

  However, when a resin is embedded in the groove, a liquid resin is applied to the surface of the device wafer, and the resin may not enter the groove well. In particular, when the depth of the groove is increased or the width is reduced, the resin may hardly enter.

  On the other hand, a plurality of devices are built in the device wafer, and wirings connected to the devices are formed after the insulating layer is formed.

  However, since the wiring connected to each device is also formed on the upper side of the groove, when a portion not filled with resin (also referred to as an unfilled portion or a void) appears in the groove, the grooved device wafer is stacked. Further, there is a possibility that the wiring connected to each device is deformed due to the surface of the insulating layer being recessed. If it does so, there exists a possibility that the electrical connection between each device plate may become uncertain in a laminated chip package, and the reliability regarding the electrical connection of a laminated chip package could not be improved.

The present invention has been made to solve the above problems, and provides a semiconductor substrate having a structure capable of enhancing the reliability of electrical connection of a layered chip package, a method for manufacturing the same, and a method for manufacturing a layered chip package. The purpose is to provide.

In order to solve the above problems, the present invention provides a semiconductor substrate in which a plurality of groove portions are formed along a scribe line, a unit region in contact with at least one of the plurality of groove portions, and in the unit region and a wiring electrode portion is disposed, the plurality of grooves, wider wide portion width than the groove bottom including the bottom have a wide-port structure formed at the entrance, without a gap in a plurality of grooves It further has an insulating layer formed by filling the resin, and the insulating layer includes a lower insulating layer formed inside the groove lower portion and an upper insulating layer formed inside the wide portion. The semiconductor substrate has a two-layer structure that is overlapped, and the lower insulating layer is formed using a low-viscosity resin having a lower viscosity than the resin that forms the upper insulating layer .

In the semiconductor substrate, since each groove portion has a wide structure, the resin easily enters the inside of each groove portion, and an unfilled portion is less likely to be generated inside each groove portion. Moreover, since the wide part is formed in the whole length direction of an entrance, resin becomes easy to enter inside about the whole length direction of a some groove part, and it becomes difficult to produce an unfilled part. Furthermore, in the semiconductor substrate, the lower insulating layer using the low-viscosity resin is formed inside the groove lower portion where the resin is relatively difficult to enter, so that an unfilled portion is less likely to be generated inside the groove portion. .

  In the semiconductor substrate, the unit region is formed as a device region having a semiconductor device, is formed so as to cover the device region, and further includes a surface insulating layer constituting a surface layer of the semiconductor substrate. It is preferable that the layer is integrally formed using the same resin as the upper insulating layer without a joint.

  Such a semiconductor substrate can be easily manufactured because the upper insulating layer and the surface insulating layer can be formed in one step using the same resin.

  Furthermore, the wiring electrode can have an extended terminal portion that extends from the unit region to the inside of the groove.

  Furthermore, the wiring electrode has an extended terminal portion that extends from the device region to the inside of the groove portion, and is formed in a convex shape that rises above the surface of the surface insulating layer. You can also.

  Furthermore, the wiring electrode protrudes outward from the surface of the surface insulating layer, intersects with the surface of the surface insulating layer, protrudes outward from the surface of the surface insulating layer, and It is also possible to have a top end face along the surface and an embedded portion that enters inside the surface of the surface insulating layer.

  Then, in the semiconductor substrate, a connection pad connected to the semiconductor device, a connection hole is formed at the formation position of the connection pad, and is disposed below the surface insulating layer so as to cover the device region. The wiring electrode preferably includes an electrode pad having an extended height from the outside of the surface insulating layer to the connection pad.

Then, the present invention provides a first groove portion forming step of forming a plurality of first groove portions having a first width and a first depth along a scribe line for a pre-process substrate on which a semiconductor device is formed. And forming a second groove portion having a second width wider than the first width and having a second depth shallower than the first depth at the entrance of the plurality of first groove portions. A second groove forming step, and an insulation for forming an insulating layer inside the first groove and the second groove by applying a resin to the surface on which the first groove and the second groove are formed A layer forming step and a wiring electrode forming step for forming the wiring electrode connected to the semiconductor device after the insulating layer, and in the insulating layer forming step, the viscosity before the resin is applied before the resin is applied. A low-viscosity resin with low viscosity is applied to the surface to form a lower insulating layer inside the first groove To provide a method of manufacturing a semiconductor substrate that.

  In the insulating layer forming step, a surface insulating layer is formed of a resin on the surface on which the first groove portion and the second groove portion are formed. In the wiring electrode forming step, the wiring electrode is placed above the surface of the surface insulating layer. It is preferable to form it in a convex shape that emerges.

  Further, in the wiring electrode forming step, the extended terminal portion extending from the device region in contact with at least one of the plurality of first groove portions to the first groove portion is raised above the surface of the surface insulating layer. It is preferable to form a convex shape.

  Further, according to the present invention, at least two semiconductor substrates manufactured by the above manufacturing method are stacked to form a stacked device wafer, and a lower insulating layer is formed on the cut surface when the stacked device wafer is cut along the first groove. A device block is manufactured by causing a cross section of an insulating layer having a two-layer structure including a layer and an end face of a wiring electrode formed on each semiconductor substrate to be connected, and a connection electrode connecting the end faces of each wiring electrode is connected to the device block A method for manufacturing a layered chip package formed on a cut surface is provided.

  Moreover, when manufacturing a device block, it is preferable to make the end surface of a wiring electrode appear as a protruding end surface which protrudes outside the surface of the surface insulating layer.

As described above in detail, according to the present invention, a semiconductor substrate having a structure capable of enhancing the reliability of electrical connection of a layered chip package, a method for manufacturing the same, and a method for manufacturing a layered chip package are obtained.

1 is a perspective view showing an entire semiconductor wafer according to a first embodiment of the present invention. It is a top view which shows the device area | region currently formed in the semiconductor wafer, and its peripheral area | region. FIG. 3 is a sectional view taken along line 3-3 in FIG. 2. It is sectional drawing centering on the memory cell of the laminated chip package using two semiconductor wafers. It is the perspective view which a part of which showed the principal part of the semiconductor wafer of FIG. 1 was abbreviate | omitted. FIG. 6 is a sectional view taken along line 6-6 of FIG. It is a top view similar to FIG. 2 which shows the semiconductor wafer in the middle of manufacture. FIG. 8 is a plan view similar to FIG. 2 showing the semiconductor wafer subsequent to FIG. 7. FIG. 9 is a plan view similar to FIG. 2 showing the semiconductor wafer subsequent to FIG. 8. FIG. 10 is a plan view similar to FIG. 2 showing the semiconductor wafer subsequent to FIG. 9. FIG. 11 is a plan view similar to FIG. 2 showing the semiconductor wafer subsequent to FIG. 10. FIG. 6A is a cross-sectional view of a semiconductor wafer centered on a groove portion, where FIG. 5A shows a state in which a first groove portion forming step has been executed, and FIG. 12A is a cross-sectional view of the semiconductor wafer subsequent to FIG. 12, in which FIG. 12A shows a state where a lower insulating layer is formed, and FIG. 12B shows a state where an upper insulating layer and a surface insulating layer are formed. FIG. 14 is a cross-sectional view taken along line 14-14 of FIG. FIG. 15 is a cross-sectional view taken along line 15-15 in FIG. 8. FIG. 16 is a cross-sectional view taken along line 16-16 in FIG. 9. It is a 17-17 line sectional view of Drawing 10. FIG. 18 is a cross-sectional view taken along line 18-18 in FIG. 11. FIG. 4 is a cross-sectional view similar to FIG. 3 showing a semiconductor wafer and a base in the middle of manufacturing a layered chip package. FIG. 20 is a cross-sectional view similar to FIG. 3 illustrating a step subsequent to FIG. 19. FIG. 21 is a cross-sectional view similar to FIG. 3 illustrating a step subsequent to FIG. 20. FIG. 22 is a cross-sectional view similar to FIG. 3 illustrating a step subsequent to FIG. 21. It is a perspective view which shows an example of the device plate which comprises a laminated chip package. It is a perspective view which shows an example of a device block. It is the perspective view which abbreviate | omitted a part which shows an example of a laminated chip package. FIG. 26 is a perspective view showing an example of the same layered chip package as FIG. 25. It is a top view which shows the device area | region currently formed in the semiconductor wafer which concerns on the 2nd Embodiment of this invention, and its peripheral area | region. It is a perspective view which shows the whole semiconductor wafer which concerns on other embodiment of this invention. It is a top view which shows the device area | region currently formed in the semiconductor wafer of FIG. 28, and its peripheral area | region. It is a perspective view which shows the whole semiconductor wafer which concerns on another embodiment. It is a perspective view which shows another layered chip package. It is a perspective view which shows another device plate. (A) is a cross-sectional view schematically showing the case where the groove is provided with only the lower part of the groove, and (B) is a cross-sectional view of the resin when the groove is wider than (A). It is sectional drawing which showed typically the time of apply | coating. It is the perspective view which showed the principal part of the corner | angular part in a device block by making one side into a cross section, and showed the other side with the internal structure. (A) is sectional drawing similar to FIG. 6 which concerns on a modification, (B) is sectional drawing similar to FIG. 6 which concerns on another modification.

Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol is used for the same element and the overlapping description is abbreviate | omitted.
First embodiment (semiconductor wafer structure)
First, the structure of a semiconductor wafer 1 as an example of a semiconductor substrate according to an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a perspective view showing the entire semiconductor wafer 1 according to the first embodiment of the present invention. FIG. 2 is a plan view showing the device region 10 formed in the semiconductor wafer 1 and its peripheral region, and FIG. 3 is a sectional view taken along line 3-3 in FIG. 5 is a partially omitted perspective view showing the main part of the semiconductor wafer 1, and FIG. 6 is a sectional view taken along line 6-6 of FIG.

  The semiconductor wafer 1 is configured using a silicon wafer 2. As shown in FIG. 1, the semiconductor wafer 1 has scribe lines 3A and 3B formed on the first surface 1a of the silicon wafer 2 (the back surface side of the first surface 1a is the second surface 1b). A plurality of scribe lines 3A and 3B are formed on the first surface 1a, respectively, and are formed on a straight line at a predetermined interval along a certain direction. The scribe line 3A and the scribe line 3B are orthogonal to each other. A device region 10 to be described later is formed in a region surrounded by adjacent scribe lines 3A, 3A and 3B, 3B.

  The semiconductor wafer 1 has grooves 20 and 21 formed on the first surface 1a. The groove portions 20 and 21 are formed along the scribe lines 3A and 3B, respectively.

  As shown in detail in FIG. 6, the groove portion 20 has a groove lower portion 20a and a wide portion 20b, and is formed in a direction substantially orthogonal to the first surface 1a.

  The groove lower portion 20a includes a bottom portion 20c of the groove portion 20 and is a portion having a certain height from the bottom portion 20c (see FIGS. 12 and 13 for the bottom portion 20c). The groove lower part 20a is a lower part in which the resin is relatively difficult to enter in the groove part 20, and as shown in FIGS. 12A and 12B, the width w1 (about 60 to 80 μm) and the depth d1 ( About 10 to 40 μm). A lower insulating layer 23 to be described later is formed inside the groove lower portion 20a as shown in FIGS.

  The wide portion 20b is a portion disposed above the groove lower portion 20a in the groove portion 20 and is a portion having a certain depth from the entrance 20d including the entrance 20d of the groove portion 20. The wide portion 20b is formed wider than the groove lower portion 20a, and is formed in the entire length direction of the entrance 20d in the groove portion 20. That is, as shown in FIGS. 12A and 12B, the width w2 of the wide portion 20b is larger than the width w1 of the groove lower portion 20a (w2> w1). The wide portion 20b has a width w2 of about 80 to 120 μm and a depth d2 of about 10 to 40 μm. An upper insulating layer 22a described later is formed inside the wide portion 20b.

  The groove part 21 has a groove lower part 21a and a wide part 21b, and is formed in a direction substantially orthogonal to the first surface 1a. The groove lower part 21a is a part of a certain height from the bottom similar to the groove lower part 20a, and has the same width and depth as the groove lower part 20a. A lower insulating layer 23 is formed inside the groove lower portion 21a in the same manner as the groove lower portion 20a. The wide portion 21b is a portion disposed above the groove lower portion 21a. The wide part 21b is formed wider than the groove lower part 21a, and has the same width and depth as the wide part 20b. An upper insulating layer 22a is formed inside the wide portion 21b, similarly to the wide portion 20b.

  Thus, the groove parts 20 and 21 have a wide structure in which the wide part 20b and the wide part 21b which are wider than the groove lower parts 20a and 21a are respectively formed at the entrances. An insulating layer having a two-layer structure in which the upper insulating layer 22 a overlaps the lower insulating layer 23 is formed inside the groove portions 20 and 21.

  The semiconductor wafer 1 has a surface insulating layer 22 as shown in detail in FIG. The surface insulating layer 22 is formed so as to cover the device region 10, covers almost the entire first surface 1 a of the semiconductor wafer 1, and constitutes a surface layer of the semiconductor wafer 1. The surface insulating layer 22 is thicker than a protective insulating layer 31 to be described later, and the surface 22c is formed to be flat, and the semiconductor wafer 1 is excluded except for portions where wiring electrodes 15 and wiring electrodes 16 to be described later are formed. It is arranged on the outermost side.

  In addition, the surface insulating layer 22 is configured integrally with the upper insulating layer 22a formed inside the groove portions 20 and 21, and is formed as a single unit without a joint between the upper insulating layer 22a and other portions. Yes. A plurality of contact holes 22b are formed in the surface insulating layer 22, and one wiring electrode 15 or one wiring electrode 16 is formed in each contact hole 22b.

  The surface insulating layer 22 can be formed using a resin such as an epoxy resin or a polyimide resin, or an insulating material made of silicon silicate glass (SOG) or the like. In this embodiment, it is assumed that a resin is used. In particular, the surface insulating layer 22 is preferably formed using a resin having a small thermal expansion coefficient. By doing so, when the semiconductor wafer 1 is cut along the groove portions 20 and 21 with a dicing saw, the cutting can be easily performed.

  Similarly to the surface insulating layer 22, the lower insulating layer 23 is also formed using a resin. However, the lower insulating layer 23 is formed using a low-viscosity resin having a lower viscosity than the resin forming the surface insulating layer 22.

  Further, the semiconductor wafer 1 has a silicon substrate 30 constituted by the silicon wafer 2, and the upper portion thereof is a device region 10. The device region 10 has a plurality of connection pads 32 formed on the surface, and a portion other than the connection pads 32 is covered with a protective insulating layer 31.

The protective insulating layer 31 is disposed below the surface insulating layer 22 and is formed so as to cover the device region 10. The protective insulating layer 31 is made of silicon dioxide (SiO ₂ ) or the like, and a connection hole 31 a is formed at a position where each connection pad 32 is formed. The connection hole 31a is formed to expose the connection pad 32 and connect wiring electrodes 15 and 16 to be described later to the connection pad 32. The connection pad 32 is connected to the semiconductor device in the device region 10 (see FIG. 4 for details).

  As shown in detail in FIG. 2, the device region 10 is a rectangular region surrounded by the adjacent groove portions 20 and 20 and the groove portions 21 and 21. A plurality of device regions 10 are formed on the first surface 1 a, and each of them is a unit region that is separated from adjacent regions by the grooves 20 and 21.

  Each device region 10 has a memory portion formed on the first surface 1a by performing a wafer process, and a plurality of wiring electrodes 15 and 16 are formed. The wafer process means a manufacturing process in which a semiconductor element or an integrated circuit is formed on a wafer such as the silicon wafer 2.

  In the device region 10, an integrated circuit and a semiconductor element such as a CPU, a sensor, and a sensor driving circuit may be formed in addition to a memory unit as a semiconductor device. The device region 10 may be formed with an integrated circuit constituting a memory unit and a controller for controlling the memory unit.

  The wiring electrode 15 is made of a conductive material such as Cu. The wiring electrode 15 has an extension terminal portion 15a and a rectangular electrode pad 15b, and the extension terminal portion 15a and the electrode pad 15b as a whole float above the surface 22c of the surface insulating layer 22 in a three-dimensional manner. It has a convex structure.

  The wiring electrode 15 is shown in detail in FIGS. 5 and 23 in addition to FIG. The wiring electrode 15 is a protruding end surface in which the end surface 15 g of the extended terminal portion 15 a protrudes outward from the surface 22 c of the surface insulating layer 22. Further, the wiring electrode 15 has an intersecting side surface 15d, a top end surface 15e, and an embedded portion 15f.

  The intersecting side surface 15d is a side surface portion that protrudes outward from the surface 22c of the surface insulating layer 22 and intersects so as to stand up from the surface 22c (substantially orthogonally). The top end face 15e is connected to the intersecting side face 15d, protrudes outward from the surface 22c, and extends in the direction along the surface 22c toward the groove 20 from the rectangular portion arranged in the direction along the surface 22c. It has a belt-like part. The embedded portion 15 f is a portion that enters inside the surface 22 c and is connected to the connection pad 32.

  The electrode pad 15b is constituted by the intersecting side face 15d, the top end face 15e and the embedded part 15f, and the extended terminal part 15a is constituted by the intersecting side face 15d and the top end face 15e.

  The electrode pad 15 b is connected to the connection pad 32 via the contact hole 22 b and the connection hole 31 a that are arranged one above the other so as to reach the connection pad 32. That is, the electrode pad 15b has an expanded height (expanded height) h15 from the top end surface 15e outside the surface 22c to the connection pad 32 through the contact hole 22b and the connection hole 31a. This extended height h15 is larger than the height h32 of the connection pad 32 (h15> h32). For example, h15 is about 2 to 6 μm, and h32 is about 0.5 to 1 μm.

  The wiring electrode 16 is also made of a conductive material such as Cu. The wiring electrode 16 has an extended terminal portion 16 a and a rectangular electrode pad 16 b, and the extended terminal portion 16 a and the entire electrode pad 16 b have a convex structure similar to that of the wiring electrode 15. The wiring electrode 16 has a protruding end surface in which the end surface 16g of the extended terminal portion 16a protrudes outward from the surface 22c.

  The wiring electrode 16 has an intersecting side surface 16d, a top end surface 16e, and an embedded portion 16f. The intersection side surface 16d is a side surface portion that intersects the surface 22c in the same manner as the intersection side surface 15d. Similarly to the top end face 15e, the top end face 16e has a rectangular part arranged in the direction along the surface 22c and a band-like part extending from the rectangular part toward the groove part 20 in the direction along the surface 22c. The embedded portion 16f is a portion that enters the inside of the surface 22c and is connected to the connection pad 32 in the same manner as the embedded portion 15f. The electrode pad 16b is configured by the intersecting side surface 16d, the top end surface 16e, and the embedded portion 16f, and the extended terminal portion 16a is configured by the intersecting side surface 16d and the top end surface 16e. The electrode pad 16b also has an extension height similar to that of the electrode pad 15b.

  In the wiring electrode 15, the extended terminal portion 15 a and the electrode pad 15 b are formed along a part of the outer periphery of the device region 10, but the wiring electrode 16 extends over the device region 10. 16a is formed. In addition, the electrode pad 16b is disposed along a part of the outer periphery of the device region 10 so as to face the electrode pad 15b.

  A portion of each of the extended terminal portion 15 a and the extended terminal portion 16 a extends from the device region 10 to the inside of the groove portion 20. That is, in the extended terminal portion 15a and the extended terminal portion 16a, a part of the tip side away from the electrode pads 15b and 16b protrudes from the edge portion (the entrance 20d described above) of the groove portion 20 and fits inside the groove portion 20 in the width direction. It is formed in this way. The extended terminal portion 15 a and the extended terminal portion 16 a are formed in a convex shape in which the portions extending from the device region 10 in each of the extended terminal portions 15 a are raised above the surface 22 c of the surface insulating layer 22.

  Further, as shown in FIGS. 2, 5, and 6, the extended terminal portion 15 a and the extended terminal portion 16 a protrude from both sides in the width direction of the groove portion 20, and end faces 15 g near the width direction center of the groove portion 20. The end faces 16g are slightly separated from each other.

  The semiconductor wafer 1 has an extended terminal portion 15a and an extended terminal portion 16a. Therefore, the semiconductor wafer 1 is configured such that end surfaces 15c and 16c, which will be described later, protrude outward from the surface 22c on the cut surface when cut along the groove portion 20.

  Furthermore, a large number of wiring electrodes 15 and 16 are alternately arranged along the groove 20. These wiring electrodes 15 and 16 form a unified wiring electrode group 17. In addition, the wiring electrodes 15 and 16 surround the device region 10, and are all of the groove portions that are in contact with the device region 10, that is, of the two adjacent groove portions 20 and 20 and the two groove portions 21 and 21. The extended terminal portions 15a and 16a extend only to the left or right groove 20 which is a part of the four grooves. The wiring electrode group 17 has an uneven distribution structure due to such an uneven arrangement of the extended terminal portions 15a and 16a.

  Many memory cells 41 as semiconductor devices are formed in the memory portion of the device region 10. The memory cell 41 has a structure as shown in FIG. FIG. 4 is a cross-sectional view of a layered chip package 100 (to be described later) using two semiconductor wafers 1 with a memory cell 41 as the center.

  The memory cells 41 are connected to the wiring electrodes 15 and 16 via the connection pads 32. The memory cell 41 is formed on the surface of an N-type substrate 71 constituting the semiconductor wafer 1. In FIG. 4, two memory cells 41 are stacked via an adhesive layer 33. The adhesive layer 33 is composed of an adhesive used when the semiconductor wafer 1 is bonded.

  Each memory cell 41 constitutes a flash memory, and is formed on a P-type well 72 formed on the surface of an N-type substrate 71. The memory cell 41 includes a source 73A and a drain 73B, an insulating layer 77, an insulating film 81, a floating gate 82, an insulating film 83, and a control gate 84. Further, the memory cell 41 has a source electrode 74, a drain electrode 76, and a gate electrode 75.

  The source 73A and the drain 73B are both N-type regions, and the source electrode 74 and the drain electrode 76 are connected to each other. The insulating layer 77 has contact holes for connecting the connection pads 32 to the source electrode 74 and the drain electrode 76, respectively. The source electrode 74, the gate electrode 75, and the drain electrode 76 are connected to the source 73A, the control gate 84, and the drain 73B through corresponding contact holes, respectively.

(Semiconductor wafer manufacturing method)
Next, a method for manufacturing the semiconductor wafer 1 having the above configuration will be described with reference to FIGS. 7 is a plan view similar to FIG. 2 showing a semiconductor wafer being manufactured, and FIG. 8 is a plan view similar to FIG. 2 showing a semiconductor wafer subsequent to FIG. 9 to 11 are plan views similar to FIG. 2 showing subsequent semiconductor wafers in order. 12A and 12B are cross-sectional views of the semiconductor wafer with the groove portion as the center. FIG. 12A shows a state in which the first groove portion forming step has been executed, and FIG. 12B shows a state in which the second groove portion forming step has been executed. Yes. 13A and 13B are cross-sectional views of the semiconductor wafer subsequent to FIG. 12, in which FIG. 13A shows a state where a lower insulating layer is formed, and FIG. 13B shows a state where an upper insulating layer and a surface insulating layer are formed. 14 to 18 are sectional views taken along lines 14-14, 15-15, 16-16, 17-17, and 18-18, respectively, of FIGS. For convenience of illustration, in FIGS. 10 and 11, the surface insulating layer 22 is hatched.

  When the semiconductor wafer 1 is manufactured, first, a wafer process (wafer before processing) in which a memory portion and a plurality of connection pads 32 are formed in the device region 10 is prepared by performing a wafer process. Then, as shown in FIG. 14, for the unprocessed wafer, the protective insulating layer 31 is formed on the first surface 1a, and the connection holes 31a are formed at the positions where the connection pads 32 of the protective insulating layer 31 are formed. . Next, the groove portions 20 and 21 are formed along the scribe lines 3A and 3B. The groove portions 20 and 21 are formed by a dicing saw method. The grooves 20 and 21 may be formed by etching such as reactive ion etching.

  When the groove portions 20 and 21 are formed, a first groove portion forming step and a second groove portion forming step described below are sequentially performed.

  In the first groove forming step, as shown in FIGS. 7, 12A, and 14, the first surface 1a is formed along the scribe lines 3A and 3B using a first blade (cutting blade) (not shown). Thus, a groove (first groove 120) having a first width and a first depth is formed. In the first groove 120, a portion having a certain height from the bottom becomes the groove lower portion 20a or the groove lower portion 21a later. Here, the first width is the aforementioned width w1, which is about 60-80 μm, and the first depth is the depth d0 shown in FIG. 12A, which is about 40-80 μm.

  Subsequently, a second groove forming process is performed. In the second groove forming step, as shown in FIGS. 8, 12B, and 15, the length of the first groove 120 is entered at the entrance of the first groove 120 using a second blade (not shown). A second groove 121 is formed along the entire direction. The second groove 121 has a second width and a second depth. The second width is the aforementioned width w2, which is about 80 to 120 μm, and the second depth is the aforementioned depth d2, which is about 10 to 40 μm. The second width is larger than the first width, and the second depth d2 is shallower than the first depth d0 (d0> d2). By forming the second groove 121, a portion of the first groove 120 having a certain height from the bottom becomes the groove lower portion 20a and the groove lower portion 21a, and the upper portion of the groove lower portion 20a and the groove lower portion 21a is the wide portion 20b. The wide portion 21b is formed.

  Next, an insulating layer forming step is performed. In the insulating layer forming step, a low-viscosity resin having a viscosity lower than that of the surface layer resin is applied to the first surface 1a in advance before applying a resin for forming the surface insulating layer 22 (also referred to as a surface layer resin). Apply. Then, the applied low-viscosity resin is uniformly distributed on the first surface 1a using a spin coater (not shown). The low viscosity resin has a low viscosity and is smooth and has good fluidity. Therefore, the low-viscosity resin surely enters the inside of the groove lower part 20a and the groove lower part 21a that are relatively difficult to enter. In addition, since the wide portions 20b and 21b are formed above the groove lower portion 20a and the groove lower portion 21a, the low-viscosity resin is more likely to enter the groove lower portion 20a and the groove lower portion 21a.

  Then, as shown in FIGS. 9, 13A, and 16, the lower insulating layer 23 is formed by the low-viscosity resin remaining inside the groove lower portion 20a and the groove lower portion 21a. The low-viscosity resin enters the inside of the groove portions 20 and 21 and may remain outside the groove portions 20 and 21 (for example, above the protective insulating layer 31), but the low-viscosity resin remaining outside the groove portions 20 and 21. Is not shown.

  Next, as shown in FIGS. 10, 13B, and 17, the surface layer resin is applied to the entire first surface 1a. Then, the applied surface layer resin is uniformly distributed on the first surface 1a using a spin coater (not shown) or the like. The surface layer resin is, for example, an epoxy resin or a polyimide resin, but has a higher viscosity and lower fluidity than a low viscosity resin. For this reason, the surface layer resin has a narrow width and is difficult to enter inside the deep groove. However, wide portions 20 b and 21 b are formed at the entrances of the groove portions 20 and 21. Therefore, the surface layer resin is likely to enter inside the groove portions 20 and 21.

  Then, by applying a low-viscosity resin in advance before applying the surface layer resin, the lower insulating layer 23 is formed in the groove lower part 20a and the groove lower part 21a. Therefore, when the surface layer resin enters inside the groove portions 20 and 21, an insulating layer different from the lower insulating layer 23 is formed inside the groove portions 20 and 21 by the surface layer resin. This insulating layer becomes the upper insulating layer 22a. In this way, an insulating layer having a two-layer structure is formed inside the groove portions 20 and 21.

  Subsequently, when the surface of the unprocessed wafer is polished and planarized, the surface insulating layer 22 is formed so as to cover the entire surface of the unprocessed wafer. Since the portion of the applied surface layer resin that enters the inside of the grooves 20 and 21 becomes the upper insulating layer 22a, the surface insulating layer 22 is formed integrally with the upper insulating layer 22a.

  Next, as shown in FIGS. 11 and 18, contact holes 22 b are formed in the surface insulating layer 22 to expose the connection pads 32. Thereafter, a wiring electrode forming step is performed to form the wiring electrodes 15 and 16. The wiring electrodes 15 and 16 have the convex structure described above and are formed in a shape including the extended terminal portions 15a and 16a. The wiring electrodes 15 and 16 can be formed by the following procedure, for example.

  First, a seed layer (not shown) for plating is formed on the surface insulating layer 22. Next, a frame (not shown) having a groove is formed on the seed layer. The frame is formed by patterning a photoresist, for example, by photolithography. Further, a plating layer that is a part of the wiring electrodes 15 and 16 is formed on the seed layer inside the groove portion of the formed frame. Next, the frame is removed, and a portion of the seed layer other than the portion existing under the plating layer is removed by etching. As described above, the wiring electrodes 15 and 16 can be formed by the plating layer and the seed layer therebelow.

  Since the wiring electrodes 15 and 16 are formed after the surface insulating layer 22, the extended terminal portions 15 a and 16 a are formed so that the entirety thereof is disposed above the surface 22 c of the surface insulating layer 22. The electrode pads 15b and 16b are formed such that the peripheral portion is disposed on the upper side of the surface 22c and the central portion enters the inner side of the surface 22c and is connected to the connection pad 32.

  By passing through the above process, the semiconductor wafer 1 provided with the structure mentioned above can be manufactured. In the semiconductor wafer 1, since the groove portions 20 and 21 have a wide structure, liquid resin easily enters the inside of the groove portions 20 and 21. Therefore, when an insulating layer is formed inside the grooves 20 and 21 using a liquid resin, the resin surely enters inside the grooves 20 and 21. Therefore, unfilled portions (voids) that are not filled with resin are not formed inside the grooves 20 and 21. That is, the entire inside of the grooves 20 and 21 is filled with resin.

  In the semiconductor wafer 1, the lower insulating layer 23 and the upper insulating layer 22a are formed of resin filled without forming such voids. That is, the semiconductor wafer 1 has grooves 20 and 21 having a structure in which the inside is filled without gaps by an insulating layer made of a plurality of resins, a low-viscosity resin and a surface layer resin (this structure is referred to as a “full structure”). Yes.

  By the way, when manufacturing the layered chip package 100 using the semiconductor wafer 1, it is necessary to stack a plurality of semiconductor wafers 1 (details will be described later). Therefore, a load from the semiconductor wafer 1 stacked on the top acts on the semiconductor wafer 1 stacked on the bottom, and the load also acts on the extension terminal portions 15a and 16a. The extended terminal portions 15 a and 16 a partially extend from the device region 10 on the tip side and are disposed on the upper side of the groove portion 20. Therefore, when a load from above acts on the extended terminal portions 15a and 16a, the distal end side is easily bent downward with the entrance 20d of the groove portion 20 as a boundary.

  However, in the semiconductor wafer 1, since the groove portions 20 and 21 have a full structure, the lower insulating layer 23 and the upper insulating layer 22 a do not move inside the groove portions 20 and 21. The position of the surface 22c of 22 does not change. The surface insulating layer 22, the upper insulating layer 22a, and the lower insulating layer 23 are supporting members that support the extended terminal portions 15a and 16a. However, since their positions do not change, the extended terminal portions 15a and 16a are surface-insulated. It is reliably supported by the layer 22, the upper insulating layer 22a, and the lower insulating layer 23 (see FIG. 6). Therefore, the extended terminal portions 15a and 16a are not deformed even when a load from above is applied, and the original shape can be reliably maintained. Thus, by using the semiconductor wafer 1, the electrical connection of the layered chip package can be ensured (details will be described later).

  Moreover, in the groove parts 20 and 21, the wide parts 20b and 21b are formed in the whole length direction of the entrance 20d. Therefore, the resin easily enters the inside of the entire groove portions 20 and 21. Therefore, the extended terminal portions 15a and 16a that are not deformed can be formed in any portion of the groove portions 20 and 21.

  And since the groove lower parts 20a and 21a are located in the groove parts 20 and 21 from the bottom part, resin hardly enters relatively more than other parts. Therefore, in the semiconductor wafer 1, the lower insulating layer 23 is formed inside the groove lower portions 20a and 21a using a low-viscosity resin. Since the low viscosity resin has good fluidity, it will surely enter the part that is difficult to enter. Therefore, the low-viscosity resin is extremely suitable for making the groove portions 20 and 21 full. As described above, the semiconductor wafer 1 uses the low-viscosity resin so that the filling structure of the grooves 20 and 21 is more reliably formed.

  On the other hand, the surface layer resin has higher viscosity and lower fluidity than the low viscosity resin. Therefore, if the groove portions 20 and 21 are configured only by the groove lower portions 20a and 21a and are not wide structures, as shown in FIG. 33A, the surface layer resin is located near the entrance of the groove portion 20 (21). It becomes difficult to get inside the stay. As a result, the voids 25 in which no resin is present appear inside the grooves 20 and 21, so that the surface insulating layer 22 on the upper side of the grooves 20 and 21 is bent. Further, since the resin for the surface layer has low fluidity, it is difficult to make the groove 20 (21) full structure even if the width of the groove 20 (21) is widened as shown in FIG. Therefore, with the surface layer resin alone, it is difficult to avoid a situation in which the air gap 25 appears inside the groove 20 (21), and it is also difficult to avoid deformation of the extended terminal portions 15a and 16a.

Therefore, when the semiconductor wafer 1 is manufactured, the low-viscosity resin is applied to the first surface 1a in advance before applying the surface layer resin. In this way, before the entrance 20d of the groove portions 20 and 21 is covered with the surface layer resin, the resin is relatively difficult to enter, and the inside of the groove lower portions 20a and 21a where the surface layer resin is difficult to enter is filled with the low viscosity resin. I can leave. By doing so, the generation of the air gap 25 is eliminated, and the filling structure of the groove portions 20 and 21 can be obtained more reliably.
Furthermore, since the upper insulating layer 22a and the surface insulating layer 22 can be formed in one step using the same resin, the semiconductor wafer 1 can be easily manufactured.

(Manufacturing method of layered chip package, structure of layered chip package and device plate)
The laminated chip package 100 can be manufactured by using the same semiconductor wafer 1 having the above-described configuration. A method for manufacturing the layered chip package 100 will be described with reference to FIGS.

  Here, FIG. 19 is a cross-sectional view similar to FIG. 3 showing the semiconductor wafer 1 and the pedestal 34 in the middle of manufacturing the layered chip package 100. 20 is a cross-sectional view similar to FIG. 3 showing the subsequent step of FIG. 12, FIG. 21 is a cross-sectional view similar to FIG. 3 showing the subsequent step of FIG. 20, and FIG. 22 is a view showing the subsequent step of FIG. 3 is a cross-sectional view similar to FIG.

  The layered chip package 100 is manufactured as follows. First, an adhesive is applied to the first surface 1 a of the semiconductor wafer 1 described above and fixed to the pedestal 34. FIG. 19 shows an adhesive layer 33 made of the adhesive applied at this time. The semiconductor wafer 1 is used as an uppermost substrate disposed at the top of a laminated device wafer 98 described later. The pedestal 34 is a member for supporting the semiconductor wafer 1, and a glass plate is used in FIG. Subsequently, the second surface 1b of the semiconductor wafer 1 is polished until the grooves 20 and 21 appear to reduce the thickness of the semiconductor wafer 1 as shown in FIG.

  Next, another semiconductor wafer 1A having the same configuration as that of the semiconductor wafer 1 is prepared, and is bonded to the second surface 1b side of the semiconductor wafer 1 using an adhesive as shown in FIG. At this time, the semiconductor wafer 1 and the semiconductor wafer 1A are aligned so that the positions of both the grooves 20 and 21 are aligned. Then, the second surface 1b of the semiconductor wafer 1A is polished until the grooves 20 and 21 appear. When the thickness of the semiconductor wafer 1A is reduced by this polishing, a laminated device wafer is obtained. In the laminated device wafer, a plurality of semiconductor wafers 1 are laminated.

  Furthermore, as shown in FIG. 21, other semiconductor wafers 1B and 1C having the same configuration as the semiconductor wafer 1 are prepared. Then, for each of the semiconductor wafers 1B and 1C, a step of bonding (polishing / polishing step) is performed after bonding to the second surface 1b side of the laminated device wafer.

  Subsequently, the adhesion / polishing process is repeatedly performed, and then the base 34 and the adhesive layer 33 are removed, whereby a laminated device wafer 98 as shown in FIG. 22 is manufactured. In the laminated device wafer 98, the semiconductor wafer 1 and the semiconductor wafers 1A, 1B, 1C, 1D, 1E, 1F, and 1G are overlapped and a total of eight semiconductor wafers are laminated. Since the pedestal 34 and the adhesive layer 33 are removed from the laminated device wafer 98, the wiring electrodes 15 and 16 of the semiconductor wafer 1 appear in a convex shape.

  Subsequently, the laminated device wafer 98 is cut along the groove portions 20 and 21. Then, as shown in FIG. 24, a rectangular parallelepiped device block 99 is obtained. FIG. 24 is a perspective view showing the device block 99. One of the four side surfaces of the device block 99 is a wiring side surface 99a. End surfaces 15c and 16c, which will be described later, of the extended terminal portions 15a and 16a protrude outward from the surface 22c of the surface insulating layer 22 on the wiring side surface 99a.

  On the other hand, when the laminated device wafer 98 is cut along the groove portions 20 and 21, the groove portions 20 and 21 are cut along the cut line CL as shown in FIG. Then, the extended terminal portion 16a (the same applies to the extended terminal portion 15a) is cut along the cut line CL. Further, as described above, in each semiconductor wafer 1, an insulating layer having a two-layer structure is formed inside the groove portions 20 and 21. Therefore, a cross section of the insulating layer having a two-layer structure (the cross section of the insulating layer is also referred to as “insulating cross section”) appears on the cut surface when the laminated device wafer 98 is cut along the groove portions 20 and 21. This insulating cross section has a two-layer structure in which an insulating cross section 22d, which is a cross section of the upper insulating layer 22a, overlaps an insulating cross section 23c, which is a cross section of the lower insulating layer 23.

  Further, in each semiconductor wafer 1, the widths of the wide portions 20b and 21b are formed wider than the widths of the groove lower portions 20a and 21a. Therefore, the upper insulating layer 22 a has a greater depth than the lower insulating layer 23 on the four side surfaces of the device block 99. This depth refers to the insulation cross section 22d and the inner surface of the wide portion 20b (21b) as shown in FIGS. 6 and 34 in the device block 99 (same for the layered chip package 100 and device plates 50 and 51 described later). Distance d11, and the distance d12 between the insulating cross section 23c and the inner surface of the groove lower portion 20a (21a). Since the distance d11 is larger than the distance d12, d11> d12.

  Subsequently, when the connection electrode 60 is formed on the wiring side surface 99a as shown in FIG. 25, the layered chip package 100 is manufactured. The connection electrode 60 is formed in a band shape on the wiring side surface 99a so as to connect a plurality of end faces 15c arranged in the vertical direction or a plurality of end faces 16c.

  As shown in FIG. 26 in addition to FIG. 25, the layered chip package 100 has a structure in which one device plate 50 and seven device plates 51 overlap and a total of eight device plates are stacked. .

  In the layered chip package 100, the device plates 50 and 51 are wired by the connection electrodes 60. In the layered chip package 100, all connection electrodes 60 are formed on one wiring side surface 99a among the four side surfaces. As a result, the layered chip package 100 realizes a one-sided wiring structure. In the layered chip package 100, a plurality of end faces 15c and 16c are formed, and the connection electrodes 60 are formed so as to connect them in the vertical direction.

  The layered chip package 100 can realize memories having various storage capacities such as 64 GB (gigabyte), 128 GB, and 256 GB by changing the memory unit of the semiconductor wafer 1. In the layered chip package 100, eight device plates are stacked, but a plurality of device plates may be stacked, and the number of stacked device plates is not limited to eight.

  The layered chip package 100 is manufactured by forming the connection electrode 60 on the wiring side surface 99a, but the end faces 15c and 16c connected by the connection electrode 60 are formed so as to protrude upward from the surface 22c.

  When the connection electrode 60 is formed, a mask pattern for forming the connection electrode 60 must be accurately arranged, and the layered chip package 100 can be manufactured even if the alignment of the mask pattern is rough. . Even in rough alignment, the connection electrodes 60 that connect the end faces 15c arranged vertically and the end faces 16c can be formed.

  That is, in the layered chip package 100, when the connection electrode 60 is formed, the alignment need not be performed with high accuracy. Therefore, the process after obtaining the rectangular parallelepiped device block 99 can be simplified, and the entire manufacturing process of the layered chip package 100 can be simplified. Therefore, the manufacturing time of the layered chip package 100 can be shortened. As a result, the number of layered chip packages 100 that can be manufactured per unit time can be increased, and the unit price of the layered chip package 100 can be reduced.

  The reason why the alignment does not have to be performed with high accuracy when forming the connection electrode 60 is as follows.

  First, the device block 99 is configured by a cut surface when all four side surfaces are cut from the laminated device wafer 98. The end faces 15c and 16c appear as end faces protruding in the same manner as the end faces 15g and 16g (for details, see FIG. 5). This is due to the following reason. In the present embodiment, the protruding end surface is also referred to as a protruding end surface.

  The wiring electrodes 15 and 16 of each semiconductor wafer 1 (the same applies to the semiconductor wafers 1A, 1B, 1C, 1D, 1E, 1F, and 1G) have an extended terminal portion 15a and an extended terminal portion 16a. The extended terminal portion 15 a and the extended terminal portion 16 a are extended inside the groove portion 20. Therefore, when the laminated device wafer 98 is cut along the groove portions 20 and 21, the extended terminal portions 15a and the extended terminal portions 16a are also cut. Then, end surfaces 15c and 16c formed when the extended terminal portion 15a and the extended terminal portion 16a are cut appear on one of the cut surfaces.

  On the other hand, the extended terminal portions 15a and 16a are formed in a convex shape like the electrode pads 15b and 16b having the expanded height h15. Therefore, the end faces 15c and 16c appear as protruding end faces that protrude upward from the surface 22c.

  Here, consider a case where a terminal portion extending to the inside of the groove portion 20 is formed for the connection pad 32 (this terminal portion is referred to as a virtual terminal portion). In this case, the end face of the virtual terminal portion appears on the side surface of the device block.

  However, the extended terminal portions 15a and 16a have top end faces 15e and 16e common to the electrode pads 15b and 16b having the extended height h15, and are formed to be thicker than the connection pads 32. Therefore, the end surfaces 15c and 16c appear with a size larger than the end surface of the virtual terminal portion described above. In the device block 99, such large end surfaces 15c and 16c appear side by side in the vertical direction, so that the end surfaces 15c are easily connected to each other, and the end surfaces 16c are also easily connected to each other. Since the connection electrode 60 only needs to be able to connect the end faces 15c and the end faces 16c, the mask pattern may be roughly aligned when the connection electrode 60 is formed. For this reason, in the device block 99, when the connection electrode 60 is formed, the alignment need not be performed with high accuracy.

  On the other hand, the fact that the sizes of the end faces 15c and 16c are large means that the cross-sectional areas of the wiring electrodes 15 and 16 are expanded. Therefore, the resistance value of the wiring electrodes 15 and 16 can be reduced. As a result, the current passing through the wiring electrodes 15 and 16 can easily flow, so that the power consumption of the layered chip package 100 can be reduced.

  Thus, the semiconductor wafer 1 has the wiring electrodes 15 and 16 as described above, whereby the manufacturing process of the layered chip package 100 can be simplified and the manufacturing time can be shortened.

  Furthermore, the device block 99 has electrode pads 15b and 16b that protrude in a convex shape on the upper surface thereof. When a pad-like terminal floating above the surface of the insulating layer is required, a terminal layer having such a pad-like terminal (such a terminal layer is an interposer having no semiconductor device) is overlaid. Thus, a laminated chip package must be manufactured.

  However, in the device block 99, the device plate 50 with the electrode pads 15b and 16b rising in a convex shape is laminated on the top. This eliminates the need for overlapping interposers. Accordingly, since the layered chip package 100 does not require a terminal layer, the layered chip package 100 has a compact structure with a lower height.

  Further, since the semiconductor wafer 1 has the extended terminal portions 15a and 16a extending to the inside of the groove portion 20, the end surfaces 15c and 16c are formed on the cut surfaces when the laminated device wafer is cut along the groove portion 20. Can appear. That is, if the laminated device wafer 98 on which the semiconductor wafer 1 is laminated is cut along the groove portion 20, the end faces 15c and 16c are obtained.

  Therefore, when the semiconductor wafer 1 is used, it is not necessary to provide a separate process for causing the wiring connected to the device region 10 to appear on the cut surface. If the wiring electrodes 15 and 16 do not have the extended terminal portions 15a and 16a, the wiring electrodes 15 and 16 cannot be cut even if they are cut along the groove portion 20. Therefore, the wiring connected to the device region 10 cannot appear on the cut surface only by cutting the laminated device wafer along the groove. Therefore, another process must be performed to make such wiring appear on the cut surface.

  However, when the semiconductor wafer 1 is used, since the end faces of the wiring electrodes 15 and 16 can appear on the cut surface when the laminated device wafer is cut along the groove, a process for causing the wiring to appear on the cut surface There is no need to do this. Therefore, by using the semiconductor wafer 1, the manufacturing process of the layered chip package can be further simplified.

  The wiring electrodes 15 and 16 are formed so as to float on the surface insulating layer 22. Therefore, when the end surfaces 15c and 16c appear on the cut surface, the end surfaces 15c and 16c positioned above and below are arranged with the surface insulating layer 22 interposed therebetween. Therefore, it is possible to avoid a situation in which the device plates positioned above and below are short-circuited.

  Further, the wiring electrodes 15 and 16 in the semiconductor wafer 1 form a wiring electrode group 17, and the wiring electrode group 17 has an unevenly distributed structure that is biased to a part of the groove portions 20 and 21 in contact with the device region 10. doing. Therefore, when the layered chip package 100 is manufactured using the semiconductor wafer 1, the wiring connected to the device region 10 can be brought to one side surface, and the one side surface wiring of the layered chip package 100 can be realized.

  Therefore, the semiconductor wafer 1 is suitable for manufacturing the layered chip package 100 that can realize one-side side wiring. Further, the semiconductor wafer 1 may be inspected for a defective device only for a part of cut surfaces. Therefore, by using the semiconductor wafer 1, the manufacturing process of the layered chip package can be further simplified.

  In addition, since the extended terminal portions 15 a and 16 a have a narrow structure that is narrower than the electrode pads 15 b and 16 b, a large number of wiring electrodes 15 and 16 can be arranged in the device region 10. Therefore, the semiconductor wafer 1 can increase the wiring density of the wiring electrodes 15 and 16. Further, in the semiconductor wafer 1, since the memory portions of the device regions 10 are formed on the same plane, the alignment error is zero.

  On the other hand, the device block 99 has a structure in which the device plate 51 shown in FIG. 24 is stacked below the device plate 50 shown in FIG.

  The device block 99 has end faces 15c and 16c appearing on one wiring side surface 99a. The wiring side surface 99 a is a cut surface when the laminated device wafer 98 is cut along the groove portions 20 and 21.

The device plate 50 is a first semiconductor plate related to the present invention, and as shown in FIG. 23, the device plate 50 is formed into a thin rectangular plate as a whole, and its four side surfaces are covered with an insulating layer. Yes.

  This insulating layer has a two-layer structure like the device block 99 and the layered chip package 100 described above. That is, as shown in FIG. 34, the device plate 50 is covered with an insulating layer having a two-layer structure in which the upper insulating layer 22a overlaps the lower insulating layer 23. In addition, on the four side surfaces of the device plate 50, the upper insulating layer 22 a has a greater depth than the lower insulating layer 23. Thus, the device plate 50 has a clear structure that is formed using the semiconductor wafer 1 described above.

  In the device plate 50, a flat surface on one side becomes the surface 22c of the surface insulating layer 22, and a plurality of three-dimensional wiring electrodes 15 and wiring electrodes 16 that float above the surface 22c are formed. The end surfaces 15c and 16c of the wiring electrode 15 and the wiring electrode 16 appear as protruding end surfaces on one side surface 50A of the four side surfaces. The end faces 15 c and 16 c are first projecting end faces and can be connected to the connection electrode 60. The surface insulating layer 22 of the device plate 50 forms its own surface layer, but in the layered chip package 100, it forms the surface layer.

The device plate 51 is a second semiconductor plate related to the present invention, and is different from the device plate 50 in that it has an adhesive layer 33 that covers the surface 22c, the wiring electrode 15, and the wiring electrode 16, and the like. Have the same configuration. In the device plate 51, the end surfaces 15 c and 16 c of the wiring electrode 15 and the wiring electrode 16 become protruding end surfaces that protrude outward from the surface 22 c of the surface insulating layer 22, and are below the end surfaces 15 c and 16 c of the device plate 50. Is formed. The device plate 51 is laminated on the lower side of the device plate 50 with the adhesive layer 33 interposed therebetween.

  The layered chip package 100 described above is manufactured by stacking the semiconductor wafers 1. Therefore, the wiring electrodes 15 and 16 of the device plates 50 and 51 are surely supported by the surface insulating layer 22, the upper insulating layer 22a, and the lower insulating layer 23, and are not deformed by bending downward.

  In the layered chip package 100, since there is no deformation of the wiring electrodes 15 and 16, the end faces 15c and 16c of the wiring electrodes 15 and 16 are determined at the determined positions in the device plates 50 and 51, respectively. It is definitely appearing. If the extended terminal portions 15a and 16a are deformed by bending downward, the angle with respect to the side surface 50A may be changed, and the contact between the end surfaces 15c and 16c and the connection electrode 60 may be insufficient. However, the layered chip package 100 and the device plates 50 and 51 have no fear.

  Therefore, in the layered chip package 100, the end surfaces 15 c and the end surfaces 16 c of the device plates 50 and 51 can be reliably connected by the connection electrode 60. Therefore, the layered chip package 100 has extremely high reliability regarding electrical connection. Thus, by manufacturing the layered chip package 100 using the semiconductor wafer 1, it is possible to improve the reliability of the electrical connection of the layered chip package 100.

Second Embodiment (Semiconductor Wafer Structure)
First, the structure of a semiconductor wafer 91 according to the second embodiment of the present invention will be described with reference to FIG.

  The semiconductor wafer 91 according to the present embodiment is different from the semiconductor wafer 1 in that a device region 92 is provided instead of the device region 10 and a wiring electrode 86 is provided instead of the wiring electrode 16.

  The device region 92 is different from the device region 10 in that the wiring electrode 86 is formed together with the wiring electrode 15.

  The wiring electrode 86 is made of a conductive material such as Cu, and has an extended terminal portion 86a and a rectangular electrode pad 86b. Similarly to the wiring electrode 15, the wiring electrode 86 has an extended terminal portion 86 a and an electrode pad 86 b formed along a part of the outer periphery of the device region 92. Thus, in the device region 92, the wiring electrodes 15 and 86 form the same wiring electrode group 17 as that in the device region 10, and all of the electrode pads 15b and 86b are gathered on one side of the device region 92. ing. Thus, in the device region 92, the wiring electrodes 15 and 86 gather together to form a pad group 88.

  In the semiconductor wafer 1 according to the first embodiment, the extended terminal portion 16 a of the wiring electrode 16 is formed so as to straddle the device region 10. Therefore, in the semiconductor wafer 1, it has been necessary to secure the length of the extended terminal portion 16a with a certain length.

  On the other hand, in the semiconductor wafer 91, since the extended terminal portion 86a is formed along a part of the outer periphery of the device region 92, the length of the extended terminal portion 86a can be shorter than that of the extended terminal portion 16a. . In the semiconductor wafer 91, the length of the extended terminal portion 86a is shortened, so that the device region 92 can be accessed quickly. Further, as compared with the case where the wiring electrode 16 is formed, a small amount of plating or the like is required for forming the wiring electrode 86, and the cost can be reduced.

  In addition, like the semiconductor wafer 1, the semiconductor wafer 91 can simplify the manufacturing process of the layered chip package capable of realizing the one-side side wiring.

  Further, by manufacturing a device plate 151 similar to the device plate 50 using the semiconductor wafer 91 and stacking eight of the device plates 151, a layered chip package 102 as shown in FIG. 31 can be manufactured.

(Semiconductor wafer manufacturing method)
The semiconductor wafer 91 is manufactured in the same manner as when the semiconductor wafer 1 is manufactured until the wiring electrodes 15 and 86 are formed. Thereafter, the wiring electrodes 15 and 86 are formed in the shape including the extended terminal portions 15a and 86a described above. The wiring electrodes 15 and 86 can be formed by the same procedure as that for the semiconductor wafer 1.

Other Embodiments A semiconductor wafer 111 will be described with reference to FIGS. In the semiconductor wafer 1 according to the first embodiment, the groove portions 20 and 21 are formed. The semiconductor wafer 111 is different from the semiconductor wafer 1 in that the groove portion 21 is not formed and only the groove portion 20 is formed. Therefore, the semiconductor wafer 111 is formed in a stripe shape in which a plurality of groove portions 20 are arranged at regular intervals and the groove portions do not intersect with each other.

  Next, the semiconductor wafer 112 shown in FIG. 30 coincides with the semiconductor wafer 111 in that only the grooves 20 are formed, but the grooves 20 are formed along every other scribe line 3A.

  In the semiconductor wafer 1, since the device region 10 is in contact with the four groove portions 20 and 21, the four directions of the device region 10 are in contact with the groove portions 20 and 21. Therefore, as shown in FIG. 23, the device plate 50 manufactured from the semiconductor wafer 1 has four side surfaces covered with an insulating layer having a two-layer structure.

  On the other hand, in the semiconductor wafer 111, the device region 10 is in contact with the groove 20 only in the left and right directions. Therefore, a device plate 55 using a semiconductor wafer in which grooves like the semiconductor wafer 111 are formed in a stripe shape is as shown in FIG. The device plate 55 has two sets of opposite side surfaces, that is, the side surface 55A and its opposite side, and the side surface 55B and its opposite side, but only the side surface 55A and its opposite side are covered with an insulating layer having a two-layer structure. The opposite side is not covered with a two-layer insulating layer.

  The device plate 55 has wiring end faces 15c and 86c of the wiring electrodes 15 and 86 formed on both of two opposing side surfaces 55A. Although not shown, when the device plate 55 is stacked, a stacked chip package is obtained by forming connection electrodes on two opposing side surfaces. In this layered chip package, connection electrodes are formed on both opposing surfaces to form a double-sided wiring structure.

  In the semiconductor wafer 112, the device region 10 is in contact with the groove 20 only in one of the left and right directions. Therefore, when using a semiconductor wafer in which every other groove portion is formed along the scribe line, such as the semiconductor wafer 112, the device plate has an end face of the wiring electrode and an insulating layer having a two-layer structure on only one side surface. Appears. The other side is not covered with a two-layer insulating layer.

  On the other hand, in the semiconductor wafer 1 described above, the wide portions 20b and 21b are formed with the same depth as the groove lower portions 20a and 21a in the groove portions 20 and 21, but as shown in FIG. A groove 120 may be formed instead of 20. The groove part 120 is different from the groove part 20 in that it has a groove lower part 120a and a wide part 120b. The groove lower part 120a is different in that the depth is deeper than that of the groove lower part 20a. The wide portion 120b is different from the wide portion 20b in that the depth is shallower.

  Even if the wide portion 120b is shallower than the groove lower portion 120a, the resin can easily enter the groove portion 120 by forming the wide portion 120b. Therefore, even when the groove 120 is formed in the semiconductor wafer 1 instead of the groove 20, the reliability regarding the electrical connection of the layered chip package can be improved.

  In the semiconductor wafer 1 described above, a groove 121 as shown in FIG. 35B may be formed instead of the groove 20. The groove part 121 is different from the groove part 20 in that it has an inclined edge part 20f. The inclined edge portion 20f is formed at the entrance of the wide portion 20b. The inclined edge portion 20f is an inclined surface that is gently inclined downward from the outside toward the inside.

  In the semiconductor wafer 1 described above, since the inclined edges 20f are not formed in the grooves 20 and 21, the entrance 20d has a rounded structure (see FIG. 6). On the other hand, since the inclined edge portion 20f is formed in the groove portion 121, the liquid resin easily flows inward from the outer side of the groove portion 20 through the inclined edge portion 20f. Therefore, forming the groove 121 makes it easier for the resin to enter.

  In each of the above embodiments, a device wafer in which a plurality of devices are built is described as an example of a semiconductor substrate. However, the present invention can also be applied to a semiconductor substrate that does not have a semiconductor device. Moreover, although the wiring electrodes 15 and 16 have a convex structure, the present invention can also be applied to a semiconductor substrate provided with a wiring electrode that does not have a convex structure. Further, as in the extended terminal portions 15a and 16a, not the terminal portion extending from the device region 10 to the inside of the groove portion, but the terminal portion having a structure arranged across the groove portion in the two adjacent device regions 10 It may be formed.

  The above description is the description of the embodiment of the present invention, and does not limit the apparatus and method of the present invention, and various modifications can be easily implemented. In addition, an apparatus or method configured by appropriately combining components, functions, features, or method steps in each embodiment is also included in the present invention.

By applying the present invention, it is possible to improve the reliability regarding the electrical connection of the layered chip package. The present invention can be used in the fields of a semiconductor substrate, a manufacturing method thereof, and a manufacturing method of a layered chip package .

  DESCRIPTION OF SYMBOLS 1,91,111,112 ... Semiconductor wafer, 3A, 3B ... Scribe line 10, 92 ... Device area | region, 15, 16, 86 ... Wiring electrode, 15a, 16a, 86a ... Extension terminal part, 15b, 16b, 86b ... electrode pads, 15c, 16c, 86c ... end faces, 15d, 16d ... crossing side faces, 15e, 16e ... top end faces, 15f, 16f ... buried portions, 15g, 16g ... end faces, 17 ... wiring electrode groups, 20, 21, 120, 121 ... groove portion, 20a, 21a, 120a ... groove lower portion, 20b, 21b, 120b ... wide portion, 22 ... surface insulating layer, 22a ... upper insulating layer, 22c ... surface, 23 ... lower insulating layer, 31 ... protective insulation Layer, 32... Connection pad, 50, 51, 55... Device plate, 88.

Claims (12)

A semiconductor substrate having a plurality of grooves formed along a scribe line,
A unit region in contact with at least one of the plurality of grooves, and
A wiring electrode partially disposed in the unit region,
The plurality of groove parts have a wide structure in which a wide part wider than the groove lower part including the bottom part is formed at the entrance,
It further has an insulating layer formed by filling the plurality of grooves with resin without gaps, and the insulating layer is formed on the inner side of the wide portion and the lower insulating layer formed on the inner side of the lower portion of the groove. It has a two-layer structure in which overlaps the upper insulating layer formed, and that is formed with a lower low viscosity resin viscosity than the resin in which the lower insulating layer forms the upper insulating layer semi conductor substrate. A semiconductor substrate having a plurality of grooves formed along a scribe line,
A unit region in contact with at least one of the plurality of grooves, and
A wiring electrode partially disposed in the unit region,
The plurality of groove parts have a wide structure in which a wide part wider than the groove lower part including the bottom part is formed at the entrance,
In the plurality of grooves, the wide portion is formed in the entire length direction of the entrance,
It further has an insulating layer formed by filling the plurality of grooves with resin without gaps, and the insulating layer is formed on the inner side of the wide portion and the lower insulating layer formed on the inner side of the lower portion of the groove. It has a two-layer structure in which overlaps the upper insulating layer formed, and that is formed with a lower low viscosity resin viscosity than the resin in which the lower insulating layer forms the upper insulating layer semi conductor substrate. The unit region is formed as a device region having a semiconductor device,
A surface insulating layer that is formed so as to cover the device region and forms a surface layer of the semiconductor substrate,
3. The semiconductor substrate according to claim 1 , wherein the surface insulating layer is integrally formed using the same resin as the upper insulating layer without joints. The semiconductor substrate according to claim 1 , wherein the wiring electrode has an extended terminal portion that extends from the unit region to the inside of the groove portion. The wiring electrode, the device region from having an extended terminal portion is extended to the inside of the groove, and the surface insulating layer according to claim 3 which is formed in a convex shape that have been raised above the surface of the The semiconductor substrate as described. The wiring electrode protrudes outward from the surface of the surface insulating layer, intersects with the surface of the surface insulating layer, protrudes outward from the surface of the surface insulating layer, and the surface The semiconductor substrate according to claim 5 , further comprising: a top end surface along a surface of the insulating layer; and a buried portion that enters inside the surface of the surface insulating layer. A connection pad connected to the semiconductor device;
A connection hole is formed at a position where the connection pad is formed, and a protective insulating layer is provided on the lower side of the surface insulating layer so as to cover the device region;
The semiconductor substrate according to claim 5 , wherein the wiring electrode has an electrode pad having an extended height from the outside of the surface insulating layer to the connection pad. About the substrate before processing on which the semiconductor device is formed,
A first groove portion forming step of forming a plurality of first groove portions having a first width and a first depth along the scribe line;
A second groove having a second width wider than the first width at the entrance of the plurality of first grooves and a second depth shallower than the first depth; A second groove forming step to be formed;
An insulating layer forming step of forming an insulating layer inside the first groove portion and the second groove portion by applying a resin to the surface on the side where the first groove portion and the second groove portion are formed;
A wiring electrode forming step of forming a wiring electrode connected to the semiconductor device after the insulating layer;
Wherein the insulating layer formation step, prior to applying the resin, that to form a lower insulating layer on the inside of the first groove a low viscosity resin lower viscosity than the resin is applied to the surface half A method for manufacturing a conductor substrate. In the insulating layer forming step, a surface insulating layer is formed of the resin on the surface on which the first groove and the second groove are formed,
9. The method of manufacturing a semiconductor substrate according to claim 8 , wherein, in the wiring electrode formation step, the wiring electrode is formed in a convex shape that rises above the surface of the surface insulating layer. In the wiring electrode forming step, an extended terminal portion extending from the device region in contact with at least one of the plurality of first groove portions to the first groove portion is above the surface of the surface insulating layer. 10. The method of manufacturing a semiconductor substrate according to claim 9 , wherein the semiconductor substrate is formed in a raised convex shape. A laminated device wafer is formed by laminating at least two semiconductor substrates produced by the production method according to claim 10 ;
A cross-section of the insulating layer having a two-layer structure including the lower insulating layer on a cut surface when the laminated device wafer is cut along the first groove, and the wiring electrodes formed on the semiconductor substrates. The device block is produced by making the end face appear,
A method for manufacturing a layered chip package, wherein connection electrodes for connecting end faces of the respective wiring electrodes are formed on the cut surface of the device block. 12. The method of manufacturing a layered chip package according to claim 11 , wherein when the device block is manufactured, the end face of the wiring electrode appears as a protruding end face protruding outward from the surface of the surface insulating layer.