JP5615367B2 - High resolution output driver - Google Patents

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority to US Provisional Patent Application No. 61 / 242,319, “Fine Granularity Voltage-Mode Transmitter Equalizer”, filed Sep. 14, 2009, which is incorporated herein by reference. Incorporate into.

The present invention relates generally to the field of electronic communications, and more specifically to an output driver for signal transmission between integrated circuit elements.

FIG. 1 is a diagram of a conventional push-pull output driver 100 used to output information bearing signals from one integrated circuit (IC) element to another via a chip-to-chip signaling link. It is. The output driver is designed to match a specified output impedance, equalization range, and impedance calibration range, with 4-bit resolution in both equalization and impedance calibration. Internally, the output driver includes two parallel driver elements. One is a driver element 101 dedicated to transmitting the target data bit (d _n ), and the other is a variable strength post-tap equalized signal (ie, transmitted) according to an equalizer control value (“eq”). An “equalization” driver element 103 to contribute to d _{n + 1} ), sourced by the next data bit. Referring to detail view 105, the equalization driver element has four driver components 109 that contribute to pull-up or pull-down currents equal to α / 2, α / 4, α / 8, and α / 16, respectively. Implemented as a 4-bit DAC (digital / analog converter), α is the maximum post-tap equalization current contribution (eg, the maximum amount of output signaling current sourced or sinked by the post-tap assignment sub-driver) . As shown, the individual bits of the equalizer control value are fed to a separate multiplexer 107 to select either the post tap or the main tap as the data source for the corresponding DAC driver component, and thus , In increment α / 16, ranging from approximately α (ie, a post tap applied to all DAC driver components) to zero (a main tap applied to all DAC driver components).

The pull-up and pull-down loads that form the equalization driver component 109 are nominally sized to match the specified output impedance, Z _TERM , but process variations, temperature, and voltage (collectively, (Referred to as “process variation”) may result in an actual impedance that is arbitrarily different from the specified value, and thus an impedance discontinuity that generates noise that degrades signaling performance. To avoid this result, each of the dedicated driver element 101 and equalizer driver component 109 itself is a given driver component (by ± β, which is the maximum and minimum predicted process variation or “process corner” ( Thus, implemented by an impedance calibration DAC 112 that allows adjustment of the actual impedance of the overall driver element). As a result of this arrangement, each of the calibration DAC driver components (113, 115) (which is itself a slice of a given equalization driver element 109) is further sliced into sub-driver components of the impedance calibration DAC. As a result, the α / 16 DAC driver component itself occupying a percentage of the overall output driver size, α / 15, is sliced into a number of sub-driver components, the minimum of which is the proportion of α / 16 driver component, Occupies 2β / 15 and thus 2βα / 225. In order to avoid scaling errors, the minimum sub-driver component is typically 117 ₀ (single pull-up and pull-down transistors, each with unit conductance G _u ), 117 ₁ (net conductance 2G _u To implement larger sub-driver components, as shown in ₂ parallel pull-up transistors to establish), 117 ₂ (4 parallel pull-up / pull-down transistors to establish net conductance 4G _u ) , Replicated in multiple instances (thermometer coded). Hence, the overall driver is divided into (Q _EQ * Q _CAL ) / 2βα slices or branches (Q _EQ and Q _CAL , which are the quantization steps required in the equalizer and impedance calibrator, respectively) , Have a uniform conductance G _u (or resistance 1 / G _u ), and the individual quantity of those branches (ie 1, 2, 4, 8, 16, 32, etc.) is impedance according to a defined resolution. Operates as an inseparable unit for quantizing the calibration and equalization range.

Although acceptable in some signaling applications, the aforementioned driver arrangement presents several implementation challenges as process geometry shrinks. First, the net transistor width (ie, the desired termination impedance, W _PHYS corresponding to Z _TERM ) can be subdivided into the required number of branches without violating the process minimum. It may be insufficient. Also, the transistor length may be expanded to overcome this limitation, but such expansion exponentially increases the driver's overall driver size, thus reducing the substantial die area and power consumption penalties. suffer. Similarly, a large number of driver branches demand pre-drivers that are large and require a lot of power. That is, area and power penalties are typically doubled by many parallel output drivers 100 included in the IC signaling interface.

The present invention is illustrated by way of example and not limitation in the accompanying drawings, in which like reference numerals refer to like elements.
It is a figure of the conventional output driver. FIG. 4 is a diagram of a hierarchical output driver implemented using a differential equalizer element and reducing the required number of driver branches to less than half compared to an implementation with a uniform equalizer element. FIG. 2B is a conceptual diagram of a differential element approach applied to FIG. 2A. FIG. 5 is a comparison diagram of net transistor width subdivision in a differential equalizer element driver and subdivision provided using a uniform element approach. FIG. 6 is a diagram of a hierarchical output driver implemented using a differential impedance calibration element and again reducing the required number of driver branches to less than half compared to an implementation with a uniform equalizer element. FIG. 3B is a conceptual diagram of stepwise calibration achieved using the differential element approach of FIG. 3A. FIG. 6 is a comparison diagram of net transistor width subdivision in a differential calibration element driver and subdivision provided using a uniform element approach. FIG. 6 is a diagram of yet another hierarchical output driver embodiment, in this case having a differential element impedance calibration sub-driver nested within a differential element equalizer, and implementation based on a uniform equalizer element Compared with, the required number of driver branches is reduced by about 80%. FIG. 4B is a comparison diagram of net transistor width subdivision in a nested differential element DAC output driver and the subdivision provided using the uniform element approach shown in FIG. 4A. FIG. 4 is an illustration of an alternative technique for extending the range of interest using non-uniform conductance. FIG. 4 is an illustration of an alternative technique for extending the range of interest using non-uniform conductance. Of an alternative embodiment of an output driver where impedance calibration and equalization is implemented in each parallel part in the overall output driver, thus resulting in a bi-directionally adjacent DAC rather than hierarchically to a nested DAC. FIG. FIG. 4 is a diagram of a physical arrangement of driver branches that may be used to implement an equalizer and impedance calibrator in a bi-directional output driver embodiment. FIG. 2 is a diagram of a target driven equalizer calibration engine with an impedance calibration engine. FIG. 7B is a diagram of an impedance calibration operation provided by the impedance calibration engine of FIG. 7A. FIG. 7B is a diagram of equalizer calibration provided by the target driven equalizer calibration engine of FIG. 7A. FIG. 6 is a diagram of an alternative embodiment of an equalization calibrator that may be used to calibrate an equalization sub-driver in a bi-directional output driver. Illustration of an alternative equalizer scaling embodiment in which impedance calibration settings are fed into equalizer scaling logic and applied therein to anticipate or determine a desired scaling maximum setting for the equalizer. It is. FIG. 5 is a diagram of an example scaling engine or scaling logic circuit that looks up a scaled equalizer step size based on values determined by an equalizer calibration engine or an impedance calibration engine. Impedance calibration settings (eg, cal_pu and / or cal_pd) are fed into the equalizer scaling logic and applied therein to predict (or determine) the desired scaling maximum setting for the equalizer FIG. 4 is a diagram of an alternative equalizer scaling embodiment being performed. FIG. 6 is a diagram of an exemplary implementation of a differential element driver branch. FIG. 6 is a diagram of an alternative implementation of a differential element driver branch. FIG. 4 is a diagram of an exemplary approach for determining G ₀ -G _N-1 for a given differential element DAC and used, for example, in an equalization sub-driver or impedance calibration sub-driver. FIG. 3 is a diagram of an exemplary embodiment of a bi-directional output driver having a differential element impedance calibration DAC, a differential element equalizer DAC, and a set of fixed sub-drivers. FIG. 12B is a diagram of specific impedance values, R0-R12, that may be used to provide a calibration range, described with reference to FIG. 12A.

High resolution output drivers implemented with a relatively small number of sub-driver branches or slices are disclosed in various embodiments. In some embodiments, the number of sub-driver slices (also referred to herein as driver slices or driver branches) has a nominal impedance that is substantially greater than the quantization step and is greater than the quantization step. Through the use of non-uniform sub-driver load elements that are substantially small, only the impedance step, differing incrementally from each other, are reduced without sacrificing range critical resolution. In one such embodiment, such a “differential element” or “non-uniform element” sub-driver slice implements individual elements of an n-choose-k equalizer, and each such differential element sub-driver slice. Is implemented by a uniform element impedance calibration DAC. In another embodiment, each component of the uniform element equalizer is implemented by a differential element impedance calibration DAC, and in yet another embodiment, each component of the differential element equalizer is a differential element. Implemented by an impedance calibration DAC, all such “hierarchical” embodiments have a reduced number of driver slices compared to the output driver of FIG.

In an additional set of embodiments, equalization and impedance calibration functions are implemented bi-directionally in separate parallel set driver branches, rather than the nested “DAC in DAC” arrangement of the hierarchical embodiment. The Through such a bi-directional arrangement, double the equalizer and calibrator quantization (ie, the range divided by resolution) is avoided, and dramatically the sub-driver slice required to meet the specified range and resolution. Decrease the total number of. Further, the equalization range and resolution may be implemented by differential slices or uniform slices, and the calibrator range and resolution may also be differential slices or so that multiple bi-directional embodiments are possible. It may be implemented by uniform slices. In addition, dual-loop calibration, which independently calibrates the impedance and equalization portion of the output driver, and a scaled calibration technique that automatically adjusts the equalizer control values according to process variations determined during impedance calibration Various calibration techniques and circuits are disclosed in connection with the bi-directional embodiment. These and other embodiments are described in further detail below.

FIG. 2A is a diagram of a hierarchical output driver 200 that is implemented using a differential equalizer element and reduces the required number of driver branches to less than half compared to an implementation with a uniform equalizer element. is there. As shown, the output driver 200 includes a dedicated driver component 201 and an equalizer driver component 203, each with data bits, d _n (ie, “main tap”, at a given transmission interval). A source of data to be transmitted) and an impedance control value ("cal"). In addition, the equalizer driver component 203 is coupled to a single post-tap (ie, receives data bits, d _{n + 1} , transmitted in the immediately subsequent transmission interval) in the illustrated embodiment, and an equalizer. The control value “eq” is received. In the various embodiments below, a single post tap example is discussed, but in all such embodiments, the equalizer driver component may additionally or alternatively include one or more different post taps. (Eg, supplying post-tap data d _{n + 2} , d _{n + 3,} etc.) and / or one or more pre-tap (eg, supplying pre-tap data d _n−1 , d _n−2, etc.) The equalizer control value includes a control vector, if necessary, to define the number of equalizer driver branches assigned to a given data tap.

As shown in detail view 205, equalizer driver components 203 each have a set of differential element sub-drivers 206 (G ₀ -G ₅ , thus having a nominal conductance (or admittance) G _NOM . In the example shown, but more or fewer driver elements may be provided), but may be perturbed from there by a different offset value, Δ _i , The change in offset value between successive driver elements “i” and “i−1” (ie, Δ _i −Δ _i−1 ) generally results in a desired equalization resolution (ie, a desired “equalization step”). ) Further, an input equalization control value (ie, an equalizer having a 4-bit value “eq [3: 0]” in this embodiment, but having a certain number of bits M greater than or less than 4) Control value may alternatively be used) expands the input control value into a selection code with configuration bits, s [5: 0], and the data source (post) for each differential element sub-driver 206 The tap or main) is supplied to the decoder 209. By this arrangement and by establishing a differential offset value (Δ _i ) such that different combinations of differential element sub-drivers 206 result in non-redundant equalization values, 63 different differential element sub-drivers 63 A combination (ie, 2 ^N -1 where N is the number of differential element sub-drivers), otherwise an equalizer is connected to 2 ^M -1 uniform sub-driver elements (ie Can be used to approximate the incremental equalization step, achieved by dividing into 15 uniform sub-driver elements, controlled in a set of 1, 2, 4, and 8), ascending order, etc. Of the output signaling current that is sunk or sourced in response to the state of the post-tap data. That is, in the particular example shown, the selection code corresponding to 15 of the 63 possible differential element sub-driver combinations determined to best approximate the desired quantization of the equalizer range is: Stored in decoder 209 so that a given equalizer control value, eq [3: 0] forms a lookup table that indexes (or “looks up”) the best match selection code. May be. The individual bits of the indexed selection code are applied to multiplexer 207, optionally switchably connecting each differential element sub-driver to main or post-tap, thereby establishing the desired equalizer settings. .

FIG. 2B is a conceptual diagram of the differential element sub-driver approach. In effect, the goal is to build a stepwise recursion through the equalization range (ie, quantize the range) using a conductance that is substantially larger than the conductance corresponding to the equalization step itself. . Thus, instead of assigning a uniform conductance increment number to the post-tap (or main depending on the recurrence direction), each is substantially larger than the increment conductance step (ie, in the example shown, each increment The difference between the conductance elements of at least twice the conductance step) is used to establish a stepwise recurrence, thereby quantizing the equalization range. Observations on differential element quantization include, but are not limited to, the following (none of the following necessarily require a given implementation):
The conductance (and hence the size), G _du , of the minimum differential element sub-driver 206 is approximately twice the unit conductance, G _uu , in the uniform element sub-driver implementation.
The differential conductance between any two nearest sized differential element sub-drivers (ie, G _i -G _i-1 ) is less than or equal to the conductance corresponding to the desired equalization step.
An exclusive combination of differential element sub-drivers, each having the same number of differential element sub-drivers, is used to implement incremental conductance values from one step to the next within the equalization range (For example, as shown in FIG. 2B, the differential element sub-drivers 0 and 1 are selected or interlocked to affect the conductance corresponding to a given equalization step. Element sub-drivers 2 and 4 are selected to affect the next higher step conductance).
• The number of selection signals (ie, multiplexer control signals) in a given state is monotonically grading and affects the grading through the equalization range (ie, the differential element sub-driver has Assuming that it is assigned to the equalizer stack in response to the assertion, the number of select signals asserted for each of the 13 equalizer steps shown is 1, 1, 2, 2, 2, 3 3, 4, 4, 4, 5, 5, 6, in contrast, the number of asserted bits in the equalizer control value is 1, 1, 2, 1, 2, 2, 3 , 1, 2, 2, 3, 2, 3, 3, 4 and non-monotonic recurrence).
The freedom to choose any subset k of N differential element sub-drivers, k tends to be approximately halfway between 1 and N (ie k = N / 2), so resolution tends to be most important Affects the N-choose-k function, which provides the highest resolution (ie, the maximum number of combinations) when at the center of the quantization range.
In some implementations, resolution at both extremes of the quantization range, including that shown in FIG. 2B, may be sacrificed.
In some implementations, including those shown in FIG. 2B, the sum of the conductances of the differential element sub-drivers matches or corresponds to the quantization range (ie, N * G _NOM is the quantization range) a net conductance corresponding to _equal to _{G RANGE,} or equal approximately).
Incremental equalization adjustment (ie, equalizer quantization) is accomplished by assigning a continuous set of differential element sub-drivers (ie, main to post-tap data), where each sub-driver has the desired equalization Contributing to a conductance substantially greater than the conductance corresponding to the step size, the conductance difference between any two consecutively selected sets of differential element sub-drivers approximately matches the desired equalization step size (As opposed to incremental equalization achieved by incrementing the number of uniformly sized elements assigned to post-tap data)

Referring again to FIG. 2A, each of the differential element sub-drivers 206 in the equalization driver component 203 is implemented by a separate uniform element impedance calibration DAC, as shown in the detailed view 220. That is, each differential element sub-driver 206 is implemented by a separate impedance calibration DAC, which itself has sub-drivers formed by individual quantities of uniform element driver slices. In one embodiment, (either to receive a _{d n} or depicted as _{d n + 1 (d x)} ) selectively with the calibration sub-driver 223 is enabled parallel conductance each impedance calibration DAC (1- β) * G _i (G _i includes a base calibration sub-driver 221 to contribute to the i th differential element equalization sub-driver 206 intended conductance). As shown in detail view 240, respectively calibration sub-driver (241 ₀ and 241 _1), ^{2 j} uniform loading elements 249,251 (j = 0,1,2, ...) is data tap, the _{d x} It includes logic (eg, gates 245 and 247) to enable or disable the source or sink (ie, “contribute”) output current via output node 252 depending on the state. Explicit instances of load elements 249, 251 such as 1, 2, 4, etc. that have unitary pull-down or pull-up conductance (G _d-el ) are coupled in parallel within a given calibration sub-driver 241, in which The desired impedance may be implemented, or a singular load element is provided for each calibration sub-driver, and the load element in driver 241 _j is 2 ^j * G _d-el (ie, j = 0, 1, 2, Note that it may have a conductance of. Thus, the output driver 200 has a hierarchical architecture (or “nested” so that the configuration DAC driver itself of the equalization driver component 203 is implemented by a separate impedance calibration DAC, as shown at 220. DAC "architecture). While not specifically shown, dedicated driver component 201 is similarly implemented by the impedance calibration DAC, all such impedance calibration DAC _spans from _G DC _(1-β) in the range of _G DC (1 + _β) ( May be designed). G _DC is the nominal net conductance of a given driver component.

FIG. 2C shows the net transistor width subdivision (ie, W _PHYS = (1 + β) W _TERM ) in the differential element equalizer shown at 205 in FIG. 2A and the _subdivision resulting from using the uniform element approach. FIG. As shown, compared to 225 driver branches (15 uniform equalizer DAC components, each subdivided into a separate set of 15 impedance calibration branches), 90 driver branches (6 Differential element equalizer DAC sub-drivers, each subdivided into a separate set of 15 impedance calibration branches) is only required to span the equalizer range and thus 60% of the number of driver branches Bring about a reduction. More specifically, under the uniform element approach, the equalizer range corresponds to a portion of the net transistor width, αW _PHYS , and thus 15 uniform element equalizer sub-drivers (ie, Q _EQ = 15), it is quantized to the width of (α / 15) W _PHYS . Each of their widths is further quantized over a range of 2β (ie ± β) by 15 uniform impedance calibration elements (ie, Q _CAL = 15 for a 4-bit resolution impedance calibration implementation) The minimum transistor width, W _u-el, is (2βα / 225) W _PHYS . Some headroom may be obtained by having equalizer quantization (eg, over a range of 0 to 33% (α = 0.33), with about 5% resolution at full scale, etc.) The required transistor slice is still approximately (1/525) W _PHYS (assuming an acceptable process variation of ± 30%). Assuming that the net transistor width corresponding to the specified 40 ohm output impedance in an exemplary 40 nm (40 nanometer) manufacturing process is about 13.6 microns (13.6 μm), the required basic transistor width is Will be about 26 nanometers and will therefore be below the minimum acceptable feature size (ie, 40 nm). In contrast, the minimum transistor width required under the differential element approach, W _d-el, is approximately twice W _u-el and is therefore required for implementation in the exemplary 40 nm manufacturing process. Get critical headroom. It should be noted that in the several embodiments described below, the above specifications and dimensions, which are discussed further, are provided for illustrative purposes only and may be changed in alternative embodiments. I want to be.

FIG. 3A illustrates a hierarchical output driver 280 having an impedance calibration circuit implemented with a differential element sub-driver to reduce the required number of output driver branches to less than half compared to a uniform element implementation. FIG. As in the embodiment of FIG. 2A, the output driver includes a dedicated driver component 281, an equalizer driver component 283, the respective main tap data, and _{d n,} impedance control value ( "cal") And are coupled to receive. In addition, the equalizer driver component is concatenated to a single post-tap data source (ie, receives the data bits, d _{n + 1} transmitted in the immediately subsequent transmission interval) and equalized in the illustrated embodiment. Receive the instrument control value.

As shown in detail view 285, the equalizer driver component includes a set of binary weighted DAC drivers, each of which includes a uniform sub-driver load element (which may include a binary scaled weight of the load element). Binary weighted numbers (in this example, 1, 2, 4, or 8). With this arrangement, the constituent bits of the binary control word are applied directly to the individual multiplex element 287 and selectively (switched) either main or post-tap data source to the input of the corresponding uniform element sub-driver 289. ) Linking may be enabled. Thus, the specified equalization range is quantized into 15 increment equalization steps, each quantization step adding an additional one of the uniform load elements in the sub-driver 289 to the post-tap data source (or Assign to the main data source) according to the recurrence direction.

Referring to detail view 291, each uniform element sub-driver in equalizer driver component 283 is itself implemented using a differential element impedance calibration sub-driver. That is, instead of employing 15 uniform calibration driver loads (including binary weighted loads, including implementation) to achieve 4-bit impedance calibration resolution, an exemplary set of N = 6 differential element sub-drivers Provided. Each of the N differential element sub-drivers G _i has a nominal conductance (or admittance) G _NOM but is perturbed from the nominal value by a separate offset value, Δ _i , (ie, G _i = G _NOM + Δ _i ). , The change in offset value between the continuous differential element sub-drivers G _i and G _i-1 (ie, Δ _i −Δ _i−1 ) generally results in a desired impedance resolution (ie, a desired incremental impedance calibration step). ) Furthermore, the input impedance control value (ie, in this example, the 4-bit value “cal [3: 0]”, but a control value having a certain number of bits, M greater than or less than 4, is replaced by As an enable value, e [5: 0] with configuration bits to control (ie enable or disable) each differential element sub-driver. This is supplied to a decoder 293 for development. By establishing a differential offset value (Δ _i ) with this arrangement and so that different combinations of differential element sub-drivers result in non-redundant calibration values, the 63 different combinations of differential element sub-drivers are , Otherwise achieved by dividing the calibrator into 2 ^M −1 uniform driver elements (ie, 15 uniform driver elements grouped into 1, 2, 4, and 8 sets). Resulting in an ascending impedance calibration profile that can be used to approximate the incremental calibration step. That is, in the particular embodiment shown, an enable value corresponding to 15 of 63 possible differential driver combinations determined to best approximate the desired quantization of the calibration range (ie, 2βG _{PHYS Where} G _PHYS is the net transistor width, net conductance corresponding to W _PHYS , and β is the maximum process variation to be compensated) is stored in decoder 293, thereby giving a given The impedance control value may form a lookup table that indexes (or “looks up”) the best match enable value. As shown in the detailed diagram 300, each bit of the indexed enable value applies to the logic gates 303 and 305 or other switching circuits within a separate one of the differential element sub-drivers 297 ₀ -297 _5. Enable or disable switchable signal transmission contribution from the differential element sub-driver. As shown (and discussed in detail below), each individual differential element sub-driver is implemented by one or more identical switching transistors (ie, identical PMOS transistor 312 and identical NMOS transistor 314). The differential offset includes pull-up and pull-down load elements 307, 308, which are achieved through a length modulation of the polysilicon resistance element 316.

FIG. 3B is a conceptual diagram of stepped impedance calibration achieved using a differential element sub-driver approach. As shown, the selection of a particular predetermined combination of differential element sub-drivers uses an element having a conductance substantially greater than the conductance corresponding to the impedance calibration step (“Z-Cal step”) itself, A stepwise recursion is achieved through the impedance calibration range (ie, the range is quantized). Thus, instead of assigning an incremental number of uniform element conductances, G _u-el, to the post-tap (or main, depending on the recurrence direction), each has a conductance substantially larger than the increment conductance step (ie, In the example shown, the difference between nominally equal sized differential elements is used to establish stepwise recursion, each at least twice the incremental conductance step. Observations on differential element quantization include, but are not limited to, the following (none of the following necessarily require a given implementation):
The minimum required load element, G ₀ conductance (and hence the size) is approximately twice the size of the minimum required load element, G _u-el in the uniform element implementation.
The differential conductance between any two nearest sized differential element sub-drivers (ie, G _i -G _i-1 ) is less than or equal to the conductance of the impedance calibration step.
An exclusive combination of differential element sub-drivers, each having the same number of differential element sub-drivers, is used to implement incremental conductance values from one step to the next within the impedance calibration range. (For example, as shown in FIG. 3B, differential element sub-drivers 0 and 1 are enabled and all others are disabled to affect the conductance corresponding to a given impedance calibration step. Differential element sub-drivers 2 and 4 are enabled and all others are disabled to affect the next higher step conductance)
The number of enable signals (ie, multiplexer control signals) in a given state is monotonically gradual and affects the grading through the impedance calibration range (ie, the differential element affects the assertion of the corresponding enable signal) Assuming that it is enabled in response to contribute to the signal to the output node of the output driver, the number of enable signals asserted for each of the 13 impedance calibration steps shown is 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, in contrast, the number of asserted bits of the impedance control value is 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 and non-monotonic recurrence).
The freedom to choose any subset k of the N differential element sub-drivers, k is approximately halfway between 1 and N (ie k = N / 2), so the process variation is most statistically When at the center of the quantization range, which is likely to decrease, it affects the N-choose-k function, which provides the highest resolution (ie, the maximum number of combinations).
In some implementations, resolution at the extremes of the quantization range, including that shown in FIG. 3B, may be sacrificed.
In some implementations, including those shown in FIG. 3B, the sum of the conductances of the differential element sub-drivers matches the quantization range (ie, N * G _NOM is the net conductance corresponding to the quantization range). _Is equal to or approximately equal to G _RANGE ).
The incremental impedance calibration step enables a continuous set of differential element sub-drivers (ie, switches off a given set of differential element sub-drivers and switches on a subsequent set of differential element sub-drivers) Each differential element sub-driver has a conductance substantially greater than the conductance corresponding to the desired calibration step size, and between any two consecutively selected sets of differential element sub-drivers. The conductance difference is approximately equal to the desired impedance calibration step size (as opposed to incremental impedance calibration, achieved by incrementing the enabled number of uniform element sub-drivers).

FIG. 3C is a _comparison of net transistor width subdivision in a differential element impedance calibration circuit (ie, W _PHYS = (1 + β) W _TERM ) and the subdivision effected using the uniform element approach. Again, compared to 225 driver branches in the uniform element calibration approach (15 uniform equalizer DAC components, each subdivided into a separate set of 15 uniform element calibration sub-drivers), 90 Only 15 driver branches (15 uniform equalizer DAC components, each subdivided into a separate set of 6 differential element calibration branches) are required to span the equalizer range, and therefore This results in a 60% reduction in the number of driver branches required to span the conversion and calibration ranges. As in the embodiment of FIGS. 2A-2C, the minimum transistor width required under the differential element calibration approach, W _0, is approximately twice the minimum width required when a uniform element calibration sub-driver is applied. (Ie, W ₀ ≈2W _u-el ), and thus can lead to the headroom needed for implementation in modern processes.

FIG. 4A is a diagram of another embodiment of a hierarchical output driver embodiment, where a number of differentials nested within separate differential element sub-drivers 353 of equalization driver component 343. With an element impedance calibrator 360, the required number of driver branches is reduced by approximately 80% compared to implementations based on uniform equalizer elements. As in the embodiment of FIGS. 2A and 3A, the nested differential element output driver 341 includes a dedicated driver component 341 and an equalizer driver component 343, each with a main tap (data bit, connected to d _n to receive) is coupled to receive impedance control value ( "cal"). In addition, the equalizer driver component 343 is coupled to a single post-tap (ie, receives a data bit, d _{n + 1} transmitted in the immediately subsequent transmission interval) in the illustrated embodiment, and an equalizer. The control value “eq” is received.

As shown in detail diagram 344, the equalizer driver component is implemented by an exemplary set of six differential element sub-drivers, each having a nominal conductance (or admittance) _GNOM , but with different offset values. , Δ _{i is} perturbed therefrom, and the change in offset value (ie, Δ _i −Δ _i−1 ) between the continuous driver elements G _i and G _i−1 is generally the desired equalization resolution (ie, , Desired increment equalization step) or less. As in the embodiment of FIG. 2A, an input equalization control value (ie, a 4-bit value “eq [3: 0]” in this example, but a certain number of bits greater than or less than 4), An equalizer control value with M may alternatively be used), but expands the input control value into a selection code, s [5: 0] with configuration bits, and each differential element sub-driver 353 Is supplied to a decoder 351 which selects a data source (post-tap or main) for. With this arrangement, and 63 different combinations of differential element sub-drivers, by establishing a differential offset value (Δ _i ) such that different combinations of differential element sub-drivers result in non-redundant equalization values. (Ie, 2 ^N -1 combinations, where N is the number of differential element sub-drivers), otherwise the equalizer is connected to 2 ^M -1 uniform driver elements (ie, 1 An ascending equalization profile that can be used to approximate the incremental equalization step achieved by dividing into 15 uniform driver elements grouped into 2, 4, and 8 sets) Can bring. That is, in the particular embodiment shown, the selection code corresponding to 15 of the 63 possible differential driver combinations determined to best approximate the desired quantization of the equalizer range is given by Application of the equalizer control values may be stored in the decoder 351 to index (or “look up”) the best match selection code. The individual bits of the indexed select code are applied to multiplexer 352, as shown, and optionally switchably couple each differential element sub-driver to a main or post-tap data source, thereby providing the desired Bring up equalizer settings.

Referring to the detailed view 359, each of the differential element sub-drivers 353 in the equalizer driver component 343 itself is implemented using a differential element impedance calibration sub-driver, and thus a nested pair difference A dynamic element DAC (ie, a differential element DAC within the differential element DAC) is provided. Each of the N differential element sub-drivers “i” has a nominal admittance (or conductance) _GNOM , but is perturbed from the nominal value by a separate offset value, Δ _i , and the continuous sub-driver elements G _i and G _i− The change in offset value between ₁ (ie, Δ _i −Δ _i−1 ) is generally less than or equal to the desired equalization resolution (ie, the desired increment equalization step). Further, the input impedance control value (ie, in this example, the 4-bit value “cal [3: 0]”, but a control value having a certain number of bits, M greater than or less than 4, is replaced by Expands the input control value into an enable code with configuration bits, e [5: 0], and controls (ie, enables or disables) each differential element sub-driver. This is supplied to the decoder 369. By this arrangement and by establishing a differential offset value (Δ _i ) such that different combinations of differential element sub-drivers result in non-redundant equalization values, different combinations of 63 differential element sub-drivers Otherwise achieved by dividing the calibrator into 2 ^M −1 uniform driver elements (ie, 15 uniform driver elements grouped into 1, 2, 4, and 8 sets). Resulting in an ascending impedance calibration profile that can be used to approximate the incremental calibration step. That is, in the particular embodiment shown, the enable code corresponding to 15 of 63 possible differential driver combinations (ie, 2βG _PHYS) determined to best approximate the desired quantization of the calibration range. _Where G _PHYS is the net transistor width, net conductance corresponding to W _PHYS , β is the maximum process variation to be compensated), and the application of the given impedance control value is the best match enable code It may be stored in decoder 369 for indexing (or “look-up”). As described above with reference to FIG. 3A, each bit of the indexed enable code is applied to a logic or switching circuit within a separate one of the differential element sub-drivers 365, which differential element sub-drivers. The signal transmission contributions from may be switchably enabled or disabled (the base sub-driver 363 is involved during the transmission interval regardless of the calibration control value). As discussed in further detail below, each individual sub-driver element is implemented by one or more identical switching transistors, each with a differential conductance offset, Δ _i , achieved through length modulation of the polysilicon resistance element. May be.

FIG. 4B illustrates the net transistor width subdivision (ie, W _PHYS = (1 + β) W _TERM ) in the nested differential element output driver shown in FIG. It is a comparison figure with a division | segmentation. In a nested differential element implementation, 225 driver branches in a uniform element approach (15 uniform element equalizer DAC components, each subdivided into a separate set of 15 uniform element calibration branches) ) Only 36 driver branches (6 differential element equalizer DAC sub-drivers, each subdivided into a separate set of 6 differential element impedance calibration sub-drivers) And required to provide impedance calibration, thus reducing the number of required driver branches by about 85%. Further, the minimum conductance differential element equalizer sub-driver (ie, 353, G _E0 ) has about twice the width (ie, twice the conductance) of the corresponding component in the uniform element equalizer. , The minimum differential element calibrator sub-driver (ie, 365G ₀ ) can also be used otherwise (ie, as in the embodiment of FIG. 2A), approximately twice as wide as the uniform calibrator element Because of the impedance calibration of each equalizer sub-driver 353, the minimum component width required to span the equalizer range is a nested uniform element equalizer, uniform element calibrator implementation. Is approximately a quarter of the minimum required component width (ie, a quarter width). That is, as shown in FIG. 4B, in a nested uniform element approach with 4 bit resolution in the equalizer and 4 bit resolution in the impedance calibrator, the equalization range αW _PHYS is Sliced to 15 equalization steps by the uniform element equalizer, and the 2β range in each equalization step is sliced to 15 components by the uniform element calibrator, and thus the minimum feature width, G _{u -El} = 2 [beta] [ _alpha] W _PHYS / 225 is established. In contrast, using a nested differential element equalizer and calibrator DAC, the minimum feature width, W _0, is about 4 W _u-el and thus G ₀ is about 4 G _u-el. It is. As a result, the equalizer and calibrator range spans that range with the desired resolution (or nearly desired) without the need for transistor widths that violate the process minimum, and so on. May provide headroom for higher resolution implementations of the generator, impedance calibrator, or both.

In light of the quantization profiles shown in FIGS. 2B and 3B, it is clear that the minimum differential element conductance available to quantize the equalization or calibration range shown is greater than the initial and final steps. . In some embodiments, the loss of resolution at both poles of this range of interest is completely acceptable (in fact, the higher resolution achievable at the center of the quantized range is a favorable tradeoff). In other cases, unreachability of steps within the scope of interest may be less desirable.

5A and 5B are diagrams of alternative techniques for more fully quantizing the range of interest using non-uniform or differential element conductance. That is, the minimum differential element conductance (ie, G ₀ ) available to quantize the range shown in FIGS. 2B and 3B is the initial step and final required to span the range of interest at a given resolution. Because it is larger than the step, the range of interest is not fully quantized, as indicated by the lost first and last quantization steps. In contrast, as shown in FIG. 5A, the actual range spanned by the differential (non-uniform) element, the starting fixed conductance, G _FIX, is covered by G ₀ (ie, G ′ _RANGE > G _RANGE ). More fully quantize the range of interest without increasing the net transistor width (ie, providing a quantization step at the base of the range shown) when reduced to G ′ _FIX to exceed Is possible. That is, even if N * G ′ _NOM exceeds N * G _NOM by G ₀ , G ′ _Fix is G ₀ less than G _FIX and thus establishes equal overall conductance. Also, the range covered by N differential elements is expanded, but any loss of resolution may be compensated by increasing the number of differential element sub-drivers (N) used to cover that range. Good.

In FIG. 5B, in this case, the range of interest is even more fully quantized by increasing the range covered by G ₀ at both ends of the range of interest. This arrangement provides an equalization or impedance calibration step at points 384 and 385. Also, even if the net transistor size is currently extended by 2G ₀ beyond the size otherwise required to span the coverage, the additional width is to achieve R _term. The width / length ratio required without the transistor length infringing on the process minimum, which tends to be insignificant (representing a very small percentage) compared to the overall transistor width required for It does not result in an exponential increase in area that is brought about when expanded to achieve. Further, any loss of resolution due to the extended range may be offset by increasing the number of differential element sub-drivers used to span that range.

FIG. 6A shows an output driver in which impedance calibration and equalization is implemented in separate parallel parts of the overall output driver, thus resulting in bidirectionally adjacent DACs rather than hierarchically to nested DACs. FIG. 4 is an illustration of 450 alternative embodiments. Thus, as shown in detail view 451, the entire set of driver branches is divided into at least two parts, Z-CAL and EQ, which are required to match a defined termination impedance, Z _TERM. the remaining branches are arranged in "fixed" branch (i.e., the driver is enabled, is involved at all times when transmitting transmission data, comprising continuously main data, and d _n-only).

As shown in detail views 461 and 463, the equalizer DAC may be implemented using a uniform element sub-driver (detail view 461) or by a differential element sub-driver (detail view 463). . In a uniform element implementation, the equalizer DAC includes 2 ^N -1 uniform driver branches (ie, each with a separate pull-up element and a separate pull-down element, and the total pull-up load element is substantially In general, the overall pull-down load element is also uniform, but the pull-up in each branch takes into account the different PMOS / NMOS features and the corresponding pull-down element in that branch. As a unit, sourced by either main or post-tap data, and stepwise equalization in response to an incremental recurrence of the equalizer control value, EQ [3: 0] Includes groups of 1, 2, 4, or 8 load elements (in this example) that provide adjustment (or increment). As discussed, the group of load elements forming the binary weighted sub-drivers (α / 16, α / 8, α / 4, α / 2) can alternatively be pulled within the smallest sub-driver (α / 16). It may be implemented as a single element with a width that is a multiple (2x, 4x, 8x) of the width of the up / pull down element.

In the differential element implementation shown in detail FIG. 463, the input equalizer control values (eq [3: 0]) are in turn given a given N-choose-k combination of differential element sub-drivers, G ₀ -G _N-1 is selected and supplied to a decoder 481 (eg, a look-up table) that outputs a selection signal, s [5: 0] (in this six-element embodiment, a 6-bit value). In the example, N = 6). As described above, each of the N differential element sub-drivers includes a pull-down load element and a pull-up load element that are nominally sized to match the nominal conductance G _NOM and the deviation Δ _i therefrom, where N * G _NOM is Corresponding to the total conductance of that range (and possibly the amount of increment beyond the range of interest, as discussed with reference to FIGS. 5A and 5B). Each of the 2 ^N -1 possible differential element combinations is substantially larger than the minimum size load element required in the uniform element approach, respectively, by establishing Δ _i such that each yields a different net conductance. A set of load elements can be used to approximate the gradual recurrence provided by the uniform set of elements shown in detail view 461. Thus, a sequence of gradual equalization increments (respectively assigning a greater or less equalization contribution to the post-tap data source) may be achieved by selecting individual combinations of differential element sub-drivers, The combination has a net conductance that differs from the net conductance of the combination previously selected by the desired equalization step size (or approximation thereof).

Still referring to the equalizer DAC and its uniform and differential element implementations, in contrast to the equalizer DAC implementation shown in FIGS. 2A and 3A, each individual sub-driver (473 or 485) is Note that it is implemented without an underlying calibration DAC. Thus, the impedance of the individual sub-drivers forming the equalizer DAC may be variable depending on process variations, whether implemented by uniform elements or differential elements. This impedance variation can result in an equalization step by incrementing the equalizer control value to be larger or smaller than the desired step size. Furthermore, since the impedance calibrator as a whole serves to adjust the impedance of the bi-directional output driver (ie, does not adjust the impedance of each constituent sub-driver as in the hierarchical approach), the equalization step size is Even after the bidirectional output driver impedance is calibrated, it may remain different from the desired equalization step size. As discussed below, scaling errors in the equalization step size may be overcome through alternative equalizer calibration techniques. In one embodiment, for example, any scaling error is detected either by a closed loop equalizer calibration operation or the impedance calibration itself and is corrected by applying a reaction scaling factor. In another embodiment, the scaling error minimizes the error between the actual equalization output and the target equalization output provided by an internal circuit or an external control circuit containing the bi-directional output driver 450. Is (or at least reduced) effectively ignored by providing a closed-loop equalization control (ie, control via negative feedback) that servos the equalizer control word to value.

Similar to the equalizer DAC, the impedance calibration DAC (“Z-Cal”) can be either a uniform element sub-driver or a differential element sub-driver, respectively, generally described above with reference to FIGS. 3A and 2A. May be implemented. Note that the impedance calibration range is intended to allow adjustment of the overall bidirectional output driver impedance, conductance, and therefore the overall driver transistor net width for a given pull-up or pull-down load element. Should be large enough to accommodate the slowest process corner. Thus, the net physical width of the bidirectional output driver may be expressed as W _PHYS = W _TERM (1 + β), where W _TERM is the nominal width of the net transistor corresponding to the target termination impedance, Z _TERM . Furthermore, since impedance calibration is intended to range from the fastest process corner to the slowest process corner, the impedance calibration range is W _TERM (1 + β) −W _TERM (1−β) = 2β W _TERM = (2β / (1 + β)) W _PHYS and the factor 2β / (1 + β) is referred to in FIG. 6 as λ (ie, λ = 2β / (1 + β)) and is assigned to the overall impedance calibration function Represents the percentage of physical transistor width (or net load element width), where β is the maximum expected process variation. In one embodiment, b = 0.3 (i.e., ± 30% tolerance) is the total portion of the physical output driver width allocated for impedance calibration = 2 * 30% / (1 + 0.3) = 54 %. From the point of view of the impedance calibration DAC, the difference by participating in a specific number of uniform load elements (eg 0 to 15 for a 4-bit DAC) or eg as described with reference to FIGS. 2A and 4A The range may be reached by participating in various combinations of dynamic element loads.

FIG. 6B is a diagram of a physical arrangement of driver branches that may be used to implement an equalizer and impedance calibrator in a bi-directional output driver embodiment. The driver branch is depicted as a uniform size, but this need not always be the case (ie, the branch or its constituent load elements are perturbed (or offset) from nominal to implement a differential element. You may). Also, αW _PHYS (part of the physical width of the set-up pull-up / pull-down load element assigned to the equalizer) and λW _PHYS (part of the physical width assigned to the impedance calibrator) are _expressed as W _PHYS (ie, , Α + λ <1), the remaining portion of the output driver width may be implemented as a “fixed” set of driver branches. That is, a set of driver branches with an aggregate width, W _FIX , may be provided to complement the portion of the driver assigned to the impedance calibration and equalization function, W _FIX = (1−α−λ) W _PHYS . As an example, if β = 30% and α = 33%, the remaining 12% of W _PHYS (ie, [1-0.33-2 * (0.3) / (1 + 0.3)] W _PHYS = 0.12W _PHYS ) is assigned to the main tap on a fixed basis (ie, it is not switched off for impedance calibration purposes or switchable between data sources for equalization purposes) .

Still referring to FIG. 6B, it can be seen that any of the following at least four possible configurations may be employed to implement a bi-directional output driver. Uniform element impedance calibration combined with uniform element equalization (referred to herein as “dual uniform element DAC embodiment”), uniform element impedance calibration combined with differential element equalization ( “Hybrid differential element equalizer embodiment”), differential element impedance calibration combined with uniform element equalization (“hybrid differential element impedance calibrator embodiment”), and combined with differential element impedance calibration Differential element equalization ("dual differential element DAC embodiment"). In addition, in dual uniform element DACs, the physical width allocated to bidirectional functions (equalization and impedance calibration) can be subdivided into uniform element sub-drivers to satisfy individual equalization and calibration range quantization. , May result in different size conductance elements within the two parts of the equalizer (ie, the uniform load element used to implement the equalizer is the uniform load element used to implement the impedance calibrator Note that they do not have to be the same (in fact they are not the same in the embodiment shown) as they do not have to be the same size as the load element). The same applies to the dual differential element DAC. The size of the differential element sub-driver provided to span the equalizer range need not be the same as the size of the differential element provided to span the impedance calibration range (in fact, in the illustrated embodiment, , Not the same). Also, although 4 bit resolution is shown for both calibration and equalization DAC, one or both may have higher or lower resolution. Further, the number of differential elements provided to span the two ranges (equalizer and calibrator) may differ from that shown and may be variable between the two DACs. Such an arrangement is discussed in the more specific embodiment shown in FIGS. 11A-11C.

In light of the lack of lower level calibration in the equalizer DAC in the bi-directional output driver of FIGS. 6A and 6B, the equalizer DAC may nevertheless provide the desired equalization range and resolution regardless of process variations. Be expected. To achieve this, the physical output driver may be implemented to meet the desired resolution at the slowest process corner, and therefore α (1 + β) W _TERM = αW _PHYS . One result of this implementation is that for any process factor faster than the slowest process corner, the range of the equalizer will exceed what is required. Furthermore, due to the bidirectional design of the output driver, an over-expansion of the equalizer range will remain even after the impedance calibration is complete. That is, switching the sub-driver branch on or off in the impedance calibration portion of the output driver does not affect the impedance of the equalizer DAC element as in the hierarchical embodiment of FIGS. 2A, 3A, and 4A.

In one embodiment described in more detail with reference to FIG. 7A, the lack of equalizer calibration is achieved by providing a feedback loop to drive the equalizer DAC output to a given target equalization voltage. Overcome. In another embodiment shown in FIG. 8A, the equalizer calibration voltage corresponding to the maximum desired equalization ratio (ie, the portion of the signal assigned to the post-tap data) in turn corresponds to the full scale equalization. Is provided to an equalizer calibration engine that determines the equalizer settings and then scales the input equalization settings accordingly. In the third embodiment shown in FIG. 8B, the equalizer range is scaled by the coefficients determined during impedance calibration. For example, if W _PHYS is determined to be 25% too large during impedance calibration (resulting in switching off a certain number of driver branches corresponding to 0.25 W _PHYS ), the same is true for full scale equalizer settings In addition, each step through the equalizer range is similarly scaled by 75%, up to 75% of the maximum possible setting.

FIG. 7A is a diagram of an impedance calibration engine with a target driven equalizer calibration engine, both integrated into an integrated circuit element that includes one or more bidirectional output drivers 620 ₀ -620 _N−1. Is done. The impedance calibration engine includes a pair of comparators 604, 606, a pull-up voltage simulator 603, a pull-down voltage simulator 605, a finite state machine 609 (“impedance calibration” state machine), and an impedance calibration driver 601. In the differential element embodiment, the impedance calibration engine also includes pull-up and pull-down look-up tables 611a and 611b, but the impedance of the corresponding pull-up and pull-down load elements in the bi-directional output driver is sufficiently similar A single lookup table may be sufficient. Moreover, While not specifically shown, the impedance calibration driver 601 and output driver 6200-620N-1, the impedance control value applied by the impedance calibration driver 601 is applied to the signal output driver ₆₂₀ 0 -620 _N-1 As implemented by output drivers that are substantially physically matched (eg, in terms of physical width and number and configuration of impedance calibration branches) to provide substantially the same impedance. .

FIG. 7B is a diagram of an exemplary impedance calibration operation for a pull-up output within the impedance calibration engine of FIG. 7A. Impedance calibration is performed at 661 by a control circuit (eg, a host controller, on-board CPU, or other on-chip or off-chip control circuit, not shown) at the input of the impedance calibration state machine 609 (eg, an impedance calibration enable signal (eg, , ZCal_En = 1) is asserted. The control circuit may also set the initial state of the calibration data bit (eg, d _CAL = 0, but the state machine 609 also responds to the assertion of the impedance calibration enable signal to determine the state of the calibration data bit. May be initialized).

In one embodiment, the impedance calibration state machine 609 is equal to or approximately equal to the simulation voltage generated by one of the voltage simulators 603, 605, V _SIM (or a voltage dithered around V _SIM ), Find the calibration settings that result in the output voltage, _VOUT . To begin, at 663, the impedance calibration state machine 609 sets the control value, cal_pu (in this example, a 4-bit value) to the median range value 2 ^N / 2 (ie, in a 4-bit implementation, cal_pu = 8 or 1000b), and then at 667, the output of the comparator 604 is read. At decision block 667, the comparator output is determined to be high (the pull-up voltage generated by pull-up voltage simulator 603, V _SIM exceeds V _OUT , and therefore the pull-up impedance in calibration driver 601, R _{If the PU} is too high), the impedance calibration state machine decrements R _PU at 669 and increases V _OUT , then confirms convergence between V _OUT and V _{SIM at} 673 . In one embodiment, for example, the impedance calibration state machine may indicate that the last X samples (where X is a predetermined or programmed value) has completed dithering the comparator output and thus pull-up impedance calibration. , It is assumed that V _OUT has converged to V _SIM . If V _OUT has not yet converged to V _SIM , the impedance calibration state machine continues to adjust (decrement or increment) R _PU to confirm convergence. Otherwise, the state machine proceeds to calibrate the pull-down impedance, R _PD and switches d _cal to “1” (thus generating a pull-down output in the inverting output driver) and comparing as shown at 675 The output of unit 606 is used to repeat the sequence of operations 663 and 673, making up / down adjustment decisions and adjusting cal_pd [3: 0] instead of cal_pu [3: 0].

The target equalization calibrator includes an equalization driver 640, a finite state machine 643 (“equalizer calibration state machine”), a comparator 641, and an optional lookup table 645. The comparator 641 receives the output of the equalization driver 640 and the target equalization settings (eg, including statistically updated voltage levels in response to detection of input signal levels or other runtime information). Or dynamically determined threshold voltage). As shown in FIG. 7C, when enabled by an assertion of the equalizer calibration enable signal at 691 (eg, EqCal_En = 1, a pair of equalized data values corresponding to the live post tap and main data source is “ State machine 643, at 693, the equalization control value, eq [3: 0], is set to the median range value (eg, this 4). In the bit embodiment, it is set to 1000b). The state machine 643 then adjusts the equalization control value (eq [3: 0]) up or down in response to the output state of the comparator 641 (ie, determined at 697) and at 699, etc. If the output of the equalization driver 640, V _EQ is less than the target value, V _TARG , the equalizer control value is decreased, and if the equalization driver output exceeds the target value at 701, the equalizer control value is decreased. increase. This action causes the equalizer control loop (or servo loop) to drive the equalizer control value to a state that minimizes the difference between the target EQ voltage and the actual EQ voltage. Similar to the impedance calibration operation, the state machine 643 causes the output of the comparator 641 to dither between the high and low values (ie, the equalization voltage toggles around the target voltage at 703). The convergence of the target and actual equalization voltage may be tested by determining whether or not.

The impedance and equalization calibration operations described with reference to FIGS. 7A-7C may be performed in parallel, but the adjustment of the impedance calibration is shifted to the equalizer settings for a given target. Also good. Thus, in one embodiment, the impedance calibration state machine signals, at least temporarily, to the equalizer calibration state machine in response to converging to the final determined impedance calibration setting, and thus to the equalization calibration state machine. Start the assessment of convergence. Also, if the output drivers 620 ₀ -620 _N-1 are implemented with a differential element impedance calibration DAC, the pull-up and pull-down calibration control words are stored in separate impedance calibration lookup tables 611a and 611b (or shared lookups). Table) and corresponding pull-up and pull-down enable values (e_pd and e_pu, respectively, with a number of configuration bits according to the number of differential element sub-drivers used to implement the impedance calibration function) May be obtained. As shown, such enable values are provided to both calibration driver 601 and signal output drivers 620 ₀ -620 _N−1 to establish a uniform calibration setting across the signaling interface. In alternative embodiments, separate calibration values may be generated for all signal drivers. The equalizer control word is also fed to the equalizer look-up table 645 to obtain the select signal [5: 0] that controls the data source selected in the differential element equalizer sub-driver. Also good. Similar to the Z-cal lookup table, entries in the equalizer lookup table 645 provide monotonic recurrence throughout the equalization range in response to the recurrence of the equalization control word from the minimum to the maximum setting. May be stored in order to

FIG. 8A is a diagram of an alternative embodiment of an equalization calibrator that may be used to calibrate an equalization sub-driver in a bi-directional output driver. Instead of a servo function that drives the equalizer output to the target, the equalization setting corresponding to the maximum desired equalization (ie, a or its corresponding 1-a) is determined to scale the overall equalization range. Used for. That is, if process variation results in a maximum desired equalization, eg, 75% of the actual (ie, physically available) equalization range, the total equalization setting across the desired range is within the actual range. May be scaled to its corresponding 75%. Thus, the state machine 713 adjusts the equalization step value up or down according to the output of the comparator 711 (compares the maximum equalization voltage reference with the output of the equalization driver 640), and adjusts the step value to the equalization driver 640 and Applies to scaling logic 715. By this operation, the equalization step value, eq_step [4: 0] may be servo adjusted to a value corresponding to the maximum scaling limit (or whatever maximum equalization criterion is provided). As shown, the scaling maximum equalization step value is also responsive in response to the coefficient eq_step [m−1: 0] / (2 ^m −1), 3 bits (eg, 8 steps or 6 steps), etc. The scaling control value, eq [2: 0], is supplied to scaling logic 715 that scales the value (“m” is the number of bits in the equalization step value (in this example, 5 bits), resulting in The scaled equalization control value, sc_eq [4: 0], is applied directly to the signal output driver (eg, in a uniform element implementation) or to the differential element lookup table 717 to provide individual scaled equalization control settings. A combination of differential element sub-drivers corresponding to can be selected, which causes the equalizer to be determined by an equalization feedback loop. According scaling up limit regulation is effectively calibrated.

FIG. 8B shows that the impedance calibration settings (eg, cal_pu and / or cal_pd, generated by the impedance calibration engine, implemented as discussed with reference to FIGS. 7A and 7B, respectively) are the equalizer scaling logic 725. FIG. 5 is a diagram of an alternative equalizer scaling embodiment that is applied to and applied therein to predict (or determine) a desired scaling maximum setting for an equalizer. With this arrangement, separate equalization drivers and equalization calibration state machines may be eliminated, reducing the overall footprint of the output driver calibration circuit.

FIG. 9A is a diagram of an exemplary scaling engine or scaling logic 755 that may be used to implement the scaling logic 715 of FIG. 8A or the scaling logic 725 of FIG. 8B. As shown, scaling logic 755 includes multiplexer 757 and eq_step [4: 0] (ie, generated in the embodiment of FIG. 8A) or cal_pd or cal_pu (ie, generated in the embodiment of FIG. 8B). And a table of scaled equalization step values 756 that operate to “look up” the scaled equalizer step size. The scaled equalizer step size is multiplied in multiplier 759 by the input equalization control value, eq [2: 0], scaled and expanded equalization control word, sc_eq [4: 0] (or , Generate an expanded equalization control word, xeq [4: 0]) if no further differential element lookup is required. As shown, the equalization control value is derived from a target equalization setting (eg, a dynamically generated equalization level that is adjusted in response to a bit error rate or other feedback source) or from a configuration or mode. It may be supplied from a register. In the particular embodiment shown, for example, a 3-bit equalization control value establishes an equalization step corresponding to 5% of full scale, allowing an equalization range of 0 to 30%. In one embodiment, the mode register (or individual register) may include an equalization mode field (“eqm”) that selects an equalization control source.

FIG. 9B additionally provides an alternative scaling logic embodiment that serves to select the appropriate differential element combination and equalization control word for a given equalization_step [4: 0] or cal_pd or cal_pu (or It is a figure of a scaling engine. That is, one of 32 different sets of 6 expanded equalization values is selected according to the eq_step [4: 0] setting (ie, each of the 6 expanded equalization values other than xeq0 is individually Are selected via the corresponding multiplexer 783), and are supplied to the six input ports of the output multiplexer 785, and therefore according to the equalization control word eq [2: 0] Establishes a scaled set of six values that may be selected (ie, by output multiplexer 785).

FIG. 10A is a diagram of an exemplary implementation of a differential element driver branch. More specifically, instead of implementing different sized switching transistors in order to establish a relatively accurate differential conductance between the branches, uniform switching transistors are used in each branch and separate poly The length of the silicon resistive element is modulated (ie, perturbed, adjusted, expanded, etc.) to establish an inter-branch conductance difference. In the exemplary branch shown, a pull-up load element 803a having a conductance G ₀ (ie, the minimum conductance of a set of differential pull-up elements) and a pull-down load element 803b, also having a conductance G ₀ , are connected to an output node 804. _{Coupled to a} separate voltage reference (ie a supply voltage such as V _DD or V _DDIO and a ground reference). Pull-up load element 803a is formed by a series connection of PMOS transistor 806 (ie, positive metal oxide semiconductor transistor) and polysilicon resistor 807 (“poly” element), and pull-down element 803b is similarly NMOS transistor 808. (Negative MOS transistor) and a poly element 809 are connected in series. The PMOS and NMOS transistors 806, 808 have a pull-up and pull-down poly element 807, 809 that also has a conductance G _0. To exhibit _POLY, as can be equally sized adjusted nominally equal _conductance, it is sized to exhibit _{G TR (G 0 = G TR} * G 0.POLY / (G TR + G 0.POLY) ). Furthermore, as shown in side view 811 and top view 812 of load element 803a, poly element 807 (eg, coupled to switching transistor 806 through metal layer M1) has a net impedance of the poly element that is the length of the poly element 807a. May have a fixed width (eg, minimum feature width) such that the conductance is inversely proportional to the length. Thus, a pull-up or pull-down element with a precisely controlled conductance step (Δ _i ) in the differential element DAC may be implemented by modulating the length of the poly element between the sub-driver branches. Thus, the net conductance between any two branch pull-up (or pull-down) elements is G, as shown by the comparison between the poly lengths of the load elements in sub-driver branches G _N-2 and G _N−1 . _i −G _i−1 (or ΔG _i −ΔG _i−1 ) is brought about by adjusting its individual poly-element length to be equal to the desired conductance difference between the two branches. May be.

FIG. 10B is a diagram of an alternative implementation of a differential element driver branch, which in this case has the following three poly elements: Variable conductance G _i. Pull-up and pull-down poly elements 822 having _PV (ie, conductance length-modulated between branches, where “i” is a subdriver index and ranges from 0 to N−1) and 823 and a third shared poly element 825 having conductance _GPF . With this arrangement, the shared poly element 825 between the pull-up and pull-down portions of the branch eliminates its duplication in both the sub-driver pull-up and pull-down portions, so that the overall footprint of the sub-driver branch is It may be reduced. In the particular example shown, the conductance (G _PF ) of the shared poly element 825 is G _{i. POLY} = G _{i. PV} + G _PF and G _i = G _TR + G _i. The desired conductance for each sub-driver branch is PV of variable pull-up and pull-down poly-elements 822, 823 so that _PV + G _PF (sub-driver index, “i” ranges from 0 to N−1). Fixed between sub-driver branches as provided by adjusting the length (has zero length and therefore may be absent to achieve minimum sub-driver branch conductance, G ₀ ) . In alternative embodiments, shared poly element 825 may also (or alternatively) vary between branches and establish conductance differences between branches.

FIG. 11 is a circuit model that may be used to determine a set of differential element impedances (or conductances) (ie, G ₀ -G _N-1 ) within a set of equalization sub-drivers 831. FIG. Circuit model 833 as shown in (exhibiting the characteristic impedance _{R TERM,} and / or impedance _is pulled up to _{V TERM} by _{R TERM,} depicts an equivalent circuit of the sub-driver 831 which is connected to the signal transmission link 834) , The various possible settings of the selected value [N−1: 0] are the voltage through the net pull-up and pull-down loads, R _PU and R _PD (ie during the transmission interval _where d _n = / dn _{+ 1} ). Provides a range of distributor ratios. Total equalizer impedance, _RT is equal to the parallel combination of pull-up and pull-down load elements, R _PU * R _PD / (R _PU + R _PD ), and the equalizer DAC is a set of N differential element sub-drivers The nominal conductance of each slice may be set to approximately G = 1 / (N * R _T ). The conductance of each slice may be expressed as G _i = G + Δ _i (Δ ₀ + Δ ₁ +... + Δ _N−1 = 0).

As can be seen from Thevenin's equivalent circuit at 835, the number of distinct equalization settings for a given quantity N of differential element sub-drivers maximizes the quantity of unique R _PD / R _PU values that can be achieved. May be maximized. Note that R _PD / R _PU may be expressed as:
(K / (N−k)) * [1 + N / (G * k * (N−k)) * sum _k (Δ _i )],
(“*” Indicates multiplication, and sum _k () is a summation function, in this case adding each of the Δ _i values contained in the k differential load elements of the subset), R _PD / R The maximum distinct quantity of _PU values may be maximized by ensuring that each permutation sum _k (Δ _i ) is distinct. In one embodiment, such a distinct set of permutations is achieved by using binary weights for Δ _i such that Δ _i = 2 ⁱ Δ (Δ is the unit conductance difference). In an arrangement with a non-zero sum Δ _i , the load element conductance, G _i , may be rewritten as (G + Δ _i ) * G / (N * G + (2 ^N −1)). In this case, G _i is Δ _i = 2 ⁱ Δ− (2 ^N −1) / N, and thus Δ _i = 2 ⁱ Δ (n = 1,..., N−2), Δ _N−1. = -2 ^N-1 +1 may be normalized to yield an accurate total conductance (or impedance).

In one embodiment, the principles described above may be applied to determine a specific unit conductance and nominal conductance for a given set of N differential element sub-drivers, where N is the required resolution as well. It may be determined on a base or trial and error basis (eg, determining the impedance value and resolution that N results from taking steps between the minimum and maximum practicable values). Also described in the context of a voltage divider formed in an equalization subdriver, the approach is specific unit conductance and nominal for a given set of N differential element subdrivers in an impedance calibrator. It may be applied to determine conductance.

FIG. 12A shows a differential element impedance calibration DAC 853, a differential element equalizer DAC 855, and a set of fixed sub-drivers 857 (ie, dedicated to main data transmission, regardless of the calibration setting, during the data transmission interval, FIG. 6 is a diagram of an exemplary embodiment of a bi-directional output driver 851 with Referring to detail view 858, impedance calibrator 853 is collectively formed by a set of 12 sub-drivers that provide 40-step calibration resolution. More specifically, as shown in 859, the 6-bit calibration control value, cal [5: 0], is one of 40 pairs of 12-bit enable values, ep [11: 0] and en [11: 0]. Is supplied to a look-up table 871, which outputs the selected one in a responsive manner. The individual pull-up and pull-down bits within the selected pair of enable values are applied to separate differential element driver branches 873 ₀ -873 ₁₁ (ie, ep [0] and en [0] are supplied to driver branch 873 ₀ . And ep [1] and en [1] are fed to driver branch 873 ₁ etc.) and enable a set of pull-up and pull-down driver elements corresponding to a given state of the calibration control value. To. In one embodiment, the calibration control value may be incremented or decremented and stepped step by step through impedance ranges in separate calibration operations for the pull-up and pull-down portions of the calibration driver branch. Thus, the set of 40 pull-up enable values ep [11: 0] are stored in the look-up table 871 to enable monotonic recurrence through the impedance range and the set of 40 pull-down enable values en [11 : 0] is also stored for monotonic impedance recurrence.

Still referring to the detail view 859 of the impedance calibration DAC 853, the input main tap data bits (d _n ) are logically ANDed by the enable values ep [i] and en [i] in each driver branch 873 _i ( Ie, in NAND gate 875 and AND gate 877), thereby enabling the pull-up or pull-down output drive function. That is, when the input data bit is low and the enable value ep [i] is high, the output of NAND gate 875 (with the inverted data input as shown) is low, switching PMOS transistor 879 to the conducting state, and thus , A load G _i (formed by the conductance of PMOS transistor 879 and polyelement 883) is switchably coupled to output node 884. Conversely, when the input data bit is high and the enable value en [i] is also high, the output of the AND gate 877 is high, switching the NMOS transistor 881 to the conductive state, and thus the load G _i (NMOS transistor 881 and polyelement). 885) is switchably coupled to output node 884. Thus, individual pull-up or pull-down load elements within the differential element sub-driver are switchably coupled to output node 884 in a particular combination selected by the input calibration value. Although an inverting sub-driver implementation is shown (ie, output node 884 is pulled high in response to logic low data and pulled low in response to logic high data), a non-inverting implementation is an alternative May be implemented (eg, by removing the inversion to gate 875 at the data input and adding the inversion to gate 877 at the data input).

Referring to the detailed diagram 860 of the differential element equalizer DAC 855, the input 2-bit equalization control value, eq [2: 0], is used to look up the 5-bit selection code, s [5: 0]. The configuration bits are supplied to six differential element sub-drivers 903 _{0 to} 903 ₅ , respectively. As shown in the detailed view of the sub-driver 903 _0, each selection bit, the multiplexer 905 (its output, generally, as mentioned above, is connected to the PMOS and NMOS switching transistors, whereby the pull-down or pull-up load element Select data bits from either a post-tap or main tap data source (ie, d _{n + 1} or d _n ) and thus span the desired equalization range As used.

Referring to detail view 861, the fixed sub-driver set 857 includes six uniformly sub-driver branch ₈₉₀ 0 -890 _5, respectively, as shown in the detail view of a sub-driver 890 _0, pairs of data switchable Implemented by transistors and polysilicon resistor elements. The overall nominal impedance of the fixed sub-driver set is 120 ohms (ie, 720 ohms per sub-driver branch) and the nominal impedance of the equalizer branch is also 120 ohms (provided that the latter is a differential element sub-driver) Established). The nominal impedance of each load element in the calibration sub-driver is such that a set of six elements corresponding to the nominal midpoint of the calibration range (ie calibration control word = 14 hex or 20 decimal) is 120 ohms. 720 ohms so that it can be chosen to provide a nominal impedance and thus establish an overall driver impedance at R _TERM = 40 ohms. In the case of a slow process corner that results in a conductance below nominal (ie higher impedance than the target R _TERM ), the calibration control value is incremented from its starting (middle range) value and increased net conductance (ie the initial of the subdriver) Transition to combinations of elements that result in progressively higher net conductance, including selecting one or more combinations of six calibration sub-driver branches that exhibit (compared to the selected combination) , Transition to a larger number of enabled sub-driver branches. Conversely, at a fast process corner that results in conductance above nominal (ie, impedance below target R _TERM ), the calibration control value is decremented from its starting value and is one of the six sub-driver branches that exhibit reduced net conductance. Transition to a combination of elements that results in progressively lower net conductance, including selecting one or more combinations, and then transition to a smaller number of enabled sub-drivers if necessary . Overall, as the calibration control value is transitioned from the lowest to the highest setting, an impedance calibration ranging from 2βW _PHYS / (1 + β) is achieved, thus process variation ranging from + 30% to −30%. The overall bidirectional output driver 851 can be calibrated.

FIG. 12B is a diagram of an exemplary set of load element impedances, R0-R12, that may be used to quantize the impedance calibration range in the embodiment of FIG. 12A. As shown, each load element has an impedance formed by a common transistor impedance (or resistance), R _TR , individual polyimpedance, P0-P11. As described above, separate pull-up and pull-down poly elements (eg, each having an impedance Pi, where i is a load element index) may be provided in each differential element sub-driver branch. , At least a portion of each poly element may be shared between the pull-up and pull-down load elements. More or less load element impedance (ie, more or less sub-drivers) and / or different impedance values for the provided load elements may be used in alternative embodiments. 40 selectable combinations of pull-down load elements (profile 921) and 40 selectable combinations of pull-up load elements (profile 923), showing the descending impedance (ascending conductance) for the slow nominal and fast process corners, respectively. As shown in the individual net impedance profiles for the given code index (ie, enable value) in all cases to provide the desired output driver impedance (40 ohms in this example) It may be selected.

FIG. 12C is a diagram of an exemplary set of load element impedances, R0-R5, that may be used to quantize the equalization range within the embodiment of FIG. 12A. Used to implement the impedance calibration DAC, like the loading element impedance, the equalizer loading element has an impedance R _TR, a common transistor, individual poly impedance, formed by the P0-P5 Also good. As discussed, separate pull-up and pull-down poly elements (eg, each having an impedance Pi, where i is a load element index) may be provided within each differential element sub-driver branch. , At least a portion of each poly element may be shared between the pull-up and pull-down load elements. More or less load element impedance (ie, more or less sub-drivers) and / or different impedance values for a provided load element may be used in alternative embodiments.

The various circuits disclosed herein are described using computer-aided design tools in terms of their behavior, register transfer, logic components, transistors, layout geometry, and / or other features. Note that it may be expressed (or depicted) as data and / or instructions embodied as various computer-readable media. The format of files and other objects in which such circuit representation may be implemented include behavioral language compatible formats such as C, Verilog, and VHDL, register level description language compatible formats such as RTL, and GDSII, GDSIII, GDSIV, CIF Including, but not limited to, geometric shape description language compatible formats such as MEBES, and any other suitable formats and languages. Computer readable media from which such formatted data and / or instructions may be embodied include, but are not limited to, computer storage media in various forms (eg, independently distributed in such manner). Or optical, magnetic, or semiconductor storage media, whether stored in-situ within the operating system).

When received in a computer system via one or more computer-readable media, such data and / or instruction-based representations of the aforementioned circuits include netlist generators, location and route programs, etc. Which are processed by a processing entity (eg, one or more processors) in a computer system in conjunction with execution of one or more other computer programs to generate a physically explicit depiction and image of such circuitry. May be. Such depictions and images are subsequently used in device manufacturing, for example, by allowing the generation of one or more masks used to form various components of the circuit in the device manufacturing process. Also good.

In the foregoing description and accompanying drawings, specific terms and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terms and symbols may imply specific details that are not required to practice the invention. For example, any particular number of bits, signal path widths, signal transmission or operating frequencies, component circuits or elements, etc. may differ from those described above in alternative embodiments. In addition, integrated circuit elements, or internal circuit elements, or links or other interconnections between blocks may be shown as buses or single signal lines. Each bus may alternatively be a single signal line, and each single signal line may alternatively be a bus. However, the signal and signaling links shown or described may be single-ended or differential. A signal driver circuit receives a signal when the signal driver circuit asserts (or deasserts, if explicitly described or indicated by context) a signal on a signal line coupled between the signal driver and the signal receiver circuit. The signal is to be “output” to the circuit. The term “coupled” is used herein to denote a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit element “programming” can be performed on a register or other storage circuit in the element, eg, in response to a host command or through a one-time programming operation (eg, blowing a fuse in a component circuit during element production). Loading control values (and thus controlling the operational aspects of the device and / or establishing the device configuration) and / or one or more selected pins or other connection structures of the device to the reference voltage line ( It may also include, but is not limited to, establishing a specific device configuration or operating mode of the device. The terms “exemplary” and “embodiments” are used to represent examples, not preferences or requirements.

Although the invention has been described with reference to specific embodiments thereof, it will be apparent that various modifications and changes may be made without departing from the broader spirit and scope. For example, any feature or aspect of an embodiment may be applied in combination with any other of the embodiments, or instead of its corresponding feature or aspect, at least when practicable. The specification and drawings are accordingly to be regarded in an illustrative rather than a restrictive sense.

Claims (26)

An output driver for use in an integrated circuit element,
A plurality of impedance calibration signal drivers coupled in parallel to the signal output node, each enabled one of the impedance calibration signal drivers contributing to a separate output signal carrying current corresponding to the first data input An impedance calibration driver that is selectively enabled based on the impedance control value, and
A plurality of equalization signal drivers coupled to the signal output node in parallel with the plurality of impedance calibration signal drivers, wherein the plurality of impedance calibration signal drivers in the first and second subsets are equalized controlled. According to the value, regardless of the impedance control value, the plurality of equalized signal drivers of the first subset each contribute to a separate output signal carrying current corresponding to the first data input, Each of the plurality of equalization signal drivers of the second subset each contributes to a separate output signal transfer current corresponding to a second data input; and
An output driver comprising:   Each of the impedance calibration signal drivers is different from each of the other impedance calibration signal drivers and is set to be substantially less than a stepped increase in output driver impedance that can be achieved by incrementing the impedance control value. The output driver of claim 1, having an impedance.   The output driver of claim 1, wherein one of the impedance calibration signal drivers has an impedance that is substantially equal to a stepped increment of the output driver impedance achievable by incrementing the impedance control value. .   Each of the equalization signal drivers is intentionally different from the output signal transfer current contributed by any of the other equalization signal drivers, and the output driver current of the output driver current achieved by incrementing the equalization control value. The output driver of claim 1 that contributes to an individual output signaling current that is substantially greater than a stepped increment.   The one of the equalization signal drivers contributes a signaling current substantially equal to a stepped increment of the output driver current achieved by incrementing the equalization control value. The listed output driver.   The impedance control value has a number of configuration bits that is less than the number of impedance calibration signal drivers, and the output driver has a number of configuration bits equal to the number of impedance calibration signal drivers. The output driver of claim 1, further comprising first decoding logic for converting to an enable value.   The output driver of claim 6, wherein the enable value is provided to the at least one other output driver to control impedance of at least one other output driver. The output driver of claim 6, wherein the first decoding logic comprises a lookup table having a plurality of enable values stored therein.   The equalization control value has a number of configuration bits that is less than the number of equalization signal drivers, and the output driver has a number of equalization control values equal to the number of equalization signal drivers. The output driver of claim 6, further comprising second decoding logic for converting to a selected value having a configuration bit. An output driver for use in an integrated circuit element, the output driver being coupled in parallel to a signal output node, the impedance of the output driver being achievable by incrementing a first impedance control value A first plurality of impedance calibration signal drivers that allow adjustment within stepped impedance increments of the output driver impedance , wherein each impedance calibration signal driver of the first plurality of impedance calibration signal drivers includes the stepped impedance increments. theft by Ri substantially smaller, has an impedance, output driver.   The output driver is configured to enable the first plurality of impedance calibration signal drivers in a subset according to the first impedance control value, the output driver being a first data source or a second data The output driver of claim 10, further comprising a multiplexer for selecting data bits output by the first plurality of impedance calibration signal drivers of the enabled subset from any of the sources.   And a second plurality of impedance calibration signal drivers coupled in parallel to the signal output node, the first plurality of impedance calibration signal drivers forming a first sub-driver in the equalization signal driver. 11. The output driver of claim 10, wherein the second plurality of impedance calibration signal drivers constitute a second sub-driver in the equalization signal driver.   An input for receiving an equalization control value, wherein the first bit of the equalization control value is output by the first plurality of impedance calibration signal drivers of the enabled subset; A second bit of the equalization control value is supplied to the first sub-driver to select either a data bit or a second data bit, and the second plurality of enabled subsets 13. The output of claim 12, wherein the output is provided to the second sub-driver to select either the first data bit or the second data bit output by an impedance calibration signal driver of driver. Each further comprises first and second impedance control inputs for receiving the first impedance control value and the second impedance control value, wherein the first impedance control value is the subset of the enabled subset. 14. The first plurality of impedance calibration signal drivers is selected, and the second impedance control value selects the second plurality of impedance calibration signal drivers in the enabled subset. Output driver. A method of operating an output driver in an integrated circuit element, comprising:
Optionally, in response to an impedance control value, enables an impedance calibration signal driver and establishes the desired impedance of the output driver, the impedance calibration signal driver being coupled in parallel with the output node of the output driver. And
A plurality of equalized signal drivers of the selected first and second subsets are coupled to a separate one of the first and second transmission data sources to establish a desired equalization setting for the output driver And each of the plurality of equalization signal drivers is coupled to the output node in parallel with the impedance calibration signal driver, and the plurality of equalization signal drivers of the first and second subsets are configured to transmit the impedance control value. Regardless of the state of being selected,
Including a method.   Optionally, coupling the equalization signal driver to the first transmission data source or the second transmission data source equalizes so as to generate an output equalization voltage corresponding to the target equalization voltage. The method of claim 15, comprising adjusting the control value. Concatenating the selected first and second subset of equalization signal drivers to an individual one of the first and second data sources;
Determining a scale factor corresponding to the ratio of the equalized voltage generated as a result of the desired equalization voltage and the first equalization setting;
Scaling an equalization control value supplied to the equalization signal driver according to the scale factor;
The method of claim 15 comprising:   Optionally, coupling the equalization signal driver to either the first transmission data source or the second transmission data source may be performed according to a ratio of the impedance control value and the maximum possible value of the impedance control value. The method of claim 15, comprising scaling the equalization control value provided to the equalization signal driver. A method of operating an output driver in an integrated circuit element, comprising:
Incrementing the first impedance control value;
Optionally, the method comprising: enabling an individual combination of impedance calibration signal drivers, a combination which is in each enabled impedance calibration signal driver is different from the combination, which is the other enable the impedance calibration signal driver Providing an output driver impedance, each impedance calibration signal driver having an individual impedance substantially less than a stepped impedance increment of the output driver impedance achievable by incrementing the impedance control value ;
Including a method.   Optionally, enabling individual combinations of impedance calibration signal drivers in response to incrementing the impedance control value looks for individual enable values in response to each increment of the impedance control value. 20. The method of claim 19, wherein each enable value corresponds to a separate one of the combinations of impedance calibration signal drivers.   21. The method of claim 20, wherein the enable value comprises more configuration bits than the impedance control value.   21. The method of claim 20, wherein the impedance control value comprises fewer configuration bits than the number of impedance calibration signal drivers, and the enable value comprises a number of configuration bits that matches the number of impedance calibration signal drivers.   An output driver for use in an integrated circuit device, the output driver coupled in parallel to a signal output node and responsive to an equalization control value incrementing an equalization setting of the output driver. A plurality of equalization signal drivers that are adjustable within a stepwise equalization increment, wherein each equalization signal driver of the plurality of equalization signal drivers is a given one of the stepwise equalization increments An output driver that produces an equalization contribution that is substantially greater than one.   24. The multiplexer of claim 23, further comprising a multiplexer for selecting data bits output by the plurality of equalization signal drivers in an enabled subset from either a first data source or a second data source. Output driver.   24. The output driver of claim 23, further comprising a plurality of impedance calibration signal drivers coupled to the signal output node in parallel with the plurality of equalization signal drivers. An integrated circuit element comprising:
Means for incrementing the first impedance control value;
Optionally, a means to enable individual combinations of impedance calibration signal drivers, a combination which is in each enabled impedance calibration signal driver is different from the combination, which is the other enable impedance calibration signal driver output Means for providing a driver impedance , each impedance calibration signal driver having an individual impedance substantially less than a stepped impedance increment of the output driver impedance achievable by incrementing said impedance control value ;
An integrated circuit device comprising:

Images