CN116682476A - Impedance calibration circuit and memory - Google Patents
Impedance calibration circuit and memory Download PDFInfo
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- CN116682476A CN116682476A CN202310699296.XA CN202310699296A CN116682476A CN 116682476 A CN116682476 A CN 116682476A CN 202310699296 A CN202310699296 A CN 202310699296A CN 116682476 A CN116682476 A CN 116682476A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the disclosure provides an impedance calibration circuit and a memory, wherein the impedance calibration circuit comprises: a pull-up driving circuit including a plurality of pull-up driving branches configured to: receiving a pull-up signal and a pull-up calibration code, gating a designated number of pull-up driving branches by using the pull-up signal, and adjusting the voltage of an output end by using the pull-up calibration code; the pull-up driving circuit is used for pulling up the voltage of the output end; a plurality of switching circuits, each pull-up driving branch being connected to the power supply through a corresponding one of the switching circuits, configured to: receiving a pull-up switch signal, and communicating a specified number of pull-up driving branches with a power supply by using the pull-up switch signal; a first generation circuit configured to: a first target voltage and a voltage at an output terminal are received, and a pull-up calibration code and a pull-up signal are generated based on a difference between the first target voltage and the voltage.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to an impedance calibration circuit and a memory.
Background
As the operating speed of electronic apparatuses increases, the swing width (swing width) of signals transmitted between semiconductor memory devices within the electronic apparatuses decreases to minimize the delay time spent transmitting the signals. However, as the swing width decreases, signals transferred between semiconductor memory devices may be more easily distorted due to impedance mismatch caused by process, voltage and temperature (PVT, process Voltage Temperature) variations, and it is difficult to transfer data at high speed.
How to reduce or eliminate impedance mismatch and to perform high-speed data transmission is a technical problem to be solved.
Disclosure of Invention
Accordingly, embodiments of the present disclosure provide an impedance calibration circuit and a memory for solving at least one technical problem existing in the prior art.
According to a first aspect of embodiments of the present disclosure, there is provided an impedance calibration circuit comprising: a pull-up driving circuit including a plurality of pull-up driving branches configured to: receiving a pull-up signal and a pull-up calibration code, gating a designated number of pull-up driving branches by using the pull-up signal, and adjusting the voltage of an output end by using the pull-up calibration code; the pull-up driving circuit is used for pulling up the voltage of the output end; a plurality of switching circuits, each pull-up driving branch being connected to the power supply through a corresponding one of the switching circuits, configured to: receiving a pull-up switch signal, and communicating a specified number of pull-up driving branches with a power supply by using the pull-up switch signal; a first generation circuit configured to: a first target voltage and a voltage of the output terminal are received, a pull-up calibration signal is generated based on the first target voltage, and a pull-up calibration code is generated based on a difference between the first target voltage and the pull-up calibration signal.
In the above scheme, the pull-up driving circuit includes a first pull-up driving branch, a second pull-up driving branch and a third pull-up driving branch; the plurality of switching circuits includes a first switching circuit, a second switching circuit, and a third switching circuit; the pull-up switch signal comprises a first pull-up switch signal, a second pull-up switch signal and a third pull-up switch signal; the first switching circuit is configured to: receiving a first pull-up signal, and communicating the first pull-up driving branch with a power supply; and the first pull-up driving leg is configured to: receiving a first pull-up signal to enable a first pull-up driving branch; the second switching circuit is configured to: receiving a second pull-up signal, and communicating a second pull-up driving branch with a power supply; and the second pull-up drive leg is configured to: receiving a second pull-up signal to enable a second pull-up driving branch; the third switching circuit is configured to: receiving a third pull-up signal, and communicating a third pull-up driving branch with a power supply; and the third pull-up drive leg is configured to: and receiving a third pull-up signal to enable a third pull-up driving branch.
In the above aspect, the first generating circuit is configured to: generating a first pull-up signal in response to the calibration enable signal; when the difference between the first target voltage and the preset intermediate voltage is greater than or equal to a first preset value and less than a second preset value, the first generating circuit is configured to: generating a second pull-up signal; the preset intermediate voltage is a theoretical voltage of the output end when one pull-up driving branch is started; when the difference between the first target voltage and the preset intermediate voltage is greater than or equal to a second preset value, the first generating circuit is configured to: generating a third pull-up signal; the second preset value is greater than the first preset value.
In the above aspect, the first generating circuit includes: a comparator configured to: comparing the first target voltage with the voltage of the output end to output a first difference signal, wherein the first difference signal is used for representing the voltage difference between the first target voltage and the voltage of the output end; and a feedback circuit configured to: the pull-up calibration code is increased or decreased in response to the first difference signal.
In the above scheme, each pull-up driving branch includes: one end of the pull-up switch is connected with one switch circuit, and the other end of the pull-up switch is connected to the output end and is used for receiving a pull-up signal; and the pull-up unit is connected with the pull-up switch in parallel and is used for receiving the pull-up calibration code.
In the above scheme, the gate resistance of the transistor in the switch circuit is larger than the gate resistance of the transistor in the pull-up switch.
In the scheme, the impedance calibration circuit further comprises a pull-down driving circuit; the pull-down driving circuit and the pull-up driving circuit are connected to the output end; the pull-down driving circuit includes at least two pull-down driving legs, each configured to: receiving a pull-down switch signal and a pull-down calibration code, gating a designated number of pull-down driving branches by using the pull-down switch signal, and adjusting the voltage of an output end by using the pull-down calibration code; the pull-down driving circuit is used for pulling down the voltage of the output end; wherein the number of pull-down driving branches is smaller than the number of pull-up driving branches.
In the above scheme, each pull-down driving branch includes: one end of the pull-down switch is connected to the output end, and the other end of the pull-down switch is connected with the ground voltage and is used for receiving a pull-down switch signal; and the pull-down unit is connected with the pull-down switch in parallel and is used for receiving the pull-down calibration code.
In the above aspect, the impedance calibration circuit further includes: a second generation circuit configured to: receiving a second target voltage and a voltage of an external calibration terminal, generating a pull-down calibration signal based on the second target voltage, and generating the pull-down calibration code based on a difference between the second target voltage and the voltage of the external calibration terminal; wherein the external calibration end is connected in series between an external standard resistor and an external pull-down driving circuit, and the external pull-down driving circuit and the pull-down driving branch receive the same pull-down signal and pull-down calibration code
According to a second aspect of embodiments of the present disclosure, there is provided a memory comprising: an impedance calibration circuit according to any one of the above aspects.
In various embodiments of the present disclosure, a first generating circuit is configured to: before the impedance calibration operation, it is determined that several pull-up driving branches are to be turned on based on the first target voltage, and accordingly, one or more of the plurality of switching circuits are turned on. Therefore, no redundant switch circuit is opened, so that the overall equivalent resistance of the switch circuit can be improved, and accordingly, the resistance value of the equivalent resistance of the pull-up driving branch circuit can be reduced, and the resistance value of the equivalent resistance of the pull-up calibration cannot be increased. Therefore, under different PVT, the resistance value of the pull-up driving circuit is not easy or can not exceed the resistance value range specified by the design specification, and the impedance calibration circuit can accurately complete the impedance calibration.
Drawings
Fig. 1 is a schematic diagram of an impedance calibration circuit according to an embodiment of the disclosure;
FIG. 2 is a schematic diagram of another impedance calibration circuit including a plurality of pull-up driving legs according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a first generating circuit according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of another first generating circuit according to an embodiment of the disclosure;
fig. 5 is a schematic diagram of a pull-up driving branch circuit and a switching circuit according to an embodiment of the disclosure;
fig. 6 is a schematic diagram of a switching circuit according to an embodiment of the disclosure;
FIG. 7 is a schematic diagram of another switching circuit provided by an embodiment of the present disclosure;
FIG. 8 is a schematic diagram of a pull-down drive leg provided by an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of yet another impedance calibration circuit provided by an embodiment of the present disclosure;
FIG. 10 is a schematic diagram of a memory provided in an embodiment of the present disclosure;
fig. 11 is a schematic diagram of a memory system according to an embodiment of the disclosure.
Detailed Description
The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the embodiments of the present disclosure and the accompanying drawings, in which the described embodiments are only some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.
In the stage of transmitting and/or receiving data of the semiconductor memory device, an impedance calibration operation is performed by an impedance calibration (ZQ calibration) circuit for adjusting the output impedance and/or the termination impedance of the semiconductor memory device, reducing or eliminating impedance mismatch, and transmitting data at high speed.
The impedance calibration circuit may include a Pull-up (Pull-up) circuit and a Pull-down (Pull-down) circuit; accordingly, the impedance calibration may include a pull-up calibration and a pull-down calibration.
The pull-up circuit is connected between the supply voltage Vddq and the output terminal. When the high level data transmission is needed, the pull-up calibration is carried out, the pull-up circuit can receive the pull-up calibration code, and the voltage of the output end is pulled up to the high level required by the data transmission.
The pull-down circuit is connected between the output terminal and the ground voltage Vssq. When the low level data transmission is needed, the pull-down calibration is performed, the pull-down circuit can receive the pull-down calibration code, and the voltage of the pull-down output end is pulled down to the low level required by the data transmission.
The pull-up circuit may include a plurality of pull-up transistors connected between the power supply voltage Vddq and the output terminal. The pull-up transistor may be a P-channel metal oxide semiconductor (PMOS) transistor.
The pull-down circuit may include a plurality of pull-down transistors connected between the output terminal and the ground voltage Vssq. The pull-down transistor may be an N-channel metal oxide semiconductor (NMOS) transistor.
During an impedance calibration operation, the impedance calibration circuit may adjust the output impedance and/or termination impedance by comparing the output impedance and/or termination impedance to an external standard resistance, meeting the resistance values specified by the design specification (SPEC: standard performance assessment organization).
For example, the impedance calibration circuit calibrates the pull-down circuit through a standard resistor externally connected with 240 ohms, and then calibrates the pull-up circuit by using the calibrated pull-down circuit, so that the equivalent resistance value of each branch in the pull-up circuit meets the expected requirement. Meanwhile, since both the pull-up resistor and the pull-down resistor are formed by transistors, the equivalent resistance is greatly influenced by the process, the voltage and the temperature (PVT), so that the finally obtained calibration result may deviate, and the current SPEC prescribes that the equivalent resistance obtained after the final calibration is within +/-10% of the standard resistor externally connected with 240 ohms.
In the prior art, when impedance calibration operation is performed, no matter how many pull-up driving branches are opened, all the switch circuits are opened, and because different switch circuits are connected in parallel, the whole equivalent resistance of the switch circuits is smaller when all the switch circuits are opened. Further, since the sum of the overall equivalent resistance of the turned-on pull-up driving branch and the overall equivalent resistance of the switching circuit is determined by the target calibration voltage at the output terminal (the target calibration voltage determines the ratio of the sum of the resistances to the standard resistance, and the resistance value of the standard resistance is determined), the sum of the resistances is fixed after the target calibration voltage is determined, and in the case where all the switching circuits are turned on so that the overall equivalent resistance of the switching circuit is small, the equivalent resistance of the pull-up driving branch is large.
Meanwhile, as the pull-up circuit and the pull-down circuit are both composed of transistors, the equivalent resistance is greatly influenced by PVT, so that the equivalent resistance of the pull-up driving branch may further fluctuate under the condition of being too large, and the sum of the resistances cannot meet the specification of SPEC. Under the same PVT conditions, even if the resistance increase value of the large resistor is the same as that of the small resistor, the fluctuation of the resistance due to the resistance increase of the large resistor is larger than that due to the resistance increase of the small resistor, for example, the fluctuation range of the large resistor is originally R1, is affected by PVT, and is R11 to R12, R11< R1< R12, and the fluctuation range of the small resistor is originally R2, is affected by PVT, and is R21 to R22, R21< R2< R22, and when the fluctuation range of the small resistor and the large resistor are simultaneously increased by Δr, the fluctuation range of the large resistor is changed to R111 to R112, and the fluctuation range of the resistance of the small resistor is changed to R211 and R212, and at this time, (R112-R111) - (R12-R11) > (R212-R211) - (R22-R21).
Fig. 1 is a schematic diagram of an impedance calibration circuit according to an embodiment of the disclosure. Referring to fig. 1, according to a first aspect of an embodiment of the present disclosure, there is provided an impedance calibration circuit 10 comprising:
The pull-up driving circuit, including a plurality of pull-up driving branches 100, is configured to: receiving a pull-up signal ZqPuMain and a pull-up calibration code ZqPu < N:0>, gating a specified number of pull-up driving branches by using the pull-up switch signal ZqPuMain, and adjusting the voltage ZqOut of the output end by using the pull-up calibration code ZqPu < N:0 >; the pull-up driving circuit is used for pulling up the voltage ZqOut of the output end;
a plurality of switching circuits 120, each pull-up driving leg 100 being connected to the power supply 140 through a corresponding one of the switching circuits 120, is configured to: receiving a pull-up signal ZqPuMain, and communicating a specified number of pull-up driving branches 100 with a power supply 140 using the pull-up switching signal ZqPuMain;
the first generation circuit 300 is configured to: the first target voltage Vref1 and the voltage ZqOut of the output terminal are received, and a pull-up signal ZqPuMain is generated based on the first target voltage Vref1, and a pull-up calibration code ZqPu < N:0> is generated based on the difference therebetween.
The pull-up driving leg 100 may be composed of a plurality of pull-up transistors connected between the power supply voltage Vddq and the output terminal. The pull-up transistor may be a PMOS transistor.
The plurality of pull-up transistors are for receiving a corresponding pull-up signal ZqPuMain and a pull-up calibration code ZqPu < N:0>. For example, the pull-up signal ZqPuMain turns on/off at least one pull-up transistor, enabling one pull-up driving leg; the pull-up calibration code ZqPu < N:0> includes n+1 bit calibration codes, and if n+1 pull-up transistors are correspondingly provided, each bit calibration code of the pull-up calibration code ZqPu < N:0> corresponds to turning on/off one pull-up transistor. The pull-up driving branch 100 may include a main pull-up driving tube (refer to a pull-up enabling transistor M0 of fig. 5) receiving a pull-up signal ZqPuMain and a plurality of sub pull-up driving tubes (refer to pull-up transistors M1 to mn+1 of fig. 5) receiving one bit pull-up calibration codes in pull-up calibration codes ZqPu < N:0>, the main pull-up driving tube and the sub pull-up driving tube are connected in parallel, the equivalent resistances after receiving the calibration codes characterizing conduction are different from each other, and finally, calibration of the pull-up resistance is achieved by turning on the main pull-up driving tube and the sub pull-up driving tubes. Here and hereinafter N takes the value zero or a natural number.
In some embodiments, each pull-up driving leg may receive the same or different pull-up signal ZqPuMain, respectively. In some embodiments, each pull-up driving leg may receive the same or different pull-up calibration code ZqPu < N:0>, respectively.
One of the plurality of switching circuits 120 receives the pull-up switching signal ZqPuMain and communicates a designated number of pull-up driving branches 100 with the power supply 140 using the pull-up switching signal ZqPuMain.
One of the plurality of switching circuits 120 may include a switching transistor connected between the power supply voltage Vddq and each pull-up driving leg. Illustratively, referring to fig. 5, the control terminal of the switching transistor Mc receives the third pull-up switching signal ZqPuMainc, and controls whether the third pull-up driving branch 103 is connected to the power supply 140 based on whether the third pull-up switching signal ZqPuMainc is on or off. The switching transistor may be a PMOS transistor.
In some embodiments, each switching circuit may receive the same or different pull-up signals, respectively.
In some embodiments, each switch circuit and the pull-up driving branch corresponding to each switch circuit may respectively receive the same pull-up signal, or may synchronously receive the same pull-up signal but independent of each other.
The first generation circuit 300 is configured to: before the impedance calibration operation, judging that a plurality of pull-up driving branches are to be opened based on a first target voltage, wherein the impedance calibration aims to adjust the sum of the resistances of a pull-up driving branch and a switching circuit to be equal to a standard resistance, so that after the first target voltage is determined, the need of opening a plurality of pull-up driving branches can be known; during an impedance calibration operation, a corresponding number of pull-up drive legs are turned on for impedance calibration, one or more of the plurality of pull-up drive legs 100 are turned on, and accordingly, one or more of the plurality of pull-up drive legs 100 are turned on.
For example, the first generation circuit 300 is configured to: prior to the impedance calibration operation, a first target voltage Vref1 is received, a pull-up signal ZqPuMain is generated based on the first target voltage Vref1, and one or more switching circuits are opened for impedance calibration. Illustratively, when the first target voltage is high, for example, the first target voltage is 0.8 vddq, a plurality of switching circuits need to be opened for impedance calibration before the impedance calibration operation; when the first target voltage is low, for example, the first target voltage is 0.5 vddq, a switching circuit needs to be opened for impedance calibration before the impedance calibration operation.
In some embodiments, the first target voltage Vref1 may be generated by a reference voltage supply unit (not shown in fig. 1). The reference voltage supply unit may supply a plurality of different first target voltages Vref1, and may be selectively supplied to the first generation circuit 300 according to actual needs.
The first generation circuit 300 is configured to: a first target voltage Vref1 and a voltage ZqOut of an output terminal are received, and a pull-up calibration code ZqPu < N:0> is generated based on a difference between the first target voltage Vref1 and the voltage ZqOut.
For example, before the impedance calibration operation, the first target voltage is 0.5×vddq, and a pull-up driving branch is opened; when the difference between the first target voltage and the initial voltage of the output terminal is smaller, the initial voltage of the output terminal is 0.4×vddq, during the impedance calibration operation, a pull-up calibration code ZqPu < N:0> is generated based on the difference between the first target voltage Vref1 and the voltage ZqOut of the output terminal, and an equivalent resistance value of a pull-up driving branch is adjusted by adding the pull-up calibration code ZqPu < N:0>, so that the initial voltage of the output terminal is 0.4×vddq and pulled up to the first target voltage is 0.5×vddq.
For example, before an impedance calibration operation, a plurality of pull-up driving branches need to be turned on based on a first target voltage of 0.8×vddq; when the difference between the first target voltage and the initial voltage of the output end is larger, the initial voltage of the output end is 0.5×vddq, a pull-up calibration code ZqPu < N:0> is generated based on the difference between the first target voltage Vref1 and the voltage ZqOut of the output end during the impedance calibration operation, and the equivalent resistance of the pull-up driving branches is adjusted by adding the pull-up calibration code ZqPu < N:0>, so that the initial voltage of the output end is 0.5×vddq and pulled up to the first target voltage of 0.8×vddq.
Since the sum of the overall equivalent resistance of the turned-on pull-up driving branch and the overall equivalent resistance of the switching circuit is determined by the first target voltage at the time of the impedance calibration operation, the sum of the equivalent resistances Rzqu of the plurality of pull-up driving branches 100 in the calibration circuit and the equivalent resistances RzqSw of the plurality of switching circuits 120 in the calibration circuit is fixed after the first target voltage is determined. And no redundant switch circuit is opened, so that the resistance of the equivalent resistor RzqSw of the switch circuit can be improved, correspondingly, the resistance of the equivalent resistor Rzqu of the pull-up driving branch can be reduced, the resistance of pull-up calibration cannot be larger, the variation range of the equivalent resistance of the pull-up driving circuit under the same PVT condition is reduced, and the equivalent resistor of the pull-up driving branch is ensured to meet the resistance range specified by SPEC.
Therefore, no redundant switch circuit is opened, so that the resistance of the equivalent resistor RzqSw of the switch circuit can be improved, and accordingly, the resistance of the equivalent resistor Rzqu of the pull-up driving branch can be reduced, and the resistance of pull-up calibration cannot be caused to be larger. Therefore, under the influence of different PVT, the equivalent resistance of the pull-up driving circuit is not easy or cannot further fluctuate, the sum of the equivalent resistances Rzqu of the pull-up driving branches and the equivalent resistances RzqSw of the switching circuits can meet the resistance value range specified by SPEC, and the impedance calibration circuit can accurately complete impedance calibration.
Fig. 2 is a schematic diagram of another impedance calibration circuit including a plurality of pull-up driving legs according to an embodiment of the present disclosure. Referring to fig. 2, the pull-up driving circuit may include more than three pull-up driving legs, for example, the pull-up driving circuit may include four, five, or even more pull-up driving legs. Here and hereinafter, the description will be made taking an example in which the pull-up driving circuit includes three pull-up driving branches.
In some embodiments, the pull-up drive circuit includes a first pull-up drive leg 101, a second pull-up drive leg 102, and a third pull-up drive leg 103; the plurality of switching circuits includes a first switching circuit 121, a second switching circuit 122, and a third switching circuit 123; the pull-up switching signals comprise a first pull-up switching signal ZqPuMaina, a second pull-up switching signal ZqPuMainb and a third pull-up switching signal ZqPuMainc;
the first switch circuit 121 is configured to: receiving a first pull-up signal ZqPuMaina, and communicating the first pull-up driving branch 101 with the power supply 140; and the first pull-up driving leg 101 is configured to: receiving a first pull-up signal ZqPuMaina, enabling a first pull-up driving leg 101;
the second switching circuit 122 is configured to: receiving a second pull-up signal ZqPuMainb, and communicating the second pull-up driving branch 102 with the power supply 140; and the second pull-up drive leg 102 is configured to: receiving a second pull-up signal ZqPuMainb, enabling the second pull-up driving leg 102;
The third switching circuit 123 is configured to: receiving a third pull-up signal ZqPuMainc, and communicating the third pull-up driving branch 103 with the power supply 140; and the third pull-up driving leg 103 is configured to: the third pull-up driving branch 103 is enabled by receiving the third pull-up signal ZqPuMainc.
The first switching circuit 121 outputs the first output voltage VddqSw <0> to the corresponding first pull-up driving leg 101; the second switching circuit 122 outputs the second output voltage VddqSw <1> to the corresponding second pull-up driving leg 102; the third switching circuit 123 outputs the third output voltage VddqSw <2> to the corresponding third pull-up driving leg 103. Illustratively, the outputs of the first, second, and third switching circuits 121, 122, and 123 are coupled as one common terminal, and the first, second, and third output voltages VddqSw <0>, vddqSw <1>, and VddqSw <2> may be made to be the same potential.
The equivalent resistance Rzqua of the first pull-up driving branch 101 and the equivalent resistance Rzqub of the second pull-up driving branch 102; the equivalent resistance Rzquc of the third pull-up driving leg 103.
The equivalent resistance RzqSwa of the first switch circuit 121, and the equivalent resistance RzqSwb of the second switch circuit 122; the equivalent resistance RzqSwc of the third switching circuit 123.
In some embodiments, the first pull-up switching signal ZqPuMaina, the second pull-up switching signal ZqPuMainb, and the third pull-up switching signal ZqPuMainc may be the same or different. When the three signals are the same, the signals can be the same pull-up signal or the pull-up signals which are the same but are controlled independently.
In some embodiments, each switching circuit may receive a pull-up signal separately. In some embodiments, each pull-up driving leg may receive a pull-up signal separately.
In connection with fig. 2 and 5, the third switching circuit 123 and the third pull-up driving branch 103 are taken as examples.
The third switching circuit 123 includes a switching transistor Mc. The third switching circuit 123 may receive the third pull-up signal ZqPuMainc, turn on the switching transistor Mc, and communicate the third switching circuit 123 with the power supply 140, and the third switching circuit 123 outputs the third output voltage VddqSw <2> to the third pull-up driving branch 103.
The third pull-up driving leg 103 may include a pull-up enabling transistor M0 (refer to fig. 5). The third pull-up driving leg 103 may receive the third pull-up signal ZqPuMainc, turn on/off the pull-up enabling transistor M0, and enable the third pull-up driving leg 103.
Referring to fig. 2 and 5, 6, in some embodiments, the third switching circuit 123 includes a third level shifter circuit 343 and a switching transistor Mc. The third level shifter 343 receives the third pull-up switching signal ZqPuMainc, generates a third switching voltage EnSwcVwlp according to the third pull-up switching signal ZqPuMainc, and the third switching voltage EnSwcVwlp is used for turning on the switching transistor Mc to connect the third switching circuit 123 to the power supply 140.
Referring to fig. 2 and 5, and fig. 7, in other embodiments, the third switching circuit 123 includes a third level shifter circuit 343 and a switching transistor Mc. The third level conversion circuit 343 receives the calibration enable signal ZqCalPu, generates a third switching voltage EnSwcVwlp according to the calibration enable signal ZqCalPu, and the third switching voltage EnSwcVwlp is used to turn on the switching transistor Mc to connect the third switching circuit 123 to the power supply 140.
Referring to fig. 2, in some embodiments, the first generation circuit 300 is configured to: generating a first pull-up signal ZqPuMaina in response to a calibration enable signal EnCalPu;
when the difference between the first target voltage Vref1 and the preset intermediate voltage is greater than or equal to the first preset value and less than the second preset value, the first generating circuit is configured to: generating a second pull-up signal ZqPuMainb; the preset intermediate voltage is a theoretical voltage of an output end when one pull-up driving branch is started;
When the difference between the first target voltage Vref1 and the preset intermediate voltage is greater than or equal to the second preset value, the first generating circuit is configured to: generating a third pull-up signal ZqPuMainc; the second preset value is greater than the first preset value.
In some embodiments, the first preset value and the second preset value may be set according to actual needs. In some embodiments, the first preset value and the second preset value may be set according to a value of the first target voltage.
The first target voltage Vref1 has a value of 0.5×vddq, the first preset value has a value of 0.1×vddq, and the second preset value has a value of 0.3×vddq.
In some embodiments, prior to the impedance calibration operation, the first generation circuit 300 is configured to generate the first pull-up signal ZqPuMaina in response to the calibration enable signal EnCalPu during the impedance calibration operation; the first pull-up signal ZqPuMaina is used to turn on the first pull-up driving leg 101 because at least one pull-up driving leg needs to be turned on for calibration regardless of the first target voltage;
after determining that only one pull-up driving leg needs to be turned on according to the first target voltage, the first generating circuit 300 is configured to turn on the first pull-up driving leg 101 in response to the calibration enable signal EnCalPu, adjust the equivalent resistance of the first pull-up driving leg 101 by increasing the pull-up calibration code ZqPu < N:0 >.
In some embodiments, prior to the impedance calibration operation, the first generating circuit 300 is configured to open two switching circuits for impedance calibration if needed based on the first target voltage Vref 1; then, at the impedance calibration operation, in response to the calibration enable signal EnCalPu, the first generation circuit is configured to generate a first pull-up signal ZqPuMaina; the first pull-up signal ZqPuMaina is used to turn on the first pull-up driving leg 101;
if the preset intermediate voltage is 0.5×vddq, when the value of the first target voltage is 0.65×vddq, the first generating circuit is configured to generate the second pull-up signal ZqPuMainb because the difference between the first target voltage Vref1 and the preset intermediate voltage is greater than or equal to 0.1×vddq and less than 0.3×vddq; the second pull-up signal ZqPuMainb is used to turn on the second pull-up driving leg 102.
The preset intermediate voltage is a theoretical voltage of an output end when only one pull-up driving branch is started, and theoretically, if the sum of the equivalent resistance of each pull-up driving branch and the equivalent resistance of the corresponding switching circuit are calibrated to be the same as that of the pull-down branch, the sum is 240 ohms of standard resistance, and the theoretical voltage of the output end should be 0.5Vddq; in practical production, the theoretical voltage may deviate from the PVT value due to the influence of the PVT and parasitic resistance, but in any case, a reasonable theoretical voltage can be obtained by taking an average value through multiple tests. Since the first target voltage and the theoretical voltage are determined before calibration, the number of pull-up driving branches to be turned on can be determined directly according to the first target voltage, because the adjusting effect of the calibration code on the equivalent resistance of the pull-up driving branches is fixed and has smaller amplitude, when the first target voltage has large change, the adjustment can be generally realized only by adjusting the number of turned-on pull-up driving branches.
That is, after the first target voltage is determined, before the impedance calibration is performed, all the pull-up driving branches to be turned on are turned on, so that the voltage ZqOut at the output end approaches the first target voltage, then the difference between the first target voltage and the voltage at the output end determines and generates a pull-up calibration code, and the pull-up calibration code adjusts the equivalent resistance of the pull-up driving branches, so that the voltage at the output end is further close to or even equal to the first target voltage.
In some embodiments, prior to the impedance calibration operation, the first generating circuit 300 is configured such that, based on the first target voltage Vref1, three switching circuits need to be opened for impedance calibration; in an impedance calibration operation, in response to a calibration enable signal EnCalPu, the first generation circuit is configured to generate a first pull-up signal ZqPuMaina; the first pull-up signal ZqPuMaina is used to turn on the first pull-up driving leg 101;
if the preset intermediate voltage is 0.5×vddq, when the value of the first target voltage is 0.8×vddq, the first generating circuit is configured to generate the third pull-up signal ZqPuMainc because the difference between the first target voltage and the preset intermediate voltage is greater than or equal to 0.3×vddq; the third pull-up signal ZqPuMainc is used to turn on the third pull-up driving leg 103;
When the preset intermediate voltage is 0.5Vddq, the difference between the first target voltage Vref1 and the preset intermediate voltage is greater than or equal to 0.3×vddq, and the first generating circuit is configured to generate a third pull-up signal ZqPuMainc; the third pull-up signal ZqPuMainc is used to turn on the third pull-up driving leg 103.
Fig. 3 is a schematic diagram of a first generating circuit according to an embodiment of the disclosure. Referring to fig. 3, in some embodiments, a first generation circuit 300 includes: a first NOT gate 320, a second NOT gate 322, a first NOT gate 324, a second NOT gate 326;
the output of the first NOT gate 320 is connected to the input of the second NOT gate 322, the first input of the first NOR gate 324, and the first input of the second NOR gate 326; the first not gate 320 receives the calibration enable signal EnCalPu, and the second not gate 322 receives the inverse signal EnCalPu of the calibration enable signal and outputs a first pull-up signal ZqPuMaina;
a second input terminal of the first nor gate 324 receives the first comparison signal Comp1_v1; the first comparison signal Comp1_V1 indicates: the difference between the first target voltage Vref1 and the preset intermediate voltage is greater than or equal to a first preset value and less than a second preset value; the first nor gate 324 outputs a second pull-up signal ZqPuMainb;
A second input terminal of the second nor gate 326 receives the second comparison signal Comp 1V 2; the second comparison signal Comp1_V2 indicates: the difference value between the first target voltage Vref1 and the preset intermediate voltage is greater than or equal to a second preset value; the second nor gate 326 outputs a third pull-up signal ZqPuMainc. It can be appreciated that the voltage of the preset intermediate voltage can be stored in a register or can be directly generated by a specific circuit; in addition, in the circuit structure shown in fig. 3, the first comparison signal and the second comparison signal are active low, and in other embodiments, the first comparison signal and the second comparison signal may be active high.
Fig. 4 is a schematic diagram of another first generating circuit according to an embodiment of the disclosure. Referring to fig. 4, in some embodiments, the first generation circuit includes:
a comparator 301 configured to: comparing the first target voltage Vref1 with the voltage ZqOut of the output end to output a first difference signal Vdiff, wherein the first difference signal Vdiff is used for representing the voltage difference between the first target voltage Vref1 and the voltage ZqOut of the output end; and
feedback circuit 302 configured to: in response to the first difference signal Vdiff, the pull-up calibration code ZqPu < N:0> is increased or decreased.
In some embodiments, feedback circuit 302 may include an adder/subtractor.
When the first difference signal Vdiff output by the comparator 301 is characterized in that the voltage difference between the first target voltage Vref1 and the voltage ZqOut at the output terminal is greater than zero (i.e., the first target voltage is greater than the voltage at the output terminal), the feedback circuit 302 increases the pull-up calibration code ZqPu < N:0> to reduce the equivalent resistance of the pull-up driving branch, or when the first difference signal Vdiff output by the comparator 301 is characterized in that the voltage difference between the first target voltage Vref1 and the voltage ZqOut at the output terminal is less than zero, the feedback circuit 302 decreases the pull-up calibration code ZqPu < N:0> until the first target voltage Vref1 and the voltage ZqOut at the output terminal are equal.
Fig. 5 is a schematic diagram of a pull-up driving branch circuit and a switching circuit according to an embodiment of the disclosure. Referring to fig. 5, in some embodiments, each pull-up drive leg (taking the third pull-up drive leg 103 of fig. 2 as an example) includes:
a pull-up switch 1031 having one end connected to one switching circuit (taking the third switching circuit 123 of fig. 2 as an example) and the other end connected to the output terminal for receiving a pull-up signal (taking the third pull-up signal ZqPuMainc as an example);
The pull-up unit 1032 is connected in parallel with the pull-up switch 1031 and is used for receiving the pull-up calibration code ZqPu < N:0>.
The pull-up switch 1031 receives the third pull-up switch signal ZqPuMainc and enables the third pull-up driving branch 103.
The pull-up switch 1031 may include at least one pull-up enable transistor M0 connected between the power supply voltage Vddq and the output terminal. The control terminal of the pull-up enable transistor receives the pull-up signal ZqPuMainc, turns on/off the pull-up enable transistor, and enables the third pull-up driving branch 103. The pull-up enable transistor M0 may be a PMOS transistor. It should be noted that, when the pull-up switch 1031 is turned on, the equivalent resistance is smaller than that when the pull-up unit 1032 receives any calibration code and is turned on, when the pull-up switch 1031 is turned off, only the pull-up unit 1032 is turned on to make the voltage ZqOut at the output end lower than the preset intermediate voltage, so as to perform the calibration function, and the enabling function of the pull-up switch 1031 means that the voltage ZqOut at the output end is only close to the preset intermediate voltage when the pull-up switch 1031 is turned on, so as to calibrate the sum of the equivalent resistances of the pull-up driving branch and the switching circuit.
The pull-up unit 1032 may include n+1 pull-up transistors M1 to mn+1 connected in parallel with the pull-up switch 1031; each bit of the pull-up calibration code ZqPu < N:0>, one of the pull-up calibration codes ZqPu <0> to ZqPu < N >, corresponds to turning on/off one of the pull-up transistors (one of the pull-up transistors M1 to MN+1). The pull-up transistors M1-MN+1 may be PMOS transistors.
Illustratively, when N takes a value of 5, the pull-up unit 1032 includes 6 pull-up transistors M1-M6 connected in parallel with the pull-up switch 1031 for receiving pull-up calibration codes ZqPu <0> to ZqPu <5>, each bit of the calibration code ZqPu <5:0> (one of the pull-up calibration codes ZqPu <0> to ZqPu <5 >) corresponding to turning on/off a corresponding one of the pull-up transistors (one of the pull-up transistors M1-M6).
In some embodiments, the equivalent resistances of the pull-up transistors M1-MN+1 in the on state sequentially form an equi-differential arrangement or an equi-ratio arrangement. Illustratively, the ratio of the equivalent resistances of the pull-up transistors M1-MN+1 in the on state is 1:2:4:8 … … 2 in order N 。
Referring to fig. 5, in some embodiments, the gate resistance of the transistor in the switching circuit is greater than the gate resistance of the transistor in the pull-up switch.
The third switch circuit 123 includes a switch transistor Mc, the pull-up switch of the third pull-up driving branch 103 includes a pull-up enabling transistor M0, and setting the gate resistance of the switch transistor Mc to be greater than the gate resistance of the pull-up enabling transistor M0 is beneficial to reducing the noise factor of the switch circuit, reducing the fluctuation formed by the influence of PCT on the equivalent resistance of the switch circuit, and increasing the equivalent resistance of the switch circuit, that is, increasing the equivalent resistance of one or more switch circuits that are finally turned on, the equivalent resistance of the pull-up driving branch is further reduced, so that the sum of the equivalent resistances of the switch circuit and the pull-up driving branch is less affected by PVT, and the sum of the equivalent resistances is guaranteed to meet the requirements of JEDEC, that is, to be closer to 240 ohms as standard resistance.
Fig. 6 is a schematic diagram of a switching circuit according to an embodiment of the disclosure; fig. 7 is a schematic diagram of another switching circuit according to an embodiment of the disclosure. In conjunction with fig. 2 and 6, or in conjunction with fig. 2 and 7, in some embodiments, each switching circuit includes a respective one of the level shifting circuits configured to receive the pull-up pull-down signal and output a switching voltage that communicates the respective switching circuit to the power supply. The level shift circuit includes a first level shift circuit 341, a second level shift circuit 342, and a third level shift circuit 343.
In some embodiments, referring to fig. 2 and 6, the first level conversion circuit 341 receives the first pull-up switching signal ZqPuMaina, generates the first switching voltage EnSwaVwlp according to the first pull-up switching signal ZqPuMaina, and the first switching voltage EnSwaVwlp is used to turn on a switching transistor (not shown in fig. 2) to connect the first pull-up driving leg 101 to the power supply 140; the second level conversion circuit 342 receives the second pull-up signal ZqPuMainb, generates a second switching voltage EnSwbVwlp according to the second pull-up signal ZqPuMainb, and the second switching voltage EnSwbVwlp is used for turning on a switching transistor (not shown in fig. 2) to communicate the second pull-up driving leg 102 with the power supply 140; the third level conversion circuit 343 receives the third pull-up switching signal ZqPuMainc, generates the third switching voltage EnSwcVwlp according to the third pull-up switching signal ZqPuMainc, and the third switching voltage EnSwcVwlp is used for turning on the switching transistor Mc (refer to fig. 5) to connect the third pull-up driving leg 103 to the power supply 140.
In other embodiments, referring to fig. 2 and 7, the first level conversion circuit 341, the second level conversion circuit 342, and the third level conversion circuit 343 each receive the calibration enable signal ZqCalPu, and generate the first switching voltage EnSwaVwlp, the second switching voltage EnSwbVwlp, and the third switching voltage EnSwcVwlp according to the calibration enable signal ZqCalPu, where the first switching voltage EnSwaVwlp, the second switching voltage enswbvvlp, and the third switching voltage enswcvvlp are respectively used to turn on the corresponding switching transistors to connect the first pull-up driving branch 101, the second pull-up driving branch 102, and the third pull-up driving branch 103 to the power supply 140.
Referring to fig. 1 described above, in some embodiments, the impedance calibration circuit 10 further includes a pull-down drive circuit 200; the pull-down driving circuit 200 and the pull-up driving circuit 100 are connected at the output end;
the pull-down driving circuit 200 includes at least two pull-down driving legs, each configured to: receiving a pull-down switch signal ZqPdMain and a pull-down calibration code ZqPd < N:0>, gating a designated number of pull-down driving branches by using the pull-down switch signal ZqPdmain, and adjusting the voltage of an output end by using the pull-down calibration code ZqPd < N:0 >; the pull-down driving circuit is used for pulling down the voltage ZqOut of the output end; wherein the number of pull-down driving legs 200 is smaller than the number of pull-up driving legs 100.
Referring to fig. 2 described above, the number of pull-down driving legs 200 is smaller than the number of pull-up driving legs 100. Here and hereinafter, the description will be made taking an example in which the pull-down driving circuit includes two pull-down driving branches.
In some embodiments, the pull-down drive circuit includes a first pull-down drive leg 201 and a second pull-down drive leg 202; the pull-down switching signal comprises a first pull-down switching signal ZqPdMaina and a second pull-down switching signal ZqPdMainb;
the first pull-down driving leg 201 is configured to: receiving a first pull-down signal ZqPdMaina, enabling the first pull-down driving leg 201; receiving a pull-down calibration code ZqPd < N:0> to adjust the voltage ZqOut of the output end;
the second pull-down drive leg 202 is configured to: receiving a second pull-down signal ZqPdMainb, enabling the second pull-down drive leg 202; the voltage ZqOut at the output is adjusted by receiving the pull-down calibration code ZqPd < N:0 >.
Here, the first pull-down driving leg 201 has a first equivalent resistance Rzqda and the second pull-down driving leg 202 has a second equivalent resistance Rzqdb.
Fig. 8 is a schematic diagram of a pull-down driving leg according to an embodiment of the present disclosure. Referring to fig. 8, in some embodiments, each pull-down drive leg (exemplified by the second pull-down drive leg 202 of fig. 2) includes:
A pull-down switch 2021, one end of which is connected to the output terminal, and the other end of which is connected to the ground voltage Vssq, for receiving the pull-down switch signal ZqPdMainb;
the pull-down unit 2022, the pull-down unit 2022 is connected in parallel with the pull-down switch 2021 for receiving the pull-down calibration code ZqPd < N:0>.
The pull-down switch 2021 may include at least one pull-down enable transistor Md0 connected between the ground voltage Vssq and the output terminal. The pull-down enable transistor Md0 may be an NMOS transistor.
The pull-down unit 2022 may include n+1 pull-down transistors Md1 to MdN +1 connected in parallel with the pull-down switch 2021; each bit of the pull-down calibration code ZqPd < N:0> (one of the pull-down calibration codes ZqPd <0> -ZqPd < N >) correspondingly turns on/off one pull-down transistor (one of the pull-down transistors Md 1-MdN +1). The pull-down transistors Md 1-MdN +1 may be NMOS transistors.
Illustratively, when N takes a value of 5, the pull-down unit 2022 includes 6 pull-down transistors Md 1-Md 6 connected in parallel with the pull-down switch 2021 for receiving pull-down calibration codes ZqPd <0> to ZqPd <5>, each bit of the calibration code ZqPd <5:0> (one of the pull-down calibration codes ZqPd <0> -ZqPd <5 >) corresponding to turn on/off a corresponding one of the pull-down transistors (one of the pull-down transistors Md 1-Md 6).
In some embodiments, the resistances of the pull-down transistors Md 1-MdN +1 in the on state sequentially form an equi-differential arrangement or an equal-ratio arrangement. Illustratively, the ratio of the equivalent resistances of the pull-down transistors Md 1-MdN +1 in the on state is 1:2:4:8 … … 2 in order N 。
Fig. 9 is a schematic diagram of another impedance calibration circuit according to an embodiment of the present disclosure. Referring to fig. 9, in some embodiments, the impedance calibration circuit 10 further includes:
the second generation circuit 500 is configured to: receiving a second target voltage Vref2 and the voltage ZqOutside of the external calibration terminal, generating a pull-down signal ZqPdMain based on the second target voltage Vref2, and generating a pull-down calibration code ZqPd < N:0> based on the difference between the second target voltage Vref2 and the voltage ZqOutside of the external calibration terminal; the external calibration terminal is connected in series between the external standard resistor Rzqs and the external pull-down driving circuit 400, and the external pull-down driving circuit 400 and the pull-down driving branch 200 receive the same pull-down signal ZqPdMain and the pull-down calibration code ZqPd < N:0>.
The external calibration terminal may include a calibration pad 601. The external standard resistor Rzqs is coupled between the power supply voltage Vddq and the calibration pad 601, and the external pull-down driving circuit 400 is coupled between the ground voltage Vssq and the calibration pad 601. The external standard resistor Rzqs may have a resistance value of 240 ohms. The external pull-down driving circuit 400 may have the same configuration as the pull-down driving circuit 200 in fig. 1.
The second generation circuit 500 may have the same configuration as the first generation circuit 300 in fig. 1.
In some embodiments, the reference voltage providing unit (not shown in fig. 9) may generate the first target voltage Vref1 and the second target voltage Vref2 as needed. The first target voltage Vref1 and the second target voltage Vref2 may have different voltage levels. Illustratively, the first output terminal of the reference voltage providing unit is configured to provide a first target voltage Vref1, the second output terminal of the reference voltage providing unit is configured to provide a second target voltage Vref2, and the first target voltage Vref1 is greater than the second target voltage Vref2.
Fig. 10 is a schematic diagram of a memory according to an embodiment of the disclosure. Referring to fig. 10, according to a second aspect of the presently disclosed embodiments, there is provided a memory 22 comprising: the impedance calibration circuit 10 of any of the above aspects.
The memory 22 includes the impedance calibration circuit 10 of any of the above schemes. The memory 22 may perform an impedance calibration operation in response to an impedance calibration command sent by a memory controller (not shown in fig. 10).
In some embodiments, memory 22 may include volatile memory and nonvolatile memory.
In an exemplary embodiment, the memory 22 may be any of a variety of memory devices that support high speed operation, such as dynamic random access memory (DRAM, dynamic Random Access Memory). For example, the impedance calibration operation may be performed in response to an impedance calibration command sent by the memory controller.
Before data is transmitted and/or received in the memory 22, an impedance calibration operation is performed by the impedance calibration circuit 10, and after calibration is completed, the output impedance and/or the termination impedance of the memory 22 are adjusted, so that impedance mismatch between the memory 22 and the memory controller is reduced or eliminated, and high-speed data transmission is facilitated.
Fig. 11 is a schematic diagram of a memory system according to an embodiment of the disclosure. Referring to fig. 11, according to a third aspect of an embodiment of the present disclosure, there is provided a memory system 20 comprising: the memory 22 of any of the above schemes.
The memory system 20 includes at least one memory 22 and a memory controller 24 coupled to the at least one memory.
The Memory system 20 may be implemented in a module structure such as a Dual-Inline-Memory-Modules (DIMM) or high-bandwidth Memory (HBM, high Bandwidth Memory) device in which the Memory 22 and the Memory controller 24 are integrated into one substrate.
Under control of a host (not shown in fig. 11), the memory controller 24 may send write commands, read commands, impedance calibration commands to the memory 22. The memory 22 may perform a write operation in response to a write command, a read operation in response to a read command, and a resistance calibration operation in response to a resistance calibration command.
The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure, but rather, the equivalent structural changes made by the present disclosure and the accompanying drawings under the inventive concept of the present disclosure, or the direct/indirect application in other related technical fields are included in the scope of the present disclosure.
Claims (10)
1. An impedance calibration circuit, comprising:
a pull-up driving circuit including a plurality of pull-up driving branches configured to: receiving a pull-up switching signal and a pull-up calibration code, gating a designated number of pull-up driving branches by using the pull-up switching signal, and adjusting the voltage of an output end by using the pull-up calibration code; the pull-up driving circuit is used for pulling up the voltage of the output end;
a plurality of switching circuits, each of the pull-up driving branches being connected to a power supply through a corresponding one of the switching circuits, configured to: receiving the pull-up switch signal and communicating a specified number of the pull-up drive legs with the power supply using the pull-up switch signal;
A first generation circuit configured to: the method includes receiving a first target voltage and a voltage of the output terminal, generating the pull-up signal based on the first target voltage, and generating the pull-up calibration code based on a difference therebetween.
2. The impedance calibration circuit of claim 1 wherein the pull-up drive circuit comprises a first pull-up drive leg, a second pull-up drive leg, and a third pull-up drive leg; the plurality of switching circuits includes a first switching circuit, a second switching circuit, and a third switching circuit; the pull-up switch signal comprises a first pull-up switch signal, a second pull-up switch signal and a third pull-up switch signal;
the first switching circuit is configured to: receiving the first pull-up signal, and communicating the first pull-up driving branch with the power supply; and the first pull-up drive leg is configured to: receiving the first pull-up signal, enabling the first pull-up driving branch;
the second switching circuit is configured to: receiving the second pull-up signal, and communicating the second pull-up driving branch with the power supply; and the second pull-up drive leg is configured to: receiving the second pull-up signal, enabling the second pull-up driving branch;
The third switching circuit is configured to: receiving the third pull-up signal, and communicating the third pull-up driving branch with the power supply; and the third pull-up drive leg is configured to: and receiving the third pull-up driving signal to enable the third pull-up driving branch.
3. The impedance calibration circuit of claim 2, wherein the first generation circuit is configured to: generating the first pull-up signal in response to a calibration enable signal;
when the difference between the first target voltage and the preset intermediate voltage is greater than or equal to a first preset value and less than a second preset value, the first generating circuit is configured to: generating the second pull-up signal; the preset intermediate voltage is a theoretical voltage of the output end when one pull-up driving branch is started;
when the difference between the first target voltage and the preset intermediate voltage is greater than or equal to a second preset value, the first generating circuit is configured to: generating the third pull-up signal; the second preset value is greater than the first preset value.
4. The impedance calibration circuit of claim 1 wherein the first generation circuit comprises:
A comparator configured to: comparing the first target voltage with the voltage of the output end to output a first difference signal, wherein the first difference signal is used for representing the voltage difference between the first target voltage and the voltage of the output end; and
a feedback circuit configured to: the pull-up calibration code is increased or decreased in response to the first difference signal.
5. The impedance calibration circuit of claim 1 wherein each of the pull-up drive legs comprises:
one end of the pull-up switch is connected with one switch circuit, and the other end of the pull-up switch is connected to the output end and is used for receiving the pull-up signal;
and the pull-up unit is connected with the pull-up switch in parallel and is used for receiving the pull-up calibration code.
6. The impedance calibration circuit of claim 5 wherein the gate resistance of the transistor in the switching circuit is greater than the gate resistance of the transistor in the pull-up switch.
7. The impedance calibration circuit of claim 1 further comprising a pull-down drive circuit; the pull-down driving circuit and the pull-up driving circuit are connected to the output end;
The pull-down driving circuit includes at least two pull-down driving legs, each configured to: receiving a pull-down switch signal and a pull-down calibration code, gating a designated number of pull-down driving branches by using the pull-down switch signal, and adjusting the voltage of an output end by using the pull-down calibration code; the pull-down driving circuit is used for pulling down the voltage of the output end; the number of the pull-down driving branches is smaller than that of the pull-up driving branches.
8. The impedance calibration circuit of claim 7 wherein each of the pull-down drive legs comprises:
one end of the pull-down switch is connected to the output end, and the other end of the pull-down switch is connected with the ground voltage and is used for receiving the pull-down signal;
and the pull-down unit is connected with the pull-down unit in parallel and is used for receiving the pull-down calibration code.
9. The impedance calibration circuit of claim 7 further comprising:
a second generation circuit configured to: receiving a second target voltage and a voltage of an external calibration terminal, generating a pull-down calibration signal based on the second target voltage, and generating the pull-down calibration code based on a difference between the second target voltage and the voltage of the external calibration terminal; the external calibration end is connected in series between an external standard resistor and an external pull-down driving circuit, and the external pull-down driving circuit and the pull-down driving branch circuit receive the same pull-down signal and pull-down calibration code.
10. A memory, comprising:
an impedance calibration circuit as claimed in any one of claims 1 to 9.
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| CN202310699296.XA CN116682476A (en) | 2023-06-12 | 2023-06-12 | Impedance calibration circuit and memory |
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| CN202310699296.XA CN116682476A (en) | 2023-06-12 | 2023-06-12 | Impedance calibration circuit and memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117497020A (en) * | 2023-12-29 | 2024-02-02 | 长鑫存储技术(西安)有限公司 | Output driving circuit and memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117497020A (en) * | 2023-12-29 | 2024-02-02 | 长鑫存储技术(西安)有限公司 | Output driving circuit and memory |
| CN117497020B (en) * | 2023-12-29 | 2024-04-19 | 长鑫存储技术(西安)有限公司 | Output driving circuit and memory |
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