JP5601046B2 - Failure analysis device - Google Patents

Description

  The present invention relates to a failure analysis apparatus.

  When the yield of the semiconductor device is lowered, it is important to clarify which process has the cause in order to improve the yield. Therefore, conventionally, a net in which a failure has occurred in a semiconductor device is identified by failure diagnosis, and thereafter, physical peeling and cross-sectional observation are performed to identify the cause process. However, in this specific method, the greater the integration degree of the semiconductor device, the more time and effort are required.

  Techniques aimed at eliminating the need for physical peeling and cross-sectional observation have also been proposed, but with the proposals so far, it is impossible to reliably identify which process has the cause.

JP 2007-335603 A JP 2002-156418 A

  An object of the present invention is to provide a failure analysis apparatus that can specify which manufacturing process of a semiconductor device has a cause of failure.

  One aspect of the failure analysis apparatus includes an estimation unit that estimates a failure net in which a failure has occurred from a result of failure diagnosis of a plurality of semiconductor devices of the same design, and the failure net for all wiring layers included in the semiconductor device. The number of wirings, the length of wirings, or the number of vias is calculated, and the ratio of the number of wirings, wiring lengths, or the number of vias used by the fault net between all the wiring layers is calculated. From the first ratio calculation means and the design data of the semiconductor device, for each wiring layer included in the semiconductor device, a net that may use the wiring layer is specified, and the number of wirings that the net uses, A second length for calculating the length of the wiring or the number of vias for each wiring layer, and calculating a ratio of the sum of the number of wirings, the sum of the lengths of the wirings, or the sum of the number of vias between all the wiring layers. By the ratio calculation means and the second ratio calculation means Of issued proportions of each wiring layer, and the specifying means is provided for identifying what is most approximate to the ratio calculated by the first ratio calculating means.

  According to the above failure analysis device, etc., without performing physical peeling and cross-sectional observation, identify the wiring layer that causes the yield reduction and identify which manufacturing process of the semiconductor device has the cause of failure. can do.

It is a figure showing composition of a failure analysis system concerning a 1st embodiment. It is a flowchart which shows operation | movement of the failure analysis system which concerns on 1st Embodiment. It is a figure which shows the example of the multilayer wiring contained in a semiconductor device. It is a figure which shows an example of the comparison method of a ratio. It is a figure which shows another example of the comparison method of a ratio. It is a flowchart which shows operation | movement of the failure analysis system which concerns on 2nd Embodiment.

  Hereinafter, embodiments will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. FIG. 1 is a diagram illustrating a configuration of a failure analysis system according to the first embodiment.

  In the failure analysis system according to the first embodiment, an analysis device 1 (failure analysis device), an analysis database 2, a test pattern database 3, and a design data database 4 are connected to a network 10. In addition, a tester 11 is provided, and a failure data database 12 that stores failure data obtained by the tester 11 is also connected to the network 10.

  The test pattern database 3 stores test patterns used when the tester 11 performs a pass / fail test of a semiconductor device, and test patterns used when the analysis device 1 performs a failure diagnosis of the semiconductor device. The design data database 4 stores semiconductor device wiring information and cell library design data such as GDS (Graphic Data System), DEF (design exchange format), LEF (library exchange format), and / or NetList. ing. The analysis database 2 stores the results of failure diagnosis performed by the analysis apparatus 1. The analysis apparatus 1 performs failure diagnosis of a semiconductor device, identification of a wiring layer in which a failure has occurred, and the like. The processing of the analysis device 1 is executed by operating a CPU (center processing unit) based on a program stored in a storage device such as a ROM (read only memory) or a hard disk provided therein. For example, an engineering workstation (EWS) or a personal computer (PC) is used as the analysis apparatus 1.

  Next, the operation of the failure analysis system will be described. FIG. 2 is a flowchart showing the operation of the failure analysis system according to the first embodiment.

  First, the tester 11 performs a pass / fail test on a plurality of semiconductor devices of the same design using the test patterns stored in the test pattern database 3 (step S1). When there is a lot or wafer whose yield is a predetermined value or less, failure data of the semiconductor device belonging to the lot or wafer is stored in the failure data database 12. Further, even when there is a lot or wafer showing a characteristic defective in-plane distribution, failure data of the semiconductor device belonging to the lot or wafer is stored in the failure data database 12.

  Next, the analysis device 1 refers to the test pattern stored in the test pattern database 3 and / or the NetList stored in the design data database 4, and the failure stored in the failure data database 12. Fault diagnosis is performed using the data (step S2).

  Thereafter, the analysis apparatus 1 estimates, as estimation means, a net that has a high estimation accuracy of the fault diagnosis and can narrow down the estimation candidates to a predetermined number or less from the result of the fault diagnosis (step S3). That is, the analysis apparatus 1 selects a semiconductor device failure estimation net.

  Subsequently, the analysis apparatus 1 extracts the number of wirings used by the failure estimation net from the design data stored in the design data database 4 for each wiring layer (step S4).

  Here, the process of step S4 will be described. FIG. 3 is a diagram illustrating an example of multilayer wiring included in the semiconductor device. In the example shown in FIG. 3, a plurality of sink transistors are connected to one source transistor 101. In this example, wiring layers L1 to L7 are provided in order from the semiconductor substrate side. One wiring layer includes a plug that connects the wiring and a conductive layer (such as a wiring or a diffusion layer) therebelow. Furthermore, in this example, it is assumed that the cell terminal comes out of the second wiring layer L2 from the bottom.

  In such a configuration, there are six types of routes (nets) in the portion shown in FIG. That is, there are a path connecting to the sink transistor 111 through the wiring layers L1 and L2, a path connecting to the sink transistor 112 through the wiring layers L1 to L3, a path connecting to the sink transistor 116 through the wiring layers L1 to L7, and the like. . In these paths, only one wiring layer is located at the uppermost position, and two other wiring layers are passed.

  On the other hand, as shown in FIG. 3B, there is a path that leads to the sink transistor 117 through the wiring layers L1 to L5. The path leading to the sink transistor 114 in FIG. 3A also passes through the wiring layers L1 to L5. However, the number of wiring layers and the number of vias that pass through these two types of paths are different. .

  Similarly, as shown in FIG. 3C, there is a path that connects to the sink transistor 118 through the wiring layers L1 and L2. The path leading to the sink transistor 111 in FIG. 3A also passes through the wiring layers L1 and L2. However, the number of wiring layers and the number of vias that pass through these two types of paths are different. .

  As described above, there are various paths in the semiconductor device, and there are many different paths from the example shown in FIG. In step S4, the route of the failure estimation net selected in step S3 is specified, and the number of wires in this route is extracted for each wiring layer. For example, the following Table 1 is obtained. “1” in Table 1 indicates that the failure estimation net uses (passes through) the wiring layer, and “0” indicates that the failure estimation net does not use (passes through) the wiring layer. Not).

  After step S4, the analysis apparatus 1 obtains how many wiring layers are used by the wiring extracted in step S4 as the first ratio calculation means, and calculates the ratio for each wiring layer (step S5). For example, ratios as shown in Table 2 below are obtained.

  On the other hand, the analysis apparatus 1 calculates the number of wirings used by all the paths (nets) included in the semiconductor device from the design data stored in the design data database 4 for each wiring layer. Extract (step S11). For example, the following Table 3 is obtained. “1” in Table 3 indicates that the path (net) from the source transistor 101 to the sink transistors 111 to 118 uses (passes) the wiring layer, and “0” indicates the path (net). Indicates that the wiring layer is not used (not passing).

  Next, the analysis apparatus 1 obtains the number of all wirings passing through the wiring layer for each wiring layer for each wiring layer included in the semiconductor device as a second ratio calculation means, and calculates the ratio for each wiring layer. Calculate and store in the analysis database 2 (step S12). For example, ratios as shown in Table 4 below are obtained.

  For example, the numerical value shown in the column “L1 passing” in Table 2 indicates which wiring layer is used at what ratio for all wiring that may pass through the wiring layer L1. Similarly, the numerical value indicated by the column “L7 passing” in Table 2 indicates which wiring layer is used at what ratio for all the wirings that may pass through the wiring layer L7.

  In step S6, the analyzing apparatus 1 compares the ratio calculated in step S5 with the ratio calculated in step S12 as the specifying unit, and among the ratios calculated in step S12, the ratio calculated in step S5 is the most. Identify the approximations. From this result, the wiring layer causing the yield reduction is specified. This determination of approximation is performed by, for example, the least square method. That is, the sum of squares of the differences for each wiring layer is obtained, and the one with the smallest value is specified as the closest one. When the results shown in Tables 1 and 2 are obtained, the sum of squares of the differences shown in Table 5 below is obtained, so that the wiring layer L4 is specified as the wiring layer causing the yield reduction. .

  The method for determining the approximation is not particularly limited, and may be specified from a graph as shown in FIG. 4A shows the numerical values in Tables 1 and 2 in a line graph, and FIG. 4B shows the numerical values in Table 5 in a radar chart. Further, statistical identification may be performed using an MT system or a support vector machine (SVM).

  According to the first embodiment as described above, it is possible to identify the wiring layer causing the yield reduction without performing physical peeling and cross-sectional observation. In addition, when performing physical separation analysis or cross-sectional analysis, it is possible to shorten the analysis TAT (turn around time) because the wiring layer to be noted can be preliminarily estimated, and to improve the analysis accuracy. Is also possible.

  Here, the reason will be described. For example, it is assumed that the wiring layer L4 in FIG. In this case, the failure is not detected in the path connected to the sink transistor 111 or 112, and the failure is detected in the path connected to the sink transistors 113 to 116. Therefore, the ratio of the wiring in the route including the cause location 120 approximates the ratio in all the wirings that may pass through the wiring layer L4.

  Note that steps S11 and S12 may be omitted when data as shown in Table 2 is stored in the analysis database 2 in advance.

  In this embodiment, processing based on the number of wirings is performed, but processing based on the wiring length or the number of vias for each wiring layer included in the net may be performed. In these cases, calculation regarding the wiring length or the number of vias may be performed instead of the calculation regarding the number of wirings.

  For example, when processing based on the wiring length is performed, the ratio shown in Table 6 below is obtained in Step S5, and the ratio shown in Table 7 below is obtained in Step S12. In step S6, the results shown in Table 8 below are obtained. A line graph shown in FIG. 5A is also obtained.

  Similarly, when processing based on the number of vias is performed, the ratio shown in Table 9 below is obtained in Step S5, and the ratio shown in Table 10 below is obtained in Step S12. In step S6, the results shown in Table 11 below are obtained. Moreover, the line graph shown in FIG.5 (b) is also obtained.

  As shown in Table 8 and Table 11, when the processing based on the wiring length or the number of vias for each wiring layer is performed, the wiring layer L4 is similar to the case where the processing based on the number of wirings for each wiring layer is performed. Therefore, it can be specified that the wiring layer causes a decrease in yield. Two or more types of processing based on the number of wirings, processing based on the wiring length, and processing based on the number of vias may be combined.

  Note that the ratio of the wiring layer L1 is small and the number of vias in the wiring layer L1 is 0 as shown in FIG. 5A. As described above, the cell terminals are exposed from the wiring layer L2. This is because the inter-cell wiring (router wiring) in this case is to be counted.

(Second Embodiment)
Next, a second embodiment will be described. The first embodiment is effective when the cause of the yield reduction is concentrated in a specific wiring layer, but when the cause is dispersed in many wiring layers, it becomes difficult to specify the cause. May be. In the second embodiment, it is possible to easily specify even when causes are dispersed in a large number of wiring layers.

  In order to solve this problem, high estimation accuracy can be obtained by using a method in which all combinations of failure estimation nets are created and a combination including only a single failure layer is forcibly generated. However, in this method, as the number of failure estimation nets increases, the processing becomes enormous and time is required. Therefore, in the second embodiment, the failure estimation net is allocated to a plurality of groups, and all combinations are generated within the group. FIG. 6 is a flowchart showing the operation of the failure analysis system according to the second embodiment.

  First, similarly to the first embodiment, the processes of steps S1 to S4 are performed. Next, when the number of failure estimation nets exceeds a predetermined number (N), the analysis apparatus 1 creates a group for every N pieces divided so as not to overlap each other as a dividing unit. At this time, for example, a failure estimation net is distributed using random numbers (step S21).

  Thereafter, the analysis apparatus 1 selects one unprocessed group, and creates all combinations of failure estimation nets belonging to the group (step S22).

  Subsequently, the analysis apparatus 1 calculates the ratio for each wiring layer as the first ratio calculation unit, as in step S5 of the first embodiment, for all combinations created in step S22 (step S23).

  On the other hand, the analysis apparatus 1 performs the processes of steps S11 and S12 as in the first embodiment.

  After step S23, in step S24, the analysis apparatus 1 compares the ratio calculated in step S23 with the ratio calculated in step S12, and calculates an error for each wiring layer.

  Next, the analysis apparatus 1 specifies a combination with the smallest error or a combination with the error equal to or less than a threshold as the specifying means, and sets a flag for these combinations (step S25).

  In the second embodiment, the processes in steps S22 to S25 are performed for all groups. Furthermore, after the processing for all the groups is performed, the division of the group is changed, and the processing of steps 21 to S25 is performed a predetermined number of times.

  Then, after the repetition of the predetermined number of times of the processes in steps 21 to S25, the analysis apparatus 1 counts the flags as the counting means, and identifies the wiring layer that causes the yield reduction for each failure estimation net. . For example, the results shown in Table 12 are obtained. In Table 12, seven types of repetitions are listed as examples, but the number of repetitions may be one predetermined type.

  Table 12 shows, for example, no. The failure estimation net of 10 indicates that the wiring layer L2 has a cause of yield reduction regardless of the number of repetitions. Table 12 shows, for example, No. In the case of 20 failure estimation nets, when the number of repetitions was 5, the result was that there was a cause in the wiring layer L3. However, when the number of repetitions exceeded 10, the cause of the decrease in yield in the wiring layer L2 was obtained. It also shows that there was a result. Other failure estimation nets can be similarly analyzed.

  Then, the analysis apparatus 1 further aggregates the results as shown in Table 12, calculates which wiring layer has the most influence on the yield reduction, and identifies the wiring layer causing the yield reduction. For example, the results shown in Table 13 are obtained.

  In this example, the analysis apparatus 1 determines that the wiring layer L2 has the most influence on the yield reduction, and that the wiring layer L2 causes the yield reduction. From Table 13, it is clear that the wiring layer L2 has the most influence on the yield reduction regardless of the number of repetitions. For this reason, the number of repetitions is preferably 5 or more. Moreover, when the number of repetitions exceeds 10, the change in the influence distribution is small. For this reason, it is more preferable that the number of repetitions is 10 or more.

  Note that these embodiments can be realized by, for example, a computer executing a program. In addition, means for supplying a program to a computer, for example, a computer-readable recording medium such as a CD-ROM in which such a program is recorded, or a transmission medium such as the Internet that transmits such a program can also be applied as an embodiment. The above program can also be applied as an embodiment.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
Estimating means for estimating a fault net in which a fault has occurred from the result of fault diagnosis of a plurality of semiconductor devices of the same design;
First ratio calculating means for obtaining the number of wirings used by the fault net for all wiring layers included in the semiconductor device and calculating a ratio of the number of wirings used by the fault net between all the wiring layers. When,
From the design data of the semiconductor device, for each wiring layer included in the semiconductor device, identify a net that may use the wiring layer, obtain the number of wirings used by the net for each wiring layer, Second ratio calculating means for calculating a ratio of the sum of the number of wirings between the wiring layers;
A specifying unit that specifies a ratio that is closest to the ratio calculated by the first ratio calculating unit among the ratios for each wiring layer calculated by the second ratio calculating unit;
A failure analysis apparatus comprising:

(Appendix 2)
Estimating means for estimating a fault net in which a fault has occurred from the result of fault diagnosis of a plurality of semiconductor devices of the same design;
A first ratio for obtaining a length of a wiring used by the fault net for all wiring layers included in the semiconductor device and calculating a ratio of a length of the wiring used by the fault net between all the wiring layers. A calculation means;
From the design data of the semiconductor device, for each wiring layer included in the semiconductor device, identify a net that may use the wiring layer, determine the length of wiring used by the net for each wiring layer, A second ratio calculating means for calculating a ratio of the sum of the lengths of the wirings between all the wiring layers;
A specifying unit that specifies a ratio that is closest to the ratio calculated by the first ratio calculating unit among the ratios for each wiring layer calculated by the second ratio calculating unit;
A failure analysis apparatus comprising:

(Appendix 3)
Estimating means for estimating a fault net in which a fault has occurred from the result of fault diagnosis of a plurality of semiconductor devices of the same design;
First ratio calculating means for obtaining the number of vias used by the fault net for all wiring layers included in the semiconductor device and calculating the ratio of the number of vias used by the fault net between all the wiring layers. When,
From the design data of the semiconductor device, for each wiring layer included in the semiconductor device, identify a net that may use the wiring layer, determine the number of vias used by the net for each wiring layer, Second ratio calculating means for calculating a ratio of the sum of the number of vias between the wiring layers;
A specifying unit that specifies a ratio that is closest to the ratio calculated by the first ratio calculating unit among the ratios for each wiring layer calculated by the second ratio calculating unit;
A failure analysis apparatus comprising:

(Appendix 4)
A dividing unit that divides each fault net into a plurality of groups when the number of the fault nets estimated by the estimation unit exceeds a predetermined number;
The specifying means specifies a wiring layer for each group,
A counting means for counting the wiring layers specified by the specifying means;
4. The failure analysis apparatus according to any one of appendices 1 to 3, wherein

(Appendix 5)
The dividing unit executes the division into the plurality of groups a plurality of times,
5. The failure analysis apparatus according to appendix 4, wherein the specifying unit specifies a wiring layer for each group every time the dividing unit performs a plurality of divisions.

(Appendix 6)
6. The failure analysis apparatus according to any one of appendices 1 to 5, wherein the plurality of semiconductor devices of the same design are manufactured from the same lot or wafer.

(Appendix 7)
An estimation step for estimating a failure net in which a failure has occurred from the result of failure diagnosis of a plurality of semiconductor devices of the same design,
A first ratio calculating step of obtaining the number of wirings used by the fault net for all wiring layers included in the semiconductor device and calculating a ratio of the number of wirings used by the fault net between all the wiring layers. When,
From the design data of the semiconductor device, for each wiring layer included in the semiconductor device, identify a net that may use the wiring layer, obtain the number of wirings used by the net for each wiring layer, A second ratio calculating step for calculating a ratio of the sum of the number of wirings between the wiring layers;
A specifying step for specifying a ratio that is closest to the ratio calculated in the first ratio calculating step among the ratios for each wiring layer calculated in the second ratio calculating step;
A failure analysis method characterized by comprising:

(Appendix 8)
An estimation step for estimating a failure net in which a failure has occurred from the result of failure diagnosis of a plurality of semiconductor devices of the same design,
A first ratio for obtaining a length of a wiring used by the fault net for all wiring layers included in the semiconductor device and calculating a ratio of a length of the wiring used by the fault net between all the wiring layers. A calculation step;
From the design data of the semiconductor device, for each wiring layer included in the semiconductor device, identify a net that may use the wiring layer, determine the length of wiring used by the net for each wiring layer, A second ratio calculating step for calculating a ratio of the sum of the lengths of the wirings between all the wiring layers;
A specifying step for specifying a ratio that is closest to the ratio calculated in the first ratio calculation step among the ratios for each wiring layer calculated in the second ratio calculation step;
A failure analysis method characterized by comprising:

(Appendix 9)
An estimation step for estimating a failure net in which a failure has occurred from the result of failure diagnosis of a plurality of semiconductor devices of the same design,
A first ratio calculating step of obtaining the number of vias used by the fault net for all wiring layers included in the semiconductor device and calculating a ratio of the number of vias used by the fault net between all the wiring layers. When,
From the design data of the semiconductor device, for each wiring layer included in the semiconductor device, identify a net that may use the wiring layer, determine the number of vias used by the net for each wiring layer, A second ratio calculating step for calculating a ratio of the sum of the number of vias between the wiring layers;
A specifying step for specifying a ratio that is closest to the ratio calculated in the first ratio calculation step among the ratios for each wiring layer calculated in the second ratio calculation step;
A failure analysis method characterized by comprising:

(Appendix 10)
A division step of dividing each failure net into a plurality of groups when the number of the failure nets estimated in the estimation step exceeds a predetermined number;
In the specifying step, a wiring layer is specified for each group,
A tabulation step of tabulating the wiring layers identified in the identifying step;
10. The failure analysis method according to any one of appendices 7 to 9, characterized by comprising:

1: Analysis device 2: Analysis database 3: Test pattern database 4: Design data database 10: Network 11: Tester 12: Failure data database

Claims (5)

Estimating means for estimating a fault net in which a fault has occurred from the result of fault diagnosis of a plurality of semiconductor devices of the same design;
First ratio calculating means for obtaining the number of wirings used by the fault net for all wiring layers included in the semiconductor device and calculating a ratio of the number of wirings used by the fault net between all the wiring layers. When,
From the design data of the semiconductor device, for each wiring layer included in the semiconductor device, identify a net that may use the wiring layer, obtain the number of wirings used by the net for each wiring layer, Second ratio calculating means for calculating a ratio of the sum of the number of wirings between the wiring layers;
A specifying unit that specifies a ratio that is closest to the ratio calculated by the first ratio calculating unit among the ratios for each wiring layer calculated by the second ratio calculating unit;
A failure analysis apparatus comprising: Estimating means for estimating a fault net in which a fault has occurred from the result of fault diagnosis of a plurality of semiconductor devices of the same design;
A first ratio for obtaining a length of a wiring used by the fault net for all wiring layers included in the semiconductor device and calculating a ratio of a length of the wiring used by the fault net between all the wiring layers. A calculation means;
From the design data of the semiconductor device, for each wiring layer included in the semiconductor device, identify a net that may use the wiring layer, determine the length of wiring used by the net for each wiring layer, A second ratio calculating means for calculating a ratio of the sum of the lengths of the wirings between all the wiring layers;
A specifying unit that specifies a ratio that is closest to the ratio calculated by the first ratio calculating unit among the ratios for each wiring layer calculated by the second ratio calculating unit;
A failure analysis apparatus comprising: Estimating means for estimating a fault net in which a fault has occurred from the result of fault diagnosis of a plurality of semiconductor devices of the same design;
First ratio calculating means for obtaining the number of vias used by the fault net for all wiring layers included in the semiconductor device and calculating the ratio of the number of vias used by the fault net between all the wiring layers. When,
From the design data of the semiconductor device, for each wiring layer included in the semiconductor device, identify a net that may use the wiring layer, determine the number of vias used by the net for each wiring layer, Second ratio calculating means for calculating a ratio of the sum of the number of vias between the wiring layers;
A specifying unit that specifies a ratio that is closest to the ratio calculated by the first ratio calculating unit among the ratios for each wiring layer calculated by the second ratio calculating unit;
A failure analysis apparatus comprising: A dividing unit that divides each fault net into a plurality of groups when the number of the fault nets estimated by the estimation unit exceeds a predetermined number;
The specifying means specifies a wiring layer for each group,
A counting means for counting the wiring layers specified by the specifying means;
The failure analysis apparatus according to claim 1, wherein the failure analysis apparatus includes: The dividing unit executes the division into the plurality of groups a plurality of times,
The failure analysis apparatus according to claim 4, wherein the specifying unit specifies a wiring layer for each of the groups every time the dividing unit performs division a plurality of times.

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