JP5590014B2 - Display device and driving method of display device - Google Patents

Description

The present invention relates to a pixel circuit that current-drives a light emitting element arranged for each pixel. Further, a display device which is arranged the pixel circuits in a matrix, in particular, by the insulated gate field effect transistor provided in each pixel circuit, the amount of current flowing through the light-emitting element such as an organic EL element The present invention relates to a so-called active matrix display device.

An image display device, for example, in a liquid crystal display, arranged a number of liquid crystal pixels in a matrix, by controlling the transmission intensity or the reflection intensity of the incident light for each pixel in accordance with image information to be displayed, to display an image . This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel , the organic EL element is a self-luminous element. Therefore, the organic EL display has a high image visibility than a liquid crystal display, a backlight is unnecessary, has advantages such as high response speed. Also, the brightness level of each light-emitting element (gradation) can be controlled by a current value flowing thereto, differs significantly from the voltage-controlled, such as a liquid crystal display in that a so-called current-controlled.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. The former has a simple structure, large, and, because of a problem such as it is difficult to realize a high-definition display, is currently developing an active matrix system has been popular. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.

JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

A conventional pixel circuit is arranged at a portion where a row scanning line supplying a control signal and a column signal line supplying a video signal intersect, and at least a sampling transistor, a capacitor, a drive transistor, and a light emission Element. The sampling transistor conducts in response to a control signal supplied from the scanning line, and samples the video signal supplied from the signal line. The capacitor unit holds an input voltage corresponding to the sampled video signal. The drive transistor supplies an output current during a predetermined light emission period in accordance with the input voltage held in the capacitor unit. In general, the output current on the carrier mobility and the threshold voltage of the channel region of the drive transistor, having a dependency. The light emitting element emits light with luminance according to the video signal by the output current supplied from the drive transistor.

In the drive transistor, an output current flows between the source and the drain in accordance with the input voltage held in the capacitor portion, and this current flows in the light emitting element. In general, the light emission luminance of a light emitting element is proportional to the amount of current . Furthermore, the output current of the drive transistor, a gate / source voltage, i.e., is controlled by the input voltage written in the capacitor unit. The conventional pixel circuit controls the amount of current supplied to the light emitting element by changing the input voltage applied between the gate / source of the drive transistor in accordance with the video signal .

Here, the operation characteristics of the drive transistor is expressed by Equation 1 below.
I _ds = (1/2) μ (W / L) C _ox ( V _gs −V _th ) ² Formula 1
In the transistor characteristic equation 1, I _ds represents a drain current flowing between the source and the drain, and is an output current supplied to the light emitting element in the pixel circuit. V _gs represents a gate-source voltage applied to the gate with reference to the source, and is the above-described input voltage in the pixel circuit. V _th is the threshold voltage of the transistor. Further, mu denotes the mobility of a semiconductor thin film constituting the channel region of the transistor. In addition , W represents the channel width, L represents the channel length, and C _ox represents the capacitance of the gate insulating film . As apparent from the transistor characteristic equation 1, when the thin film transistor operates in the saturation region, when the gate / source voltage V _gs exceeds the threshold voltage V _th , the thin film transistor is turned on and the drain current I _ds flows. . When principle view, as shown the transistor characteristic expression (1) described above, if the gate / source voltage V _gs constant, always drain current I _ds of the same amount is supplied to the light emitting element. Therefore, if video signals of the same level are supplied to all the pixels constituting the screen, all the pixels should emit light with the same luminance, and the uniformity of the screen should be obtained.

However , in reality, thin film transistors (TFTs) composed of a semiconductor thin film such as polysilicon have variations in individual device characteristics. In particular, the threshold voltage V _th is not constant and varies from pixel to pixel. As apparent from the transistor characteristic equation 1 described above, when the threshold voltage V _th of each drive transistor varies, even if the gate-source voltage V _gs is constant, the drain current I _ds varies, resulting in a pixel-by-pixel variation. since thus variations in brightness, impairing the uniformity of the screen. Conventionally, the pixel circuits incorporating a function to cancel the variations in the threshold voltage of the drive transistor have been developed, for example, there is disclosed in Patent Document 3 above.

Pixel circuits incorporating a function to cancel the variations in the threshold voltage can be somewhat improved the uniformity of the screen. However, the characteristics of polysilicon thin film transistors vary not only in the threshold voltage but also in the mobility μ from element to element. As is clear from the transistor characteristic equation 1 described above, when the mobility μ varies , the drain current I _ds varies even if the gate-source voltage V _gs is constant. As a result , since the light emission luminance changes for each pixel, there is a problem that the uniformity of the screen is impaired.

In view of the problems of the prior art described above, the present invention cancels the influence of the mobility, than Te, the drive transistor supplies drain current (output current) can be compensated pixel circuit and a display device variations in the driving It aims to provide a method. In order to achieve this purpose , the following measures were taken. That is, the present invention, the control signal and a column-like signal line for supplying a scan line and the video signal of rows supplying disposed at the intersection, at least a sampling transistor, a capacitance portion, and the drive transistor , and a light emission element, the sampling transistor is rendered conductive in response to the control signal supplied from the scanning line at a predetermined sampling period to sample the video signal supplied from the signal line to the capacitive unit, the capacity The unit applies an input voltage between the gate and the source of the drive transistor according to the sampled video signal, and the drive transistor outputs an output current according to the input voltage during a predetermined light emission period. The output current depends on the carrier mobility of the channel region of the drive transistor, and the light emitting element In a pixel circuit that emits light with a luminance corresponding to the video signal by an output current supplied from a transistor, in order to cancel the dependency of the output current on carrier mobility, the capacitor unit is previously set in the capacitor unit before or at the beginning of the light emission period. Compensating means for correcting the held input voltage is provided. The correcting means operates in a part of the sampling period in accordance with a control signal supplied from a scanning line, and the video signal is sampled. In this state, an output current is taken out from the drive transistor and negatively fed back to the capacitor to correct the input voltage.

Preferably, the drive transistor has an output current dependent on a threshold voltage in addition to the carrier mobility of the channel region, and the correcting means cancels the dependence of the output current on the threshold voltage. The threshold voltage of the drive transistor is detected in advance prior to the sampling period, and the detected threshold voltage is added to the input voltage. In one aspect, the drive transistor is an N-channel transistor, the drain is connected to the power supply side, and the source is connected to the light emitting element side, and the correction means emits light that overlaps a rear portion of the sampling period. The output current is taken out from the drive transistor at the beginning of the period and negatively fed back to the capacitor side. In this case, the correction means causes the output current taken from the source side of the drive transistor at the beginning of the light emission period to flow into the capacitance of the light emitting element. Further, the light emitting element is composed of a diode type light emitting element having an anode and a cathode, the anode side is connected to the source of the drive transistor, and the cathode side is grounded. When the output current taken from the source side of the drive transistor flows into the light emitting element, the diode type light emitting element functions as a capacitive element. Control. In another aspect, the drive transistor is a P-channel transistor, the source is connected to the power supply side, and the drain is connected to the light-emitting element side, and the correction means includes the sampling that precedes the light-emission period. During a part of the period, the output current is extracted from the drive transistor and negatively fed back to the capacitor side. Preferably, the correction means can adjust the time range for taking out an output current from the drive transistor in the sampling period, thereby, optimize the negative feedback amount of the output current to the capacitive part.

Further, the present invention includes a pixel array section and a scanner section and a signal section, the pixel array having scanning lines arranged in rows, and signal lines arranged in columns, at respective intersections consists of a disposed a matrix of pixels, the signal unit, and supplies the video signal to the signal lines, the scanner unit supplies a control signal to the scanning lines, scanning the pixels in each sequential line each pixel has at least includes a sampling transistor, a capacitance portion, and the drive transistor, and a light emission element, the sampling transistor is rendered conductive in response to a control signal supplied from the scanning line at a predetermined sampling period Te samples the video signal supplied from the signal line to the capacitive unit, the capacitor unit, an input voltage is applied between the gate and source of the drive transistor in response to the sampled video signal, the de Eve transistor during a predetermined light emission period, the output current corresponding to the input voltage supplied to the light emitting element, the output current has a dependency on a carrier mobility in the channel region of the drive transistor, wherein In the display device in which the light emitting element emits light with the luminance corresponding to the video signal by the output current supplied from the drive transistor, each pixel cancels the dependence on the carrier mobility of the output current of the drive transistor. A correction unit that corrects the input voltage held in the capacitor unit in advance before or at the head of the light emission period is provided, and the correction unit performs a part of the sampling period according to a control signal supplied from a scanning line. The output current is taken out from the drive transistor while the video signal is sampled, and the output current is negatively applied to the capacitor unit. Barb and correcting the input voltage.

Preferably, the drive transistor has an output current dependent on a threshold voltage in addition to the carrier mobility of the channel region, and the correcting means cancels the dependence of the output current on the threshold voltage. The threshold voltage of the drive transistor is detected in advance prior to the sampling period, and the detected threshold voltage is added to the input voltage. In one aspect, the drive transistor is an N-channel transistor, the drain is connected to the power supply side, and the source is connected to the light emitting element side, and the correction means emits light that overlaps a rear portion of the sampling period. The output current is taken out from the drive transistor at the beginning of the period and negatively fed back to the capacitor side. In this case, the correction means causes the output current taken from the source side of the drive transistor at the beginning of the light emission period to flow into the capacitance of the light emitting element. Further, the light emitting element is composed of a diode type light emitting element having an anode and a cathode, the anode side is connected to the source of the drive transistor, and the cathode side is grounded. When the output current taken from the source side of the drive transistor flows into the light emitting element, the diode type light emitting element functions as a capacitive element. Control. In another aspect, the drive transistor is a P-channel transistor, the source is connected to the power supply side, and the drain is connected to the light emitting element side, and the correction means includes the sampling that precedes the light emission period. in some periods, remove the output current from said drive transistor is negatively fed back to the capacitive side. Preferably, the correction means can adjust the time range for taking out an output current from the drive transistor in the sampling period, thereby, optimize the negative feedback amount of the output current to the capacitive part.

The present invention includes a pixel array section and a scanner section and a signal section, the pixel array having scanning lines arranged in rows, and signal lines arranged in columns, distributing at respective intersections consists of a matrix of pixels, the signal unit supplies a video signal to the signal lines, the scanner unit supplies a control signal to the scanning lines, scanning the pixels in each sequential line, each pixel includes at least a sampling transistor, a capacitance portion, and the drive transistor, a driving method of a display device including a light emission element, wherein the scanner unit, the sampling transistor from the scanning line at a predetermined sampling period A control signal is supplied to the signal line to conduct the current and the video signal supplied from the signal line is sampled in the capacitor unit. The capacitor unit is configured to sample the gate and the source of the drive transistor in accordance with the sampled video signal. Scan input voltage is applied between the drive transistor during a predetermined light emission period, the output current corresponding to the input voltage supplied to the light emitting element, the output current, the carrier moves in the channel region of the drive transistor a dependency on degree, the light emitting element, the output current supplied from the drive transistor and emits light with a luminance corresponding to the video signal, further, the scanner unit, the output current of the drive transistor In order to cancel the dependence on the carrier mobility, the pixel is subjected to a correction procedure for correcting the input voltage held in the capacitor unit in advance before or at the head of the light emission period, and the correction procedure is performed in the sampling period. The output current is taken out from the drive transistor while the video signal is being sampled in the circuit, and this is negatively fed back to the capacitor section to input the input current. It is corrected.

According to the present invention, to counteract the dependence on the carrier mobility of the output current of the drive transistor, the pixel circuit, the correction means for correcting the input voltage for the drive transistor prior to or at the beginning of the emission period (voltage between gate / source) It has. This correction means operates during a part of the sampling period, takes out the output current (drain current) from the drive transistor while the potential of the video signal (signal potential) is sampled, and negatively feeds this back to the capacitor unit. The input voltage ( gate / source voltage ) is corrected. As apparent from the transistor characteristic equation 1 described above, the output current (drain current) is proportional to the mobility. Therefore, the mobility of the drive transistor of a pixel is large, the output current is relatively large. This is negatively fed back to the capacitor to correct the input voltage ( gate / source voltage ). When the mobility is large , the negative feedback amount is increased as a result, so that the input voltage ( gate / source voltage ) is corrected downward by that much. Since the gate-source voltage is lowered , the drain current is suppressed as a result. On the other hand, when the mobility of the drive transistor of another pixel is relatively small, the drain current is also small . Accordingly, the amount of negative feedback with respect to the capacitor is small, so that the downward correction of the gate / source voltage is small. Consequently, the mobility of the drive transistor is small, the output current is ho not Tadashisa throat complement. In this way, the correction means of the present invention feedback corrects the input voltage so as to cancel the variation in mobility, so that the uniformity of the screen is improved. In particular, mobility correction is performed in a state where the signal potential is being sampled. The amplitude of the video signal changes from the black level to the white level, but it is possible to perform mobility correction appropriately at any level. Further, the amount of negative feedback applied to the input voltage depends on the output current extraction time. The longer the extraction time, the larger the negative feedback amount. In the present invention, the extraction time of the output current during the sampling period is variably adjusted, it is possible to optimize the negative feedback amount. In the present invention, the signal potential is sampled to drive the light emitting element with current. It is the same as the conventional liquid crystal display in that the signal potential is sampled. Therefore, a voltage signal driver has been widely used in active matrix liquid crystal display, it can be used for signal section of the present invention. Further, the in the same manner as conventional polysilicon thin film transistor active matrix liquid crystal panel integrated form, in the display device of the present invention, to form a scanner portion and the signal portion surrounding the integrally pixel array section near It is also possible to put together a panel with a built-in circuit.

It is a block diagram which shows the reference example of a display apparatus. FIG. 2 is a circuit diagram illustrating a configuration of a pixel circuit included in the display device illustrated in FIG. 1. 3 is a reference timing chart for explaining the operation of the pixel circuit shown in FIG. 2. It is a graph which shows the input voltage / output current characteristic of a drive transistor. 1 is a block diagram showing a first embodiment of a display device according to the present invention. It is the schematic diagram which took out the pixel circuit contained in the display apparatus shown in FIG. 7 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 6. FIG. 7 is a schematic diagram for explaining an operation of the pixel circuit shown in FIG. 6. It is a graph similarly provided for operation | movement description. It is a schematic diagram for explaining the operation in the same manner. 7 is a graph showing operating characteristics of a drive transistor included in the pixel circuit shown in FIG. 6. It is a block diagram which shows 2nd Embodiment of the display apparatus concerning this invention. 13 is a timing chart for explaining the operation of a pixel circuit included in the display device shown in FIG. It is a pixel circuit diagram for the same explanation of operation. It is a block diagram which shows 3rd Embodiment of the display apparatus concerning this invention. FIG. 16 is a schematic diagram for explaining an operation of a pixel circuit included in the display device illustrated in FIG. 15. 6 is a timing chart for explaining the operation. It is a schematic diagram for explaining the operation in the same manner.

Hereinafter , embodiments of the present invention will be described in detail with reference to the drawings. First, to clarify the background of the present invention, with reference to FIG. 1, illustrating a reference example of the active matrix display device having a V _th correction function first. As shown in the figure, the active matrix display device includes a pixel array 1 as a main part and a peripheral circuit part. The peripheral circuit unit includes a horizontal selector 3, a write scanner 4, a drive scanner 5, a correction scanner 7, and the like. Pixel array 1 includes scan lines WS in rows, and a and column-like signal line SL, and the pixel arranged at the intersection of both the matrix R, G, and B. Order to enable a color display, but are prepared three primary colors pixel of RGB, not limited to Re this. Each pixel R, G, B is constituted by a pixel circuit 2. The signal line SL is driven by the horizontal selector 3. The horizontal selector 3 forms a signal unit and supplies a video signal to the signal line SL. The scanning line WS is scanned by the write scanner 4. Incidentally, in parallel with the scanning lines WS, it is also wired another scan line DS and AZ. The scanning line DS is scanned by the drive scanner 5. The scanning line AZ is scanned by the correction scanner 7. Write scanner 4, the drive scanner 5 and the correction scanner 7 constitute a scanner unit, sequentially scans the rows of pixels every horizontal period. Each pixel circuit 2, when selected by the scanning line WS, samples the video signal from the signal line SL. Further , when selected by the scanning line DS, the light emitting element included in the pixel circuit 2 is driven in accordance with the sampled video signal. In addition , the pixel circuit 2 performs a predetermined correction operation when scanned by the scanning line AZ.

Pixel array 1 described above, typically, it is formed on an insulating substrate such as glass, and has a flat panel. Transistors constituting the pixel circuits 2 is formed of an amorphous silicon thin film transistor (TFT) or a low-temperature polysilicon TFT. For amorphous silicon TFT, a scanner unit panel and is configured by a different TAB, it is connected to the flat panel by flexible cables. In the case of the low-temperature polysilicon TFT, the signal portion and the scanner portion can be formed of the same low-temperature polysilicon TFT, so that the pixel array portion, the signal portion, and the scanner portion can be integrally formed on the flat panel.

FIG. 2 is a circuit diagram showing a configuration of a pixel circuit included in the pixel array shown in FIG. As shown, the pixel circuit 2, and five thin-film transistors _{Tr 1, Tr 3 ~Tr 5,} Tr d, and two capacitive elements C _s1, C _s2, is composed of a single light emitting element EL Yes. Transistors _{Tr 1, Tr 3 ~Tr 5,} Tr d is a polysilicon TFT of all P-channel type. However , the present invention is not limited to this, and N-channel polysilicon TFTs may be mixed. Alternatively, the pixel circuit may be formed of an N channel type amorphous silicon TFT. Two capacitive elements C _s1 and C _s2 constitute a capacitance section of the pixel circuit 2 combined both. The light emitting element EL is composed of , for example , a diode type organic EL element having an anode and a cathode. However , the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

Drive transistor Tr _d which is the center of the pixel circuit 2, a gate (G) is connected to the point G, the source (S) is connected to the S point, the drain (D) is connected to the D point. The light emitting element EL has an anode connected to the point D and a cathode grounded. The switching transistor Tr ₄ is connected between the power supply potential V _cc and the point S, to control the light emitting element EL on / off. The gate of the transistor Tr ₄ is connected to the scan line DS.

On the other hand, the sampling transistor Tr ₁ is connected between the signal line SL and the point A. The gate of the sampling transistor Tr ₁ is connected to the scanning line WS. Between the point A and point S, the detection transistor Tr ₅ is connected. The gate is connected to the scanning line AZ. The switching transistor Tr ₃ is connected between the point G and a predetermined offset potential V _ofs. The gate is connected to the scanning line AZ. The detection transistor Tr ₅ and the switching transistor Tr ₃ constitute correcting means for V _th cancellation. One of the capacitor C _s1 is connected between the point A and the point G, the other capacitor element C _s2, is connected between the power supply potential V _cc and A points.

The drive transistor Tr _d causes the drain current I _ds to flow between the source and drain in accordance with the gate / source voltage V _gs applied between the source and gate, thereby driving the light emitting element EL. In this specification , the gate / source voltage V _gs is defined as an input voltage, and the drain current I _ds is defined as an output current. The gate / source voltage V _gs is set according to the video signal V _sig supplied from the signal line SL, and the drain current I _{ds is} thereby flowed to control the light emission luminance of the light emitting element EL according to the gray level of the video signal. it can.

The threshold voltage V _th of the drive transistor Tr _d varies from pixel to pixel. In order to cancel this, the threshold voltage V _th of the drive transistor Tr _d is detected in advance and held in the capacitive element C _s1 . Thereafter , the sampling transistor Tr ₁ is turned on and the signal potential V _sig is written to the capacitive element C _s2 . By such a manner set gate / source voltage V _gs, to drive the drive transistor Tr _d.

FIG. 3 is a timing chart for explaining the operation of the pixel circuit shown in FIG. Along the time axis T, the scanning lines WS, is represented the waveform of the control signal applied to the AZ and DS. In order to simplify the notation, hereinafter , in the present specification , control signals are also denoted by the same reference numerals as the corresponding scanning lines. Since all transistors are P-channel type, the scanning line is turned off when the high level, and turned on when a low level. Therefore , in order to simplify the notation, in this reference example, the case where the control signal falls from the high level to the low level is represented as “on”, and the case where the control signal rises from the low level to the high level is referred to as “off”. Along with the waveforms of the control signals WS, AZ, and DS, potential changes at points A and G are also shown. In the case of the N channel type, conversely, the case where the control signal falls from the high level to the low level is represented as “off”, and the case where the control signal rises from the low level to the high level is referred to as “on”.

In the timing chart shown , timings T1 to T7 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. The timing chart represents the waveforms of the control signals WS, AZ, DS applied to the pixels for one row.

At the timing T0 before the field starts, the control signals WS and AZ are off while the control signal DS is on. Therefore , the sampling transistor Tr ₁ , the detection transistor Tr _5, and the switching transistor Tr ₃ are in an off state, whereas only the switching transistor Tr ₄ is in an on state. In this state, the point A potential is at the signal potential V _sig , and the point G potential is at a potential that is lower than V _sig by V _th . In this case, S the potential at the point, since the transistor Tr ₄ is turned on, and has a V _cc. Therefore, between the source and the gate of the transistor Tr _d is sufficient voltage is applied in excess of V _th, the output current I _ds is supplied to the light emitting element EL. Therefore , at the timing T0, the light emitting element EL is in a light emitting state.

Thereafter , the control signal AZ is turned on at the timing T1 when entering the field, and the transistors Tr ₅ and Tr ₃ are turned on. This result, A point and S point directly connected, A point potential rises rapidly to supply potential V _cc. Meanwhile, since the transistor Tr ₃ is turned on, G point potential falls rapidly to a predetermined offset potential V _ofs.

Immediately after this, the control signal DS is turned off at timing T2, the switching transistor Tr ₄ is turned off. Thus, S point is disconnected from the power supply potential V _cc, changes to the non-emission state. In the period T1-T2 from the timing T1 to the timing T2, A point potential V _cc, and the the G point potential becomes V _ofs, the potential of the capacitance elements C _s1, C _s2 is reset. This reset operation is a preparation for stabilizing the subsequent detection operation, and the period T1-T2 is referred to as a reset period.

Since the control signal DS at the timing T2 is the point S is turned off is disconnected from V _cc, while the power supply from the power supply is interrupted, the discharge begins in the capacitance element C _s1, transient current flows through the transistor Tr _5, A point potential but it decreases from V _cc. When the A point potential drops to V _{th with} respect to the G point potential, the transient current stops flowing. As a result , the potential difference between the point A and the point G becomes V _th , and this is held in the capacitive element C _s1 .

Off control signal AZ at timing T3, and off the transistor Tr ₅ and Tr _3, G point side of the capacitor C _s1 is with disconnected from V _ofs, A point side is disconnected from the S point. Detecting the V _th period from the timing T2 to T3, and so holds the C _s1, the period T2-T3, in particular, referred to as a detection period. This detection period T2-T3 has a sufficient time width so that the transient current flowing through the drive transistor becomes zero.

As described above , the threshold voltage V _th correction operation is performed by the reset operation in the reset period T1-T2 and the detection operation in the detection period T2-T3. Therefore, the period T1-T3 of the combined detection period and the reset period, referred to as V _th correction period. In some cases, the calling period T2-T3 and V _th correction period. As is apparent from the timing chart of FIG. 3, V _th correction period T1-T3 is defined by the control signal AZ. On the other hand, in the V _th correction period T1-T3, it is to divide the detection period T2-T3 and reset period T1-T2, a control signal DS. Control signal DS is a pulse which controls the basic on / off switching transistor Tr _4, therefore, it defines the light emission period and the non-emission period.

After V _th correction period T1-T3 has elapsed, the control signal WS is turned on at the timing T4, the sampling transistor Tr ₁ is turned on. As a result, the video signal V _sig supplied from the signal line SL is sampled by the capacitive element C _s2 . As a result , the potential at point A rises from V _th to the signal potential V _sig . In conjunction with this increase, it rises while also maintaining the difference V _th G point potential. As apparent from the timing chart, the potential difference between the A point potential and the G point potential is maintained at V _th even after sampling. Thereafter, the control signal WS at a time T5 where 1 horizontal period elapses is turned off, the sampling transistor Tr ₁ is turned off. Since the sampling operation of holding the V _sig to C _s2 by sampling carried out in the period T4-T5, it referred to as a sampling period. The sampling period T4-T5 is equal to one horizontal period 1H.

Thereafter, the control signal DS is turned on again at timing T6, the switching transistor Tr ₄ is turned on. As a result , the drive transistor Tr _d supplies the drain current I _ds to the light emitting element EL according to the difference V _gs between the S point potential and the G point potential. The light emitting element EL, thereby, emits light with a brightness corresponding to V _gs.

Thereafter , at the timing T7, the field ends, and the process proceeds to the next field. In the next field, the reset period is first entered.

Based on the timing chart of FIG. 3, the input voltage V _gs in the sampling period T4-T5 and the subsequent light emission period is obtained. Input voltage V _gs is the potential at the point G relative to the S point. Since the light emission period after the sampling period T4-T5 are transistor Tr ₄ is turned on, the potential point S is connected to the power source has a V _cc. On the other hand , the potential at point A is lower by V _sig than V _{cc as} described above. Furthermore , the G point potential is lower than the A point potential by V _th . Therefore , V _gs representing the G point potential with respect to the S point potential is V _cc − ( V _sig −V _th ). Substituting V _cc − ( V _sig −V _th ) obtained here into V _gs of the transistor characteristic equation 1 gives the following equation.
I _ds = (1/2) μ (W / L) C _ox ( V _cc −V _sig ) ²
In the above characteristic equation, the term of V _th included in the above basic characteristic equation 1 is canceled and replaced with V _cc −V _sig . Therefore , the pixel circuit 2 shown in FIG. 2 can supply the light emitting element EL with the output current I _ds corresponding to the value of V _sig without depending on V _th of the drive transistor Tr _d . Therefore , even if V _th of the drive transistor Tr _d varies from pixel to pixel, the pixel array can supply the output current from which the variation is removed to the light emitting element EL of each pixel.

FIG. 4 is a graph of the above characteristic equation. The vertical axis represents the output current I _ds , and the horizontal axis represents the input voltage V _cc −V _sig . At the same time, the above characteristic formula is shown again alongside the graph. As is apparent from the above characteristic equation, the V _th term of the drive transistor disappears. However , the mobility μ remains. This mobility μ is device-dependent, as is V _th, and varies from pixel to pixel. Therefore, the variation in the output current I _ds cannot be completely suppressed only by canceling V _th . In the graph, a transistor characteristic having a large μ is represented by a solid line, and a transistor characteristic having a small μ is represented by a dotted line. As is apparent from the graph, the characteristic curve becomes steeper as the coefficient μ of the characteristic equation increases. Therefore, the input voltage V _cc - be constant at V _sig = V0, since variation in the mobility mu occurs between the pixel output current I _ds is varied depending on the mu, the brightness variation between pixels It will occur. In particular , when V _cc −V _sig is from gray to white , the luminance variation depending on the mobility μ becomes prominent, resulting in display unevenness and a problem to be solved.

FIG. 5 is a circuit diagram showing a first embodiment of a display device according to the present invention. As shown in the figure, the active matrix display device includes a pixel array 1 as a main part and a peripheral circuit part. The peripheral circuit unit includes a horizontal selector 3, a write scanner 4, a drive scanner 5, a first correction scanner 71, a second correction scanner 72, and the like. Pixel array 1 is composed of the scanning lines WS in rows, and columns of the signal line SL, and the pixel circuits 2 arranged in a matrix form at the intersection of both. For ease of understanding in the figure, it is expanded display only one pixel circuit 2. The signal line SL is driven by the horizontal selector 3. The horizontal selector 3 forms a signal unit and supplies a video signal to the signal line SL. The scanning line WS is scanned by the write scanner 4. Incidentally, in parallel with the scanning lines WS, another scan line DS, AZ1 and AZ2 are also wired. The scanning line DS is scanned by the drive scanner 5. The scanning line AZ1 is scanned by the first correction scanner 71. The scanning line AZ2 is scanned by the second correction scanner 72. The write scanner 4, the drive scanner 5, the first correction scanner 71, and the second correction scanner 72 constitute a scanner unit, and sequentially scan the pixel rows every horizontal period. Each pixel circuit 2, when selected by the scanning line WS, samples the video signal from the signal line SL. Further, when selected by the scan line DS, driving the light emitting element EL included in the pixel circuit 2 in response to the sampled video signal. In addition, the pixel circuit 2, when scanned by the scanning lines AZ1, AZ2, performs predetermined correction operation.

The pixel circuit 2 includes five thin film transistors Tr ₁ to Tr ₄ and Tr _d , one capacitor element (pixel capacitor) C _s , and one light emitting element EL. Transistors Tr ₁ ~ Tr ₃ and Tr _d is an N-channel polysilicon TFT. Only the transistor Tr ₄ is a P-channel type polysilicon TFT. One capacitive element C _s constitutes a pixel capacitance of the pixel circuit 2. The light emitting element EL is , for example , a diode type organic EL element having an anode and a cathode. However , the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

Drive transistor Tr _d which is the center of the pixel circuit 2, a gate G is connected to one end of the pixel capacitor C _s, the source S is also connected to the other end of the pixel capacitor C _s. The gate G of the drive transistor Tr _d via a switching transistor Tr _2, and is connected to another reference potential V _ss1. The drain of the drive transistor Tr _d via the switching transistor Tr _4, are connected to a power supply V _cc. The gate of the switching transistor Tr ₂ is connected to the scan line AZ1. The gate of the switching transistor Tr ₄ is connected to the scanning line DS. The anode of the light emitting element EL is connected to the source S of the drive transistor Tr _d, the cathode is grounded. This ground potential may be expressed as V _cath . Further , the switching transistor Tr ₃ is interposed between the source S of the drive transistor Tr _d and a predetermined reference potential V _ss2 . The gate of the transistor Tr ₃ is connected to the scanning line AZ2. On the other hand , the sampling transistor Tr ₁ is connected between the signal line SL and the gate G of the drive transistor Tr _d . The gate of the sampling transistor Tr ₁ is connected to the scanning line WS.

In such a configuration, the sampling transistor Tr ₁ conducts according to the control signal WS supplied from the scanning line WS during a predetermined sampling period, and samples the video signal V _sig supplied from the signal line SL into the pixel capacitor C _s . . The pixel capacitor C _s applies an input voltage V _gs between the gate G and the source S of the drive transistor in accordance with the sampled video signal V _sig . Drive transistor Tr _d during a predetermined light emission period, it supplies an output current I _ds according to the input voltage V _gs to the light emitting element EL. Note that the output current (drain current) I _ds has a dependency on the carrier mobility μ and the threshold voltage V _th of the channel region of the drive transistor Tr _d. The light emitting element EL emits light with luminance according to the video signal V _sig by the output current I _ds supplied from the drive transistor Tr _d .

As a feature of the present invention, the pixel circuit 2 includes correction means including switching transistors Tr ₂ to Tr ₄ , and in order to cancel the dependency of the output current I _{ds on} the carrier mobility μ, the light emission period is previously set. The input voltage V _gs held in the pixel capacitor C _s at the beginning is corrected. Specifically, the correcting means ( Tr ₂ to Tr ₄ ) operate in a part of the sampling period according to the control signals WS and DS supplied from the scanning lines WS and DS, and the video signal V _sig is sampled. In this state, the output current I _ds is taken out from the drive transistor Tr _d and negatively fed back to the pixel capacitor C _s to correct the input voltage V _gs . Further, this correction means (Tr ₂ ~ Tr _4), in order to cancel the dependence on the threshold voltage V _th of the output current I _ds, detects the threshold voltage V _th of the drive transistor Tr _d prior to advance the sampling period In addition, the detected threshold voltage V _th is added to the input voltage V _gs .

In this embodiment, the drive transistor Tr _d, while the drain of N-channel transistor is connected to the power supply V _cc side, the source S is connected to the light emitting element EL side. In this case, the correction means described above takes out the output current I _ds from the drive transistor Tr _d at the beginning of the light emission period that overlaps the latter part of the sampling period, and negatively feeds back to the pixel capacitor C _s side. At this time , the correcting means causes the output current I _ds extracted from the source S side of the drive transistor Tr _d at the beginning of the light emission period to flow into the capacitance of the light emitting element EL. Specifically, the light emitting element EL, a diode-type light-emitting device having an anode and a cathode, while the anode side is connected to the source S of the drive transistor Tr _d, cathode side is grounded. With this configuration, the correcting means ( Tr ₂ to Tr ₄ ) sets the anode / cathode of the light emitting element EL in a reverse bias state in advance, and outputs the output current I _ds extracted from the source S side of the drive transistor Tr _d. When the LED flows into the light emitting element EL, the diode type light emitting element EL is caused to function as a capacitive element. Incidentally, the correcting means can adjust the time width t extracting an output current I _ds of the drive transistor Tr _d within the sampling period, thereby to optimize the negative feedback amount of the output current I _ds to the pixel capacitor C _s ing.

FIG. 6 is a schematic view of a pixel circuit portion extracted from the display device shown in FIG. For ease of understanding, and the video signal V _sig that is sampled by the sampling transistor Tr _1, the drive transistor Tr _d input voltage V _gs and the output current I _ds of the further, such a capacitance component C _oled of the light emitting element EL has Is added. Hereinafter , the basic operation of the pixel circuit 2 will be described with reference to FIG.

FIG. 7 is a timing chart of the pixel circuit shown in FIG. Referring to FIG 7, the operation of the pixel circuit shown in FIG. 6, and more specifically, and will be described in detail. 7, along the time axis T, are a waveform of the control signals applied to the scanning lines WS, AZ1, AZ2 and DS. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. Since the transistors Tr ₁ , Tr ₂ , and Tr ₃ are N-channel type, they are turned on when the scanning lines WS, AZ 1, and AZ 2 are at a high level and turned off when they are at a low level. On the other hand , since the transistor Tr ₄ is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. Note that this timing chart, with the control signals WS, AZ1, AZ2, DS waveform is represented the potential change of the drive transistor Tr _d potential change and the source S of the gate G of the.

In the timing chart of FIG. 7 , timings T1 to T8 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. The timing chart shows the waveforms of the control signals WS, AZ1, AZ2, DS applied to the pixels for one row.

At timing T0 before the field starts, all control line numbers WS, AZ1, AZ2, DS are at a low level. Accordingly, the N-channel transistors Tr ₁ , Tr ₂ , Tr ₃ are in the off state, while only the P-channel transistor Tr ₄ is in the on state. Therefore, the drive transistor Tr _d is because it is connected to the power source V _cc through transistor Tr ₄ in the ON state and supplies the output current I _ds to the light emitting element EL in accordance with the predetermined input voltage V _gs. Therefore, the light emitting element EL emits light at the timing T0. At this time , the input voltage V _gs applied to the drive transistor Tr _d is represented by the difference between the gate potential (G) and the source potential (S).

At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. Thus, the transistor Tr ₄ is turned off and the drive transistor Tr _d is disconnected from the power supply V _cc, light emission is stopped into the non-emission period. Therefore, upon entering the timing T1, preparative transistors Tr ₁ ~ Tr ₄ are turned off.

Subsequently , at timing T2, since the control signals AZ1 and AZ2 are at a high level, the switching transistors Tr ₂ and Tr ₃ are turned on. As a result, the gate G of the drive transistor Tr _d is connected to the reference potential V _ss1 , and the source S is connected to the reference potential V _ss2 . Here, V _ss1 - V _ss2> meets the V _th, V _ss1 - the V _ss2 = V _gs> V _th to it, to prepare for the place is V _th correction in the subsequent timing T3. In other words, the period T2 - T3 corresponds to a reset period of the drive transistor Tr _d. When the threshold voltage of the light emitting element EL is V _thEL , V _thEL > V _ss2 is set. Thereby, a minus bias is applied to the light emitting element EL, and a so-called reverse bias state is obtained. This reverse bias state is necessary for normal V _th correction operation and mobility correction operation to be performed later.

Timing was T3, the control signal AZ2 at low level, and, and the control signal DS is also low immediately. Thereby , the transistor Tr ₃ is turned off, while the transistor Tr ₄ is turned on. As a result , the drain current I _ds flows into the pixel capacitor C _s and the V _th correction operation is started. At this time, the gate G of the drive transistor Tr _d is held in V _ss1, flows current I _ds to the drive transistor Tr _d is cut off. When cut off , the source potential (S) of the drive transistor Tr _d becomes V _ss1 −V _th . Drain current returned to the high level again a control signal DS at the timing T4 after the cut-off and turns off the switching transistor Tr _4. Furthermore, the control signal AZ1 is also returned to the low level, the switching transistor Tr ₂ is also turned off. As a result, V _th is held and fixed in the pixel capacitor C _s . Thus, the timing T3 - T4 is a period for detecting the threshold voltage V _th of the drive transistor Tr _d. Here, this detection period T3 - are the T4, it is referred to as V _th correction period.

Thus, after the V _th correction switches the control signal WS to the high level at a timing T5, writing the video signal V _sig in the pixel capacitor C _s to turn on the sampling transistor Tr _1. Compared to the equivalent capacitance C _oled of the light-emitting device EL, pixel capacitor C _s is sufficiently small. As a result, most of the video signal V _sig is written in the pixel capacitor C _s. To be precise, the difference V _sig of V _sig against the V _ss1 - V _ss1 is written to the pixel capacitor C _s. Accordingly, the voltage V _gs between the gate G and the source S of the drive transistor Tr _d is a level _obtained by adding V _th previously detected and held to V _sig −V _ss1 sampled this time , ( V _sig −V _ss1 + V _th ). Since, for purposes of explanation simplicity, when V _ss1 = 0 volts, the gate / source voltage V _gs is as shown in the timing chart of FIG. 7, a V _sig + V _th. Sampling of such video signal V _sig, the control signal WS is performed until time T7 back to low level. That is, the timing T5 - T7 corresponds to the sampling period.

At timing T6 prior to timing T7 to the end of the sampling period, the control signal DS goes low, the switching transistor Tr ₄ are turned on. Thus, the drive transistor Tr _d is connected to the power supply V _cc, the pixel circuit goes to the light emission period from the non-emission period. Thus, the sampling transistor Tr ₁ is still turned on, and the period T6 in which the switching transistor Tr ₄ enters the on state - at T7, perform mobility correction of the drive transistor Tr _d. That is , in the present embodiment, the mobility correction is performed in the period T6 - T7 in which the rear part of the sampling period overlaps with the head part of the light emission period. In the beginning of the emission period of the mobility correction is performed, the light emitting element EL, because in fact is in a reverse bias state, are not able to emit light. The mobility correction period T6 - At T7, in a state in which the gate G of the drive transistor Tr _d is fixed at the level of the video signal V _sig, the drain current I _ds flows to the drive transistor Tr _d. Here, V _ss1 - V _th <By setting the V _thEL, the light emitting element EL to be placed in a reverse bias state, exhibits a simple capacitance characteristics, rather than diode characteristics. Therefore , the current I _ds flowing through the drive transistor Tr _d is written into a capacitance C = C _s + C _oled that combines both the pixel capacitance C _s and the equivalent capacitance C _oled of the light emitting element EL. Thus, the source potential of the drive transistor Tr _d (S) is rises. In the timing chart of FIG. 7 , this increase is represented by ΔV. The rise ΔV eventually, it means that subtracted from the voltage V _gs between the gate / source held in the pixel capacitor C _s, it will be multiplied by the negative feedback. Thus, by negatively feeding back the output current I _ds of the drive transistor Tr _d also to the input voltage V _gs of the drive transistor Tr _d, it is possible to correct the mobility mu. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T6 - T7.

At timing T7, the control signal WS becomes low level, and the sampling transistor Tr ₁ is turned off. As a result, the gate G of the drive transistor Tr _d is disconnected from the signal line SL. Since the application of the video signal V _sig is cancelled, the gate potential (G) of the drive transistor Tr _d can be increased and increases with the source potential (S). Meanwhile, the pixel capacitance C _s gate / source voltage V _gs held in maintains the value of _{(V sig -ΔV + V th)} . With increasing the source potential (S), the reverse bias state of the light emitting element EL is because it is eliminated, the inflow of the output current I _ds, the light emitting device EL actually starts emitting light. The relationship between the drain current I _{ds and the} gate / source voltage V _gs at this time is given by the following equation 2 by substituting V _sig −ΔV + V _th into V _gs of the previous transistor characteristic equation 1. .
I _ds = kμ ( V _gs −V _th ) ² = kμ ( V _sig −ΔV) ² Equation 2
In the above formula 2, k = (1/2) (W / L) C _ox . It can be seen from the characteristic formula 2 that the term V _th is canceled and the output current I _ds supplied to the light emitting element EL does not depend on the threshold voltage V _th of the drive transistor Tr _d . Basically, the drain current I _ds is determined by the signal voltage V _sig of the video signal. In other words, the light emitting element EL will emits light at a luminance corresponding to the video signal V _sig. At that time , the negative feedback amount ΔV is subtracted from V _sig . The negative feedback amount ΔV acts to cancel the effect of the mobility μ is located in the coefficient of characteristics equation 2. Accordingly , the drain current I _ds substantially depends only on the video signal V _sig .

Finally, the control signal DS reaches the timing T8 is at a high level, the switching transistor Tr ₄ is turned off, the light emission is finished, the field is completed. Thereafter, proceeds to the next field, again, V _th correction operation, mobility correction operation and light emitting operation will be repeated.

8, the mobility correction period T6 - is a circuit diagram showing a state of the pixel circuit 2 in the T7. As illustrated, the mobility correction period T6 - At T7, while the sampling transistor Tr ₁ and the switching transistor Tr ₄ is on, the remaining switching transistors Tr ₂ and Tr ₃ are turned off. In this state, the source potential (S) of the drive transistor Tr ₄ is V _ss1 −V _th . This source potential S is also the anode potential of the light emitting element EL. As described above, V _ss1 - V _th <By setting the V _thEL, the light emitting element EL is placed in a reverse bias state, and to exhibit a simple capacitance characteristics, rather than diode characteristics. Therefore , the current I _ds flowing through the drive transistor Tr _d flows into the combined capacitance C = C _s + C _oled of the pixel capacitance C _s and the equivalent capacitance C _oled of the light emitting element EL. In other words, a part of the drain current I _ds is negatively fed back to the pixel capacitor C _s and the mobility is corrected.

FIG. 9 is a graph of the transistor characteristic equation 2 described above, with I _ds on the vertical axis and V _sig on the horizontal axis. The characteristic formula 2 is also shown below the graph. In the graph of FIG. 9, a characteristic curve is drawn in a state where the pixel 1 and the pixel 2 are compared. The mobility μ of the drive transistor of the pixel 1 is relatively large. Conversely, the mobility μ of the drive transistor included in the pixel 2 is relatively small. Thus, when the drive transistor is formed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels. For example , when the video signal V _sig of the same level is written to both the pixels 1 and 2, the output current I _ds1 ′ flowing through the pixel 1 having the high mobility μ is equal to that of the mobility μ without any mobility correction. A large difference occurs compared to the output current I _ds2 ′ flowing through the small pixel 2. Thus, since a large difference between the output current I _ds due to variation in the mobility μ occurs, so that the impairing the uniformity of the screen.

Therefore , in the present invention, the variation in mobility is canceled by negatively feeding back the output current to the input voltage side. As is clear from the transistor characteristic equation, the drain current I _ds increases as the mobility increases. Therefore, the negative feedback amount ΔV increases as the mobility increases. As shown in the graph of FIG. 9, the negative feedback amount ΔV1 of large pixel 1 of the mobility μ is greater than the negative feedback amount ΔV2 of small pixels 2 mobility. Accordingly , the larger the mobility μ is, the more negative feedback is applied, and the variation can be suppressed. As shown, when applying a correction of the mobility in large pixel 1 mu [Delta] V1, the output current is large drops from I _ds1 'to I _ds1. On the other hand , since the negative feedback amount ΔV2 of the pixel 2 having a small mobility μ is small, the output current I _ds2 ′ does not decrease so much to I _ds2 . Consequently, I _ds1 and I _ds2 become substantially equal, variations in mobility is canceled. Since the cancellation of the variation in mobility is performed in the entire range of V _sig from the black level to the white level , the uniformity of the screen becomes extremely high. In summary, when there mobilities of different pixels 1 and 2, the negative feedback amount ΔV1 of the larger mobility pixel 1 is greater with respect to the negative feedback amount ΔV2 of small pixels 2 mobility. That is , as the mobility increases , ΔV increases and the decrease value of I _ds increases. As a result , the current values of the pixels having different mobilities are made uniform, and variations in mobility can be corrected.

Hereinafter, for reference, with reference to FIG. 10, performs numerical analysis of the mobility correction described above. As shown in FIG. 10, in a state where the transistor Tr ₁ and Tr ₄ are turned on, and analyzes by taking the source potential of the drive transistor Tr _d to the variable V. When the source potential of the drive transistor Tr _d the (S) to is V, the drain current I _ds flowing through drive transistors Tr _d, are as shown in Equation 3 below.

Further , due to the relationship between the drain current I _ds and the capacitance C (= C _s + C _oled ) , I _ds = dQ / dt = CdV / dt is established as shown in Equation 4 below.

By substituting equation 3 into equation 4, integrating both sides. Here, the initial state of the source potential V is - and V _th, the mobility correction time - the (T6 T7) and t. Solving this differential equation, the pixel current for the mobility correction time t is given by the following Equation 5.

FIG. 11 shows a graph of current values at t = 0 us and 2.5 us for pixels with different mobilities, using Equation 5. In addition, Equation 5 is also placed at the bottom of this graph. Compared to the state not to apply mobility correction of t = 0us, it is understood that the correction is afflicted with enough for variations in the mobility at t = 2.5 us. When there is no mobility correction, there is 40% variation, but when mobility correction is applied, it is suppressed to 10% or less. In the mobility correction operation, it is necessary to always satisfy V < V _thEL . In the pixel circuit of the first embodiment described above, using equivalent capacitance C _oled of the light emitting element EL and the pixel capacitance C _s during the mobility correction. Since C _oled is larger than C _s , the combined capacity C is also increased, and a mobility correction time margin can be obtained.

By performing the above operation, it can be seen that mobility correction can be performed even in a signal potential sampling pixel circuit. The driving method of a liquid crystal display that has already been put into practical use is basically voltage driving for sampling a signal potential . Therefore , since the mobility can be corrected by voltage driving even in the organic EL panel, an external source driver used in a conventional liquid crystal display, a panel built-in source driver using a low-temperature polysilicon TFT, or the like is used. This makes it possible to produce an organic EL panel module at a low cost. Further, in the pixel circuit of the first embodiment the switching transistor other than the drive transistor is used to mix N-channel and P-channel type, the characteristics of each transistor may be a P-channel in the N channel.

FIG. 12 is a block diagram showing a second embodiment of the display device according to the present invention. For ease of understanding , corresponding reference numerals are used for portions corresponding to those in the first embodiment shown in FIG. The display device includes a pixel array 1 and peripheral circuits surrounding it. The peripheral circuit includes a horizontal selector 3, a write scanner 4, a drive scanner 5, a first correction scanner 71, and a second correction scanner 72. The pixel array 1 is composed of pixel circuits 2 arranged in a matrix. In the figure, only one pixel circuit 2 is shown for easy understanding. The pixel circuit 2 includes six transistors Tr _1, Tr _d, and Tr ₃ ~ Tr _6, and two capacitive elements C _s1, C _s2, is composed of a single light emitting element EL. All transistors are N-channel type. Drive transistor Tr _d which is the main part of the pixel circuit 2 has its gate G connected to one end of the capacitors C _s1, C _s2. One capacitive element C _s1 is a coupling capacitor that connects the output side and the input side of the pixel circuit 2. Other capacitor element C _s2 is the pixel capacitance of the video signal is written through the coupling capacitor C _s1. With the source S of the drive transistor Tr _d is connected to the other end of the pixel capacitor C _s2, it is connected to the light emitting element EL. The light emitting element EL is a diode-type device, while its anode is connected to the source S of the drive transistor Tr _d, cathode de is connected to the ground potential V _cath. Further , the switching transistor Tr ₃ is interposed between the source S of the drive transistor Tr _d and a predetermined reference potential V _ss2 . The gate of the transistor Tr ₃ is connected to the scanning line AZ2. The drain of the drive transistor Tr _d via the switching transistor Tr _4, are connected to a power supply V _cc. The gate of the switching transistor Tr ₄ is connected to the scanning line DS. In addition , a switching transistor Tr ₅ is interposed between the gate G and the drain of the drive transistor Tr _d . The gate of the transistor Tr ₅ is connected to the scanning line AZ1. On the other hand , the sampling transistor Tr ₁ on the input side is connected between the signal line SL and the other end of the coupling capacitor C _s1 . The gate of the sampling transistor Tr ₁ is connected to the scanning line WS. Between the other end of the coupling capacitance C _s1 and the predetermined reference potential V _ss1, the transistor Tr ₆ is interposed. The gate of the transistor Tr ₆ are connected to the scanning line AZ1.

FIG. 13 is a timing chart for explaining the operation of the pixel circuit shown in FIG. Control signal WS along the time axis T, DS, AZ1, with represents the AZ2 waveform, is represented also change in the gate potential (G) and the source potential of the drive transistor Tr _d (S). At timing T1 when the field starts, the control signals WS, AZ1, and AZ2 are at a low level, and only the control signal DS is at a high level. Therefore, only the switching transistor Tr ₄ at the timing T1 is in the ON state, the remaining transistors _{Tr 1, Tr 3, Tr 5} , Tr 6 are off. At this time, since the drive transistor Tr _d is connected to the power supply V _cc through a switching transistor Tr ₄ in the on state, the predetermined drain current I _ds flows into the light-emitting device EL, and has a light emission state.

At timing T2 , the control signals AZ1 and AZ2 become high level, and the switching transistors Tr ₅ and Tr ₆ are turned on. Since the gate G of the drive transistor Tr _d is connected through the transistor Tr ₅ to the power supply V _cc side, the gate potential (G) increases sharply.

Thereafter, the control signal DS goes low at the timing T3, the transistor Tr ₄ is turned off. Since power supply to the drive transistor Tr _d is cut off, the drain current I _ds attenuates. Thus, the source potential (S) and the gate potential (G) is lowered together, but where the potential difference between the both who becomes V _th, current does not flow. At this time, V _th is held in the pixel capacitor C _s2 . V _th held in the pixel capacitance C _s2 is used to cancel the threshold voltage of the drive transistor Tr _d. Further, the switching transistor Tr ₃ is on, and the source S of the drive transistor Tr ₂ is connected to the reference potential V _ss2 via the transistor Tr ₃ . This V _ss2 is set lower than the threshold voltage of the light emitting element EL, and the light emitting element EL is placed in a reverse bias state.

Thereafter , at timing T4 , the control signal AZ1 becomes low level, the transistors Tr ₅ and Tr ₆ are turned off, and V _th written in C _s2 is fixed. A period from timing T2 to T4 is referred to as a _Vth correction period (T2 - T4). Since the Tr ₆ is turned on at V _th correction period, the other end of the coupling capacitance C _s1 is held to a predetermined reference potential V _ss1.

When it is time T5, the control signals WS and AZ2 goes high, the sampling transistor Tr ₁ is turned on. As a result, the gate G of the drive transistor Tr _d, via the sampling transistor Tr ₁ which coupling capacitance C _s1 and turned on, it is connected to the signal line SL. As a result , the video signal is coupled to the gate G of the drive transistor Tr _d via the coupling capacitor C _s1 , and the potential increases. In the timing chart of FIG. 13, a voltage obtained by combining the coupling component and V _th of the video signal, is represented by V _in. This V _in is held _{in the} pixel capacitor C _s2 . Thereafter, the flow returns to control signal WS goes low at the timing T7, potential written in the pixel capacitor C _s2 is held fixed. In this way, the period during which the video signal is written into the pixel capacitance C _s2 via the coupling capacitor C _s1, the sampling period T5 - referred to as T7. The sampling period T5 - T7 usually corresponds to one horizontal period (1H).

In the present embodiment, at timing T6 before timing T7 when the sampling period ends, the control signal DS becomes high level, while the control signal AZ2 becomes low level. As a result , the source S of the drive transistor Tr _d is _disconnected from V _ss2, while a current flows from the drain side to the source S side. On the other hand , since the sampling transistor Tr ₁ is still on, the gate potential (G) of the drive transistor Tr _d is held on the video signal side. Since the output current to drive transistor Tr _d in such a state flows, it becomes possible to charge the equivalent capacitance of the light emitting device EL in the pixel capacitance C _s2 and the reverse bias state. Thus, the source potential of the drive transistor Tr _d (S) is increased by [Delta] V, that much voltage V _in held in the C _s2 is decreased. In other words, the output current on the source S side is negatively fed back to the input voltage on the gate G side during the period T6 - T7. This negative feedback amount is represented by ΔV. The negative feedback operation, mobility correction of the drive transistor Tr _d is performed.

Thereafter , when the control signal WS becomes low level at the timing T7 and the application of the video signal is released, a so-called bootstrap operation is performed, and the gate potential (G) and the source potential (S) are different from each other ( V _in- ΔV) and rise. As the source potential (S) rises, the reverse bias state of the light-emitting element EL is canceled, so that the output current I _ds flows into the light-emitting element EL, and light emission is performed with luminance according to the video signal. Thereafter , when the field 1f ends at the timing T8, the process proceeds to the next field. In the next field, V _th correction, signal writing, and mobility correction are performed.

14, the mobility correction period T6 shown in FIG 13 - shows the state of the pixel circuit 2 in the T7. The pixel circuit 2 is also provided with a switching transistor Tr _3, Tr _4, Tr ₅ correcting means constituted like. The correcting means for canceling the dependence on the carrier mobility μ of the output current I _ds, previously emission period T6 - T8 before or the top pixel capacitance C _s2 input voltage V _in that is held in the (V _gs) the correction To do. The correction means, the control signal WS supplied from the scanning line WS and DS, the sampling period T5 according to the DS - operate with some T7, from the drive transistor Tr _d in a state where the video signal V _sig is sampled The output current I _ds is taken out and negatively fed back to the pixel capacitor C _s2 to correct the input voltage V _gs . In addition, the correction means _{(Tr 3, Tr 4, Tr} 5) , in order to cancel the dependence on the threshold voltage V _th of the output current I _ds, advance the sampling period T5 - drive transistor T4 - period T2 prior to T7 The threshold voltage V _th of Tr _d is detected, and the detected threshold voltage V _th is added to the input voltage V _gs .

In this embodiment, the drive transistor Tr _d, while the drain of N-channel transistor is connected to the power supply V _cc side, the source S is connected to the light emitting element EL side. In this configuration, the correction unit takes out the output current I _ds from the drive transistor Tr _{d in} the head part (T6 - T7) of the light emission period T6 - T8 that overlaps the rear part of the sampling period T5 - T7, and the pixel capacitance C _s2 Negative feedback to the side. At that time, the correcting means, the leading portion of the light-emitting period (T6 - T7) output current I _ds extracted from the source S of the drive transistor Tr _d in that, so as to flow into the equivalent capacitance C _oled included in the light emitting element EL Yes. The light emitting element EL, a diode-type light-emitting device having an anode and a cathode, while the anode is connected to the source S of the drive transistor Tr _d, cathode side is grounded to V _cath. As described above , the correction means sets the anode / cathode of the light emitting element EL in a reverse bias state in advance, and the output current I _ds extracted from the source S side of the drive transistor Tr _d flows into the light emitting element EL. At this time, the diode-type light-emitting element EL functions as the capacitive element C _oled .

FIG. 15 is a block diagram showing a third embodiment of the display device according to the present invention. For ease of understanding, the parts corresponding to the first embodiment shown in FIG. 5 are denoted by the corresponding reference number. This display device is also composed of a central pixel array 1 and peripheral circuits surrounding it. The peripheral circuit includes a horizontal selector 3, a write scanner 4, a drive scanner 5, a first correction scanner 71, and a second correction scanner 72. The pixel array 1 is composed of pixel circuits arranged in a matrix. In the figure, for ease of understanding, an enlarged view of only one pixel circuit 2.

The pixel circuit 2, and five transistors _{Tr 1, Tr 2, Tr 4} , Tr 5, Tr d, and two capacitive elements C _s1, C _s2, is composed of a single light emitting element EL. Unlike the first embodiment and the second embodiment, the drive transistor Tr _d is P-channel type. Remaining transistors _{Tr 1, Tr 2, Tr 4} , Tr 5 are all N-channel type. Incidentally, depending on the characteristics of the pixel size and the light emitting element EL, generally, the drive transistor can be found the following N-channel type have a large capacity of the mobility correction value, there is a margin for the mobility correction.

The source of the drive transistor Tr _d is connected to the power supply V _cc. The gate is connected to one end of the pixel capacitor C _s1 . When the drive transistor Tr _d is a P-channel type, the gate / source voltage V _gs is defined with reference to the power supply V _cc on the source side. The drain of the drive transistor Tr _d via the switching transistor Tr _4, is connected to the light emitting element EL. The light emitting element EL, a diode type, while the anode is connected to the drain of the drive transistor Tr _d via the switching transistor Tr _4, the cathode is grounded. Note that the gate of the switching transistor Tr ₄ is connected to the scanning line DS. Between the gate and drain of the drive transistor Tr _d, switching transistor Tr ₅ is interposed. Its gate is connected to the scanning line AZ1.

On the other hand , the sampling transistor Tr ₁ on the input side of the pixel circuit 2 is connected between the signal line SL and the other end of the pixel capacitor C _s1 . The gate of the sampling transistor Tr ₁ is connected to the scanning line WS. Between the other end and the power supply V _cc of the pixel capacitor C _s1, another pixel capacitance C _s2 is connected. Further, between the other end and a predetermined offset potential V _ofs of the pixel capacitor C _s1, the switching transistor Tr ₂ are connected. The gate of the transistor Tr ₂ is connected to the scan line AZ2.

FIG. 16 is a circuit diagram clearly showing the relationship between the transistors of the pixel circuit shown in FIG. 15 and the control signals corresponding thereto. Together, clearly the gate of the drive transistor Tr _d by the symbol G, are clearly the anode of the light emitting element EL by the symbol X. Control signals applied to the gates of the transistors Tr ₁ , Tr ₂ , Tr ₄ and Tr ₅ are represented by the same symbols as the corresponding scanning lines.

FIG. 17 is a timing chart for explaining the operation of the pixel circuit shown in FIG. Together represent the waveform of the control signals WS, AZ1, AZ2, DS along the time axis T, is represented also change in the anode potential of the gate potential (G) and the light emitting element EL of the drive transistor Tr _d (X).

At timing T0 before entering the field, the control signals WS, AZ1 and AZ2 are at a low level, while the control signal DS is at a high level. Thus, while the transistor Tr ₄ at the timing T0 is in the ON state, the remaining transistors Tr _1, Tr _2, Tr ₅ is off. Drive transistor Tr _d is connected to the light emitting element EL via the transistor Tr ₄ in the ON state. Therefore, an output current corresponding to the gate / source voltage V _gs flows through the light emitting element EL to emit light. In the timing chart of FIG. 17, the gate / source voltage V _gs is represented by the difference between the power supply potential V _cc and the gate potential (G).

At the timing T1 when entering the field, the control signals AZ1 and AZ2 become high level, and the transistors Tr ₂ and Tr ₅ are turned on. Thereby , the other end of the pixel capacitor C _s1 is fixed at a predetermined offset potential V _ofs . In addition, a drain and a gate of the drive transistor Tr _d is directly connected. For this reason, the gate potential (G) is rapidly lowered by being pulled by the drain potential, while the anode potential (X) is rapidly raised by a voltage drop generated in the light emitting element EL. The drive transistor Tr _d In this operation becomes ready for threshold voltage detection.

Subsequently, the control signal DS goes low at timing T2, the switching transistor Tr ₄ is turned off. Period far T1 - T2 is called the reset period or overlap period. When the switching transistor Tr ₄ is turned off , the current path of the drive transistor is cut off, and the gate capacitance C _gs and the pixel capacitance C _s1 are charged. As a result , the gate potential (G) rises . Where the difference between the power supply potential V _cc and the gate potential (G) becomes V _th, the drive transistor Tr _d is cut off. At timing T3 after the cutoff , the control signals AZ1 and AZ2 return to the low level, and the transistors Tr ₂ and Tr ₅ are turned off. As a result , the threshold voltage V _th written in the pixel capacitor C _s1 is held. This period T2 - the T3, referred to as V _th correction period or V _th detection period. In addition, since the energization to the light emitting element EL is cut off, the anode potential (X) is lowered to the ground potential GND.

Thereafter, the process proceeds to the timing T4, the control signal WS is the sampling transistor Tr ₁ becomes a high level to turn on. As a result , the video signal V _sig is sampled and V _ofs − V _sig is written in the pixel capacitor C _s2 . This voltage V _ofs - V _sig is coupled to the gate G of the drive transistor Tr _d through the pixel capacitance C _s1. The amount is given by C _s1 ( V _ofs −V _sig ) / ( C _s1 + C _gs ). C _gs is the source / gate capacitance of the drive transistor. The coupling voltage of only the further, the gate potential (G) is lowered, eventually, the gate / source voltage V _{gs is, V th + C s1 (V} ofs - V sig) / (C s1 + C gs) It becomes. Thereafter, in one horizontal period (1H) after the elapse of the timing T7, the control signal WS returns to the low level, the sampling transistor Tr ₁ is turned off. Period T4 corresponding to the 1H - at T7, the sampling of the video signal V _sig is executed.

The sampling period T4 - period T5 of some T7 - at T6, the control signal AZ1 goes high, transistor Tr ₅ becomes conductive. As a result, through the drain-side from the power supply V _cc side (source side of the drive transistor Tr _d), the drain current flows into the gate G side. As the drain current flows , the gate potential (G) increases by ΔV. ΔV is proportional to the mobility of the drive transistor. As the mobility of the drive transistor increases, ΔV increases and the gate potential (G) rises. Therefore, the gate-source voltage V _gs is compressed by that amount, and the output current is suppressed. Thus, by applying a negative feedback toward the drain side of the drive transistor Tr _d to the gate side, it is possible to suppress variations in mobility. A period T5 - T6 set in the sampling period T4 - T7 is called a mobility correction period. By performing the mobility correction, the gate / source voltage V _gs of the drive transistor Tr _d, eventually, V _th + C _s1 - given by _{(V ofs V sig) / (} C s1 + C gs) -ΔV . This is the gate / source voltage V _gs, in addition to the signal components of the net, the component V _th to cancel the threshold voltage of the drive transistor includes a component ΔV for correcting the mobility.

When it is time T8, the control signal DS is switching transistor Tr ₄ becomes high level to turn on. As a result , the drive transistor Tr _d is directly connected to the light emitting element EL, and an output current in which variations in the threshold voltage V _th and the mobility μ are corrected flows to the light emitting element EL. Thereafter, when the field is completed at the timing T9, move to the next field, again, V _th correction, video signal sampling, each operation of the mobility correction is performed.

18, the mobility correction period T5 - a circuit diagram showing a state of the pixel circuit in T6. As described above, the mobility correction period T5 - At T6, the sampling transistor Tr ₁ and the switching transistor Tr ₅ is because it is turned on, the drain current I _ds is written to the pixel capacitor C _s1. As a result , the gate potential (G) of the drive transistor Tr _d increases by ΔV. The drain current I _ds flowing at this time is expressed by the following Equation 6. In Equation 6, the coupling coefficient C _s1 / ( C _s1 + C _gs ) is omitted as 1. In fact, C _s1 is considerably larger than that of the C _gs.

As described above , ΔV = I _ds · t / C _s1 indicates that ΔV is different for pixels having different mobilities. As the mobility increases, ΔV increases and the correction amount of I _ds also increases. With these operations, I _ds can be made uniform and mobility correction can be performed even in pixels with variations in mobility .

Detailed calculation formula, by the same manner as in Embodiment 1 above analysis, given as shown in Equation 7 below.

The right side of Equation 7 includes two mobility μ. Since μ in the coefficient part and μ located in the denominator of the left side cancel each other, as a result, the influence of mobility μ can be removed from the drain current I _ds . The effect of μ in the denominator of Equation 7 can be adjusted by the time width t of the mobility correction period T5 - T6. Thereby , the mobility correction of the present invention can be optimized.

1 ... pixel array, 2 ... pixel circuit, 3 ... horizontal selector, 4 ... write scanner, 5 ... drive scanner, 7 ... correction scanner, Tr ₁ ... sampling transistor Tr _d: Drive transistor, EL: Light emitting element, C _s: Capacitor element

Claims (4)

A drive unit and a pixel array unit;
The drive unit includes a scanner unit and a signal unit,
The pixel array unit includes a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixel circuits arranged in a matrix,
Each of the plurality of scanning lines and the plurality of signal lines is connected to the driving unit,
Each of the plurality of pixel circuits includes at least a sampling transistor, a drive transistor, a pixel capacitor, a light emitting element, and a correction unit .
In the sampling transistor, the gate is connected to the scanning line, the source is connected to the signal line, the drain is connected to the gate of the drive transistor,
In the drive transistor, the source is connected to one end of the light emitting element,
The pixel capacitance is arranged between the gate and source of the drive transistor ,
The correction means includes at least a switching transistor interposed in a current path including the drive transistor and configured to operate in accordance with a control signal from a scanning line different from the scanning line for the sampling transistor, and the scanning unit receives the scanning line from the driving unit. In response to a control signal supplied via the signal line, the output potential of the drive transistor is negatively fed back to the pixel capacitor while the signal potential is supplied from the signal line to the gate of the drive transistor .
While the signal potential is supplied from the signal line to the gate of the drive transistor, current flows through the drive transistor whose drain is connected to the power supply by the control of the correction unit according to the control signal from the drive unit , The source potential of the drive transistor is configured to be close to the signal potential .
Display device. 2. A time width of a period in which a current flows through a drive transistor having a drain connected to a power supply while a signal potential is supplied from the signal line to the gate of the drive transistor can be adjusted by control of a correction unit. The display device described in 1. A drive unit and a pixel array unit;
The drive unit includes a scanner unit and a signal unit,
The pixel array unit includes a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixel circuits arranged in a matrix,
Each of the plurality of scanning lines and the plurality of signal lines is connected to the driving unit,
Each of the plurality of pixel circuits includes at least a sampling transistor, a drive transistor, a pixel capacitor, a light emitting element, and a correction unit .
In the sampling transistor, the gate is connected to the scanning line, the source is connected to the signal line, the drain is connected to the gate of the drive transistor,
In the drive transistor, the source is connected to one end of the light emitting element,
The pixel capacitance is arranged between the gate and source of the drive transistor ,
The correction means includes at least a switching transistor interposed in a current path including the drive transistor and configured to operate in accordance with a control signal from a scanning line different from the scanning line for the sampling transistor, and the scanning unit receives the scanning line from the driving unit. through in response to a control signal supplied, the signal potential from the signal line is configured to perform control to negative feedback the output current of the drive transistor in the pixel capacitor while being supplied to the gate of the drive transistor,
A driving method of a display device,
While supplying the signal potential from the signal line to the gate of the drive transistor, a current flows through the drive transistor whose drain is connected to the power supply by the control of the correction unit according to the control signal from the drive unit , A step of bringing the potential of the source of the drive transistor close to the signal potential ;
A driving method of a display device. 4. A time width during which a current flows through a drive transistor having a drain connected to a power supply while a signal potential is supplied from the signal line to the gate of the drive transistor can be adjusted by control of a correction unit. A driving method of the display device according to the above.

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