JP5061530B2 - Display device - Google Patents

Description

The present invention relates to a display device that displays an image by integrating pixel circuits for current-driving light emitting elements arranged for each pixel in a matrix. Specifically, the present invention relates to a so-called active matrix display device that controls the amount of current that is supplied to a light emitting element such as an organic EL by an insulated gate field effect transistor provided in each pixel circuit. More specifically , the present invention relates to a display device incorporating a transistor mobility correction function for each pixel.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  A conventional pixel circuit is arranged at a portion where a row scanning line for supplying a control signal and a column signal line for supplying a video signal intersect, and includes at least a sampling transistor, a pixel capacitor, a drive transistor, and a light emitting element. . The sampling transistor conducts in response to the control signal supplied from the scanning line and samples the video signal supplied from the signal line. The pixel capacitor holds an input voltage corresponding to the signal potential of the sampled video signal. The drive transistor supplies an output current as a drive current during a predetermined light emission period in accordance with the input voltage held in the pixel capacitor. In general, the output current depends on the carrier mobility and threshold voltage of the channel region of the drive transistor. The light emitting element emits light with luminance according to the video signal by the output current supplied from the drive transistor.

  The drive transistor receives an input voltage held in the pixel capacitor at the gate, causes an output current to flow between the source and the drain, and energizes the light emitting element. In general, the light emission luminance of a light emitting element is proportional to the amount of current applied. Further, the output current supply amount of the drive transistor is controlled by the gate voltage, that is, the input voltage written in the pixel capacitor. The conventional pixel circuit controls the amount of current supplied to the light emitting element by changing the input voltage applied to the gate of the drive transistor in accordance with the input video signal.

Here, the operating characteristic of the drive transistor is expressed by the following Equation 1.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ² Formula 1
In the transistor characteristic formula 1, Ids represents a drain current flowing between the source and the drain, and is an output current supplied to the light emitting element in the pixel circuit. Vgs represents a gate voltage applied to the gate with reference to the source, and is the above-described input voltage in the pixel circuit. Vth is the threshold voltage of the transistor. Μ represents the mobility of the semiconductor thin film constituting the channel of the transistor. In addition, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from the transistor characteristic equation 1, when the thin film transistor operates in the saturation region, if the gate voltage Vgs increases beyond the threshold voltage Vth, the thin film transistor is turned on and the drain current Ids flows. In principle, as shown in the above transistor characteristic equation 1, if the gate voltage Vgs is constant, the same amount of drain current Ids is always supplied to the light emitting element. Therefore, if video signals of the same level are supplied to all the pixels constituting the screen, all the pixels should emit light with the same luminance, and the uniformity of the screen should be obtained.

  However, in reality, thin film transistors (TFTs) composed of semiconductor thin films such as polysilicon have variations in individual device characteristics. In particular, the threshold voltage Vth is not constant and varies from pixel to pixel. As apparent from the transistor characteristic equation 1 described above, if the threshold voltage Vth of each drive transistor varies, even if the gate voltage Vgs is constant, the drain current Ids varies and the luminance varies from pixel to pixel. , Damage the screen uniformity. Conventionally, a pixel circuit incorporating a function for canceling variations in threshold voltages of drive transistors has been developed, and is disclosed in, for example, Patent Document 3 described above.

  However, the variation factor of the output current with respect to the light emitting element is not only the threshold voltage Vth of the drive transistor. As is apparent from the transistor characteristic equation 1 described above, the output current Ids varies even when the mobility μ of the drive transistor varies. As a result, the uniformity of the screen is impaired. Correcting the variation in mobility is also a problem to be solved.

In view of the above-described problems of the related art, it is a general object of the present invention to provide a display device having a drive transistor mobility correction function for each pixel. In particular, it is an object of the present invention to provide a display device capable of adaptively correcting mobility for different luminance levels. In order to achieve this purpose, the following measures were taken. That is, the present invention includes at least a light emitting element, a sampling transistor, a drive transistor, and a pixel capacitor, and the sampling transistor is turned on in response to a control signal applied to its gate, and the signal potential of the video signal is set. The drive transistor supplies a drive current corresponding to the signal potential held in the pixel capacitor to the light-emitting element, and the light-emitting element has a luminance corresponding to the signal potential by the drive current. A pixel array unit including a pixel circuit that emits light and a drive unit that drives the pixel array unit, the pixel circuit turning on the sampling transistor and starting sampling of the signal potential. During the correction period from the timing to the second timing when the control signal falls and the sampling transistor is turned off, Negative feedback means for negatively feeding the current back to the pixel capacitance and correcting the mobility of the drive transistor, and when the driving unit turns off the sampling transistor at the second timing, The control signal having a second waveform that gradually falls is applied to the gate of the sampling transistor. Here, when the driving unit turns off the sampling transistor at the second timing, a first waveform that continues to fall after it falls excessively beyond a predetermined level and then returns to the predetermined level. The control signal including the first waveform is supplied to the scanning line connected to the gate of the sampling transistor, and the control signal propagates through the scanning line, and then falls sharply and gently. It is applied to the gate of the sampling transistor as the second waveform that descends.

Specifically, the negative feedback means includes a switching transistor inserted to connect the drive transistor to a power source, and the switching transistor is turned on at the first timing and starts to flow to the drive transistor. Is negatively fed back to the pixel capacitance. Preferably, an additional transistor is included that resets the gate voltage of the drive transistor to a predetermined voltage that exceeds a threshold voltage prior to sampling the video signal, while the switching transistor is temporarily turned on prior to sampling the video signal. and, it holds the pixel capacitor a voltage flowing a drive current to the drive transistor which is reset corresponding to the threshold voltage.

The display device according to the present invention basically includes a pixel array section and a drive section for driving the pixel array section. The pixel array section includes row-like first scanning lines and second scanning lines, column-like signal lines, matrix-like pixels arranged at intersections thereof, power supply lines for supplying power to each pixel, and grounding Line. The driving unit sequentially supplies a first control signal to each first scanning line to scan the pixels line by line in a row unit, and sequentially outputs a second scanner to each second scanning line in accordance with the line sequential scanning. A second scanner for supplying a control signal and a signal selector for supplying a video signal to the column-shaped signal lines in accordance with the line sequential scanning are provided. The pixel includes a light emitting element, a sampling transistor, a drive transistor, a switching transistor, and a pixel capacitor. The sampling transistor has a gate connected to the first scanning line, a source connected to the signal line, and a drain connected to the gate of the drive transistor. The drive transistor and the light emitting element are connected in series between the power line and the ground line to form a current path. The switching transistor is inserted into the current path, and its gate is connected to the second scanning line. The pixel capacitor is connected between the source and gate of the drive transistor. In this configuration, the sampling transistor is turned on in response to the first control signal supplied from the first scanning line, samples the signal potential of the video signal supplied from the signal line, and holds it in the pixel capacitor. The switching transistor is turned on in response to the second control signal supplied from the second scanning line to make the current path conductive, and the drive transistor is driven in accordance with the signal potential held in the pixel capacitor. A current is passed through the light emitting element through a current path placed in the conductive state. The driving unit applies the first control signal to the first scanning line to turn on the sampling transistor to start sampling of the signal potential, and then the second control signal is applied to the second scanning line. The mobility of the drive transistor during the correction period from the first timing when the switching transistor is turned on to the second timing when the first control signal applied to the first scanning line is released and the sampling transistor is turned off Is applied to the signal potential held in the pixel capacitor. That is, when the first scanner turns off the sampling transistor at the second timing, the first control signal applied to the gate of the sampling transistor has a second waveform that falls sharply and then falls gently. Thus, the second timing is automatically adjusted so that the correction period is shortened when the signal potential of the video signal supplied to the signal line is high, while the correction period is lengthened when the signal potential is low. Wherein the first scanner produces a first waveform gradually following the flat after returning to the predetermined level by excessively subsequently fall beyond a predetermined level, said comprising the first waveform the 1 control signal is supplied to the first scanning line, and in the process in which the first control signal propagates through the first scanning line, the second waveform gradually falls and then gradually falls. It is characterized by being applied to the gate of the sampling transistor.

Specifically, the driving unit includes a power pulse generation circuit that generates a power pulse including the first waveform that is a source of the second waveform of the first control signal and supplies the power pulse to the first scanner. wherein said first scanner is sequentially taken out first waveform from the power supply pulse is supplied to the first scan line as the first control signal. Preferably, each pixel includes an additional switching transistor that resets the gate voltage of the drive transistor to a predetermined voltage exceeding a threshold voltage prior to sampling of the video signal, and the second scanner is prior to sampling of the video signal. Then, the switching transistor is temporarily turned on via the second control line, and a drive current is supplied to the reset drive transistor to hold a voltage corresponding to the threshold voltage in the pixel capacitor. .

  According to the present invention, the mobility of the drive transistor is corrected using a part of the period during which the signal potential is sampled into the pixel capacitance (sampling period). Specifically, in the latter half of the sampling period, the switching transistor that constitutes the negative feedback means is turned on, the current path is made conductive, and the drive current is supplied to the drive transistor. This drive current has a magnitude corresponding to the sampled signal potential. At this stage, the light emitting element is in a reverse bias state, and the drive current does not flow through the light emitting element but is charged to its parasitic capacitance and pixel capacitance. Thereafter, the sampling pulse falls, and the gate of the drive transistor is disconnected from the signal line. In the correction period from when the switching transistor (negative feedback means) is turned on to when the sampling transistor is turned off, the drive current is negatively fed back from the drive transistor to the pixel capacitor, and the signal potential is sampled by the pixel capacitor. Deducted from. Since this negative feedback amount acts in a direction to suppress variation in mobility of the drive transistor, mobility correction can be performed for each pixel. That is, when the mobility of the drive transistor is large, the amount of negative feedback with respect to the pixel capacitance is increased, the signal potential held in the pixel capacitance is greatly reduced, and as a result, the output current of the drive transistor is suppressed. On the other hand, when the mobility of the drive transistor is small, the negative feedback amount is also small, and the signal potential held in the pixel capacitor is not significantly affected. Therefore, the output current of the drive transistor does not drop so much. Here, the negative feedback amount has a level corresponding to the signal potential applied directly from the signal line to the gate of the drive transistor. That is, the negative feedback amount increases as the signal potential increases and the luminance increases. As described above, the mobility correction is performed according to the luminance level.

  However, the optimum correction period is not necessarily the same between the case where the luminance is high and the case where the luminance is low. In general, when the luminance is high (white level), the optimum correction period is relatively short. Conversely, when the luminance is intermediate (gray level), the optimum correction period tends to be longer. In the present invention, the correction period is automatically optimized according to the luminance level. That is, the present invention automatically adjusts the second timing at which the sampling transistor is turned off according to the signal potential with respect to the first timing at which the switching transistor is turned on. Specifically, adaptive control is performed so that the correction period is shortened when the signal potential of the video signal supplied from the signal line is high, while the correction period is lengthened when the signal potential of the video signal supplied to the signal line is low. doing. Thereby, it is possible to optimally variably control the correction period according to the signal potential. With such a configuration, the uniformity of the screen can be further improved.

  In particular, in the present invention, by applying the first control signal having a slope waveform that falls steeply toward the intermediate level and then gradually falls to the gate of the sampling transistor, the signal potential is increased when the signal potential is high. The correction period is optimized at both low times. That is, when the signal potential is at a high white level, the sampling transistor is turned off at the portion where the control signal falls sharply, and the correction period is very short. On the other hand, when the signal potential is at a relatively low gray level, the sampling transistor is cut off at a portion where the control signal gradually falls, and a relatively long correction time is obtained. In the case of the white level, even if the signal potential changes slightly, the correction period remains short and hardly needs to be changed. However, if the signal level is low, it is necessary to secure a longer correction time as the gray level shifts to the black level. Therefore, in the present invention, the correction time is optimized from the gray level to the black level by adopting a slope waveform that is steep and descends slowly thereafter.

  However, the slope waveform that is initially steep and gradually changes may become dull due to the time constant of the wiring resistance or the wiring capacitance until it propagates from the first scanner to the gate of the sampling transistor via the first scanning line. is there. When such dullness occurs, an error occurs in adaptive control in the correction period according to the luminance, and the uniformity of the display image may be impaired. Therefore, the present invention uses an overshoot waveform in consideration of the influence of wiring resistance and wiring capacity in advance. That is, the first scanner outputs an overshoot waveform, which becomes dull in the propagation process and finally becomes a desired gradient waveform and is applied to the gate of the sampling transistor. In this way, it is possible to realize an ideal slope waveform in which the beginning of the fall is early and the latter half is gentle, and the optimum correction time is adaptively controlled with respect to signal potentials of different gradations from the white level to the black level. It becomes possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram showing the overall configuration of a display device according to the present invention. As shown in the figure, this display device basically includes a pixel array unit 1 and a drive unit including a scanner unit and a signal unit. The pixel array unit 1 includes a scanning line WS, a scanning line AZ1, a scanning line AZ2, and a scanning line DS arranged in a row, a signal line SL arranged in a column, and the scanning lines WS, AZ1, AZ2, DS. And a matrix pixel circuit 2 connected to the signal line SL, and a plurality of power supply lines for supplying the first potential Vss1, the second potential Vss2, and the third potential Vcc necessary for the operation of each pixel circuit 2. The signal unit includes a horizontal selector 3 and supplies a video signal to the signal line SL. The scanner unit includes a write scanner 4, a drive scanner 5, a first correction scanner 71, and a second correction scanner 72, and supplies control signals to the scanning line WS, the scanning line DS, the scanning line AZ1, and the scanning line AZ2, respectively. The pixel circuit 2 is sequentially scanned for each row.

  Here, the write scanner 4 is composed of a shift register, operates in response to a clock signal WSCK supplied from the outside, and sequentially rolls a start signal WSST supplied from the outside and outputs it to each scanning line WS. doing. At that time, the falling waveform of the control signal WS is generated using the power supply pulse WSP supplied from the outside. The drive scanner 5 is also composed of a shift register, operates in response to an externally supplied clock signal DSCK, and sequentially outputs a control signal DS to each scanning line DS by sequentially transferring a start signal DSST supplied from the outside. doing.

  FIG. 2 is a circuit diagram illustrating a configuration example of a pixel incorporated in the image display device illustrated in FIG. As illustrated, the pixel circuit 2 includes a sampling transistor Tr1, a drive transistor Trd, a first switching transistor Tr2, a second switching transistor Tr3, a third switching transistor Tr4, a pixel capacitor Cs, and a light emitting element EL. Including. The sampling transistor Tr1 conducts in response to a control signal supplied from the scanning line WS during a predetermined sampling period, and samples the signal potential of the video signal supplied from the signal line SL into the pixel capacitor Cs. The pixel capacitor Cs applies an input voltage Vgs to the gate G of the drive transistor Trd in accordance with the signal potential of the sampled video signal. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL. The light emitting element EL emits light with a luminance corresponding to the signal potential of the video signal by the output current Ids supplied from the drive transistor Trd during a predetermined light emission period.

  The first switching transistor Tr2 is turned on according to the control signal supplied from the scanning line AZ1 prior to the sampling period, and sets the gate G of the drive transistor Trd to the first potential Vss1. The second switching transistor Tr3 is turned on in response to a control signal supplied from the scanning line AZ2 prior to the sampling period, and sets the source S of the drive transistor Trd to the second potential Vss2. The third switching transistor Tr4 is turned on in response to a control signal supplied from the scanning line DS prior to the sampling period to connect the drive transistor Trd to the third potential Vcc, and thus corresponds to the threshold voltage Vth of the drive transistor Trd. The voltage is held in the pixel capacitor Cs to correct the influence of the threshold voltage Vth. Further, the third switching transistor Tr4 is turned on again in response to the control signal supplied from the scanning line DS during the light emission period, connects the drive transistor Trd to the third potential Vcc, and causes the output current Ids to flow through the light emitting element EL.

  As is apparent from the above description, the pixel circuit 2 is composed of five transistors Tr1 to Tr4 and Trd, one pixel capacitor Cs, and one light emitting element EL. The transistors Tr1 to Tr3 and Trd are N channel type polysilicon TFTs. Only the transistor Tr4 is a P-channel type polysilicon TFT. However, the present invention is not limited to this, and N-channel and P-channel TFTs can be mixed as appropriate. The light emitting element EL is, for example, a diode type organic EL device having an anode and a cathode. However, the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

  FIG. 3 is a schematic diagram in which only the pixel circuit 2 is extracted from the image display device shown in FIG. In order to facilitate understanding, the signal potential Vsig of the video signal sampled by the sampling transistor Tr1, the input voltage Vgs and output current Ids of the drive transistor Trd, and the capacitance component Coled of the light emitting element EL are added. . The operation of the pixel circuit 2 according to the present invention will be described below with reference to FIG.

  FIG. 4 is a timing chart of the pixel circuit shown in FIG. With reference to FIG. 4, the operation of the pixel circuit according to the present invention shown in FIG. 3 will be described in detail. FIG. 4 shows the waveforms of control signals applied to the scanning lines WS, AZ1, AZ2 and DS along the time axis T. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. Since the transistors Tr1, Tr2 and Tr3 are N-channel type, they are turned on when the scanning lines WS, AZ1 and AZ2 are at a high level and turned off when the scanning lines are at a low level. On the other hand, since the transistor Tr4 is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. This timing chart also shows the change in the potential of the gate G and the change in the potential of the source S of the drive transistor Trd, along with the waveforms of the control signals WS, AZ1, AZ2, and DS.

  In the timing chart of FIG. 4, timings T1 to T8 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. The timing chart shows the waveforms of the control signals WS, AZ1, AZ2, DS applied to the pixels for one row.

  At timing T0 before the field starts, all control line numbers WS, AZ1, AZ2, DS are at a low level. Therefore, the N-channel transistors Tr1, Tr2, Tr3 are in the off state, while only the P-channel transistor Tr4 is in the on state. Therefore, since the drive transistor Trd is connected to the power supply Vcc via the transistor Tr4 in the on state, the output current Ids is supplied to the light emitting element EL according to the predetermined input voltage Vgs. Therefore, the light emitting element EL emits light at the timing T0. At this time, the input voltage Vgs applied to the drive transistor Trd is expressed by the difference between the gate potential (G) and the source potential (S).

  At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. As a result, the transistor Tr4 is turned off and the drive transistor Trd is disconnected from the power supply Vcc, so that the light emission stops and the non-light emission period starts. Therefore, at the timing T1, all the transistors Tr1 to Tr4 are turned off.

  After timing T1, the control signal AZ2 rises at timing T21, and the switching transistor Tr3 is turned on. As a result, the source (S) of the drive transistor Trd is initialized to the predetermined potential Vss2. Subsequently, at timing T22, the control signal AZ1 rises and the switching transistor Tr2 is turned on. As a result, the gate potential (G) of the drive transistor Trd is initialized to a predetermined potential Vss1. As a result, the gate G of the drive transistor Trd is connected to the reference potential Vss1, and the source S is connected to the reference potential Vss2. Here, Vss1−Vss2> Vth is satisfied, and by setting Vss1−Vss2 = Vgs> Vth, preparation for Vth correction performed at timing T3 is performed. In other words, the period T21-T3 corresponds to a reset period of the drive transistor Trd. Further, when the threshold voltage of the light emitting element EL is VthEL, VthEL> Vss2 is set. Thereby, a minus bias is applied to the light emitting element EL, and a so-called reverse bias state is obtained. This reverse bias state is necessary for normally performing the Vth correction operation and the mobility correction operation to be performed later.

  At timing T3, the control signal AZ2 is set to low level, and then the control signal DS is set to low level. As a result, the transistor Tr3 is turned off while the transistor Tr4 is turned on. As a result, the drain current Ids flows into the pixel capacitor Cs, and the Vth correction operation is started. At this time, the gate G of the drive transistor Trd is held at Vss1, and the current Ids flows until the drive transistor Trd is cut off. When cut off, the source potential (S) of the drive transistor Trd becomes Vss1-Vth. At timing T4 after the drain current is cut off, the control signal DS is returned to the high level again, and the switching transistor Tr4 is turned off. Further, the control signal AZ1 is also returned to the low level, and the switching transistor Tr2 is also turned off. As a result, Vth is held and fixed in the pixel capacitor Cs. Thus, the timing T3-T4 is a period for detecting the threshold voltage Vth of the drive transistor Trd. Here, this detection period T3-T4 is called a Vth correction period.

  After performing the Vth correction in this way, the control signal WS is switched to the high level at the timing T5, the sampling transistor Tr1 is turned on, and the signal potential Vsig of the video signal is written in the pixel capacitor Cs. The pixel capacitance Cs is sufficiently smaller than the equivalent capacitance Coled of the light emitting element EL. As a result, almost most of the signal potential Vsig of the video signal is written into the pixel capacitor Cs. To be precise, for Vss1. The difference Vsig−Vss1 of Vsig is written to the pixel capacitor Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a level (Vsig−Vss1 + Vth) obtained by adding Vth previously detected and held and Vsig−Vss1 sampled this time. In the following description, assuming Vss1 = 0V for simplification of explanation, the gate / source voltage Vgs becomes Vsig + Vth as shown in the timing chart of FIG. The sampling of the signal potential Vsig of the video signal is performed until timing T7 when the control signal WS returns to the low level. That is, the timing T5-T7 corresponds to the sampling period.

  At timing T6 before the end of the sampling period T7, the control signal DS becomes low level and the switching transistor Tr4 is turned on. As a result, the drive transistor Trd is connected to the power supply Vcc, so that the pixel circuit proceeds from the non-light emitting period to the light emitting period. In this manner, the mobility correction of the drive transistor Trd is performed in the period T6-T7 in which the sampling transistor Tr1 is still on and the switching transistor Tr4 is on. That is, in the present invention, the mobility correction is performed in the period T6-T7 in which the rear part of the sampling period and the head part of the light emission period overlap. Note that, at the beginning of the light emission period in which the mobility correction is performed, the light emitting element EL is actually in a reverse bias state, and thus does not emit light. In the mobility correction period T6-T7, the drain current Ids flows through the drive transistor Trd while the gate G of the drive transistor Trd is fixed to the level of the signal potential Vsig of the video signal. Here, by setting Vss1−Vth <VthEL, the light emitting element EL is placed in a reverse bias state, so that it exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd is written into a capacitor C = Cs + Coled obtained by combining both the pixel capacitor Cs and the equivalent capacitor Coled of the light emitting element EL. As a result, the source potential (S) of the drive transistor Trd increases. In the timing chart of FIG. 4, this increase is represented by ΔV. Since this increase ΔV is eventually subtracted from the gate / source voltage Vgs held in the pixel capacitor Cs, negative feedback is applied. In this way, the mobility μ can be corrected by negatively feeding back the output current Ids of the drive transistor Trd to the input voltage Vgs of the drive transistor Trd. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T6-T7. For this purpose, the fall of the control signal WS is inclined.

At timing T7, the control signal WS becomes low level and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since the application of the signal potential Vsig of the video signal is released, the gate potential (G) of the drive transistor Trd can be increased and increases with the source potential (S). Meanwhile, the gate / source voltage Vgs held in the pixel capacitor Cs maintains a value of (Vsig−ΔV + Vth). As the source potential (S) rises, the reverse bias state of the light emitting element EL is canceled, so that the light emitting element EL actually starts to emit light by the inflow of the output current Ids. The relationship between the drain current Ids and the gate voltage Vgs at this time is given by the following equation 2 by substituting Vsig−ΔV + Vth into Vgs of the previous transistor characteristic equation 1.
Ids = kμ (Vgs−Vth) ² = kμ (Vsig−ΔV) ² Equation 2
In the above formula 2, k = (1/2) (W / L) Cox. It can be seen from the characteristic formula 2 that the term Vth is canceled and the output current Ids supplied to the light emitting element EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal potential Vsig of the video signal. In other words, the light emitting element EL emits light with a luminance corresponding to the signal potential Vsig of the video signal. At that time, Vsig is corrected by the negative feedback amount ΔV. This correction amount ΔV acts so as to cancel the effect of the mobility μ located in the coefficient part of the characteristic formula 2 just. Therefore, the drain current Ids substantially depends only on the signal potential Vsig of the video signal.

  Finally, when the timing T8 is reached, the control signal DS becomes high level, the switching transistor Tr4 is turned off, the light emission ends, and the field ends. Thereafter, the operation proceeds to the next field, and the Vth correction operation, the signal potential sampling operation, the mobility correction operation, and the light emission operation are repeated again.

  FIG. 5 is a circuit diagram showing a state of the pixel circuit 2 in the mobility correction period T6-T7. As shown in the figure, in the mobility correction period T6-T7, the sampling transistor Tr1 and the switching transistor Tr4 are on, while the remaining switching transistors Tr2 and Tr3 are off. In this state, the source potential (S) of the drive transistor Tr4 is Vss1-Vth. This source potential (S) is also the anode potential of the light emitting element EL. By setting Vss1−Vth <VthEL as described above, the light emitting element EL is placed in a reverse bias state, and exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd flows into the combined capacitance C = Cs + Coled of the pixel capacitance Cs and the equivalent capacitance Coled of the light emitting element EL. In other words, a part of the drain current Ids is negatively fed back to the pixel capacitor Cs, and the mobility is corrected.

  FIG. 6 is a graph of the above-described transistor characteristic formula 2, in which Ids is plotted on the vertical axis and Vsig is plotted on the horizontal axis. The characteristic formula 2 is also shown below the graph. In the graph of FIG. 6, a characteristic curve is drawn in a state where the pixel 1 and the pixel 2 are compared. The mobility μ of the drive transistor of the pixel 1 is relatively large. Conversely, the mobility μ of the drive transistor included in the pixel 2 is relatively small. Thus, when the drive transistor is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels. For example, when the signal potential Vsig of the video signal of the same level is written in both the pixels 1 and 2, the output current Ids 1 ′ flowing through the pixel 1 having the high mobility μ is equal to the mobility μ unless the mobility is corrected. A large difference is generated as compared with the output current Ids2 'flowing through the small pixel 2. In this way, a large difference occurs between the output currents Ids due to the variation in the mobility μ, so that unevenness occurs and the uniformity of the screen is impaired.

  Therefore, in the present invention, the variation in mobility is canceled by negatively feeding back the output current to the input voltage side. As apparent from the previous transistor characteristic equation 1, the drain current Ids increases when the mobility is large. Therefore, the negative feedback amount ΔV increases as the mobility increases. As shown in the graph of FIG. 6, the negative feedback amount ΔV1 of the pixel 1 having a high mobility μ is larger than the negative feedback amount ΔV2 of the pixel 2 having a low mobility. Therefore, the larger the mobility μ is, the more negative feedback is applied, and the variation can be suppressed. As shown in the figure, when ΔV1 is corrected in the pixel 1 having a high mobility μ, the output current greatly decreases from Ids1 ′ to Ids1. On the other hand, since the correction amount ΔV2 of the pixel 2 having the low mobility μ is small, the output current Ids2 ′ does not decrease so much to Ids2. As a result, Ids1 and Ids2 are substantially equal, and the variation in mobility is cancelled. Since the cancellation of the variation in mobility is performed in the entire range of Vsig from the black level to the white level, the uniformity of the screen becomes extremely high. In summary, when there are pixels 1 and 2 having different mobility, the correction amount ΔV1 of the pixel 1 having high mobility is smaller than the correction amount ΔV2 of the pixel 2 having low mobility. That is, as the mobility increases, ΔV increases and the decrease value of Ids increases. As a result, pixel current values having different mobilities are made uniform, and variations in mobility can be corrected.

For reference, numerical analysis of the mobility correction described above is performed. As shown in FIG. 5, the analysis is performed by taking the source potential of the drive transistor Trd as a variable V in a state where the transistors Tr1 and Tr4 are turned on. Assuming that the source potential (S) of the drive transistor Trd is V, the drain current Ids flowing through the drive transistor Trd is as shown in Equation 3 below.

Further, Ids = dQ / dt = CdV / dt is established as shown in the following Expression 4 by the relationship between the drain current Ids and the capacitance C (= Cs + Coled).

Both sides are integrated by substituting Equation 3 into Equation 4. Here, the initial state of the source voltage V is -Vth, and the mobility variation correction time (T6-T7) is t. When this differential equation is solved, the pixel current with respect to the mobility correction time t is given as shown in Equation 5 below.

  By the way, the optimum mobility correction time t tends to vary depending on the luminance level of the pixel (the signal potential Vsig of the video signal). This point will be described with reference to FIG. In the graph of FIG. 7, the horizontal axis represents mobility correction time t (T7-T6), and the vertical axis represents luminance (signal potential). In the case of high luminance (white gradation), when the mobility correction time is set to t1 between the drive transistor with high mobility and the drive transistor with low mobility, the luminance levels are exactly equal. That is, when the input signal potential is white gradation, the mobility correction time t1 is the optimum correction time. On the other hand, when the signal potential is intermediate luminance (gray gradation), there is a difference in luminance between the high mobility transistor and the low mobility transistor at the mobility correction time t1, and complete correction cannot be performed. If a correction time t2 longer than t1 is ensured, the luminance is the same level between transistors with high mobility and low mobility. Therefore, when the signal potential is a gray gradation, the optimum correction time t2 is longer than the optimum correction time t1 when the signal potential is white.

  If the mobility correction time t is fixed regardless of the luminance level, complete mobility correction cannot be performed for all gradations, resulting in unevenness. For example, if the mobility correction time t is matched with the white gradation optimum correction period t1, streaks remain on the screen when the input video signal is in gray gradation. Conversely, when the gray gradation optimum correction period t2 is fixed, stripes appear on the screen when the video signal has a white gradation. That is, if the mobility correction time t is fixed, it is not possible to simultaneously correct the mobility variation over all gradations from white to gray gradation.

  Therefore, the present invention makes it possible to optimally automatically adjust the mobility correction period according to the level of the input video signal. The principle will be described in detail with reference to FIG. FIG. 8 shows waveforms of the control signal WS (WS gate pulse) and the control signal DS (DS gate pulse) along the time axis. The DS gate pulse is switched from the high level to the low level at timing T6, and the P-channel transistor Tr4 is turned on. The ON point T6 of this Tr4 is the start of the mobility variation correction period t. Thereafter, the WS gate pulse falls from the high level to the low level. This falling waveform is a slope waveform that falls steeply toward the intermediate level first, and then gently falls. The WS gate pulse is applied to the gate of the sampling transistor Tr1. On the other hand, the signal potential Vsig is applied to the source of the sampling transistor Tr1 through the signal line SL. The sampling transistor Tr1 is cut off when the gate potential just falls to the threshold voltage Vth (Tr1) with respect to the source potential. Since the signal potential Vsig is applied to the source of the sampling transistor, the WS gate pulse is cut off when it is just lowered to Vsig + Vth (Tr1). The OFF point of this Tr1 is timing T7, which defines the end of the mobility variation correction period t. Thus, the mobility variation correction period t is given by T7-T6.

  As apparent from the WS gate pulse waveform of FIG. 8, when the signal potential Vsig is high at the white level, the OFF point of Tr1 is close to the ON point of Tr4, and therefore the mobility correction period t is short. Even if there is a slight difference in the signal potential Vsig at the white level, basically the same short correction period t is required, so that the fall of the WS gate pulse is steep. On the other hand, when the signal potential Vsig is low at the gray level, the mobility correction period t needs to be long as apparent from the graph of FIG. For this reason, the WS gate pulse is sharply lowered and then gently lowered to separate the Tr1 OFF point from the Tr4 ON point. As a result, a sufficient mobility correction period t is secured with gray level luminance. From the gray level to the black level, the correction period t needs to be optimally adjusted according to the difference in Vsig. For this reason, the second half of the WS gate pulse is gentle, and a correction period t having a large and appropriate length is obtained according to the level of Vsig. In principle, a longer mobility correction period t is required as Vsig is lower.

  FIG. 9 illustrates a configuration example of the write scanner 4 that generates the control signal WS. The figure particularly shows the output part of the light scanner 4. In general, the write scanner 4 is composed of a shift register, operates in response to a clock signal WSCK input from the outside, and sequentially shifts a start signal WSST supplied from the outside, so that an input signal for each row of the scanning line WS. Generate WSIN. The output unit 4a of the write scanner 4 is provided for each line, operates in response to the input signal WSIN, generates a control signal WS, and applies it to the gate of the sampling transistor Tr1 of the pixel circuit 2 via the scanning line WS. .

  The output unit 4a for one line basically includes an output buffer having an inverter configuration as shown in FIG. In this inverter, a P-channel transistor WSTrP and an N-channel transistor WSTrN are connected in series between a power supply line and a ground line. A power supply pulse WSpulse formed by an external power supply pulse generation circuit is applied to the power supply line, while a predetermined ground potential VSSWS is applied to the ground line. In the configuration of FIG. 9, the pixel array unit including the light scanner 4 and the pixel 2 is mounted on a panel formed on the same substrate, and the power pulse generation circuit generates a power pulse WSpulse outside the panel, which is generated in the panel. Is supplied to the power line of the write scanner 4.

  FIG. 10 is a circuit diagram illustrating another example of the output unit of the write scanner 4. In order to facilitate understanding, parts corresponding to those of the previous embodiment shown in FIG. 9 are denoted by corresponding reference numerals. The difference from the embodiment of FIG. 9 is that the P-channel transistor WSTrP of the output buffer is replaced with a transmission gate element WSTG. Since the on-resistance of the transmission gate element is lower than that of the P-channel transistor, it can be converted into the control signal WS without adding much distortion to the waveform of the power supply pulse WSpulse.

  FIG. 11 is a timing chart for explaining the operation of the output unit 4b of the write scanner 4 shown in FIG. The input signal WSIN sequentially output from the shift register in accordance with the line sequential scanning is switched from the high level VDDWS to the low level VSSWS at the timing J1. As a result, the transmission gate WSTG included in the output unit 4b of the write scanner 4 is turned on, and the VDDWS level of the power supply pulse WSpulse is guided to the output side. As a result, the control signal WS rises from the low level VSSWS to the high level VDDWS at the timing J1. Thereafter, the power supply pulse WSpulse falls along the ramp waveform while the input signal WSIN is maintained at the low level VSSWS and the transmission gate WSTG is continuously opened. That is, it begins to steeply fall toward the intermediate level, and then gradually falls. This ramp waveform is guided to the output terminal of the output buffer through the transmission gate WSTG in the on state. Therefore, the control signal WS starts to fall along the slope waveform at the timing J2. Since this slope waveform has almost no loss in the case of the transmission gate WSTG, it is the same as the slope waveform of the power supply pulse WSpulse. Thereafter, at timing J3, the input signal WSIN returns from the low level VSSWS to the high level VDDWS, so that the transmission gate WSTG is turned off. On the other hand, the N-channel transistor WSTrN is turned on. As a result, the control signal WS becomes the low level VSSWS at the timing J3.

  Thereafter, the control signal WS propagates from the output unit 4b of the write scanner 4 through the scanning line WS and is applied to the gate of the sampling transistor Tr1 on the pixel circuit 2 side. The final gate application waveform is represented by a solid line. On the other hand, for comparison, the inclined waveform of the power supply pulse WSpulse is represented by a dotted line. As is apparent from the figure, the control signal WS is dull and loses steepness due to the wiring capacitance and wiring resistance in the propagation process. When such dullness is added, an error occurs in the optimum control of the mobility correction period.

  FIG. 12 is an equivalent circuit of the control signal transmission system shown in FIG. 9 or FIG. As shown in the figure, the power pulse WSpulse supplied from the outside to the power line of the write scanner 4 passes through the equivalent resistance Rbuf of the buffer, passes through the wiring resistance Rline of the scanning line WS, and then is applied to the gate of the sampling transistor Tr1. Is done. A wiring capacitance Cline is parasitic on the scanning line WS. The time constant of this signal transmission system is given by τ = Rbuf × Cline + Rline × Cline / 2. Since the waveform of the power supply pulse WSpulse is dulled during transmission with this time constant τ, the final waveform applied to the gate of the sampling transistor may deviate from an ideal curve.

  FIG. 13 is a schematic diagram comparing the falling waveform of the power supply pulse WSpulse and the falling waveform of the control signal WS. The waveform of the control signal WS is the final waveform applied to the gate of the sampling pulse. As is apparent from the figure, the falling waveform of the control signal WS is duller than the falling waveform of WSpulse, and both the sharpness of the first half and the gentle curve of the second half are lost. Generally, the optimum falling waveform of the control signal WS differs depending on the size factor of the drive transistor Trd included in the pixel circuit. Basically, the larger the size factor W / L of the drive transistor Trd, the faster the initial rising speed. Therefore, the control signal WS is required to have a steep falling characteristic. On the other hand, in a region where the signal potential Vsig is low, a long mobility correction period is necessary. Therefore, a control signal waveform that first falls steeply and then gently falls is required. However, since the waveform becomes dull due to the wiring resistance and wiring capacity of the signal transmission system, it may be difficult to obtain an ideal control signal waveform without taking any measures.

  Therefore, the present invention solves this problem by using an overshoot waveform. FIG. 14 is a schematic waveform diagram showing the principle of the present invention. A power pulse generation circuit outside the panel supplies a power pulse WSpulse having an overshoot waveform to the power line of the write scanner 4 as shown in the figure. As shown in the figure, this overshoot waveform is a waveform that first falls excessively from VDDWS beyond the intermediate level, then returns to the intermediate level and then continues flat. Basically, the write scanner 4 extracts the power pulse WSpulse as it is and outputs it as a control signal. However, the control signal WS having an overshoot waveform at the time of output is blunted in the propagation process, and at the stage when it reaches the gate of the sampling transistor, as shown in the figure, it begins to fall sharply toward the intermediate level, and then gently. The control signal WS has an ideal inclination waveform that descends. By using the power pulse WSpulse having an overshoot waveform in this way, a control signal WS that finally starts to fall quickly and gently sweeps in the latter half can be obtained.

  FIG. 15 is a waveform diagram showing an example of the power supply pulse WSpulse. As shown in the figure, in this embodiment, the power pulse generation circuit generates a power pulse WSpulse having an overshoot waveform defined by a straight line, and supplies the power pulse WSpulse to the power line VDDWS of the write scanner. The power supply pulse WSpulse exceeds the ground level VSSWS and drops rapidly to V1, then returns to the V2 level and continues flat. As shown in the figure, the final waveform applied to the gate of the control signal WS is influenced by the time constant of the signal transmission system, the overshoot portion disappears, the first steeply falls first, and then falls gently. It has become. Since the overshoot waveform of the power pulse WSpulse can be composed only of the power sources V1 and V2 and further switching elements such as transistors, it can be made relatively easily. It can also be built in.

  FIG. 16 shows an embodiment of a power supply pulse generation circuit according to the present invention, which generates the power supply pulse WSpulse shown in FIG. FIG. 16A shows a circuit configuration, and FIG. 16B is a timing chart showing its operation. As shown in (A), this power pulse generation circuit is composed of three switches SW1, SW2, SW3 and three power lines VDDWS, V1, V2.

  As shown in (B), the switch SW2 is turned on at the timing K1, while the switches SW1 and SW3 are turned off. As a result, the power supply pulse WSpulse rapidly decreases to the level V1 in the initial stage. Thereafter, the switch SW2 is turned off at the timing K2, while the switch SW3 is turned on. As a result, the power supply pulse WSpulse returns to the intermediate level V2. Thereafter, the intermediate level V2 is kept flat until the switch SW3 is turned off at the timing K3.

  FIG. 17 is a waveform diagram showing another example of the overshoot waveform of the power supply pulse WSpulse according to the present invention. The difference from the previous embodiment shown in FIG. 15 is that the return process of the overshoot waveform is curved. By attaching this curve, the slope waveform of the control signal WS can be made smoother.

  FIG. 18 shows another embodiment of the power supply pulse generation circuit according to the present invention. In particular, the power supply pulse WSpulse shown in FIG. 17 can be generated. In order to facilitate understanding, portions corresponding to those of the previous embodiment shown in FIG. 16 are denoted by corresponding reference numerals. The difference is that a resistor R1 and a capacitor C are connected between one end of the switch WS3 and the output terminal, and a resistor R2 is connected between the other end of the switch WS3 and the power source V2, as shown in FIG. That is. By adding the capacitance component C and the resistance component R to the output terminal portion, the return portion of the overshoot waveform shown in FIG. 17 can be curved. By placing the resistor R2 between the capacitor C and the power source V2, the effect of the capacitor C appears.

  FIG. 19 is a schematic diagram showing the wiring relationship of the power supply pulse generation circuit shown in FIG. As shown in the figure, the output node (WSpulse node) of this power supply pulse generation circuit is connected to the scanning line WS via the output section of the write scanner. In this embodiment, the capacitor C in the power supply pulse generation circuit is seen as a WSpulse node. Therefore, it is necessary to consider this capacitance C as a part of the wiring capacitance.

  FIG. 20 shows another embodiment of the power supply pulse generation circuit, and parts corresponding to those of the previous embodiment shown in FIG. 19 are denoted by corresponding reference numerals for easy understanding. In this embodiment, a resistor R1 and a capacitor C1 are attached to one end side of the switch SW3, and a resistor R2 and a capacitor C2 are attached to the other end side. That is, the resistor R and the capacitor C that round the overshoot waveform are divided on both sides of the switch SW3. In this case, the total capacitance value is C1 + C2, but only the capacitance C1 can be seen as a WSpulse node.

  FIG. 21 is a circuit diagram showing another embodiment of the power pulse generation circuit. For easy understanding, parts corresponding to those of the previous embodiment shown in FIG. 19 are denoted by corresponding reference numerals. In the present embodiment, the resistor R1 for rounding the overshoot waveform is connected to one end side of the switch SW3, while the capacitor C is connected to the other end side. As a result, the internal capacity C is invisible to the Wpulse node. By placing the resistor R2 between the capacitor C and the power source V2, the effect of the capacitor C appears.

  FIG. 22 is a circuit diagram showing another embodiment of the power supply pulse generating circuit. In consideration of actual use conditions, resistors R1 to R4 and capacitors C1 to C4 are arranged as shown in the figure. In this case, it is necessary to consider the arrangement of the resistor R as a protective resistor.

  FIG. 23 shows a power pulse WSpulse having an overshoot waveform generated by the power pulse generation circuit shown in FIG. As shown in the figure, this waveform is curved to some extent even in the initial fall process. As a result, a more practical slope waveform control signal WS can be applied to the gate of the sampling transistor.

  As described above, the display device according to the present invention basically includes the pixel array unit 1 and the drive unit that drives the pixel array unit 1. The pixel array unit 1 includes row-like first scanning lines WS and second scanning lines DS, column-like signal lines SL, matrix-like pixels 2 arranged at intersections thereof, and power supply to the respective pixels 2. Power supply line Vcc and ground line. The drive unit sequentially supplies the first control signal WS to the first scanning line WS to scan the pixels 2 line-sequentially in units of rows, and to each second scanning line DS in accordance with the line-sequential scanning. A second scanner 5 that sequentially supplies the second control signal DS and a signal selector 3 that supplies video signals to the column-shaped signal lines SL in accordance with the line sequential scanning are provided.

  Each pixel 2 includes a light emitting element EL, a sampling transistor Tr1, a drive transistor Trd, a switching transistor Tr4, and a pixel capacitor Cs. The sampling transistor Tr1 has a gate connected to the first scanning line WS, a source connected to the signal line SL, and a drain connected to the gate G of the drive transistor Trd. The drive transistor Trd and the light emitting element EL are connected in series between the power supply line Vcc and the ground line to form a current path. When the switching transistor Tr4 is inserted into this current path, its gate is connected to the second scanning line DS. The pixel capacitor Cs is connected between the source S and the gate G of the drive transistor Trd.

  In such a configuration, the sampling transistor Tr1 is turned on in response to the first control signal WS supplied from the first scanning line WS, samples the signal potential Vsig of the video signal supplied from the signal line SL, and holds it in the pixel capacitor Cs. . The switching transistor Tr4 is turned on in response to the second control signal DS supplied from the second scanning line DS to bring the aforementioned current path into a conductive state. The drive transistor Trd causes the drive current Ids to flow to the light emitting element EL through the current path set in a conductive state in accordance with the signal potential Vsig held in the pixel capacitor Cs.

  As a feature of the present invention, the driving unit (3, 4, 5) applies the first control signal WS to the first scanning line WS to turn on the sampling transistor Tr1 and starts sampling of the signal potential Vsig. From the first timing T6 at which the second control signal DS is applied to the second scanning line DS and the switching transistor Tr4 (negative feedback means) is turned on, the first control signal WS applied to the first scanning line WS is released and sampling is performed. In the correction period t until the second timing T7 when the transistor Tr1 is turned off, the mobility correction is performed by adding the correction for the mobility μ of the drive transistor Trd to the signal potential Vsig held in the pixel capacitor Cs. At this time, the drive unit shortens the correction period t when the signal potential Vsig of the video signal supplied to the signal line SL is high, while the correction period t decreases when the signal potential Vsig of the video signal supplied to the signal line SL is low. The second timing T7 is automatically adjusted to be longer.

  Specifically, when the sampling transistor Tr1 is turned off at the second timing T7, the first scanner (write scanner) 4 is supplied to the signal line SL by setting the falling edge of the first control signal WS to an inclined waveform. The second timing T7 is automatically adjusted so that the correction period t is shortened when the signal potential Vsig of the video signal is high, while the correction period t is lengthened when the signal potential Vsig is low. Here, the write scanner 4 applies a first control signal WS having a ramp waveform that first falls steeply toward the intermediate level V2 and then gradually falls to the gate of the sampling transistor Tr1, and the signal potential Vsig is high. In order to optimize the correction period t both at the time and when the signal potential Vsig is low, the write scanner 4 continues to overshoot after falling to the lower limit V1 over the intermediate level V2 and subsequently returning to the intermediate level V2. A waveform is generated, and the first control signal WS including the overshoot waveform is applied to the gate of the sampling transistor Tr1 after being dulled into a ramp waveform in the process of propagating through the first scanning line WS. In the embodiment, the drive unit of the display device includes a power pulse generation circuit that generates a power pulse WSpulse including an overshoot waveform that is a source of the gradient waveform of the first control signal WS and supplies the power pulse WSpulse to the light scanner 4. The write scanner (first scanner) 4 sequentially extracts the overshoot waveform from the power supply pulse WSpulse and supplies it as a first control signal WS to each first control line WS.

  Each pixel 2 has a drive transistor threshold voltage Vth correction function in addition to the mobility correction function described above. That is, the pixel includes additional switching transistors Tr2 and Tr3 that reset or initialize the gate potential (G) and the source potential (S) of the drive transistor Trd prior to sampling of the video signal. Prior to the sampling of the video signal, the second scanner 5 temporarily turns on the switching transistor Tr4 via the second control line DS, and passes the drive current Ids through the reset drive transistor Trd to the threshold voltage Vth. A corresponding voltage is held in the pixel capacitor Cs.

It is a typical block diagram which shows the whole structure of the display apparatus which concerns on this invention. It is a circuit diagram which shows the pixel structure of the display apparatus which concerns on this invention. It is a schematic diagram with which it uses for operation | movement description of the display apparatus which concerns on this invention. 3 is a timing chart for explaining the operation of the display device according to the present invention. It is a typical circuit diagram with which it uses for operation | movement description of the display apparatus which concerns on this invention. It is a graph with which it uses for operation | movement description of the display apparatus which concerns on this invention. It is a graph with which it uses for operation | movement description of the display apparatus which concerns on this invention. It is a wave form diagram with which it uses for operation | movement description of the display apparatus which concerns on this invention. It is a circuit diagram which shows the Example of the light scanner contained in the display apparatus concerning this invention. It is a circuit diagram which similarly shows the other Example of a write scanner. 11 is a timing chart for explaining the operation of the output unit of the light scanner shown in FIG. 10. FIG. 11 is an equivalent circuit diagram of an output system of the write scanner shown in FIGS. 9 and 10. It is a wave form diagram with which it uses for operation | movement description of the display apparatus concerning this invention. It is a wave form diagram similarly provided for operation | movement description. It is a wave form diagram similarly provided for operation | movement description. 1 is a circuit diagram and a timing chart showing an embodiment of a power pulse generation circuit included in a display device according to the present invention. It is a wave form diagram with which it uses for operation | movement description of the display apparatus concerning this invention. It is the circuit diagram and timing chart which show other embodiment of the power supply pulse generation circuit contained in the display apparatus concerning this invention. It is a circuit diagram which shows the Example of a power supply pulse generation circuit. It is a circuit diagram which shows the other Example of a power supply pulse generation circuit. It is a circuit diagram which shows another Example of a power supply pulse generation circuit. It is a circuit diagram which shows another Example of a power supply pulse generation circuit. FIG. 23 is a waveform diagram showing power supply pulses generated by the power supply pulse generation circuit shown in FIG. 22.

Explanation of symbols

0 ... Panel, 1 ... Pixel array part, 2 ... Pixel, 3 ... Horizontal selector, 4 ... Write scanner, 5 ... Drive scanner, Tr1 ... Sampling transistor, Tr4 ... Switching transistors, Trd ... Drive transistors

Claims (6)

It includes at least a light emitting element, a sampling transistor, a drive transistor, and a pixel capacitor. The sampling transistor is turned on in response to a control signal applied to the gate thereof, and holds the signal potential of the video signal in the pixel capacitor. The drive transistor supplies a driving current corresponding to the signal potential held in the pixel capacitor to the light emitting element, and the light emitting element emits light with a luminance corresponding to the signal potential by the driving current. A pixel array unit comprising:
A drive unit for driving the pixel array unit,
The pixel circuit has a correction period from a predetermined first timing after the sampling transistor is turned on to start sampling of the signal potential to a second timing at which the control signal falls and the sampling transistor is turned off. Negative feedback means for negatively feeding back the drive current to the pixel capacitor and correcting the mobility of the drive transistor;
When the sampling unit turns off the sampling transistor at the second timing, the driving unit generates a first waveform that falls excessively beyond a predetermined level, then returns to the predetermined level, and continues flat. The control signal including the first waveform is supplied to the scanning line connected to the gate of the sampling transistor, and the control signal falls sharply in the process of propagating the scanning line and then falls gently. A display device characterized by being applied to the gate of the sampling transistor in a gradual second waveform. The negative feedback means comprises a switching transistor inserted to connect the drive transistor to a power source,
2. The display device according to claim 1, wherein the switching transistor is turned on at the first timing, and the drive current that has started to flow through the drive transistor is negatively fed back to the pixel capacitor. Including an additional transistor that resets the gate voltage of the drive transistor to a predetermined voltage above a threshold voltage prior to sampling of the video signal,
The switching transistor is temporarily turned on prior to sampling of the video signal, and a driving current is supplied to the reset drive transistor to hold a voltage corresponding to the threshold voltage in the pixel capacitor. The display device according to claim 2 . It consists of a pixel array part and a drive part that drives it,
The pixel array section includes row-like first scanning lines and second scanning lines, column-like signal lines, matrix-like pixels arranged at intersections thereof, power supply lines for supplying power to each pixel, and grounding With a line,
The driving unit sequentially supplies a first control signal to each first scanning line to scan the pixels line by line in a row unit, and sequentially outputs a second scanner to each second scanning line in accordance with the line sequential scanning. A second scanner for supplying a control signal, and a signal selector for supplying a video signal to a column-shaped signal line in accordance with the line sequential scanning,
The pixel includes a light emitting element, a sampling transistor, a drive transistor, a switching transistor, and a pixel capacitor.
The sampling transistor has a gate connected to the first scanning line, a source connected to the signal line, a drain connected to the gate of the drive transistor,
The drive transistor and the light emitting element are connected in series between the power line and the ground line to form a current path,
The switching transistor is inserted in the current path, and its gate is connected to the second scanning line,
The pixel capacitor is a display device connected between a source and a gate of the drive transistor,
The sampling transistor is turned on in response to the first control signal supplied from the first scanning line, samples the signal potential of the video signal supplied from the signal line, and holds it in the pixel capacitor,
The switching transistor is turned on in response to a second control signal supplied from the second scanning line to make the current path conductive.
The drive transistor causes a drive current to flow to the light emitting element through a current path placed in the conductive state in accordance with a signal potential held in the pixel capacitor,
The driving unit applies the first control signal to the first scanning line to turn on the sampling transistor to start sampling of the signal potential, and then the second control signal is applied to the second scanning line. The mobility of the drive transistor during the correction period from the first timing when the switching transistor is turned on to the second timing when the first control signal applied to the first scanning line is released and the sampling transistor is turned off To the signal potential held in the pixel capacitance,
When the sampling transistor is turned off at the second timing, the first scanner generates a first waveform that continues excessively falling after exceeding a predetermined level and then returning to the predetermined level and continuing flat. Then, the first control signal including the first waveform is supplied to the first scanning line, and the first control signal gradually falls in a process of propagating through the first scanning line, and then gently. When the signal potential of the video signal supplied to the signal line is high, the correction period is shortened while the signal potential is low while being applied to the gate of the sampling transistor in a declining second waveform. And the second timing is automatically adjusted so that the correction period becomes longer. The driving unit includes a power pulse generation circuit that generates a power pulse including the first waveform that is a source of the second waveform of the first control signal and supplies the power pulse to the first scanner.
The first scanner sequentially retrieves the first waveform from the power supply pulse, the display device according to claim 4, wherein the supply to the respective first scan line as the first control signal. Each pixel includes an additional switching transistor that resets the gate voltage of the drive transistor to a predetermined voltage above a threshold voltage prior to sampling the video signal;
Prior to sampling the video signal, the second scanner temporarily turns on the switching transistor via the second control line, and passes a drive current to the reset drive transistor to set the threshold voltage. The display device according to claim 4 , wherein a corresponding voltage is held in the pixel capacitor.

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