CN114758621B

CN114758621B - Single-path slope type analog pixel driving circuit and driving method thereof

Info

Publication number: CN114758621B
Application number: CN202210517656.5A
Authority: CN
Inventors: 代永平; 代玉; 张俊; 刘艳艳
Original assignee: Nankai University
Current assignee: Nankai University
Priority date: 2022-05-13
Filing date: 2022-05-13
Publication date: 2023-07-21
Anticipated expiration: 2042-05-13
Also published as: CN114758621A

Abstract

A single-path slope type analog pixel driving circuit and a driving method thereof belong to the silicon-based display chip circuit application field of integrated circuit technology. The circuit comprises a digital signal latch, a counter, an enabling digital signal comparator, a slope signal amplifier, a slope signal transmission gate, a pixel addressing storage circuit, an analog display amplifier, an analog display transmission gate, a pixel analog signal output electrode, a connected signal line and a driving method comprising four sections of wave-type slope signals, wherein the circuit has a digital-to-analog conversion function, the double-tube common drain amplifier configured for each column of display analog signal line structurally cuts off electric signal crosstalk among the display analog signal lines of each column, and the driving method of the circuit distributes the behaviors of addressing sampling analog signal level and the behavior of display driving output analog signal level in the same pixel circuit to occur in different time periods, so that the phenomenon of electric signal mutual interference caused by conflict between the two behaviors is avoided in time sequence.

Description

Single-path slope type analog pixel driving circuit and driving method thereof

Technical Field

The invention belongs to the application field of a silicon-based display chip circuit of an integrated circuit technology, and particularly relates to the field of a silicon-based display drive circuit of a single-path slope type analog pixel.

Background

The single crystal silicon planar device manufacturing technology is respectively combined with active display technology such as liquid crystal (LCD, liquidCrystalDisplay) technology, organic light emitting diode (OLED, organicLight-EmittingDiode) technology and the like or passive display technology to generate various silicon-based displays, such as silicon-liquid crystal-glass sandwich structure type device technology generated by combining with liquid crystal display technology. In practice, an electric field is established between the level on the pixel output electrode and the level on the liquid crystal pixel common electrode, so that the level output to the pixel output electrode by each pixel unit circuit on the silicon substrate is modulated, and the amplitude intensity (gray scale) of the reflected light by the liquid crystal material is controlled to realize image display. (Chris Chinnock, "Microdisplaysand ManufactionInformationInformationMatureAct SID2000" ("Information Display"), 2000, 9, P18).

Typically, the pixel cell circuit of the chip active addressing matrix is formed by a series connection of 1N-channel metal oxide semiconductor (NMOS) transistor and 1 capacitor (R.Ishii, S.Katayama, H.Oka, s.yamazaki, s.lino "U.Efron, I.David, V.Sinelnikov, B.Apter" ACMOS/LCOSImage TransceiverChipforSmartGoggleApplications ", IEEETRANSACTIONSONCIRCUITSAND SYSTEMSFORVIDEOTECHNOLOGY, volume 14, stage 2, 2004, 2 months, P269), with the gate of the NMOS transistor connected to the row scanner addressing signal output. However, when a single NMOS transistor transmits a high level, not only is there a threshold voltage loss, but also the transient characteristics of the transmission process are not ideal (Chen Guican, et al, CMOS integrated circuit design, university of western traffic publishers, 1999.9, P110).

Disclosure of Invention

The invention provides a single-channel slope type analog pixel driving circuit which is composed of a digital signal latch, a counter, an enabling digital signal comparator, a slope signal amplifier, a slope signal transmission gate, a pixel addressing storage circuit, an analog display amplifier, an analog display transmission gate, a pixel analog signal output electrode, a display digital signal input bus, a slope signal line, a slope bias voltage supply line, a comparator reset signal line, a row addressing signal line, a column display analog signal line, a pixel bias voltage supply line, a global display normal-phase signal line and a global display reverse-phase signal line.

The technical scheme of the invention is as follows:

the single-channel ramp type analog pixel driving circuit is composed of a digital signal latch, a counter, an enabling digital signal comparator, a ramp signal amplifier, a ramp signal transmission gate, a pixel addressing storage circuit, an analog display amplifier, an analog display transmission gate, a pixel output electrode circuit, a display digital signal input bus, a comparator reset signal line, a ramp bias voltage supply line, a row addressing signal line, a pixel bias voltage supply line, a global display normal phase signal line, a global display inversion signal line, a column display analog signal line, and is electrically connected in series to form a functional circuit, wherein the ramp signal line, the ramp signal amplifier, the ramp signal transmission gate, the column display analog signal line, the pixel addressing storage circuit, the analog display amplifier, the analog display transmission gate are electrically connected in series to process a ramp signal constructed by four-segment waveform connection, and the analog display transmission gate outputs a level signal to the pixel output electrode circuit, and the digital signal latch has the same bit number as the counter, and is further configured with: a 2 nd connection line, a 5 th connection line, a 6 th connection line, a reset connection line, a 1 st control line, a power supply line, a ground line, and the digital signal latch receives a multi-bit digital signal transmitted by the display digital signal input bus through the 2 nd connection line to store, and the enable digital signal comparator receives a multi-bit count digital signal transmitted by the counter through the 5 th connection line, receives a multi-bit store digital signal transmitted by the digital signal latch through the 6 th connection line, receives a reset level signal transmitted by the comparator reset signal line through the reset connection line, and transmits a control level signal to the ramp signal transmission gate through the 1 st control line;

Wherein the enable digital signal comparator is provided with a logic circuit for outputting a high level to the 1 st control line when a rising edge of an enable signal transmitted on the comparator reset signal line is triggered by the reset connection line, outputting a low level to the 1 st control line when a digital signal received from the digital signal latch through the 6 th connection line is compared with a digital signal received from the counter through the 5 th connection line, and outputting a low level to the 1 st control line when the two digital signals are identical,

the ramp signal amplifier is configured with a ramp amplifying bias end, a ramp amplifying input end and a ramp amplifying output end, the ramp signal transmission gate is configured with a ramp transmission control end, a ramp transmission input end and a ramp transmission output end, the pixel addressing storage circuit is configured with a pixel addressing control end, a pixel storage input end and a pixel storage output end, the analog display amplifier is configured with a display amplifying bias end, a display amplifying input end and a display amplifying output end, the analog display transmission gate is configured with a display transmission reverse phase control end, a display transmission normal phase control end, a display transmission input end and a display transmission output end, and the pixel output electrode circuit is configured with a pixel analog signal output electrode,

The slope signal amplifier is composed of one of a PMOS type double-tube common-drain amplifier adopting a P type amplifier bias end as the slope amplifying bias end, a P type amplifier input end as the slope amplifying input end and a P type amplifier output end as the slope amplifying output end, or an NMOS type double-tube common-drain amplifier adopting an N type amplifier bias end as the slope amplifying bias end, an N type amplifier input end as the slope amplifying input end and an N type amplifier output end as the slope amplifying output end, the slope amplifying bias end is connected with the slope bias voltage supply line, the slope amplifying input end is connected with the slope signal line,

wherein the PMOS type double-pipe common drain amplifier is composed of a 1-PMOS tube at least comprising a 1-PMOS grid electrode, a 1-PMOS source electrode and a 1-PMOS drain electrode, and a 2-PMOS tube at least comprising a 2-PMOS grid electrode, a 2-PMOS source electrode and a 2-PMOS drain electrode, and is characterized in that the 1-PMOS grid electrode serves as the bias end of the P type amplifier, the 2-PMOS grid electrode serves as the input end of the P type amplifier, the 1-PMOS drain electrode and the 2-PMOS source electrode are connected to form the output end of the P type amplifier, the 1-PMOS source electrode is connected to the power supply line, the 2-PMOS drain electrode is connected to the grounding line,

Wherein the NMOS type double-tube common drain amplifier is composed of a 1-NMOS tube at least comprising a 1-NMOS grid electrode, a 1-NMOS drain electrode and a 1-NMOS source electrode and a 2-NMOS tube at least comprising a 2-NMOS grid electrode, a 2-NMOS drain electrode and a 2-NMOS source electrode, and is characterized in that the 2-NMOS grid electrode serves as the bias end of the N type amplifier, the 1-NMOS grid electrode serves as the input end of the N type amplifier, the 2-NMOS drain electrode and the 1-NMOS source electrode are connected to form the output end of the N type amplifier, the 1-NMOS drain electrode is connected to the power supply line, the 2-NMOS source electrode is connected to the grounding line,

and the ramp signal transmission gate is composed of a 3-PMOS tube at least comprising a 3-PMOS grid electrode, a 3-PMOS drain electrode and a 3-PMOS source electrode, a 3-NMOS tube at least comprising a 3-NMOS grid electrode, a 3-NMOS drain electrode and a 3-NMOS source electrode, a 4-PMOS tube at least comprising a 4-PMOS grid electrode, a 4-PMOS drain electrode and a 4-PMOS source electrode, and a 4-NMOS tube at least comprising a 4-NMOS grid electrode, a 4-NMOS drain electrode and a 4-NMOS source electrode, and is also configured with: a power supply line, a ground line, and characterized in that the 4-NMOS gate, the 4-PMOS gate, and the 3-NMOS gate are connected to form the ramp transmission control terminal, and the 4-NMOS source, the 4-PMOS drain, and the 3-PMOS gate are connected to each other, and the 4-PMOS source is connected to the power supply line, and the 4-NMOS drain is connected to the ground line, the 3-PMOS drain, and the 3-NMOS source are connected to form the ramp transmission input terminal, the 3-PMOS source, and the 3-NMOS drain are connected to form the ramp transmission output terminal, and the ramp transmission input terminal is connected to the ramp amplification output terminal, and the ramp transmission output terminal is connected to the column display analog signal line,

And the pixel addressing storage circuit is composed of one of a PMOS type switch capacitor adopting a P type switch capacitor control end as the pixel addressing control end, a P type switch capacitor input end as the pixel storage input end, a P type switch capacitor output end as the pixel storage output end, or an NMOS type switch capacitor adopting an N type switch capacitor control end as the pixel addressing control end, an N type switch capacitor input end as the pixel storage input end and an N type switch capacitor output end as the pixel storage output end, and the pixel addressing control end is connected with the row addressing signal line, the pixel storage input end is connected with the column display analog signal line,

wherein the PMOS type switch capacitor is composed of a 6-PMOS tube at least comprising a 6-PMOS grid electrode, a 6-PMOS drain electrode and a 6-PMOS source electrode, and an MIM capacitor at least comprising an MIM capacitor upper polar plate and an MIM capacitor upper polar plate, and is characterized in that the 6-PMOS grid electrode is used as the P type switch capacitor control end, the 6-PMOS source electrode is used as the P type switch capacitor input end, the 6-PMOS drain electrode is connected with the MIM capacitor upper polar plate to form the P type switch capacitor output end, the MIM capacitor lower polar plate is connected to the grounding wire,

Wherein the NMOS type switch capacitor is composed of a 6-NMOS transistor at least comprising a 6-NMOS grid electrode, a 6-NMOS drain electrode and a 6-NMOS source electrode, and an MIM capacitor at least comprising an MIM capacitor upper polar plate and an MIM capacitor upper polar plate, and is characterized in that the 6-NMOS grid electrode is used as the N type switch capacitor control end, the 6-NMOS drain electrode is used as the N type switch capacitor input end, the 6-NMOS source electrode is connected with the MIM capacitor upper polar plate to form the N type switch capacitor output end, the MIM capacitor lower polar plate is connected to the grounding wire,

and the analog display amplifier is composed of one of a PMOS type double-tube common-drain amplifier using a P type amplifier bias terminal as the display amplification bias terminal, a P type amplifier input terminal as the display amplification input terminal, a P type amplifier output terminal as the display amplification output terminal, or an NMOS type double-tube common-drain amplifier using an N type amplifier bias terminal as the display amplification bias terminal, an N type amplifier input terminal as the display amplification input terminal, an N type amplifier output terminal as the display amplification output terminal, and the display amplification input terminal is connected with the pixel storage output terminal, the display amplification bias terminal is connected with the pixel bias voltage supply line,

The analog display transmission gate is composed of a 5-PMOS tube at least comprising a 5-PMOS grid electrode, a 5-PMOS drain electrode and a 5-PMOS source electrode, and a 5-NMOS tube at least comprising a 5-NMOS grid electrode, a 5-NMOS drain electrode and a 5-NMOS source electrode, and is characterized in that the 5-PMOS drain electrode and the 5-NMOS source electrode are connected to form the display transmission input end, the 5-NMOS drain electrode and the 5-PMOS source electrode are connected to form the display transmission output end, the 5-PMOS grid electrode serves as the display transmission inversion control end, the 5-NMOS grid electrode serves as the display transmission normal phase control end, the display transmission input end is connected with the display amplification output end, the display transmission normal phase control end is connected with the global display normal phase signal line, the display transmission inversion control end is connected with the global display inversion signal line,

and the pixel output electrode circuit is constructed of an output electrode parasitic capacitor formed between the pixel analog signal output electrode and a conductor which is close to the periphery but does not make contact and is connected to the ground line, and is characterized in that the pixel analog signal output electrode serves as one electrode plate of the output electrode parasitic capacitor, the ground line serves as the other electrode plate of the output electrode parasitic capacitor,

The pixel analog signal output electrode is connected with the display transmission output end;

the driving method of the single-path slope analog pixel driving circuit is that each display period in any two adjacent display periods consists of an addressing line period capable of enabling the pixel addressing storage circuit to generate an input path state and at least one display line period capable of always enabling the pixel addressing storage circuit to keep an input off state, the addressing line period is the same as the display line period in time, is connected with the display line period in time and is commonly called as a line period, and the slope signal amplifier is configured in an effective working state in each line period,

each line period is divided into four time periods of T1, T2, T3 and T4, and a slope signal formed by connecting four wave forms is configured, and the wave form is characterized in that the slope signal jumps from the highest level of the slope signal to the central level of the slope signal in the time period of T1, the slope signal is fixed to the central level of the slope signal in the time period of T2, the slope signal jumps from the central level of the slope signal to the lowest level of the slope signal in the time period of T3, and the slope signal starts to change incrementally from the lowest level of the slope signal until the highest level of the slope signal in the time period of T4;

First, in the address line period of the previous display period,

during the T1 period: the ramp signal transmitted on the ramp signal line jumps from the highest level to a state with a fixed level in the middle, a rising edge of the pulse wave signal transmitted on the comparator reset signal line triggers the enabling digital signal comparator to output a high level, the ramp signal transmission gate is in a channel state caused by the ramp transmission control end, the level transmitted on the column display analog signal line is enabled to follow the level state transmitted on the ramp signal line in real time through the ramp signal amplifier and the ramp signal transmission gate, the invalid level transmitted on the row addressing signal line is enabled to cause the pixel addressing storage circuit and the column display analog signal line to be in an off state so as to continuously store the level stored at the end of the last row period, the level transmitted on the pixel bias voltage supply line is enabled to configure the analog display amplifier into an effective working state, the pulse wave signal transmitted on the global display inverting signal line and the pulse wave signal transmitted on the global display positive phase signal line are configured into an off state, and the pixel addressing storage circuit and the pixel bias voltage supply line are enabled to continuously store the level at the end of the parasitic electrode;

And during the T2 period: the ramp signal transmitted on the ramp signal line keeps a fixed level state in the middle, the pulse wave signal received by the ramp transmission control end keeps a level state of a previous time period, the level transmitted on the column display analog signal line keeps following the level state transmitted on the ramp signal line in real time through the ramp signal amplifier and the ramp signal transmission gate, the invalid level keeps being transmitted on the row addressing signal line, the pixel addressing storage circuit and the column display analog signal line are in an open circuit state and keep storing the level stored in the previous time period, the analog display amplifier keeps keeping an effective working state entered in the previous time period, and the pulse wave signal transmitted on the global display positive signal line and the pulse wave signal level transmitted on the global display inverted signal line change to enable the analog display transmission gate to be in a channel state, and the level stored by the pixel addressing storage circuit is driven and enhanced in real time through the analog display amplifier and kept in the parasitic capacitor of the output electrode;

And during the T3 period: the ramp signal transmitted on the ramp signal line jumps from a certain fixed level to the lowest level state of the ramp signal, the pulse wave signal received by the ramp transmission control end keeps the level state of the last time period, the level transmitted on the column display analog signal line keeps following the level state transmitted on the ramp signal line in real time through the ramp signal amplifier and the ramp signal transmission gate, the line addressing signal line changes to a transmission effective level, the pixel addressing storage circuit and the column display analog signal line enter a channel state, the analog signal transmitted on the column display analog signal line is stored in the pixel addressing storage circuit in real time, the level of the pulse wave signal transmitted on the global display positive signal line and the level of the pulse wave signal transmitted on the global display inverted signal line change again, the analog signal output on the pixel analog signal output electrode keeps the level state of the last time period, and the level transmitted on the pixel bias voltage supply line changes to configure the analog display amplifier to be in an invalid working state;

And during the T4 period: the counter is reset to zero to start counting at the beginning, a ramp signal transmitted on the ramp signal line is synchronously and incrementally changed to the highest level along with the counting speed of the counter from the lowest level, a pulse wave signal received by the ramp transmission control end continues to keep the level state of the last time period, the level transmitted on the column display analog signal line continues to follow the level state transmitted on the ramp signal line in real time through the ramp signal amplifier and the ramp signal transmission gate, when the number generated by the counter is equal to the number stored by the digital signal latch, the digital signal comparator is triggered to enable the digital signal comparator to output a low level to cause the ramp signal transmission gate to be turned off, the level transmitted on the column display analog signal line does not follow the level change transmitted on the ramp signal line in real time any more until the ramp signal transmission gate is in a fixed level, the pixel addressing storage circuit continues to keep the input path state, the analog signal transmitted on the column display analog signal line drives the analog signal at the pixel storage output end to update, and when the counter generates a number equal to the number stored by the digital signal latch, the digital signal comparator is triggered to output a low level, the analog signal is also kept to reach the full level, the analog signal is continuously in the state, the analog signal transmission gate continues to keep the analog signal output state, and the analog signal is continuously in a state is continuously turned off, and the analog signal is continuously kept at the full level, the analog signal is continuously keeps the analog signal is in the state, and the analog signal is continuously in a state;

Then, in the display line period of the previous display period,

four time periods of T1, T2, T3, T4: the ramp signal transmitted on the ramp signal line, the pulse wave signal transmitted on the comparator reset signal line and the pulse wave signal received by the ramp transmission control end in the first three time periods keep the level state of the last time period, so that the level transmitted on the column display analog signal line keeps following the level state transmitted on the ramp signal line in real time through the ramp signal amplifier and the ramp signal transmission gate, the line addressing signal line changes to a transmission invalid level, so that the pixel addressing storage circuit and the column display analog signal line keep an open circuit state, so that the pixel addressing storage circuit keeps keeping the level state of the last line period,

and the pulse wave signal transmitted on the global display inversion signal line and the pulse wave signal transmitted on the global display positive phase signal line first configure the analog display transfer gate to an off state during a period of T1 to cause the analog signal output on the pixel analog signal output electrode to continue to be in a level state for a period of time, then configure the analog display transfer gate to enter a pass state during a period of T2 and the analog display amplifier to be in an active operating state to cause the level output by the pixel addressing storage circuit to drive the pixel analog signal output electrode to be updated and held at the output electrode parasitic capacitor in real time,

And in a period of time T4 when the number generated by the counter is equal to the number stored by the digital signal latch, causing the ramp signal transmission gate to enter an off state so that the analog signal transmitted on the column display analog signal line no longer follows the ramp signal change transmitted on the ramp signal line in real time and remains at a fixed level until the ramp signal transmission gate is in a state of being in a path again, and when terminated, the ramp signal transmitted on the ramp signal line is incremented to a highest level and the counter also counts to reach a full value;

then, in the address line period of the latter display period,

four time periods of T1, T2, T3, T4: the ramp signal transmitted on the ramp signal line, the pulse wave signal transmitted on the comparator reset signal line, the pulse wave signal transmitted on the pixel bias voltage supply line, the pulse wave signal transmitted on the global display inversion signal line, the pulse wave signal transmitted on the global display positive phase signal line repeatedly transmit the waveform state transmitted in the previous row period, the pulse wave signal transmitted on the row address signal line repeatedly transmit the waveform state transmitted in the address row period of the previous display period, and the pulse wave signal received by the ramp transmission control terminal continues to maintain the level state of the previous period in the previous three periods, so that the level transmitted on the column display analog signal line continues to follow the level state transmitted on the ramp signal line in real time through the ramp signal amplifier and the ramp signal transmission gate,

And during the time periods T1, T2: the pixel addressing storage circuit is configured to continue to maintain an input off state such that the level state stored in the previous period continues to be stored and output, and to drive the pixel analog signal output electrode in real time to strengthen the level state during a T2 period when the analog display amplifier is in an active operation state and the analog display transfer gate is in a pass state,

and when the number generated by the counter is equal to the number stored in the digital signal latch, the ramp signal transmission gate is caused to enter an off state so that the analog signal transmitted on the column display analog signal line is no longer kept at a fixed level in real time following the change of the ramp signal transmitted on the ramp signal line, and the pixel addressing storage circuit enters a channel state after the pulse wave signal transmitted on the row addressing signal line jumps in opposite phase so as to store the analog signal transmitted on the column display analog signal line in real time with an update level;

then, in the display line period of the latter display period,

the ramp signal transmitted on the ramp signal line, the pulse wave signal transmitted on the comparator reset signal line, the pulse wave signal transmitted on the pixel bias voltage supply line, the pulse wave signal transmitted on the global display inversion signal line, the pulse wave signal transmitted on the global display positive phase signal line are all repeatedly transmitted in the waveform state in the previous row period,

And when the number generated by the counter is equal to the number stored by the digital signal latch will cause the ramp signal transmission gate to enter an off state such that the analog signal transmitted on the column display analog signal line no longer follows the ramp signal change transmitted on the ramp signal line in real time but remains at a fixed level until the ramp signal transmission gate is again in a pass state,

and the change to a transmission inactive level on the row address signal lines causes the pixel address memory circuit to remain in an off state with the column display analog signal lines such that the pixel address memory circuit continues to remain in a level state for the previous row period,

when the analog display amplifier is in an effective working state and the analog display transmission gate is in a channel state, the level stored by the pixel addressing storage circuit drives the pixel analog signal output electrode in real time to update the level state;

the driving method further includes: four time periods of each row period T1, T2, T3, T4 are sequentially performed and then cycled back and forth, each display period may output an analog level at the pixel analog signal output electrode corresponding to the number stored by the digital signal latch during the row address period of the current display period.

The beneficial effects of the invention are as follows:

compared with the prior art, the invention has two advantages: the driving method comprises four-section wave type slope signals and a time-section sequential circulation method thereof, and the phenomenon of signal crosstalk between addressing sampling behaviors and display behaviors in the same pixel circuit is avoided.

Drawings

Fig. 1 is a schematic diagram of a single-pass ramp type analog pixel driving circuit, in which 1: control line 1, 2: 2 nd connecting wire, 3: ramp signal amplifier, 4: ramp amplification bias terminal, 5: 5 th connecting wire, 6: 6 th connecting wire, 7: ramp amplification output, 8: counter, 9: reset connection line, 11: digital signal latch, 12: enabling the digital signal comparator, 13: ramp amplification input, 15: ramp transmission control end, 16: display digital signal input bus, 17: ramp signal line, 18: ramp bias voltage supply line, 19: comparator reset signal line, 21: display amplification output, 22: display transmission input, 23: analog display transmission gate, 24: row address signal line, 25: display transmission output terminal, 26: pixel analog signal output electrode, 28: pixel bias voltage supply line, 29: global display positive phase signal line, 30: pixel output electrode circuit, 31: global display inversion signal line, 32: display transmission inversion control terminal, 34: display transmission normal phase control terminal, 37: display magnification bias terminal, 39: display magnification input, 42: pixel storage output, 43: pixel storage input, 44: columns show analog signal lines, 46: pixel addressing memory circuit, 47: pixel addressing control terminal, 49: analog display amplifier, 51: ramp transmission output, 52: ramp signal transmission gate, 53: a ramp transmission input;

Fig. 2 is a schematic diagram of a PMOS type dual-transistor common-drain amplifier circuit, in which 77: power supply line, 85: 1 st-PMOS gate, 86: 1 st-PMOS source, 87: 1 st-PMOS drain, 88: 1 st-PMOS tube, 93: 2 nd-PMOS tube, 94: 2 nd-PMOS gate, 95: 2 nd-PMOS source, 96: 2 nd-PMOS drain, 97: p-type amplifier input, 98: p-type amplifier output, 99: p-type amplifier bias terminal, 135: a ground wire;

fig. 3 is a schematic diagram of an NMOS dual-transistor common-drain amplifier circuit, in which 77: power supply line, 101: 1 st-NMOS tube, 102: 1 st-NMOS gate, 103: 1 st-NMOS drain, 104: 1 st-NMOS source, 105: 2 nd-NMOS tube, 106: 2-NMOS gate, 107: 2-NMOS drain, 108: 2-NMOS source, 109: n-type amplifier bias terminal, 110: n-type amplifier input, 111: n-type amplifier output, 135: a ground wire;

fig. 4 is a schematic diagram of a ramp signal transmission gate, wherein 15: ramp transmission control end, 51: ramp transmission output, 53: ramp transmission input, 61: 3 rd-PMOS gate, 62: 3 rd-PMOS drain, 63: 3 rd PMOS source, 64: 3 rd-PMOS tube, 65: 3 rd-NMOS source, 66: 3 rd NMOS gate, 67: 3-NMOS drain, 68: 3-NMOS tube, 73: 4-PMOS tube, 74: 4 th-PMOS gate, 75: 4 th-PMOS source, 76: 4 th-PMOS drain, 77: power supply line, 81: 4 th-NMOS gate, 82: 4 th-NMOS source, 83: 4-NMOS tube, 84: 4 th-NMOS drain, 135: a ground wire;

Fig. 5 is a schematic diagram of a PMOS switched capacitor circuit, wherein 112: p-type switched capacitor control terminal, 113: MIM capacitor lower plate, 115: MIM capacitor, 116: MIM capacitor top plate, 117: p-type switched capacitor input, 118: p-type switched capacitor output, 121: 6 th-PMOS source, 123: 6 th-PMOS gate, 124: 6 th-PMOS drain, 125: 6 th-PMOS tube, 135: a ground wire;

fig. 6 is a schematic diagram of an NMOS switched capacitor circuit, wherein 113: MIM capacitor lower plate, 114: n-type switched capacitor control terminal, 115: MIM capacitor, 116: MIM capacitor top plate, 119: n-type switched capacitor input, 120: n-switched capacitor output, 126: 6-NMOS drain, 127: 6 th-NMOS gate, 128: 6 th-NMOS source, 129: 6 th-NMOS tube, 135: a ground wire;

fig. 7 is a schematic diagram of a transmission gate circuit for analog display, wherein 22: display transmission input, 25: display transmission output terminal, 32: display transmission inversion control terminal, 34: display transmission normal phase control terminal, 141: 5 th-PMOS gate, 142: 5 th-PMOS drain, 143: 5 th-PMOS source, 145: 5 th-PMOS tube, 146: 5 th-NMOS source, 147: 5 th-NMOS gate, 148: 5 th-NMOS drain, 149: a 5 th-NMOS tube;

Fig. 8 is a schematic diagram of a pixel output electrode circuit, wherein 20: output electrode parasitic capacitor, 26: pixel analog signal output electrode, 135: a ground wire;

fig. 9 is a ramp signal waveform diagram of one of the application scenarios of the single-path ramp type analog pixel driving circuit, wherein:

sramp: the ramp signal transmitted on the ramp signal line 17,

v1: the lowest level of the ramp signal is set,

v2: the center level of the ramp signal,

v3: the highest level of the ramp signal is set,

VD: the power supply line 77 is at a level,

VG: the ground line 135 level;

fig. 10 is a summary of signal waveforms of one driving application scenario of the single-path ramp type analog pixel driving circuit, wherein:

sramp: the ramp signal transmitted on the ramp signal line 17,

v1: the lowest level of the ramp signal is set,

v2: the center level of the ramp signal,

v3: the highest level of the ramp signal is set,

vbn: the ramp biases a fixed level transmitted on the voltage supply line 18,

vbp: the ramp biases a fixed level transmitted on the voltage supply line 18,

RST: the comparator resets the pulse wave signal transmitted on the signal line 19,

ENC: the ramp signal transmission gate 52 enables the pulse wave signal received at the control terminal,

SDi: the columns show the analog signals transmitted on analog signal line 44,

sgp: the positive pulse wave signal transmitted on the row address signal line 24,

sgn: the negative pulse wave signal transmitted on the row address signal line 24,

vsc: the pixel stores the analog signal output by the output 42,

vbp2: the P-pulse wave transmitted on the pixel bias voltage supply line 28,

vbn2: the N pulse wave transmitted on the pixel bias voltage supply line 28,

SP: the global displays the P-pulse wave signal transmitted on the inversion signal line 31,

SN: the global displays the N-pulse wave signal transmitted on the positive phase signal line 29,

vout: analog signals output on the pixel analog signal output electrodes 26;

Detailed Description

First, the structure of the single-path ramp type analog pixel circuit according to the present invention will be described in detail with reference to fig. 1, 2, 3, 4, 5, 6, 7, and 8:

the single-channel ramp type analog pixel driving circuit is composed of a digital signal latch 11, a counter 8, an enabling digital signal comparator 12, a ramp signal amplifier 3, a ramp signal transmission gate 52, a pixel addressing storage circuit 46, an analog display amplifier 49, an analog display transmission gate 23, a pixel output electrode circuit 30, and a display digital signal input bus 16, a comparator reset signal line 19, a ramp signal line 17, a ramp bias voltage supply line 18, a row addressing signal line 24, a pixel bias voltage supply line 28, a global display positive phase signal line 29, a global display inversion signal line 31, a column display analog signal line 44, and is provided with the ramp signal line 17, the ramp signal amplifier 3, the ramp signal transmission gate 52, the column display analog signal line 44, the pixel addressing storage circuit 46, the analog display amplifier 49, the analog display transmission gate 23, which are electrically connected in series, form a functional circuit to process a ramp signal constructed by four-segment waveforms, and the analog display transmission gate 23 outputs a level signal to the pixel output electrode circuit 30, and the digital signal 11 has the same bit number as the counter 8, and the configuration is also provided with: a 2 nd connection line 2, a 5 th connection line 5, a 6 th connection line 6, a reset connection line 9, a 1 st control line 1, a power supply line 77, a ground line 135, the digital signal latch 11 being connected to the display digital signal input bus 16 through the 2 nd connection line 2 and receiving and storing a multi-bit digital signal transmitted by the display digital signal input bus 16, and the enable digital signal comparator 12 being connected to the counter 8 through the 5 th connection line 5 and receiving a multi-bit count digital signal transmitted by the counter 8, being connected to the digital signal latch 11 through the 6 th connection line 6 and receiving a multi-bit store digital signal transmitted by the digital signal latch 11, being connected to the comparator reset signal line 19 through the reset connection line 9 and receiving a reset level signal transmitted by the comparator reset signal line 19, being connected to the ramp signal transmission gate 52 through the 1 st control line 1 and transmitting a control level signal to the ramp signal transmission gate 52;

And as schematically shown in the one-way ramp analog pixel driving circuit of fig. 1, the enable digital signal comparator 12 is provided with a logic circuit for outputting a high level to the 1 st control line 1 when a rising edge of an enable signal transmitted through the comparator reset signal line 19 is triggered by the reset connection line 9, outputting a low level to the 1 st control line 1 when a digital signal received through the 6 th connection line 6 from the digital signal latch 11 is compared with a digital signal received through the 5 th connection line 5 from the counter 8 and when the two digital signals are identical,

wherein the ramp signal amplifier 3 is configured with a ramp amplification bias terminal 4, a ramp amplification input terminal 13, a ramp amplification output terminal 7, and the ramp signal transmission gate 52 is configured with a ramp transmission control terminal 15, a ramp transmission input terminal 53, a ramp transmission output terminal 51, and the pixel addressing storage circuit 46 is configured with a pixel addressing control terminal 47, a pixel storage input terminal 43, a pixel storage output terminal 42, and the analog display amplifier 49 is configured with a display amplification bias terminal 37, a display amplification input terminal 39, a display amplification output terminal 21, and the analog display transmission gate 23 is configured with a display transmission inversion control terminal 32, a display transmission normal phase control terminal 34, a display transmission input terminal 22, a display transmission output terminal 25, and the pixel output electrode circuit 30 is configured with a pixel analog signal output electrode 26 and the output electrode parasitic capacitor 20 formed between conductors thereof close to the periphery but not in contact and connected to the ground line 135,

Wherein the ramp signal amplifier 3 is composed of one of a PMOS type double-tube common-drain amplifier employing a P-type amplifier bias terminal 99 as the ramp amplification bias terminal 4, a P-type amplifier input terminal 97 as the ramp amplification input terminal 13, a P-type amplifier output terminal 98 as the ramp amplification output terminal 7, or an NMOS type double-tube common-drain amplifier employing an N-type amplifier bias terminal 109 as the ramp amplification bias terminal 4, an N-type amplifier input terminal 110 as the ramp amplification input terminal 13, an N-type amplifier output terminal 111 as the ramp amplification output terminal 7, and the ramp amplification bias terminal 4 is connected to the ramp bias voltage supply line 18, the ramp amplification input terminal 13 is connected to the ramp signal line 17,

and as schematically illustrated in the PMOS type double-transistor common-drain amplifier circuit of fig. 2, the PMOS type double-transistor common-drain amplifier is composed of a 1 st-PMOS transistor 88 including at least a 1 st-PMOS gate 85, a 1 st-PMOS source 86, a 1 st-PMOS drain 87, and a 2 nd-PMOS transistor 93 including at least a 2 nd-PMOS gate 94, a 2 nd-PMOS source 95, a 2 nd-PMOS drain 96, and is characterized in that the 1 st-PMOS gate 85 serves as the P-type amplifier bias terminal 99, the 2 nd-PMOS gate 94 serves as the P-type amplifier input terminal 97, the 1 st-PMOS drain 87 is connected with the 2 nd-PMOS source 95 to form the P-type amplifier output terminal 98, the 1 st-PMOS source 86 is connected to the power supply line 77, the 2 nd-PMOS drain 96 is connected to the ground 135,

And as schematically illustrated in the NMOS type double-transistor common-drain amplifier circuit of fig. 3, the NMOS type double-transistor common-drain amplifier is composed of a 1 st-NMOS transistor 101 including at least a 1 st-NMOS gate 102, a 1 st-NMOS drain 103, a 1 st-NMOS source 104, and a 2 nd-NMOS transistor 105 including at least a 2 nd-NMOS gate 106, a 2 nd-NMOS drain 107, a 2 nd-NMOS source 108, and is characterized in that the 2 nd-NMOS gate 106 serves as the N-type amplifier bias terminal 109, the 1 st-NMOS gate 102 serves as the N-type amplifier input terminal 110, the 2 nd-NMOS drain 107 is connected with the 1 st-NMOS source 104 to form the N-type amplifier output terminal 111, the 1 st-NMOS drain 103 is connected to the power supply line 77, the 2 nd-NMOS source 108 is connected to the ground line 135,

and as schematically illustrated in the ramp signal transmission gate circuit of fig. 4, the ramp signal transmission gate 52 in fig. 1 is composed of a 3-PMOS transistor 64 including at least a 3-PMOS gate 61, a 3-PMOS drain 62, a 3-PMOS source 63, a 3-NMOS transistor 68 including at least a 3-NMOS gate 66, a 3-NMOS drain 67, a 3-NMOS source 65, a 4-PMOS transistor 73 including at least a 4-PMOS gate 74, a 4-PMOS drain 76, a 4-PMOS source 75, and a 4-NMOS transistor 83 including at least a 4-NMOS gate 81, a 4-NMOS drain 84, a 4-NMOS source 82, and is further configured with: a power supply line 77, a ground line 135, and characterized in that the 4-th NMOS gate 81, the 4-th PMOS gate 74, the 3-th NMOS gate 66 are connected to form the ramp transmission control terminal 15, and the 4-th NMOS source 82, the 4-th PMOS drain 76, the 3-th PMOS gate 61 are connected to each other, and the 4-th PMOS source 75 is connected to the power supply line 77 and the 4-th NMOS drain 84 is connected to the ground line 135, the 3-th PMOS drain 62, and the 3-th NMOS source 65 are connected to form the ramp transmission input terminal 53, the 3-th PMOS source 63, and the 3-th NMOS drain 67 are connected to form the ramp transmission output terminal 51,

And the ramp transmission input 53 is connected to the ramp amplification output 7 and the ramp transmission output 51 is connected to the column display analog signal line 44 as shown in figure 1,

and the pixel addressing storage circuit 46 is comprised of one of PMOS type switched capacitors employing P-type switched capacitor control terminal 112 as the pixel addressing control terminal 47, P-type switched capacitor input terminal 117 as the pixel storage input terminal 43, P-type switched capacitor output terminal 118 as the pixel storage output terminal 42, or NMOS type switched capacitors employing N-type switched capacitor control terminal 114 as the pixel addressing control terminal 47, N-type switched capacitor input terminal 119 as the pixel storage input terminal 43, N-type switched capacitor output terminal 120 as the pixel storage output terminal 42, with the pixel addressing control terminal 47 connected to the row addressing signal line 24, the pixel storage input terminal 43 connected to the column display analog signal line 44,

and as schematically illustrated in the PMOS-type switched capacitor circuit of fig. 5, the PMOS-type switched capacitor is formed by a 6-PMOS transistor 125 including at least a 6-PMOS gate 123, a 6-PMOS drain 124, and a 6-PMOS source 121, and a MIM capacitor 115 including at least a MIM capacitor upper plate 116 and a MIM capacitor lower plate 113, and is characterized in that the 6-PMOS gate 123 serves as the P-type switched capacitor control terminal 112, the 6-PMOS source 121 serves as the P-type switched capacitor input terminal 117, the 6-PMOS drain 124 is connected to the MIM capacitor upper plate 116 to serve as the P-type switched capacitor output terminal 118, the capacitor lower plate is connected to the ground line 135,

And as schematically illustrated in the NMOS-type switched capacitor circuit of fig. 6, the NMOS-type switched capacitor is comprised of a 6-NMOS transistor 129 comprising at least a 6-NMOS gate 127, a 6-NMOS drain 126, a 6-NMOS source 128, and a MIM capacitor 115 comprising at least a MIM capacitor upper plate 116, a MIM capacitor lower plate 113, and is characterized in that the 6-NMOS gate 127 serves as the N-type switched capacitor control terminal 114, the 6-NMOS drain 126 serves as the N-type switched capacitor input terminal 119, the 6-NMOS source 128 is connected to the MIM capacitor upper plate 116 as the N-type switched capacitor output terminal 120, the capacitor lower plate is connected to the ground line 135,

and the analog display amplifier 49 is composed of one of a PMOS type double-tube common drain amplifier employing a P-type amplifier bias terminal 99 as the display amplification bias terminal 37, a P-type amplifier input terminal 97 as the display amplification input terminal 39, a P-type amplifier output terminal 98 as the display amplification output terminal 21, or an NMOS type double-tube common drain amplifier employing an N-type amplifier bias terminal 109 as the display amplification bias terminal 37, an N-type amplifier input terminal 110 as the display amplification input terminal 39, an N-type amplifier output terminal 111 as the display amplification output terminal 21, and the display amplification input terminal 39 is connected to the pixel storage output terminal 42, the display amplification bias terminal 37 is connected to the pixel bias voltage supply line 28,

And as schematically illustrated in the schematic diagram of the analog display transmission gate circuit of fig. 7, the analog display transmission gate 23 in fig. 1 is composed of a 5-PMOS transistor 145 including at least a 5-PMOS gate 141, a 5-PMOS drain 142, a 5-PMOS source 143, and a 5-NMOS transistor 149 including at least a 5-NMOS gate 147, a 5-NMOS drain 148, and a 5-NMOS source 146, and is characterized in that the 5-PMOS drain 142 and the 5-NMOS source 146 are connected to form the display transmission input terminal 22, the 5-NMOS drain 148 and the 5-PMOS source 143 are connected to form the display transmission output terminal 25, the 5-PMOS gate 141 serves as the display transmission inversion control terminal 32, the 5-NMOS gate 147 serves as the display transmission normal phase control terminal 34,

and the display transfer input 22 is connected to the display amplification output 21, the display transfer normal phase control terminal 34 is connected to the global display normal phase signal line 29, the display transfer inversion control terminal 32 is connected to the global display inversion signal line 31 as shown in fig. 1,

and as schematically illustrated in the schematic diagram of the pixel output electrode circuit of fig. 8, the pixel output electrode circuit 30 in fig. 1 is constructed of an output electrode parasitic capacitor 20 formed between the pixel analog signal output electrode 26 and a conductor which is close to the periphery but does not make contact and is connected to the ground line 135, and is characterized in that the pixel analog signal output electrode 26 serves as one electrode plate of the output electrode parasitic capacitor 20, the ground line 135 serves as the other electrode plate of the output electrode parasitic capacitor 20,

And the pixel analog signal output electrode 26 is connected to the display transmission output terminal 25 as shown in fig. 1;

the driving method of the single-path ramp type analog pixel driving circuit according to the present invention will be further described with reference to fig. 9 and 10, wherein the high level has the same voltage value as the power supply line 77 level VD, and the low level has the same voltage value as the ground line 135 level VG:

each of any two adjacent display periods is constituted by an address line period enabling the pixel address memory circuit 46 to assume an input on state and at least one display line period always enabling the pixel address memory circuit 46 to remain in an input off state, and the address line period is the same as the display line period in duration, is connected in time and is collectively referred to as a line period, and the ramp signal amplifier 3 is configured in an active operation state in each line period,

The waveform diagram of the four-segment waveform ramp signal of one of the application scenarios of the single-path ramp type analog pixel driving circuit as shown in fig. 9 (the hatched portion in the figure represents omitted waveforms),

wherein the former display period is composed of an addressing line period TC11 and at least one display line period TP11, the latter display period is composed of an addressing line period TC21 and at least one display line period TP21, and each line period is composed of a ramp signal Vramp from a ramp signal highest level V3 to a ramp signal center level V2 in a period T1, a ramp signal Vramp is fixed to the ramp signal center level V2 in a period T2, a ramp signal Vramp from the ramp signal center level V2 to a ramp signal lowest level V1 in a period T3, and a ramp signal Vramp is incrementally changed from the ramp signal lowest level V1 to the ramp signal highest level V3 in a period T4;

the waveform diagram of the driving signal of one of the application scenarios of the single-path ramp type analog pixel driving circuit is summarized and illustrated as shown in fig. 10 (the hatched portion in the figure represents omitted waveforms),

first, in each row period, if the ramp signal amplifier 3 employs a PMOS type dual-transistor common-drain amplifier, the fixed level Vbn transmitted on the ramp bias voltage supply line 18 is characterized by being lower than the level VD of the power supply line 77, and the 1 st-PMOS gate 85 is inputted to enable the 1 st-PMOS transistor 88 to enter a saturation region to configure the ramp signal amplifier 3 into an active operation state, and if the ramp signal amplifier 3 employs an NMOS type dual-transistor common-drain amplifier, the fixed level Vbp transmitted on the ramp bias voltage supply line 18 is characterized by being higher than the level VG of the ground line 135, and the 2 nd-NMOS gate 106 is inputted to enable the 2 nd-NMOS transistor 105 to enter a saturation region to configure the ramp signal amplifier 3 into an active operation state,

Meanwhile, in the address line period TC11 of the previous display period,

during the T1 period: the ramp signal Sramp transmitted on the ramp signal line 17 jumps from the ramp signal highest level V3 to the ramp signal center level V2,

and the rising edge signal, which is initially the pulse wave signal RST transmitted on the comparator reset signal line 19 is at a low level and is identified by the ellipse 8a after the ramp signal Sramp transmitted on the ramp signal line 17 is at the ramp signal center level V2, triggers the enabling digital signal comparator 12 to output a high level as indicated by the unidirectional arrow line 9b so that the pulse wave signal ENC received by the ramp transmission control terminal 15 is at a high level as indicated by the ellipse 9 and thus the 3 rd NMOS gate 66 is connected to a high level, the 3 rd PMOS gate 61 is connected to a low level and the ramp signal transmission gate 52 is caused to be in a pass state so that the analog signal SDi transmitted on the column display analog signal line 44 follows the electrical signal of the ramp signal Sramp transmitted on the ramp signal line 17 identified by the ellipse 10 to generate the electrical signal portion identified by the ellipse 11a as indicated by the unidirectional arrow line 10b,

and if the pixel addressing storage circuit 46 employs the NMOS type switch capacitance then the transmission of a positive pulse wave signal Sgp on the row addressing signal line 24 will input to the 6-NMOS gate 127 with the 6-NMOS transistor 129 turned off and causing the MIM capacitor 115 and the column display analog signal line 44 to be in an off state, and if the pixel addressing storage circuit 46 employs the PMOS type switch capacitance then the transmission of a negative pulse wave signal Sgn on the row addressing signal line 24 will input to the 6-PMOS gate 123 with the 6-PMOS transistor 125 turned off and causing the MIM capacitor 115 and the column display analog signal line 44 to be in an off state will result in the pixel addressing storage circuit 46 entering an on-state and causing the level state of the pixel storage output 42 analog signal Vsc to continue to be stored and output as part of the oval 14a at the end of the last row period,

And if the analog display amplifier 49 employs a PMOS type dual-transistor common-drain amplifier, the P pulse Vbp2 level transmitted on the pixel bias voltage supply line 28 jumps from a high voltage to a level identified by the ellipse 16a and can cause the analog display amplifier 49 to enter a saturation region due to the 1 st-PMOS gate 85 being connected lower than the power supply line 77 level VD, thereby enabling an effective operation state, or if the analog display amplifier 49 employs an NMOS type dual-transistor common-drain amplifier, the N pulse Vbn2 level transmitted on the pixel bias voltage supply line 28 jumps from a low level to a level identified by the ellipse 17a, thereby enabling the analog display amplifier 49 to enter a saturation region due to the 2 nd-NMOS gate 106 being connected higher than the ground line 135 level VG, thereby enabling an effective operation state, with the result that the level signal stored by the pixel address storage circuit 46 in the last period is transmitted to the input terminal 22 through the analog display amplifier 49,

and the P pulse wave signal SP transmitted on the global display inversion signal line 31 is at a high level so that the 5-PMOS gate 141 is connected to a high level to cause the 5-PMOS transistor 145 to be turned off, and at the same time, the N pulse wave signal SN transmitted on the global display positive phase signal line 29 is at a low level so that the 5-NMOS gate 147 is connected to a low level to cause the 5-NMOS transistor 149 to be turned off to cause the analog display transmission gate 23 to be in an open state and also cause the analog signal Vout output on the pixel analog signal output electrode 26 to continue to be kept in the level state of the output electrode parasitic capacitor 20 at the end of the last line period, such as an oval 6 mark portion;

And during the T2 period: the level of the ramp signal Sramp transmitted on the ramp signal line 17 continues to be fixedly held at the ramp signal center level V2,

and the pulse wave signal RST transmitted on the comparator reset signal line 19 and the pulse wave signal ENC received by the ramp transmission control terminal 15 are kept in the level state of the previous period, so that the analog signal SDi transmitted on the column display analog signal line 44 is kept following the ramp signal Sramp transmitted on the ramp signal line 17 to generate the corresponding level state,

and the pixel-addressing storage circuit 46 continues to maintain the input-off state because the pulse wave signal transmitted on the row-addressing signal line 24 maintains the level state for the previous period of time and causes the level state of the analog signal Vsc of the pixel-storage output 42 identified by the oval 14a in the previous period of time to continue to be stored and output as indicated by the oval 15a as indicated by the unidirectional arrow line 11b,

and the analog display amplifier 49 continues to remain active because the analog signal transmitted on the pixel bias voltage supply line 28 remains in the level state for the previous period of time,

and the analog display transmission gate 23 is turned on by the P pulse signal SP transmitted on the global display inversion signal line 31 being turned low so that the 5-PMOS gate 141 is turned on, and at the same time, the N pulse signal SN transmitted on the global display positive phase signal line 29 is turned high so that the 5-NMOS gate 147 is turned on to be in a pass state, and also the portion of the analog signal Vsc level of the pixel storage output terminal 42 identified by the ellipse 15a is caused to be turned on by the 5-NMOS gate 147 to be in a pass state, as indicated by the unidirectional arrow line 12b, so that the analog signal Vout generated by the pixel analog signal output electrode 26 is driven in real time by the analog display amplifier 49 and is maintained in the level state of the output electrode parasitic capacitor 20 as indicated by the ellipse 18a to strengthen the level state of the portion identified by the ellipse 6;

And during the T3 period: the level of the ramp signal Sramp transmitted on the ramp signal line 17 jumps from the ramp signal center level V2 to the ramp signal minimum level V1,

and the pulse wave signal RST transmitted on the comparator reset signal line 19 and the pulse wave signal ENC received by the ramp transmission control terminal 15 are kept in the level state for the previous period of time, so that the analog signal SDi transmitted on the column display analog signal line 44 continues to follow the portion of the ramp signal Sramp transmitted on the ramp signal line 17 identified by the ellipse 7 to generate the electrical signal portion identified by the ellipse 22a as indicated by the unidirectional arrow line 8b,

and if the pixel addressing storage circuit 46 employs the NMOS type switch capacitance then the high level on the row addressing signal line 24, identified by oval 20a, of the positive pulse wave signal Sgp will be input to the 6-NMOS gate 127 and will cause the 6-NMOS transistor 129 to be on and cause the MIM capacitor 115 to be in a pass state with the column display analog signal line 44, and if the pixel addressing storage circuit 46 employs the PMOS type switch capacitance then the low level on the row addressing signal line 24, identified by oval 21a, of the negative pulse wave signal Sgn will be input to the 6-PMOS gate 123 and will cause the 6-PMOS transistor 125 to be on and cause the MIM capacitor 115 to be in a pass state with the column display analog signal line 44, and will result in the pixel addressing storage circuit 46 entering an input pass state such that the portion of the analog signal SDi transmitted on the column display analog signal line 44 identified by oval 22a will be stored in real time as indicated by the unidirectional arrow line 13b to the oval 23a in the pixel addressing storage circuit 46,

And because there is a transition of the P pulse signal SP transmitted on the global display inversion signal line 31 to a high level such that the 5-PMOS gate 141 is connected to a high level causing the 5-PMOS transistor 145 to open and at the same time there is a transition of the N pulse signal SN transmitted on the global display positive phase signal line 29 to a low level such that the 5-NMOS gate 147 is connected to a low level causing the 5-NMOS transistor 149 to shut down and thereby causing the analog display transmission gate 23 to be in an open state and will also cause the pixel analog signal output electrode 26 to produce a portion of the level state identified by the ellipse 18a in the upper time period as indicated by the unidirectional arrow line 14b that is intended to continue to be transmitted as identified by the ellipse 19a,

and after the analog display transmission gate 23 is in the off state, if the analog display amplifier 49 adopts a PMOS type dual-tube common drain amplifier, the P pulse wave Vbp2 level transmitted on the pixel bias voltage supply line 28 jumps up to the high level again, and the 1 st-PMOS gate 85 is connected to the power supply line 77 level VD to cause the 1 st-PMOS tube 88 to be turned off and the analog display amplifier 49 to enter an inactive state, and if the analog display amplifier 49 adopts an NMOS type dual-tube common drain amplifier, the N pulse wave Vbn2 level transmitted on the pixel bias voltage supply line 28 jumps down to the low level again, and the 2 nd-NMOS gate 106 is connected to the ground line 135 level VG to cause the 2 nd NMOS tube 105 to be turned off and the analog display amplifier 49 to enter an inactive state;

And during the T4 period: and the counter 8 is reset to zero at the beginning to start counting, the ramp signal Sramp transmitted on the ramp signal line 17 starts to synchronously and incrementally change from the ramp signal minimum level V1 to the ramp signal maximum level V3 along with the counting speed of the counter 8,

and when a Tx1 time of not more than the time length T4 has elapsed, if the number generated by the counter 8 is equal to the number stored by the digital signal latch 11, the enable digital signal comparator 12 will be triggered to output a low level to the 1 st control line 1 and cause the ramp transmission control terminal 15 to receive the pulse wave signal ENC as a low level identified by the ellipse 24a and further have a low level input to the 3 rd NMOS gate 66 and a converted high level access to the 3 rd PMOS gate 61 to put the ramp transmission gate in an off state and further respectively cause the analog signal SDi transmitted on the column display analog signal line 44 to no longer follow in real time the change of the level of the ramp signal Sramp transmitted on the ramp signal line 17 and remain as a fixed level identified by the ellipse 25a until the ramp signal transmission gate 52 is again in a on state,

And the pixel-addressing storage circuit 46 continues to maintain the input path state because the pulse wave signal transmitted on the row-addressing signal line 24 remains in the level state for the previous period of time and causes the analog signal SDi transmitted on the column-display analog signal line 44 to be updated by the portion identified by the oval 25a as the analog signal Vsc driving the pixel-storage output terminal 42 as indicated by the unidirectional arrow line 15b to the fixed-level portion identified by the oval 26,

and the level of the ramp signal Sramp transmitted on the ramp signal line 17 is incremented to the ramp signal maximum level V3 at the termination and the counter 8 also counts up to the full value,

and the analog display amplifier 49 keeps the inactive operation state because the pulse wave signal transmitted on the pixel bias voltage supply line 28 continues the level state for the previous period, the analog display transfer gate 23 keeps the off state because the P pulse wave signal transmitted on the global display inversion signal line 31 and the N pulse wave signal transmitted on the global display positive phase signal line 29 continue the level state for the previous period and also causes the analog signal Vout output on the pixel analog signal output electrode 26 to continue the level state identified by the ellipse 19a in the previous period as indicated by the unidirectional arrow line 16b to generate a portion identified by the ellipse 27;

Then, in the display line period TP11 of the previous display period,

four time periods of T1, T2, T3, T4: the ramp signal Sramp transmitted on the ramp signal line 17, the pulse wave signal RST transmitted on the comparator reset signal line 19, the pulse wave signal transmitted on the pixel bias voltage supply line 28, the P pulse wave signal SP transmitted on the global display inversion signal line 31, the N pulse wave signal SN transmitted on the global display positive phase signal line 29 are each repeatedly transmitted in the waveform state in the previous row period,

and if the pixel addressing storage circuit 46 employs the NMOS type switch capacitor then the transmission of the positive pulse wave signal Sgp on the row addressing signal line 24 will be input to the 6-NMOS gate 127 with the 6-NMOS transistor 129 turned off and the MIM capacitor 115 and the column display analog signal line 44 always placed in an off state, and if the pixel addressing storage circuit 46 employs the PMOS type switch capacitor then the transmission of the negative pulse wave signal Sgn on the row addressing signal line 24 will remain high as identified by the oval 29a will be input to the 6-PMOS gate 123 with the 6-PMOS transistor 125 turned off and the MIM capacitor 115 and the column display analog signal line 44 always placed in an off state will cause the pixel addressing storage circuit 46 to always remain in an off state with the level state of the pixel storage output 42 analog signal Vsc identified by the oval 26a in the last row period T4 period continuing to be stored and output as partially identified by the unidirectional arrow line 17b 30,

And during the T1 period: and if the analog display amplifier 49 adopts a PMOS type dual-tube common-drain amplifier, the level of the P pulse wave Vbp2 transmitted on the bias voltage supply line 28 jumps from a high voltage to a level identified by an ellipse 48, and the analog display amplifier 49 can be caused to enter the saturation region by the 1 st-PMOS transistor 88 because the 1 st-PMOS gate electrode 85 is connected lower than the power supply line 77 level VD, thereby realizing an effective operating state, and if the analog display amplifier 49 adopts an NMOS type dual-tube common-drain amplifier, the level of the N pulse wave Vbn2 transmitted on the bias voltage supply line 28 jumps from a low level to a level identified by the ellipse 49, and can be caused to enter the saturation region by the analog display amplifier 49 because the 2 nd-NMOS gate electrode 106 is connected higher than the ground line 135 level VG, and the level signal stored by the pixel addressing storage circuit 46 at the end of the last period is transmitted to the input terminal 22 through the analog display amplifier 49,

and the P pulse wave signal SP transmitted on the global display inversion signal line 31 is high to cause the 5-PMOS gate 141 to be high to turn off the 5-PMOS transistor 145 while the N pulse wave signal SN transmitted on the global display positive phase signal line 29 is low to cause the 5-NMOS gate 147 to be low to cause the 5-NMOS transistor 149 to be off and thereby cause the analog display transmission gate 23 to be in an off state and also cause the analog signal Vout output on the pixel analog signal output electrode 26 to be in a level state in which the level portion identified by the ellipse 31 is indicated by the unidirectional arrow line 18b to continue the last period of time identified by the ellipse 27,

And during the T2 period: and the analog display amplifier 49 continues to remain in an active operating state because the analog signal transmitted on the bias voltage supply line 28 remains in a level state for the previous period of time,

and the P pulse wave signal SP transmitted on the global display inversion signal line 31 is hopped to a low level so that the 5-PMOS gate 141 is connected to a low level to cause the 5-PMOS transistor 145 to be turned on, while the N pulse wave signal SN transmitted on the global display positive phase signal line 29 is hopped to a high level so that the 5-NMOS gate 147 is connected to a high level to cause the 5-NMOS transistor 149 to be turned on and thereby cause the analog display transfer gate 23 to be in a channel state to also cause the analog signal Vsc of the pixel storage output terminal 42 to be identified by the level portion of the ellipse 30, and the analog signal Vout of the pixel analog signal output electrode 26 is driven to be updated in real time as indicated by the unidirectional arrow line 19b through the analog display amplifier 49 and held at the output electrode parasitic capacitor 20,

and during the time periods T3, T4: and if the analog display amplifier 49 adopts a PMOS type dual-tube common-drain amplifier, the P pulse wave Vbp2 level transmitted on the bias voltage supply line 28 jumps up to a high level again, and the 1 st-PMOS gate 85 is connected to the power supply line 77 level VD to turn off the 1 st-PMOS tube 88, so that the analog display amplifier 49 enters an inactive operation state, and if the analog display amplifier 49 adopts an NMOS type dual-tube common-drain amplifier, the N pulse wave Vbn2P level transmitted on the bias voltage supply line 28 jumps down to a low level again, and the 2 nd-NMOS gate 106 is connected to the ground line 135 level VG to turn off the 2 nd-NMOS tube 105, so that the analog display amplifier 49 enters an inactive operation state,

And the P pulse wave signal SP transmitted on the global display inversion signal line 31 is restored to a high level while the N pulse wave signal SN transmitted on the global display positive phase signal line 29 is restored to a low level so that the analog display transfer gate 23 is again in the off state to cause the level portion of the analog signal Vout output on the pixel analog signal output electrode 26 identified by the ellipse 33 to continue to the level state identified by the ellipse 32 for the previous period as indicated by the unidirectional arrow line 20b,

and when a time Tx2 of not more than the time length T4 has elapsed, if the number generated by the counter 8 is equal to the number stored by the digital signal latch 11, will trigger the enabling digital signal comparator 12 to output a low level to the 1 st control line 1 and cause the ramp transmission control terminal 15 to receive the low level of the pulse wave signal ENC and thereby cause the analog signal SDi transmitted on the column display analog signal line 44 to no longer follow in real time the ramp signal Sramp level change transmitted on the ramp signal line 17 and remain as a fixed level portion identified by the oval 34 until the ramp signal transmission gate 52 is again in the on-state,

and the level of the ramp signal Sramp transmitted on the ramp signal line 17 is increased to the highest level V3 of the ramp signal at the termination, and the counter 8 also counts up to the full value;

Then, in the address line period TC21 of the latter display period,

four time periods of T1, T2, T3, T4: the ramp signal Sramp transmitted on the ramp signal line 17, the pulse wave signal RST transmitted on the comparator reset signal line 19, the pulse wave signal SP transmitted on the pixel bias voltage supply line 28, the P pulse wave signal SP transmitted on the global display inversion signal line 31, the N pulse wave signal SN transmitted on the global display positive phase signal line 29 are each repeatedly transmitted in the waveform state in the previous row period, the pulse wave signal transmitted on the row address signal line 24 is repeatedly transmitted in the waveform state in the address row period TC11 of the previous display period,

and during the time periods T1, T2, T3: the pixel address storage circuit 46 continues to maintain the input off state while the pulse wave signal transmitted on the row address signal line 24 remains in the level state for the previous period such that the level state of the analog signal Vsc at the pixel storage output 42 identified by the oval 30 in the previous period continues to be stored and output as indicated by the unidirectional arrow line 21b for the portion identified by the oval 35,

and during the T1 period: the continued on-state of the analog display transfer gate 23 causes the portion of the level of the analog signal Vout output on the pixel analog signal output electrode 26 identified by the ellipse 33 to remain in the level state of the output electrode parasitic capacitor 20 identified by the ellipse 36 for the last period of time as indicated by the unidirectional arrow line 22b,

And during the T2 period: the analog display amplifier 49 being in an active operational state and the analog display transfer gate 23 being in a pass state will cause the portion of the analog signal Vsc level of the pixel storage output 42 identified by the oval 35 to be generated and maintained in the level state of the output electrode parasitic capacitor 20 identified by the oval 37 by the analog display amplifier 49 driving the pixel analog signal output electrode 26 in real time as indicated by the unidirectional arrow line 23b to strengthen the level state of the portion identified by the oval 36,

and during the time periods T3, T4: and if the counter 8 generates a number equal to the number stored by the digital signal latch 11 when the Tx2 time of no more than the length of time T4 has elapsed will trigger the enable digital signal comparator 12 to output a low which causes the ramp signal transmission gate 52 to switch off such that the level of the analog signal SDi transmitted on the column display analog signal line 44 no longer follows the change in the level of the ramp signal Sramp transmitted on the ramp signal line 17 in real time to remain at the fixed level identified by the oval 38 and the analog signal Vsc driving the pixel storage output 42 is updated to the fixed level portion identified by the oval 39 as indicated by the unidirectional arrow line 24b,

And the reentry of the analog display transfer gate 23 into the off state causes the level portion of the analog signal Vout output on the pixel analog signal output electrode 26 identified by the ellipse 37 to continue to the level state identified by the ellipse 40 for the previous period as indicated by the unidirectional arrow line 25 b;

then, in the display line period TP21 of the latter display period,

and if the pixel addressing storage circuit 46 employs the NMOS type switch capacitance then the transmission of positive pulse wave signal Sgp on the row addressing signal line 24 will be input to the 6-NMOS gate 127 with the 6-NMOS transistor 129 turned off and causing the MIM capacitor 115 and the column display analog signal line 44 to be placed in an off state all the time, or if the pixel addressing storage circuit 46 employs the PMOS type switch capacitance then the transmission of negative pulse wave signal Sgn on the row addressing signal line 24 will be input to the 6-PMOS gate 123 with the 6-PMOS transistor 125 turned off and causing the MIM capacitor 115 and the column display analog signal line 44 to be placed in an off state will cause the pixel addressing storage circuit 46 to be kept in an on state all the time and the level state of the pixel storage output 42 analog signal c identified by the ellipse 39 to continue to be stored and output as indicated by the unidirectional arrow line 26b with the ellipse 43,

And during the T1 period: the continued on-state of the analog display transfer gate 23 causes the portion of the level of the analog signal Vout output on the pixel analog signal output electrode 26 identified by the ellipse 44 to continue the level state identified by the ellipse 40 for the previous period of time as indicated by the unidirectional arrow line 27b,

and during the T2 period: the analog display amplifier 49 being in an active operational state and the analog display transfer gate 23 being in a pass state will cause the portion of the analog signal Vsc level of the pixel storage output 42 identified by the oval 43 to be generated and maintained in the level state of the output electrode parasitic capacitor 20 as identified by the oval 45 by the analog display amplifier 49 driving the pixel analog signal output electrode 26 in real time as indicated by the unidirectional arrow line 28b to update the level state of the portion identified by the oval 44,

and during the time periods T3, T4: the re-off state of the analog display transfer gate 23 causes the level portion of the analog signal Vout output on the pixel analog signal output electrode 26 identified by the ellipse 46 to remain in the level state of the output electrode parasitic capacitor 20 identified by the ellipse 45 for the last period of time as indicated by the unidirectional arrow line 29b,

And during the T4 period: and when a period Ty2 of no more than a period T4 has elapsed, if the number generated by the counter 8 is equal to the number stored by the digital signal latch 11, the enabling digital signal comparator 12 will be triggered to output a low level to the 3 rd NMOS gate 66, switching a high level to the 3 rd PMOS gate 61 will cause the ramp signal transmission gate 52 to turn off such that the analog signal SDi level transmitted on the column display analog signal line 44 no longer follows in real time the ramp signal Sramp level change transmitted on the ramp signal line 17 and remains at a fixed level identified by the oval 47 until the ramp signal transmission gate 52 is again in a pass state;

the driving method further includes: four time periods T1, T2, T3, T4 in each row period are sequentially performed and then cycled back and forth, each display period may output an analog level corresponding to the number stored by the digital signal latch 11 in the row address period of the current display period at the pixel analog signal output electrode 26.

It should be clear that the present invention is not limited to the embodiments described herein, but that obvious improvements and modifications made according to the inventive concept should be within the scope of the present invention by those skilled in the art from the present disclosure.

Claims

1. A single-path slope type analog pixel driving circuit is characterized in that: the circuit is composed of a digital signal latch, a counter, an enabling digital signal comparator, a ramp signal amplifier, a ramp signal transmission gate, a pixel addressing storage circuit, an analog display amplifier, an analog display transmission gate, a pixel output electrode circuit, a display digital signal input bus, a comparator reset signal line, a ramp bias voltage supply line, a row addressing signal line, a pixel bias voltage supply line, a global display normal phase signal line, a global display reverse phase signal line and a column display analog signal line,

and the ramp signal line, the ramp signal amplifier, the ramp signal transmission gate, the column display analog signal line, the pixel addressing storage circuit, the analog display amplifier and the analog display transmission gate form a functional circuit through electric series connection to process the ramp signal constructed by connecting four sections of waveforms,

and the analog display transfer gate outputs a level signal to the pixel output electrode circuit, and the digital signal latch has the same number of bits as the counter, and is further configured with: a 2 nd connection line, a 5 th connection line, a 6 th connection line, a reset connection line, a 1 st control line, a power supply line, a ground line, and the digital signal latch receives a multi-bit digital signal transmitted by the display digital signal input bus through the 2 nd connection line to store, and the enable digital signal comparator receives a multi-bit count digital signal transmitted by the counter through the 5 th connection line, receives a multi-bit store digital signal transmitted by the digital signal latch through the 6 th connection line, receives a reset level signal transmitted by the comparator reset signal line through the reset connection line, and transmits a control level signal to the ramp signal transmission gate through the 1 st control line;

The ramp signal amplifier is configured with a ramp amplification bias end, a ramp amplification input end and a ramp amplification output end, the ramp signal transmission gate is configured with a ramp transmission control end, a ramp transmission input end and a ramp transmission output end, the pixel addressing storage circuit is configured with a pixel addressing control end, a pixel storage input end and a pixel storage output end, the analog display amplifier is configured with a display amplification bias end, a display amplification input end and a display amplification output end, the analog display transmission gate is configured with a display transmission reverse phase control end, a display transmission normal phase control end, a display transmission input end and a display transmission output end, and the pixel output electrode circuit is configured with a pixel analog signal output electrode,

and the enable digital signal comparator is provided with a control circuit for outputting a high level to the 1 st control line when a rising edge trigger of an enable signal transmitted on the comparator reset signal line is received through the reset connection line, outputting a low level to the 1 st control line when a digital signal received from the digital signal latch through the 6 th connection line is compared with a digital signal received from the counter through the 5 th connection line, and outputting a low level to the 1 st control line when the two digital signals are identical.

2. The single-pass ramp type analog pixel driving circuit according to claim 1, wherein: the slope signal amplifier is composed of one of a PMOS type double-tube common-drain amplifier adopting a P type amplifier bias terminal as the slope amplifying bias terminal, a P type amplifier input terminal as the slope amplifying input terminal, a P type amplifier output terminal as the slope amplifying output terminal, or an NMOS type double-tube common-drain amplifier adopting an N type amplifier bias terminal as the slope amplifying bias terminal, an N type amplifier input terminal as the slope amplifying input terminal, an N type amplifier output terminal as the slope amplifying output terminal, and the slope amplifying bias terminal is connected with the slope bias voltage supply line, the slope amplifying input terminal is connected with the slope signal line,

and the ramp signal transmission gate is composed of a 3-PMOS tube at least comprising a 3-PMOS grid electrode, a 3-PMOS drain electrode and a 3-PMOS source electrode, a 3-NMOS tube at least comprising a 3-NMOS grid electrode, a 3-NMOS drain electrode and a 3-NMOS source electrode, a 4-PMOS tube at least comprising a 4-PMOS grid electrode, a 4-PMOS drain electrode and a 4-PMOS source electrode, and a 4-NMOS tube at least comprising a 4-NMOS grid electrode, a 4-NMOS drain electrode and a 4-NMOS source electrode, and is also configured with: the power supply line and the grounding line, the 4-NMOS grid electrode, the 4-PMOS grid electrode and the 3-NMOS grid electrode are connected to form the slope transmission control end, the 4-NMOS source electrode, the 4-PMOS drain electrode and the 3-PMOS grid electrode are connected with each other, the 4-PMOS source electrode is connected to the power supply line, the 4-NMOS drain electrode is connected to the grounding line, the 3-PMOS drain electrode and the 4-NMOS source electrode are connected to form the slope transmission input end, the 3-PMOS source electrode and the 3-NMOS drain electrode are connected to form the slope transmission output end, the slope transmission input end is connected with the slope amplification output end, and the slope transmission output end is connected with the column display analog signal line.

3. The single-pass ramp type analog pixel driving circuit according to claim 1, wherein: the pixel addressing storage circuit is composed of one of a PMOS type switch capacitor adopting a P type switch capacitor control end as the pixel addressing control end, a P type switch capacitor input end as the pixel storage input end, a P type switch capacitor output end as the pixel storage output end, or an NMOS type switch capacitor adopting an N type switch capacitor control end as the pixel addressing control end, an N type switch capacitor input end as the pixel storage input end and an N type switch capacitor output end as the pixel storage output end, the pixel addressing control end is connected with the row addressing signal line, the pixel storage input end is connected with the column display analog signal line,

and the analog display amplifier is composed of one of a PMOS type double-tube common-drain amplifier adopting a P type amplifier bias end as the display amplification bias end, a P type amplifier input end as the display amplification input end, a P type amplifier output end as the display amplification output end, or an NMOS type double-tube common-drain amplifier adopting an N type amplifier bias end as the display amplification bias end, an N type amplifier input end as the display amplification input end and an N type amplifier output end as the display amplification output end, wherein the display amplification input end is connected with the pixel storage output end, and the display amplification bias end is connected with the pixel bias voltage supply line.

4. The single-pass ramp type analog pixel driving circuit according to claim 1, wherein: the analog display transmission gate is composed of a 5-PMOS tube at least comprising a 5-PMOS grid electrode, a 5-PMOS drain electrode and a 5-PMOS source electrode, and a 5-NMOS tube at least comprising a 5-NMOS grid electrode, a 5-NMOS drain electrode and a 5-NMOS source electrode, wherein the 5-PMOS drain electrode and the 5-NMOS source electrode are connected to form the display transmission input end, the 5-NMOS drain electrode and the 5-PMOS source electrode are connected to form the display transmission output end, the 5-PMOS grid electrode serves as the display transmission inversion control end, the 5-NMOS grid electrode serves as the display transmission normal phase control end, the display transmission input end is connected with the display amplification output end, the display transmission normal phase control end is connected with the global display normal phase signal line, the display transmission inversion control end is connected with the global display inversion signal line,

and the pixel output electrode circuit is constructed by an output electrode parasitic capacitor formed between the pixel analog signal output electrode and a conductor which is close to the periphery but does not make contact and is connected to the ground line, and the pixel analog signal output electrode serves as one electrode plate of the output electrode parasitic capacitor, the ground line serves as the other electrode plate of the output electrode parasitic capacitor, and the pixel analog signal output electrode is connected with the display transmission output end.

5. A single-pass ramp type analog pixel driving circuit according to claim 2 or 3, wherein: the PMOS type double-pipe common drain amplifier is composed of a 1-PMOS tube at least comprising a 1-PMOS grid electrode, a 1-PMOS source electrode and a 1-PMOS drain electrode, and a 2-PMOS tube at least comprising a 2-PMOS grid electrode, a 2-PMOS source electrode and a 2-PMOS drain electrode, wherein the 1-PMOS grid electrode serves as a bias end of the P type amplifier, the 2-PMOS grid electrode serves as an input end of the P type amplifier, the 1-PMOS drain electrode is connected with the 2-PMOS source electrode to serve as an output end of the P type amplifier, the 1-PMOS source electrode is connected to the power supply line, and the 2-PMOS drain electrode is connected to the grounding line;

the NMOS type double-tube common drain amplifier is composed of a 1-NMOS tube at least comprising a 1-NMOS grid electrode, a 1-NMOS drain electrode and a 1-NMOS source electrode, and a 2-NMOS tube at least comprising a 2-NMOS grid electrode, a 2-NMOS drain electrode and a 2-NMOS source electrode, wherein the 2-NMOS grid electrode serves as an offset end of the N type amplifier, the 1-NMOS grid electrode serves as an input end of the N type amplifier, the 2-NMOS drain electrode is connected with the 1-NMOS source electrode and serves as an output end of the N type amplifier, the 1-NMOS drain electrode is connected to the power supply line, and the 2-NMOS source electrode is connected to the grounding line.

6. A single-pass ramp type analog pixel driving circuit according to claim 3, wherein: the PMOS type switch capacitor is composed of a 6-PMOS tube at least comprising a 6-PMOS grid electrode, a 6-PMOS drain electrode and a 6-PMOS source electrode, and an MIM capacitor at least comprising an MIM capacitor upper polar plate and an MIM capacitor lower polar plate, wherein the 6-PMOS grid electrode serves as the P type switch capacitor control end, the 6-PMOS source electrode serves as the P type switch capacitor input end, and the 6-PMOS drain electrode is connected with the MIM capacitor upper polar plate to form the P type switch capacitor output end, and the MIM capacitor lower polar plate is connected to the grounding wire;

the NMOS type switch capacitor is composed of a 6-NMOS transistor at least comprising a 6-NMOS grid electrode, a 6-NMOS drain electrode and a 6-NMOS source electrode, and an MIM capacitor at least comprising an MIM capacitor upper polar plate and an MIM capacitor lower polar plate, wherein the 6-NMOS grid electrode serves as an N type switch capacitor control end, the 6-NMOS drain electrode serves as an N type switch capacitor input end, and the 6-NMOS source electrode is connected with the MIM capacitor upper polar plate to form an N type switch capacitor output end, and the MIM capacitor lower polar plate is connected to the grounding wire.

7. The driving method of the single-path ramp type analog pixel driving circuit according to any one of claims 1 to 4, wherein: each of any two adjacent display periods is composed of an addressing line period enabling the pixel addressing memory circuit to be in an input channel state and at least one display line period always enabling the pixel addressing memory circuit to be in an input off state, the addressing line period is the same as the duration of the display line period, is connected with time and is commonly called a line period, and in each line period, the ramp signal amplifier is configured in an effective working state,

And each line period is divided into four time periods of T1, T2, T3 and T4, a slope signal formed by connecting four wave forms is configured, the slope signal jumps from the highest level of the slope signal to the central level of the slope signal in the time period of T1, the slope signal is fixed to the central level of the slope signal in the time period of T2, the slope signal jumps from the central level of the slope signal to the lowest level of the slope signal in the time period of T3, and the slope signal starts to change from the lowest level of the slope signal to the highest level of the slope signal in the time period of T4.

8. The driving method of the single-path ramp type analog pixel driving circuit as claimed in claim 7, wherein: in the address line period of the preceding display period of any two adjacent display periods, in the period T1: the ramp signal transmitted on the ramp signal line jumps from the highest level to a fixed level state in the middle, and the rising edge of the pulse wave signal transmitted on the comparator reset signal line triggers the enabling digital signal comparator to output a high level, which causes the ramp signal transmission gate to be in a channel state through the ramp transmission control terminal, and causes the level transmitted on the column display analog signal line to follow the level state transmitted on the ramp signal line in real time through the ramp signal amplifier and the ramp signal transmission gate, and the inactive level transmitted on the row address signal line causes the pixel address memory circuit and the column display analog signal line to be in an off state to continue to hold the level stored at the end of the last row period, and the level transmitted on the pixel bias voltage supply line configures the analog display amplifier to be in an active operation state, and the analog display transmission gate is configured to be in an off state by the pulse wave signal transmitted on the global display inverting signal line and the pulse wave signal transmitted on the global display positive phase signal line, and also causes the pixel address memory circuit and the pixel display analog signal line to be in an off state to continue to hold the parasitic electrode at the end of the last row period,

And during the T2 period: the ramp signal transmitted on the ramp signal line keeps a fixed level state in the middle, the pulse wave signal received by the ramp transmission control end keeps the level state of the last time period, the level transmitted on the column display analog signal line keeps following the level state transmitted on the ramp signal line in real time through the ramp signal amplifier and the ramp signal transmission gate, the invalid level keeps the pixel addressing storage circuit and the column display analog signal line in an open circuit state and keeps the level stored in the last time period, the analog display amplifier keeps keeping the valid working state entered in the last time period, the pulse wave signal transmitted on the global display positive signal line and the pulse wave signal level transmitted on the global display inverted signal line change to enable the analog display transmission gate to be in a channel state, and the level stored by the pixel addressing storage circuit is driven by the analog display amplifier in real time to strengthen the pixel analog signal output electrode and keeps the pixel addressing storage circuit parasitic capacitor,

And during the T3 period: the ramp signal transmitted on the ramp signal line jumps from a certain fixed level to the lowest level state of the ramp signal, the pulse wave signal received by the ramp transmission control end keeps the level state of the last time period, the level transmitted on the column display analog signal line keeps following the level state transmitted on the ramp signal line in real time through the ramp signal amplifier and the ramp signal transmission gate, the line addressing signal line changes to a transmission active level, the pixel addressing storage circuit and the column display analog signal line enter a passage state, the analog signal transmitted on the column display analog signal line is stored in the pixel addressing storage circuit in real time, the level of the pulse wave signal transmitted on the global display positive signal line and the level of the pulse wave signal transmitted on the global display inverted signal line change again, the analog signal output on the pixel analog signal output electrode keeps the level state of the last time period, the level transmitted on the pixel bias voltage supply line changes, the analog display amplifier is configured to be in an inactive operation state,

In the display line period of the previous display period, four periods of time T1, T2, T3, T4: the ramp signal transmitted on the ramp signal line, the pulse wave signal transmitted on the comparator reset signal line and the pulse wave signal received by the ramp transmission control end in the first three time periods keep the level state of the last time period, so that the level transmitted on the column display analog signal line keeps following the level state transmitted on the ramp signal line in real time through the ramp signal amplifier and the ramp signal transmission gate, the line addressing signal line changes to a transmission invalid level, so that the pixel addressing storage circuit and the column display analog signal line keep an open circuit state, so that the pixel addressing storage circuit keeps keeping the level state of the last line period,

and the pulse wave signal transmitted on the global display inversion signal line and the pulse wave signal transmitted on the global display positive phase signal line firstly configure the analog display transmission gate to an off state in a period of time T1 to cause the analog signal output on the pixel analog signal output electrode to continue to be in a level state for a period of time, then configure the analog display transmission gate to enter a channel state in a period of time T2 and configure the analog display amplifier to be in an active operation state to cause the level output by the pixel addressing storage circuit to drive and update the pixel analog signal output electrode and to be held in an output electrode parasitic capacitor in real time,

in the address line period of the latter display period, four periods of time T1, T2, T3, T4: the ramp signal transmitted on the ramp signal line, the pulse wave signal transmitted on the comparator reset signal line, the pulse wave signal transmitted on the pixel bias voltage supply line, the pulse wave signal transmitted on the global display inversion signal line, the pulse wave signal transmitted on the global display positive phase signal line repeatedly transmit the waveform state transmitted in the previous row period, the pulse wave signal transmitted on the row address signal line repeatedly transmit the waveform state transmitted in the address row period of the previous display period, and the pulse wave signal received by the ramp transmission control terminal continues to maintain the level state of the previous period in the previous three periods, so that the level transmitted on the column display analog signal line continues to follow the level state transmitted on the ramp signal line in real time through the ramp signal amplifier and the ramp signal transmission gate,

after the pulse wave signal transmitted on the row addressing signal line jumps reversely, the pixel addressing storage circuit enters a channel state to store and update the analog signal transmitted on the column display analog signal line in real time;

in the display line period of the latter display period, the ramp signal transmitted on the ramp signal line, the pulse wave signal transmitted on the comparator reset signal line, the pulse wave signal transmitted on the pixel bias voltage supply line, the pulse wave signal transmitted on the global display inversion signal line, the pulse wave signal transmitted on the global display positive phase signal line are all repeatedly transmitted in the waveform state of the previous line period,

and when the analog display amplifier is in an effective working state and the analog display transmission gate is in a channel state, the level stored by the pixel addressing storage circuit is caused to drive the pixel analog signal output electrode in real time to update the level state.

9. The driving method of the single-path ramp type analog pixel driving circuit as claimed in claim 7, wherein: the driving method further includes: four time periods of each row period T1, T2, T3, T4 are sequentially performed and then cycled back and forth, each display period may output an analog level at the pixel analog signal output electrode corresponding to the number stored by the digital signal latch during the row address period of the current display period.