JP5588951B2 - Interrupt control circuit - Google Patents

Description

  The present invention relates to an interrupt control circuit.

  Conventionally, as an interrupt control circuit used in an IRQC (Interrupt ReQuest Controller) disposed inside a SoC (System On Chip) IC, for example, a pulse generation circuit provided on the interrupt supply side as described in Patent Document 1 below A control signal line for exclusive control of a plurality of pulse generation circuits and an interrupt recognition circuit provided on the CPU side, and an interrupt in which the CPU and a plurality of interrupt supply sources are connected by two signal lines Control circuits are known.

  Such an interrupt control circuit causes the CPU to generate an interrupt when an interrupt is generated from one of the interrupt supply sources. Also, a unique pulse is generated from one of the interrupt supply sources, and the CPU counts and latches the pulse, so that the CPU captures it and recognizes from which supply source it is an interrupt. To do.

  In addition, when an interrupt is generated from one interrupt supply source, even if another interrupt different from the interrupt is generated at the interrupt supply source, the interrupt processing corresponding to the interrupt that occurred earlier is completed. During this period, exclusive control is performed so that the CPU does not generate an interrupt.

Japanese Patent Laid-Open No. 3-75830

  However, in the conventional interrupt control circuit, since the exclusive control is performed as described above, a new interrupt is generated between the time when an interrupt is generated at one place and the interrupt processing corresponding to the interrupt is completed. Even if this occurred, it was not possible to detect the occurrence of the new interrupt, and it was impossible to know that the occurrence of the new interrupt could not be detected.

  The present invention has been made in view of such circumstances. When a new interrupt is generated before the interrupt processing corresponding to a certain interrupt is completed, the fact that the new interrupt has occurred is described. An object of the present invention is to provide an interrupt control circuit capable of detecting.

An interrupt control circuit according to the present invention includes an interrupt signal receiving unit that receives an interrupt generation signal indicating the occurrence of an interrupt, and generates an interrupt when the interrupt signal reception unit receives the interrupt generation signal. An interrupt storage unit for storing the interrupt generation information shown, and a high-level interrupt permission signal indicating that the execution of the interrupt process that is a process corresponding to the interrupt is permitted, or the execution of the interrupt process. A permission signal receiving unit that receives a low-level interrupt permission signal indicating that permission is not permitted, and the permission signal receiving unit receives the high-level interrupt permission signal, and the interrupt storage unit generates the interrupt. When information is stored, an interrupt process request unit that outputs an interrupt process request signal that requests execution of the interrupt process, and the interrupt generation information is stored in the interrupt storage unit , The new discount When the evolution signal is received by said interrupt signal receiving unit, and an interrupt lost detecting section for detecting the loss of the new interrupt generation signal, loss of the new interrupt generation signal by said interrupt lost detection unit Is detected, the information indicating the loss of the new interrupt generation signal is stored, and the information indicating the loss of the new interrupt generation signal is stored for a period of time during which the information indicating the loss of the new interrupt generation signal is stored. The lost storage unit that outputs a high level signal indicating that the interrupt enable signal received by the enable signal receiver is input to one end, the interrupt enable signal input to the one end, and the other end A first logical product circuit that outputs a first logical product signal corresponding to a logical product of the received signal, the signal output from the lost storage unit, and the first logical product output from the first logical product circuit. Second AND corresponding to the logical AND with the signal And outputs the second logical product signal as an interrupt lost signal indicating that the new interrupt generation signal is not lost when the second logical product signal is at a low level. And a second AND circuit that outputs the second AND signal as an interrupt lost signal indicating the loss of the new interrupt generation signal when the second AND signal is at a high level .

According to this configuration, when a new interrupt generation signal is received by the interrupt signal receiving unit in a state where the interrupt generation information is stored in the interrupt storage unit, the new loss detection unit detects the new interrupt generation information. Loss of the interrupt generation signal is detected. When the loss of the new interrupt occurrence signal is detected by the lost loss detection unit, the loss storage unit stores the information indicating the loss of the new interrupt occurrence signal during the period in which information indicating the loss of the new interrupt occurrence signal is stored. A high level signal indicating the loss of a new interrupt generation signal is output.

For this reason, an interrupt corresponding to a new interrupt generation signal indicated to be lost by the output high level signal was generated until the interrupt processing corresponding to a certain interrupt is completed. This can be detected , and the high-level signal can be dealt with at an arbitrary timing in the period.
When the interrupt permission signal received by the permission signal receiving unit indicates that the execution of the interrupt process is not permitted, the interrupt process requesting unit does not request the execution of the interrupt process. That is, in this case, the interrupt process is not executed, so that no new interrupt is generated until the interrupt process ends.
According to this configuration, when the interrupt permission signal indicates that execution of the interrupt process is not permitted, a new interrupt is not generated until the interrupt process is completed. It is possible to prohibit the output of a high-level interrupt loss signal indicating the loss of an interrupt generation signal.

Further, a high level loss detection prohibition signal indicating prohibition of detection of loss of the interrupt generation signal , or a low level loss detection prohibition signal indicating permission of detection of loss of the interrupt generation signal. It is preferable to further include a detection prohibition receiving unit that receives and outputs a signal indicating the logical negation of the received loss detection prohibition signal to the other end of the first AND circuit .

According to this configuration, whether to prohibit the output of the high-level interrupt loss signal by the second AND circuit is switched depending on whether the detection prohibition receiving unit receives the high-level loss detection prohibition signal. Can do.

  According to the present invention, there is provided an interrupt control circuit capable of detecting that a new interrupt has occurred when a new interrupt occurs before the interrupt processing corresponding to a certain interrupt is completed. It becomes possible.

1 is a configuration diagram illustrating an example of a configuration of a multifunction machine including an interrupt control circuit according to the present invention. 1 is a block diagram illustrating an example of an electrical configuration of a multifunction machine. The circuit diagram which shows an example of an interrupt control circuit.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS A multifunction device having an interrupt control circuit according to the present invention and having functions of, for example, a copy, a printer, a scanner, and a facsimile will be described below with reference to the drawings.

  As shown in FIG. 1, the multifunction machine 1 includes a main body unit 100, a document reading unit 200, a document feeding unit 300, an operation unit 400, and a paper post-processing unit 500.

  The document feeding unit 300 includes a document placement unit 301, a paper feed roller 303, a document transport unit 305, and a document discharge unit 307.

  The paper feed roller 303 feeds the original set on the original placement unit 301 one by one. The document transport unit 305 transports the fed document to the document reading unit 200. The document is read by the document reading unit 200 and discharged to the document discharge unit 307.

  The document reading unit 200 includes a carriage 201 on which a CCD (Charge Coupled Device) sensor and an exposure lamp are mounted, a document table 203 formed of a transparent member such as glass, and a document reading slit 205.

  When reading a document placed on the document table 203, the document is read by the CCD sensor while moving the carriage 201 in the longitudinal direction of the document table 203. On the other hand, when reading a document fed from the document feeding unit 300, the carriage 201 is moved to a position facing the document reading slit 205, and the document fed from the document feeding unit 300 is scanned. Reading is performed by the CCD sensor through the reading slit 205. The CCD sensor outputs the read original as image data.

  The main body 100 includes a paper storage unit 101, an image forming unit 103, and a fixing unit 105.

  The paper storage unit 101 includes a paper tray 107 that is disposed at the lowermost part of the main body unit 100 and stores a bundle of paper. In the stack of sheets stored in the sheet tray 107, the uppermost sheet is fed out toward the sheet conveying unit 111 by driving the pickup roller 109. The sheet is conveyed to the image forming unit 103 through the sheet conveying unit 111.

  The image forming unit 103 forms a toner image on the conveyed paper. The image forming unit 103 includes a photosensitive drum 113, an exposure unit 115, a developing unit 117, and a transfer unit 119.

  The exposure unit 115 generates light corresponding to image data (image data output from the document reading unit 200, image data transmitted from a personal computer, image data received by facsimile, etc.), and is uniformly charged photoconductor. Irradiate the peripheral surface of the drum 113. As a result, an electrostatic latent image corresponding to the image data is formed on the peripheral surface of the photosensitive drum 113.

  In this state, toner is supplied from the developing unit 117 to the circumferential surface of the photosensitive drum 113, so that a toner image corresponding to the image data is formed on the circumferential surface of the photosensitive drum 113. This toner image is transferred by the transfer unit 119 to the sheet conveyed from the sheet storage unit 101.

  The sheet on which the toner image is transferred is sent to the fixing unit 105. In the fixing unit 105, heat and pressure are applied to the toner image and the paper to fix the toner image on the paper. Thereby, the printing of the image on the paper is completed. When post-processing is performed on the printed paper, the printed paper is sent from the paper discharge port 121 of the main body 100 to the paper post-processing unit 500. On the other hand, when no post-processing is performed, the printed paper is discharged to the paper discharge tray 123.

  The paper post-processing unit 500 performs post-processing such as sorting, stapling, punching, and saddle stitching on the printed paper. The paper post-processing unit 500 includes a paper carry-in port 501, a paper transport unit 503, a paper carry-out port 505, a stack tray 507, and the like. The paper transport unit 503 sequentially transports the printed paper carried into the paper carry-in port 501 from the paper discharge port 121, and carries out the post-processed printed paper from the paper carry-out port 505 to the stack tray 507. The stack tray 507 has a configuration capable of moving up and down in the direction of the arrow in accordance with the number of sheets stacked from the paper exit 505.

  The operation unit 400 includes an operation key unit 401 and a display unit 403. The display unit 403 has a touch panel function, and displays a screen including soft keys. The user operates the soft keys while viewing the screen to make settings necessary for executing functions such as copying.

  The operation key unit 401 includes operation keys including hard keys, and specifically includes a help key 405, a start key 407, a ten key 409, a function switching key 411, and the like.

  A help key 405 is a key for displaying a help screen on the display unit 403. The help screen is a screen on which operation methods relating to functions such as a scanner, a facsimile, a printer, and a copy are displayed. A start key 407 is a key for starting operations such as copying and facsimile transmission. A numeric keypad 409 is a key for inputting numbers such as the number of copies and a facsimile number. The function switching key 411 includes a copy key, a transmission key, and the like, and is a key for switching between a copy function, a transmission function, and the like. When the copy key is operated, an initial copy screen is displayed on the display unit 403. When the transmission key is operated, an initial screen for facsimile transmission and mail transmission is displayed on the display unit 403.

  Next, the electrical configuration of the multifunction machine 1 will be described. As shown in FIG. 2, the multifunction device 1 connects a main body 100, a document reading unit 200, a document feeding unit 300, an operation unit 400, a sheet post-processing unit 500, and a storage medium 6 such as a USB memory to the multifunction device 1. The external interface (external I / F) 600, the communication unit 700, and the control unit 2 are connected by a bus.

  The control unit 2 is configured as a microcomputer in which a ROM (Read Only Memory) 21, a RAM (Random Access Memory) 22, a CPU (Central Processing Unit) 23, and an interrupt control circuit 24 are connected by a bus.

  The CPU 23 performs necessary control for each unit 100, 200, 300, 400, 500, 600, 700 by executing the control program stored in the ROM 21 while using the RAM 22 as a work area.

  The interrupt control circuit 24 receives an interrupt signal indicating the occurrence of an interrupt from each unit 100, 200, 300, 400, 500, 600, 700, and performs a process corresponding to the interrupt indicated by the interrupt signal (interrupt process). ) Is output to the CPU 23.

  Next, the configuration of the interrupt control circuit 24 will be described in detail. For example, as shown in FIG. 3, the interrupt control circuit 24 includes an interrupt signal receiving unit 31, an interrupt storage unit 32, a permission signal receiving unit 33, an interrupt processing request unit 34, an interrupt loss detection unit 35, and a detection prohibition. A receiving unit 36 and a lost signal output unit 37 are provided.

  The interrupt control circuit 24 includes an interrupt clear signal receiving unit 41 and a lost clear signal receiving unit 42. The interrupt clear signal receiving unit 41 receives an interrupt clear signal indicating an instruction as to whether or not to set (clear) the value of an interrupt generation flag stored in a D flip-flop circuit 322 described later to “0”. This is an input terminal. The lost clear signal receiving unit 42 receives a lost clear signal indicating an instruction as to whether or not to set (clear) the value of an interrupt lost flag stored in a D flip-flop circuit 382, which will be described later, to “0”. Input terminal. The interrupt clear signal receiving unit 41 and the lost clear signal receiving unit 42 may be connectors, IC signal pins, or wiring patterns.

  The interrupt signal receiving unit 31 is an input terminal for receiving an interrupt generation signal output from each unit 100, 200, 300, 400, 500, 600, 700. In the following, the interrupt generation signal is a signal indicating two levels of high level or low level, indicating that an interrupt has occurred when it is at a high level, and that no interrupt has occurred when it is at a low level. It will be described as shown. Further, the interrupt signal receiving unit 31 may be a connector, an IC signal pin, or a wiring pattern.

  The interrupt storage unit 32 stores an interrupt generation flag (interrupt generation information) indicating whether or not an interrupt has occurred according to the level of the interrupt generation signal received by the interrupt signal reception unit 31. A signal having a level corresponding to the value of the stored interrupt generation flag is output to the interrupt loss detection unit 35.

  For example, when the interrupt generation signal received by the interrupt signal receiving unit 31 is at a high level, the interrupt storage unit 32 indicates an interrupt with a value “1” indicating the occurrence of an interrupt according to the high level. The generation flag is stored, and a high level signal corresponding to the stored interrupt generation flag value “1” is output to the interrupt loss detection unit 35. In the following description, the interrupt generation flag indicates that an interrupt has occurred when the value is “1”, and indicates that no interrupt has occurred when the value is “0”.

  Specifically, the interrupt storage unit 32 includes, for example, an OR circuit 321 and a D flip-flop circuit 322 as shown in FIG.

  The OR circuit 321 outputs a high-level signal toward the D terminal of the D flip-flop circuit 322 when the interrupt generation signal received by the interrupt signal receiving unit 31 is at a high level.

  For example, a clock signal CLK generated by an oscillation circuit (not shown) is input to the clock terminal of the D flip-flop circuit 322. Note that the cycle of the clock signal CLK is shorter than the pulse width of the interrupt generation signal. The D flip-flop circuit 322 stores a value corresponding to the level of the signal input from the OR circuit 321 as an interrupt generation flag in synchronization with the positive edge (rising edge) of the clock signal CLK. The D flip-flop circuit 322 outputs a signal of a level corresponding to the value of the stored interrupt generation flag to the interrupt loss detection unit 35, the OR circuit 321 and an interrupt processing request unit 34 described later. .

  The output signal of the D flip-flop circuit 322 is fed back via the OR circuit 321 and input to the D terminal of the D flip-flop circuit 322. As a result, once the value of the interrupt generation flag of the D flip-flop circuit 322 becomes “1”, the value of the interrupt generation flag is held at “1” regardless of the level of the interrupt generation signal.

  The D flip-flop circuit 322 is provided with a clear terminal for setting (clearing) the value of the stored interrupt generation flag to “0”. Specifically, when the CPU 23 finishes executing the interrupt process, the interrupt clear signal receiving unit 41 receives a low-level interrupt clear signal indicating that the interrupt generation flag is instructed to be deleted. When the low-level interrupt clear signal is input to the clear terminal, the D flip-flop circuit 322 sets the value of the stored interrupt generation flag to “0”.

  The permission signal receiving unit 33 is an input terminal for receiving an interrupt permission signal indicating whether or not to permit execution of an interrupt process. In the following, the interrupt permission signal is a signal indicating two levels of high level or low level, and indicates that interrupt processing is permitted when it is high level, and interrupt signal when it is low level. Description will be made assuming that execution of the process is prohibited. Further, the permission signal receiving unit 33 may be a connector, an IC signal pin, or a wiring pattern.

  The interrupt processing request unit 34 receives a high-level interrupt permission signal indicating that execution of the interrupt processing is permitted by the permission signal reception unit 33, and the interrupt storage unit 32 has a value indicating the occurrence of an interrupt. When the interrupt generation flag of “1” is stored, a high level interrupt processing request signal for requesting execution of the interrupt processing is output.

  In the following, the interrupt processing request signal is a signal indicating two levels, high level and low level, and indicates that execution of interrupt processing is requested when the level is high, and interrupted when the level is low. In the following description, it is assumed that execution of the loading process is not requested.

  Specifically, the interrupt processing request unit 34 stores the interrupt permission signal received by the permission signal receiving unit 33 and the signal output from the interrupt storage unit 32, that is, stored in the interrupt storage unit 32. And a signal corresponding to the logical product of the signal corresponding to the value of the interrupt generation flag and an interrupt processing request signal.

  For example, the interrupt processing request unit 34 is a signal whose interrupt permission signal received by the permission signal receiving unit 33 is a high level, and an interrupt generation flag whose value is “1” is stored in the interrupt storage unit 32. If the signal output from the interrupt storage unit 32 is a high level signal corresponding to the value of the interrupt generation flag, a high level signal corresponding to the logical product of the two signals is stored. And output as an interrupt processing request signal.

  On the other hand, when the interrupt processing request unit 34 is at least one of the interrupt permission signal received by the permission signal receiving unit 33 and the signal output from the interrupt storage unit 32 is at a low level. Outputs a low level signal corresponding to the logical product of the two signals as an interrupt processing request signal.

  The interrupt loss detection unit 35 is a state in which an interrupt generation flag whose value indicating the occurrence of an interrupt is “1” is stored in the interrupt storage unit 32, and a new interrupt generation signal is transmitted to the interrupt signal reception unit. When it is received by 31, a high level loss detection signal indicating that the loss of the new interrupt occurrence signal has been detected is output to the loss signal output unit 37.

  In the following, the loss detection signal is a signal indicating two levels of high level or low level. When the loss detection signal is high level, it indicates that the loss of a new interrupt occurrence signal has been detected. A description will be given assuming that the loss of a new interrupt occurrence signal is not detected.

  Specifically, the interrupt loss detection unit 35 is stored in the interrupt generation signal received by the interrupt signal reception unit 31 and the signal output from the interrupt storage unit 32, that is, in the interrupt storage unit 32. And a signal corresponding to the logical product of the signal corresponding to the value of the interrupt generation flag, and a logical product circuit that outputs the signal as a loss detection signal.

  For example, the interrupt loss detection unit 35 stores an interrupt generation flag whose value is “1” in the interrupt storage unit 32, and the signal output from the interrupt storage unit 32 is the value of the interrupt generation flag. If a high-level interrupt generation signal is received by the interrupt signal receiving unit 31 and the high-level signal corresponding to the logical product of the two signals is lost, Output as a signal.

  On the other hand, the interrupt loss detection unit 35 has at least one of the signal output from the interrupt storage unit 32 and the interrupt generation signal received by the interrupt signal reception unit 31 at a low level. In this case, a low level signal corresponding to the logical product of the two signals is output as a loss detection signal.

  The detection prohibition receiving unit 36 receives a loss detection prohibition signal indicating whether or not to detect the loss of the interrupt generation signal. In the following, the loss detection prohibition signal is a signal indicating two levels, a high level and a low level. When the loss detection prohibition signal is high, it indicates that detection of the loss of the interrupt generation signal is prohibited. Will be described as indicating that the detection of the loss of the interrupt generation signal is permitted.

  Specifically, the detection prohibition receiving unit 36 includes an input terminal 361 for receiving a loss detection prohibition signal, and a logic negation circuit 362 that outputs a signal indicating the logical negation of the signal received at the input terminal 361. Yes.

  That is, when the loss detection prohibition signal indicating the high level is received by the input terminal 361, the detection prohibition reception unit 36 outputs the signal indicating the low level to the loss signal output prohibition unit 39 by the logic negation circuit 362. When a loss detection prohibiting signal indicating a low level is received by the input terminal 361, a signal indicating a high level is output to the lost signal output prohibiting unit 39 by the logic negation circuit 362. The input terminal 361 may be a connector, an IC signal pin, or a wiring pattern.

  The lost signal output unit 37 includes a loss detection signal output from the interrupt loss detection unit 35, an interrupt permission signal received by the permission signal reception unit 33, and a loss detection prohibition signal output from the detection prohibition reception unit 36. In response to the level of the signal indicating the logical negation of, an interrupt lost signal indicating whether or not a new interrupt occurrence signal is lost is output.

  In the following description, the lost interrupt signal is a signal indicating two levels of high level or low level. When it is high level, it indicates that a new interrupt occurrence signal is lost, and when it is low level, it indicates a new interrupt level. In the following description, it is assumed that there is no loss of the occurrence signal.

  Specifically, the lost signal output unit 37 includes a lost storage unit 38 and a lost signal output prohibiting unit 39.

  The lost storage unit 38 includes an interrupt lost flag (new interrupt generation signal) indicating whether or not a new interrupt generation signal has been lost in accordance with the level of the loss detection signal output by the interrupt loss detection unit 35. Is stored), and a signal at a level corresponding to the stored interrupt lost flag is output to the lost signal output prohibiting unit 39.

  For example, if the loss detection signal output by the interrupt loss detection unit 35 is at a high level, the loss storage unit 38 indicates, for example, a value “1” indicating the loss of a new interrupt occurrence signal according to the high level. The interrupt lost flag is stored, and a high level signal corresponding to the stored interrupt lost flag value “1” is output to the lost signal output prohibiting unit 39. In the following, it is assumed that the lost interrupt flag indicates that a new interrupt occurrence signal is lost when the value is “1”, and that a new interrupt occurrence signal is lost when the value is “0”. It shall be shown that there is not.

  Specifically, the lost storage unit 38 includes, for example, a logical sum circuit 381 and a D flip-flop circuit 382 as shown in FIG.

  The logical sum circuit 381 outputs a high level signal toward the D terminal of the D flip-flop circuit 382 when the loss detection signal output by the interrupt loss detection unit 35 is at a high level.

  For example, a clock signal CLK generated by an oscillation circuit (not shown) is input to the clock terminal of the D flip-flop circuit 382. Note that the cycle of the clock signal CLK is shorter than the pulse width of the interrupt generation signal. The D flip-flop circuit 382 stores a value corresponding to the level of the signal input from the OR circuit 381 as an interrupt loss flag in synchronization with the positive edge (rising edge) of the clock signal CLK. The D flip-flop circuit 382 outputs a signal of a level corresponding to the stored value of the lost interrupt flag to the lost signal output prohibiting unit 39 and the OR circuit 381.

  The output signal of the D flip-flop circuit 382 is fed back via the OR circuit 381 and input to the D terminal of the D flip-flop circuit 382. As a result, once the interrupt lost flag value of the D flip-flop circuit 382 becomes “1”, the interrupt lost flag value is held at “1” regardless of the level of the loss detection signal.

  The D flip-flop circuit 382 is provided with a clear terminal for setting (clearing) the value of the stored interrupt lost flag to “0”. Specifically, when the CPU 23 finishes executing the interrupt process, the lost clear signal receiving unit 42 receives a low-level lost clear signal indicating that the loss of interrupt flag is instructed. When the low level lost clear signal is input to the clear terminal, the D flip-flop circuit 382 sets the value of the stored interrupt generation flag to “0”.

  The lost signal output prohibition unit 39 sets the lost loss signal to a low level when the detection prohibition reception unit 36 receives a high level loss detection prohibition signal indicating that the detection of the loss of the interrupt occurrence signal is prohibited. Output. This prohibits the loss signal output unit 37 from outputting a high-level interrupt loss signal indicating the loss of a new interrupt occurrence signal. The lost signal output prohibiting unit 39 also sets the interrupt lost signal to low level when the permission signal receiving unit 33 receives a low level interrupt permission signal indicating that execution of interrupt processing is not permitted. Output. This prohibits the loss signal output unit 37 from outputting a high-level interrupt loss signal.

  Specifically, the lost signal output prohibiting unit 39 includes two logical product circuits 391 and 392.

  The logical product circuit 391 outputs a signal corresponding to the logical product of the interrupt permission signal received by the permission signal reception unit 33 and the signal output from the detection prohibition reception unit 36 to the logical product circuit 392. To do.

  The logical product circuit 392 outputs a signal corresponding to the logical product of the signal output from the lost storage unit 38 and the signal output from the logical product circuit 391 as an interrupt lost signal.

  For example, in the AND circuit 391, the interrupt permission signal received by the permission signal receiving unit 33 is a high level signal, and a high level loss detection prohibiting signal is input to the input terminal 361 of the detection prohibiting receiving unit 36. Thus, when a signal indicating a low level is output from the logical negation circuit 362, a low level signal corresponding to the logical product of the two signals is output to the logical product circuit 392.

  The AND circuit 391 determines whether the signal output from the detection prohibition receiving unit 36 is high level or low level when the interrupt permission signal received by the permission signal receiving unit 33 is a low level signal. Regardless of whether or not, a low level signal corresponding to the logical product of the two signals is output to the logical product circuit 392.

  As described above, when a low level signal is output from the AND circuit 391, the AND circuit 392 does not depend on whether the level of the signal output from the lost storage unit 38 is high level or low level. A low level signal corresponding to the logical product of the two signals is output as an interrupt lost signal.

  That is, according to the configuration of the present embodiment, whether or not the lost signal output unit 37 prohibits the output of the lost interrupt signal depending on whether or not the detection prohibition receiving unit 36 receives a high level loss detection prohibition signal. Can be switched. Further, whether or not the lost signal output unit 37 prohibits the output of the lost interrupt signal can also be switched depending on whether or not the permission signal receiving unit 33 receives a low-level interrupt enable signal.

  If the interrupt permission signal received by the permission signal receiving unit 33 is at a low level indicating that execution of the interrupt process is not permitted, it indicates that the interrupt process requesting unit 34 requests execution of the interrupt process. Does not output a high-level interrupt processing request signal. That is, in this case, the interrupt process is not executed, so that no new interrupt is generated until the interrupt process ends.

  Therefore, according to the configuration of the present embodiment, when the interrupt permission signal indicates that the execution of the interrupt process is not permitted, no new interrupt is generated until the interrupt process is completed. Accordingly, it is possible to prohibit the loss signal output unit 37 from outputting a high-level interrupt loss signal indicating the loss of a new interrupt occurrence signal.

  The lost signal output prohibiting unit 39 is configured to include only the AND circuit 392 without including the AND circuit 391. The AND circuit 392 includes the signal output from the lost storage unit 38, and The signal output from the detection prohibition receiving unit 36 may be input. Even in this configuration, it is possible to switch whether to prohibit the output of the lost lost signal by the lost signal output unit 37 depending on whether or not the detection prohibited receiving unit 36 receives the low level lost detection prohibited signal. it can.

  In addition, the lost signal output unit 37 is configured to include only the lost storage unit 38 without including the lost signal output prohibiting unit 39, and corresponds to the value of the interrupt lost flag output from the lost storage unit 38. The level signal may be output as it is as an interrupt lost signal output from the lost signal output unit 37.

  In this configuration, the lost loss detection unit 35 detects the loss of a new interrupt occurrence signal, and the loss storage unit 38 stores an interrupt loss flag whose value indicating the loss of the new interrupt occurrence signal is “1”. During this period, the lost signal output unit 37 outputs a high-level interrupt lost signal indicating the loss of a new interrupt occurrence signal. For this reason, the CPU 23 can deal with the interruption loss signal at an arbitrary timing in the period.

  Further, the lost signal output unit 37 does not include the lost storage unit 38 and the lost signal output prohibition unit 39, and outputs the lost detection signal output from the lost interrupt detection unit 35 as it is from the lost signal output unit 37. You may comprise so that it may output as an interruption loss signal.

  In this configuration, a new interrupt generation signal is received by the interrupt signal reception unit 31 while the interrupt generation flag whose value indicating the occurrence of an interrupt is “1” is stored in the interrupt storage unit 32. When this happens, the lost loss detection unit 35 detects the loss of the new interrupt occurrence signal. Then, when the high level loss detection signal indicating the detection of the loss of the new interrupt generation signal is output by the interrupt loss detection unit 35, the high level signal indicates the loss of the new interrupt generation signal. It is output as it is as a high-level interrupt loss signal.

  For this reason, an interrupt corresponding to a new interrupt generation signal indicated as lost due to the output lost interrupt signal was generated until the interrupt processing corresponding to a certain interrupt ended. Can be detected.

  The present invention is not limited to the configuration of the above embodiment, and various modifications can be made. For example, in the above-described embodiment, an example in which the control device according to the present invention is applied to the multifunction device 1 has been described. However, the present invention is not limited to this, and the interrupt control circuit according to the present invention may be a color printer or scanner for color image formation. The present invention may be applied to image forming apparatuses such as apparatuses, facsimile apparatuses, printer apparatuses, and copying apparatuses.

  In the above embodiment, the configurations and settings shown in FIGS. 1 to 3 are merely examples, and the present invention is not limited to the embodiment. For example, information indicated when various signals are at a high level or a low level may be configured to have a meaning opposite to that in the above embodiment. Then, the configuration of the interrupt control circuit 24 may be changed so that the same function as that of the interrupt control circuit 24 is obtained according to the meaning of the logic level of various signals.

  Specifically, for example, when the loss detection prohibition signal input to the lost signal output prohibition unit 39 is at a high level, it indicates that the detection of the loss of the interrupt generation signal is permitted. You may comprise so that the detection of the loss of a signal may be prohibited. In accordance with this, a logic negation circuit (NOT circuit) that outputs a signal indicating the logic negation of the loss detection prohibition signal is provided between the logic negation circuit 362 (FIG. 3) and the input terminal 361 (FIG. 3). Alternatively, the logical negation circuit 362 (FIG. 3) may be deleted as an equivalent configuration.

1 MFP 2 Controller 21 ROM
22 RAM
23 CPU
24 interrupt control circuit 31 interrupt signal receiving unit 32 interrupt storage unit 321 logical sum circuit 322 D flip-flop circuit 33 permission signal receiving unit 34 interrupt processing requesting unit 35 interrupt lost detection unit 36 detection prohibition receiving unit 361 input terminal 362 Logical negation circuit 37 Loss signal output unit 38 Loss storage unit 381 Logical sum circuit 382 D flip-flop circuit 39 Loss signal output prohibition unit 391 AND circuit 392 AND circuit 41 Interrupt clear signal reception unit 42 Loss clear signal reception unit

Claims (2)

An interrupt signal receiver for receiving an interrupt generation signal indicating the occurrence of an interrupt;
When the interrupt signal is received by the interrupt signal receiver, an interrupt storage unit that stores interrupt generation information indicating the occurrence of an interrupt;
Receives a high-level interrupt permission signal indicating that the execution of the interrupt process corresponding to the interrupt is permitted or a low-level interrupt permission signal indicating that the execution of the interrupt process is not permitted. An enabling signal receiving unit,
An interrupt processing request for requesting execution of the interrupt processing when the high-level interrupt permission signal is received by the permission signal receiving unit and the interrupt generation information is stored in the interrupt storage unit An interrupt processing request unit for outputting a signal;
When the interrupt generation information is stored in the interrupt storage unit and a new interrupt generation signal is received by the interrupt signal reception unit, the new interrupt generation signal is lost. An interrupt loss detection unit to detect,
When loss of the new interrupt occurrence signal is detected by the lost loss detection unit, information indicating the loss of the new interrupt occurrence signal is stored, and information indicating the loss of the new interrupt occurrence signal is stored. A lost storage unit that outputs a high-level signal indicating the loss of the new interrupt generation signal,
The interrupt permission signal received by the permission signal receiving unit is input to one end, and a first logical product corresponding to a logical product of the interrupt permission signal input to the one end and a signal input to the other end A first AND circuit for outputting a signal;
An AND circuit that outputs a second AND signal corresponding to an AND of the signal output from the lost storage unit and the first AND signal output from the first AND circuit; When the logical product signal is at a low level, the second logical product signal is output as an interrupt lost signal indicating that the new interrupt generation signal is not lost, and when the second logical product signal is at a high level A second AND circuit that outputs the second AND signal as an interrupt lost signal indicating the loss of the new interrupt generation signal;
An interrupt control circuit comprising: High loss detection prohibition signal indicating to prohibit detection of loss of the interrupt generation signal, or receives the missing detection prohibiting signal of a low level indicating the permission of the detection of the loss of the interrupt generation signal , the interrupt control circuit according to the signal indicating the logical negation of the lost detection prohibition signal received, the 請 Motomeko 1 further comprising a detection prohibition receiver to be output to the other end of said first aND circuit.

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