JP2007219837A - Interrupt control method, arithmetic unit, and image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interrupt control method and arithmetic unit for recognizing an interrupt processing request which occurs during another interrupt processing and executing the former interrupt request. <P>SOLUTION: The interrupt control method for the arithmetic unit X2 is provided with: an interrupt identification information write process 1-2 for writing interrupt identification information for an ASIC 110 to identify each of interrupt information successively written to a factor register 113; and interrupt request signal stop processes 1-3 and 1-4 for stopping outputs of the interrupt request signal on the basis of the interrupt identification information and information written by a CPU 120 to a clear register 114. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an interrupt control method, an arithmetic unit that executes the interrupt control method, and an image processing apparatus, and in particular, can recognize another interrupt processing request even if another interrupt processing request occurs during execution of a certain interrupt processing. The present invention relates to an interrupt control method and apparatus.

A conventional general interrupt control method will be described.
First, an outline of an arithmetic unit having a conventional general interrupt control method will be described.
As shown in FIG. 1, a conventional general arithmetic device X1 includes an ASIC (Application Specific Integrated Circuit) 10 that is an example of a semiconductor integrated circuit and a CPU (Central Processing Unit) that is an example of arithmetic means and executes a program. 20 and a memory 30 for storing a program executed by the CPU 20. A peripheral device such as a scanner is connected to the arithmetic device X1.
The outline of the processing performed by the arithmetic device X1 is as follows.
(1) When there is a request for interrupt processing from a peripheral device, the ASIC 10 requests the CPU 20 for interrupt processing.
(2) The CPU 20 executes interrupt processing based on the interrupt request from the ASIC 10.
(3) When the interrupt processing is completed, the CPU 20 executes processing for causing the ASIC 10 to stop the interrupt processing request.
The detailed configuration of the arithmetic device X1 is as follows.
The ASIC 10 includes an interrupt request output unit 12 that outputs an interrupt request signal to the CPU 20 of (1), a factor register 13 that is a storage element that stores interrupt information that is information about interrupts such as interrupt factors and processing contents, It comprises a clear register 14 that is a storage element for storing a flag for stopping the interrupt request signal in (3) above, and a control unit 11 that comprehensively controls them.
The initial value of the flag for stopping the interrupt request signal stored in the clear register 14 is 0.
The memory 30 stores a program for executing interrupt processing for each peripheral device, such as a program for reading data from the peripheral device.

An interrupt process executed by the arithmetic device X1 will be described. Reference numerals in parentheses () represent the number of the procedure described in FIG.
(1) When there is a request for interrupt processing from a peripheral device, the ASIC 10 requests the CPU 20 for interrupt processing.
First, an interrupt request signal is output by the peripheral device and input to the control unit 11 of the ASIC 10 (1-0). The control unit 11 writes the interrupt information (for example, interrupt information C) of the peripheral device that requested the interrupt to the factor register 13 (1-1). The interrupt information C is information related to predetermined interrupt processing contents to be executed by the CPU 20 such as executing a program C for reading data from a peripheral device stored in the memory 30.
When interrupt information is written in the cause register 13, the control unit 11 reads the flag of the clear register 14 (1-2). The initial value of the flag is “0”. If the flag stored in the clear register 14 is “0”, it is determined that the interrupt request signal stop request is not made from the CPU 20 and the interrupt request output means 12 is instructed to output the interrupt request signal. (1-3). When the controller 11 instructs the output of the interrupt request signal, the interrupt request output means 12 outputs the interrupt request signal (1-4). The output interrupt request signal is input to the CPU 20.
(2) The CPU 20 executes interrupt processing based on the interrupt request from the ASIC 10.
When an interrupt request signal is input, the CPU 20 reads the interrupt information stored in the factor register 13 of the ASIC 10 (2-1). Based on the read interrupt information, the CPU 20 executes the program stored in the memory 30 and performs interrupt processing (for example, processing for reading data from the peripheral device) (2-2).
(3) When the interrupt processing is completed, the CPU 20 executes processing for causing the ASIC 10 to stop the interrupt processing request.
When the interrupt process is completed, the CPU 20 writes “1” indicating stop of the interrupt request signal to the flag of the clear register 14 of the ASIC 10 (3-1).
Subsequently, in the ASIC 10, the controller 11 of the ASIC 10 instructs the interrupt request output means 12 to stop the interrupt request signal (3-2). In response to an instruction to stop the interrupt request signal from the control unit 11 of the ASIC 10, the output of the interrupt request signal from the interrupt request output means 12 of the ASIC 10 is stopped (3-3). Then, the control unit 11 of the ASIC 10 returns the flag of the clear register 14 to the initial value “0” (3-4).

In the image processing apparatus, such an interrupt process occurs for each band in which image data for one page used for image formation is divided into a plurality of parts.
In the image processing apparatus, a preceding drawing process is performed for a band that is considered not to finish the drawing process within the time for transferring the band information of one band.
In the data processing method described in Patent Document 1, the preceding drawing process is reduced, and the band that should be drawn in advance is processed within the limited drawing time adjusted with respect to the secured band region and is normally output. be able to.
JP-A-9-272231

Conventionally, for example, interrupt requests from semiconductor integrated circuits such as the ASIC 10 are rarely generated continuously. However, it is conceivable that interrupt requests from the same semiconductor integrated circuit are continuously generated as the arithmetic device is increased in speed. .
In this case, if another interrupt processing request is generated during execution of a certain interrupt processing, the conventional interrupt control method may not recognize the subsequent interrupt processing request for the following reason.
Specifically, the arithmetic unit X1 stores “1” indicating interruption of the interrupt request signal in the flag of the clear register 14 of the ASIC 10 without identifying the interrupt processing contents executed by the CPU 20 (3-1). ). As soon as the interrupt request signal stop flag “1” is stored in the clear register 14, the control unit 11 of the ASIC 10 does not check the factor register 13 of the ASIC 10, that is, performs another interrupt processing from the peripheral device. Without determining whether or not the request has been written (1-1), the interrupt request output means 12 is instructed to stop the interrupt request signal (3-2). In response to an instruction to stop the interrupt request signal from the control unit 11 of the ASIC 10, the output of the interrupt request signal from the interrupt request output means 12 of the ASIC 10 is stopped (3-3). Then, the control unit 11 of the ASIC 10 returns the flag of the clear register 14 to the initial value “0” (3-4).
That is, the control unit 11 of the ASIC 10 does not check the factor register 13 before stopping the interrupt request signal output (does not check the next interrupt processing request). Further, even if the cause register 13 is confirmed, a subsequent interrupt processing request is issued for two reasons that it is not possible to recognize what interrupt processing has been executed only by the flag written in the clear register 14. There were cases where it could not be recognized.
As a basic example, “interrupt processing request from the peripheral device” is set to “band transfer processing request executed when drawing processing for each band is completed”, and “interrupt processing executed by the CPU 20” is set to “image”. Considering the “band transfer processing of the processing device”, in the data processing method described in Patent Document 1, when a band drawing process ends during a certain band transfer process and a band transfer process request different from the above occurs. However, there is a problem that the other band transfer processing request is not recognized and the other band transfer processing is not executed.
In the present invention, even when another interrupt processing request is generated during execution of a certain interrupt processing, the other interrupt processing request can be recognized, and the other interrupt processing can be executed. An apparatus can be provided.

In order to achieve the above object, the present invention comprises arithmetic means (for example, a CPU) for executing interrupt processing and a semiconductor integrated circuit (for example, ASIC) for requesting the arithmetic means for interrupt processing. , A factor register which stores interrupt information used for the interrupt processing and can be referred to by the arithmetic means, an interrupt request output means for outputting an interrupt request signal to the arithmetic means, and a clear in which information is written by the arithmetic means The method is characterized in that it is applied to an interrupt control method for an arithmetic device comprising a register, and comprises the following steps (1) to (3).
(1) An interrupt identification information writing step in which the semiconductor integrated circuit writes identification information for identifying each interrupt information to be subsequently written in the factor register.
(2) The semiconductor integrated circuit stops outputting the interrupt request signal based on the comparison between the interrupt processing identification information written in the factor register and the information written in the clear register by the arithmetic means. Interrupt request signal stop process.
(3) A clear register writing step in which the arithmetic means writes the identification information of the interrupt processing stored in the factor register to the clear register after executing the interrupt processing based on the interrupt information stored in the factor register .
With the configuration as described above, the semiconductor integrated circuit can check the identification information of the interrupt process written in the factor register before stopping the interrupt request signal, and write it in the clear register by the arithmetic means. The output of the interrupt request signal can be stopped based on the comparison with the received information. Therefore, even if another interrupt processing request is generated during execution of a certain interrupt processing, the interrupt request signal is not stopped without confirming the other interrupt processing request, so that the other interrupt processing request is recognized. And another interrupt process can be executed.
Further, when the present invention is grasped as an arithmetic unit, it comprises arithmetic means for executing interrupt processing and a semiconductor integrated circuit for requesting the arithmetic means for interrupt processing, and the semiconductor integrated circuit is used for the interrupt processing. A computation comprising a factor register that stores information and can be referred to by the computing means, an interrupt request output means that outputs an interrupt request signal to the computing means, and a clear register in which information is written by the computing means An interrupt identification information writing means for writing identification information for identifying each interrupt information to be subsequently written to the factor register; and the interrupt identification information writing means in the factor register. The written identification information of the interrupt process and the arithmetic means Interrupt request signal stop means for stopping the output of the interrupt request signal based on comparison with the information written in the register, wherein the arithmetic means is configured to interrupt the interrupt based on the interrupt information stored in the cause register. After execution of the processing, it is grasped as an arithmetic unit characterized by comprising clear register writing means for writing the identification information of the interrupt processing stored in the factor register into the clear register.
With such a configuration, the semiconductor integrated circuit can check the identification information of the interrupt process written in the factor register before stopping the interrupt request signal, and is written in the clear register by the arithmetic means. The output of the interrupt request signal can be stopped based on the comparison with the information. Therefore, even if another interrupt processing request is generated during execution of a certain interrupt processing, the interrupt request signal is not stopped without confirming the other interrupt processing request, so that the other interrupt processing request is recognized. Therefore, it is possible to provide an arithmetic device capable of executing the other interrupt processing.
On the other hand, when the present invention is considered as an image processing apparatus, an arithmetic unit for executing an interrupt process and an interrupt process are requested to the arithmetic unit for each band in which image data for one page used for image formation is divided into a plurality of bands. The semiconductor integrated circuit stores interrupt information used for the interrupt processing, and outputs an interrupt request signal to the factor register that can be referred to by the arithmetic means and the arithmetic means. An image processing apparatus comprising: an interrupt request output unit; and a clear register into which information is written by the arithmetic unit, wherein the semiconductor integrated circuit identifies each interrupt information to be subsequently written to the factor register Interrupt identification information writing means for writing the identification information for the interrupt, and the interrupt processing written in the factor register. And interrupt request signal stop means for stopping the output of the interrupt request signal based on a comparison between the identification information and the information written in the clear register by the calculation means, and the calculation means includes the factor And a clear register writing means for writing the identification information of the interrupt processing stored in the factor register into the clear register after execution of the interrupt processing for each band based on the interrupt information stored in the register. It is configured as a featured image processing apparatus.
In the case of the image processing apparatus configured as described above, even if an interrupt processing request for another band occurs during execution of interrupt processing for a certain band, an interrupt request signal is sent without confirming the interrupt processing request for another band. Since it does not stop, it is possible to provide an image processing apparatus capable of recognizing the interrupt processing request of another band and executing the interrupt processing of the other band.

  According to the present invention, even when another interrupt processing request occurs during execution of a certain interrupt processing, the other interrupt processing request can be recognized and the other interrupt processing can be executed. , An arithmetic unit can be provided.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that the present invention can be understood. The following embodiment is an example embodying the present invention, and does not limit the technical scope of the present invention.
FIG. 1 is a block diagram of an arithmetic device X1 which is a conventional general arithmetic device, FIG. 2 is a block diagram of the arithmetic device X2 according to the embodiment of the present invention, and FIG. FIG. 4 is a diagram showing the determined interrupt identification information values and the order in which they should be written. FIG. 4 shows interrupt processing executed by the CPU 120 of the arithmetic unit X2 and interrupts executed by the control unit 111 of the ASIC 110 according to the embodiment of the present invention. It is a flowchart for demonstrating the example about the procedure of a control process.

First, the schematic configuration of the arithmetic device X2 according to the embodiment of the present invention will be described with reference to the block diagram of FIG.
As shown in FIG. 2, the arithmetic device X2 is an ASIC 110 that is an example of a semiconductor integrated circuit, an example of arithmetic means, a CPU 120 that executes a program, and a memory 130 that stores a program executed by the CPU 120, and the like. And is configured. A peripheral device such as a scanner is connected to the arithmetic device X2.
Here, an outline of the processing performed by the arithmetic device X2 will be described.
(1) When there is a request for interrupt processing from a peripheral device, the ASIC 110 stores interrupt information and interrupt identification information in the cause register 113, and stores the interrupt identification information stored in the clear register 114 and the interrupt identification information stored in the clear register 114. Based on the above, the CPU 120 requests and stops the interrupt process.
(2) The CPU 120 executes interrupt processing based on the interrupt request from the ASIC 110.
(3) When the interrupt processing ends, the CPU 120 executes processing for causing the ASIC 110 to stop the interrupt processing request.
In the present invention, when the interrupt request from the semiconductor integrated circuit such as the ASIC 110 is continuously generated along with the increase in the speed of the arithmetic unit, even if another interrupt process request is generated during execution of a certain interrupt process, This interrupt control method is such that the above-described interrupt processing request cannot be recognized and the problem that the other interrupt processing is not executed does not occur.
Details of the configuration of the arithmetic unit X2 are as follows.
The ASIC 110 includes an interrupt request output means 112 that outputs an interrupt request signal to the CPU 120 of (1), a factor register 113 that is a storage element that can be read by the CPU 120 and stores various information, and a write by the CPU 120. A clear register 114 which is a storage element capable of storing various types of information, and a storage unit 115 for storing a predetermined interrupt identification information value written in the factor register 113 and an order to be written (see FIG. 3). , And a control unit 111 for comprehensively controlling them.
The ASIC 110 requests the CPU 120 for interrupt processing by outputting an interrupt request signal from the interrupt request output means 112.
The factor register 113 stores interrupt information, which is information about interrupts such as interrupt factors and processing contents, and interrupt identification information for identifying interrupt processing. When there is an interrupt request from the peripheral device, the interrupt information and the interrupt identification information are rewritten according to the requested interrupt processing. Details of the rewriting process will be described later.
Here, the interrupt identification information stored in the factor register 113 is information for identifying an interrupt process requested continuously from the peripheral device. Specifically, certain interrupt information stored in the factor register 113 when an interrupt request from the peripheral device is generated and stored in the factor register 113 when another interrupt request is continuously generated from the peripheral device. This is identification information for identifying each other interrupt information (that is, the above-mentioned certain interrupt information is erased and rewritten). The interrupt identification information can be, for example, numbers or letters. As an example, the value written as the interrupt identification information is as follows. As shown in FIG. 3, when the initial value is “a”, the next value to be changed is “a”, the next is “c”, the next It is “e”, and after “e”, it returns to “a”.
The interrupt identification information is changed each time the interrupt information is written into the factor register 113 by the control unit 111 of the ASIC 110. Therefore, the same interrupt request is continuously received from the peripheral device, and the interrupt information written to the factor register 113 by the control unit 111 and the interrupt information having the same contents are newly written to the factor register 113 by the control unit 111. Even if it is, the interrupt identification information written in the factor register 113 is changed. Thus, even if the interrupt information stored in the cause register 113 is the same, if the interrupt identification information is changed, a request (the peripheral request) different from the previous request (the first interrupt request from the peripheral device) is changed. It can be identified as a subsequent interrupt request from the device.
When another interrupt information is written in the factor register 113 of the ASIC 110 during execution of the interrupt processing by the CPU 120, the interrupt identification information stored in the factor register 113 is changed. When interrupt processing is completed, whether or not there is a new interrupt processing request by comparing the interrupt identification information about the completed interrupt processing written in the clear register 114 with the interrupt identification information stored in the cause register 113 Can be determined. Details will be described later.
The clear register 114 stores interrupt identification information of interrupt processing executed by the CPU 120.
Here, the interrupt identification information stored in the clear register 114 is information for indicating an interrupt process executed by the CPU 120 described later. Specifically, the interrupt identification acquired from the factor register 113 together with the interrupt processing information related to the interrupt processing executed by the CPU 120 and temporarily stored in the memory 130 while the CPU 120 executes the interrupt processing. Information.
The initial value of the interrupt identification information stored in the clear register 114 is the same value (for example, “a”) as the initial value stored in the factor register 113.
Since the interrupt identification information stored in the factor register 113 and the interrupt identification information stored in the clear register 114 have the above-mentioned meanings, it is still requested by the peripheral device that they are different. This means that the interrupt process has not been terminated by the CPU 120. The fact that they are the same means that the CPU 120 has completed all the interrupt processing requested by the peripheral device. Therefore, if the interrupt identification information stored in the factor register 113 is different from the interrupt identification information stored in the clear register 114, an interrupt request signal is output from the interrupt request output means 112 of the ASIC 110 (or The output is not stopped.) If they are the same, the interrupt request signal is stopped. Details will be described later.
As described above, the cause register 113 and the clear register 114 store interrupt identification information, and based on these, the interrupt processing request and stop control for the CPU 120 are performed. It is a different point.
When an interrupt request signal is input from the ASIC 110, the CPU 120 acquires interrupt information and interrupt identification information stored in the cause register 113 of the ASIC 110, and stores the interrupt information and interrupt identification information in the memory 130 based on the acquired interrupt information. The program being executed is executed and interrupt processing is executed.
The memory 130 stores a program for executing an interrupt process for a request from each peripheral device, such as a program for reading data from the peripheral device. In addition, interrupt identification information acquired together with interrupt processing information related to interrupt processing executed by the CPU 120 is temporarily stored.

Here, FIG. 4A is a flowchart for explaining an example of the procedure of the interrupt processing executed by the CPU 120 of the arithmetic device X2 according to the embodiment of the present invention, and FIG. It is a flowchart for demonstrating the example about the procedure of the interrupt control process performed by the control part 111 of ASIC110 of the arithmetic unit X2 which concerns on this embodiment.
First, an example of the procedure of the interrupt control process executed by the control unit 111 of the ASIC 110 of the arithmetic device X2 according to the embodiment of the present invention will be described with reference to FIG.
In the figure, S10, S20,... Indicate process procedure (step) numbers, and the process starts from step S10.
Reference numerals in parentheses () represent the number of the procedure described in FIG.

(1) When there is a request for interrupt processing from a peripheral device, the ASIC 110 stores interrupt information and interrupt identification information in the cause register 113, and stores the interrupt identification information stored in the clear register 114 and the interrupt identification information stored in the clear register 114. Based on the above, the CPU 120 requests and stops the interrupt process.
In step S10, the control unit 111 determines whether or not there is an interrupt request from the peripheral device. When an interrupt request signal is input by the peripheral device (1-0), it is determined that there is an interrupt request by the peripheral device (Yes side of step S10), and the process proceeds to step S20.

In step S20, the control unit 111 writes the interrupt information (for example, interrupt information A) of the peripheral device that requested the interrupt to the factor register 113 (1-1). The interrupt information A is information related to predetermined interrupt processing contents to be executed by the CPU 120, such as executing the program A (a program for reading data from the peripheral device) stored in the memory 130, for example. is there.
Subsequently, in conjunction with the writing of the interrupt information A into the factor register 113 by the control unit 111, interrupt identification information is stored in the storage unit 115 as predetermined interrupt identification information. And the order to be written (see FIG. 3) (1-2), the process proceeds to step S30. For example, if the interrupt identification information stored in the cause register 113 is the initial value “a”, FIG. 3 is referred to, and the value is changed to “a”, which is the next value after “a”. Here, although the interrupt identification information is a character, for example, numbers such as “1”, “2”, and “3” may be sequentially written.
The reason why the interrupt information itself is not identified is that the interrupt information is the contents of the interrupt processing, and therefore cannot be identified when there is a continuous request for the same interrupt processing.
Here, the control unit 111 that executes a process of writing the interrupt identification information to the factor register 113 each time the interrupt information of the peripheral device that requested the interrupt is written to the factor register 113 corresponds to an example of the interrupt identification information writing unit. To do.
A process of writing interrupt identification information to the factor register 113 each time interrupt information of a peripheral device that has requested an interrupt is written to the factor register 113 corresponds to an example of an interrupt identification information writing process.

In step S30, the interrupt identification information stored in the factor register 113 and the interrupt identification information stored in the clear register 114 are compared, and the control unit 111 determines whether or not they are the same. An instruction relating to interrupt request signal control output from the request output means 112 is determined (1-3).
As will be described later, when the interrupt processing of the interrupt information stored in the factor register 113 has not yet been executed by the CPU 120, the control unit 111 causes the interrupt identification information ( For example, it is determined that the interrupt identification information = “I”) and the interrupt identification information stored in the clear register 114 (for example, interrupt identification information = initial value “A”) are different. In this case, the interrupt request output means 112 is instructed to output an interrupt request signal (Yes in step S30), and the process proceeds to step S40.
As will be described later, after the interrupt processing of the interrupt information stored in the factor register 113 is executed by the CPU 120, the control unit 111 causes the interrupt identification information ( For example, it is determined that the interrupt identification information = “I”) and the interrupt identification information stored in the clear register 114 (for example, interrupt identification information = “I”) are the same. In this case, an interrupt request signal output stop instruction is issued to the interrupt request output means 112 (No side of step S30), and the process proceeds to step S50.

  In step S40, the control unit 111 outputs an interrupt request signal from the interrupt request output means 112 (1-4), the process returns to step S30, and then it is determined that the interrupt identification information is the same. That is, the interrupt request signal continues to be output until an instruction to stop outputting the interrupt request signal is issued.

In step S50, the control unit 111 stops outputting the interrupt request signal output from the interrupt request output means 112 (1-5).
Here, based on the comparison between the interrupt identification information written in the factor register 113 by the control unit 111 and the interrupt identification information written in the clear register 114 by the CPU 120 as described later, the interrupt request signal The control unit 111 that executes the process of stopping the output corresponds to an example of an interrupt request signal stop unit.
The output of the interrupt request signal is stopped based on a comparison between the interrupt identification information written in the factor register 113 by the control unit 111 and the interrupt identification information written in the clear register 114 by the CPU 120 as will be described later. This process corresponds to an example of an interrupt request signal stop process.
Thus, by comparing the interrupt identification information stored in the cause register 113 with the interrupt identification information stored in the clear register 114 (1-3), an interrupt request from the ASIC 110 to the CPU 120 is obtained. The ability to control the signal (1-4, 1-5) is different from the conventional general interrupt control method.

(2) The CPU 120 executes interrupt processing based on the interrupt request from the ASIC 110.
Next, FIG. 4A illustrates an example of an interrupt processing procedure executed by the CPU 120 of the arithmetic device X2 according to the embodiment of the present invention.
In the figure, S100, S110... Indicate processing procedure (step) numbers, and the processing starts from step S100.
In step S100, the CPU 120 determines whether an interrupt request signal has been input. When the interrupt request signal output by the interrupt request output means 112 of the ASIC 110 is input to the CPU 120, the CPU 120 determines that the interrupt request signal has been input (Yes in step S100), and the processing is performed in step S110. It is transferred to.
When the output of the interrupt request signal is stopped by the interrupt request output means 112 of the ASIC 110, the CPU 120 determines that the interrupt request signal is not input, and waits until the interrupt request signal is input.

In step S110, the CPU 120 causes the interrupt information (for example, interrupt identification information A) stored in the cause register 113 of the ASIC 110 (changed in conjunction with the writing of the interrupt information to the cause register). Interrupt identification information (for example, “I”) is acquired (2-1). The acquired interrupt information and interrupt identification information are temporarily stored in the memory 130, and the process proceeds to step S120.
In step S120, the CPU 120 executes the program stored in the memory 130 based on the interrupt information temporarily stored in the memory 130, and performs interrupt processing (2-2). The process proceeds to step S130.

(3) When the interrupt processing ends, the CPU 120 executes processing for causing the ASIC 110 to stop the interrupt processing request.
In step S130, the CPU 120 writes the interrupt identification information temporarily stored in the memory 130 into the clear register 114 of the ASIC 110 (3-1). For example, if the interrupt information of the executed interrupt process, that is, the interrupt information stored in the memory 130 is the interrupt information A and the interrupt identification information stored in the memory 130 is “I”, the clear register The interrupt identification information 114 is changed to “I”, and the process ends.
That is, while the interrupt processing is executed by the CPU 120, if there is no new interrupt processing request from the peripheral device, the interrupt identification information stored in the factor register 113 of the ASIC 110 is not changed, that is, the memory 130 is not changed. It remains the same as the stored interrupt identification information, and the interrupt identification information written to the clear register 114 by the CPU 120 is also the same. This is because the interrupt identification information stored in the cause register 113 and the interrupt stored in the clear register 114 are executed after the interrupt processing of the interrupt information stored in the cause register 113 is executed by the CPU 120. This means that the identification information is the same.
On the other hand, while the interrupt processing is being executed by the CPU 120, if there is a new interrupt processing request from the peripheral device, the interrupt identification information stored in the factor register 113 of the ASIC 110 is changed (for example, “I "→" U "). That is, the value is different from the interrupt identification information (here “a”) stored in the memory 130, and is different from the interrupt identification information (here “a”) written to the clear register 114 by the CPU 120. It becomes the value of. If the interrupt processing of the interrupt information stored in the factor register 113 is not yet executed by the CPU 120, the interrupt identification information stored in the factor register 113 and the clear register 114 are stored. This means that the interrupt identification information is different.
Here, the interrupt identification information acquired from the factor register 113 and temporarily stored in the memory 130 is written to the clear register 114 after execution of interrupt processing based on the interrupt information stored in the factor register 113. The CPU 120 that executes the process corresponds to an example of a clear register writing unit.
Writing the interrupt identification information acquired from the factor register 113 and temporarily stored in the memory 130 into the clear register 114 after execution of interrupt processing based on the interrupt information stored in the factor register 113; This corresponds to an example of a clear register writing process.
As described above, when the CPU 120 writes the interrupt identification information to the clear register 114, the ASIC 110 performs the processing after the step S30.

As described above, the interrupt request signal from the ASIC 110 to the CPU 120 is controlled by comparing the interrupt identification information stored in the factor register 113 with the interrupt identification information stored in the clear register 114. This is different from the conventional general interrupt control method. And providing an arithmetic unit capable of recognizing the other interrupt processing request and executing the other interrupt processing even if another interrupt processing request occurs during execution of the interrupt processing. it can.
When the band transfer processing of a band in which image data for one page used for image formation, which is executed in the image processing apparatus is divided into a plurality of parts, is replaced with the above interrupt processing, the above interrupt control is performed. The method can also be applied to an image processing apparatus including a CPU that executes interrupt processing and an ASIC that requests the CPU for interrupt processing for each band.

The block diagram of the arithmetic unit X1 which is a conventional general arithmetic unit. The block diagram of the arithmetic unit X2 which concerns on embodiment of this invention. The figure which shows the value of the predetermined | prescribed interruption identification information written in the factor register | resistor 113, and the order which should be written. The flowchart for demonstrating the example about the procedure of the interrupt process performed by CPU120 of the arithmetic unit X2 which concerns on embodiment of this invention, and the interrupt control process performed by the control part 111 of ASIC110.

Explanation of symbols

10, 110 ... ASIC
11, 111... Control unit 12, 112... Interrupt request output means 13, 113... Factor register 14, 114.
30, 130 ... memory

Claims (3)

Comprising arithmetic means for executing interrupt processing, and a semiconductor integrated circuit for requesting interrupt processing to the arithmetic means,
The semiconductor integrated circuit stores interrupt information used for the interrupt processing and can be referred to by the arithmetic means, an interrupt request output means for outputting an interrupt request signal to the arithmetic means, and the arithmetic means An interrupt control method for an arithmetic unit comprising a clear register to which information is written,
An interrupt identification information writing step in which the semiconductor integrated circuit writes identification information for identifying each interrupt information to be subsequently written to the factor register;
An interrupt request for stopping output of the interrupt request signal based on a comparison between the interrupt processing identification information written in the factor register and information written in the clear register by the arithmetic means by the semiconductor integrated circuit. A signal stop process;
A clear register writing step for writing identification information of the interrupt processing stored in the factor register to the clear register after the arithmetic means executes the interrupt processing based on the interrupt information stored in the factor register;
An interrupt control method for an arithmetic device, comprising: Comprising arithmetic means for executing interrupt processing, and a semiconductor integrated circuit for requesting interrupt processing to the arithmetic means,
The semiconductor integrated circuit stores interrupt information used for the interrupt processing and can be referred to by the arithmetic means, an interrupt request output means for outputting an interrupt request signal to the arithmetic means, and the arithmetic means An arithmetic unit comprising a clear register to which information is written,
The semiconductor integrated circuit writes identification information for identifying each interrupt information to be subsequently written into the factor register, and the interrupt identification information writing means for writing the interrupt information written in the factor register by the interrupt identification information writing means. Interrupt request signal stop means for stopping output of the interrupt request signal based on a comparison between processing identification information and information written in the clear register by the arithmetic means;
The arithmetic means comprises clear register writing means for writing the identification information of the interrupt processing stored in the factor register into the clear register after execution of interrupt processing based on the interrupt information stored in the factor register. An arithmetic unit characterized by comprising: Comprising arithmetic means for executing interrupt processing, and a semiconductor integrated circuit for requesting interrupt processing to the arithmetic means for each band in which image data for one page used for image formation is divided into a plurality of bands. , Interrupt information used for the interrupt processing, a factor register that can be referred to by the arithmetic means, an interrupt request output means for outputting an interrupt request signal to the arithmetic means, and information is written by the arithmetic means An image processing apparatus comprising a clear register,
The semiconductor integrated circuit writes interrupt identification information writing means for writing identification information for identifying each interrupt information to be subsequently written to the factor register, the interrupt processing identification information written to the factor register, and the calculation Interrupt request signal stop means for stopping output of the interrupt request signal based on comparison with information written to the clear register by the means,
Clear register write in which the arithmetic means writes the identification information of the interrupt processing stored in the factor register to the clear register after executing the interrupt processing for each band based on the interrupt information stored in the factor register An image processing apparatus comprising: means.

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