JP2010122813A - Information processing apparatus, integrated circuit device, electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus and the like, which suppress increase of circuit scale of hardware and a processing load of a processing execution unit, and have interrupt processing corresponding even to multiple interruption. <P>SOLUTION: The information processing apparatus 10 includes: a priority setting register 51 holding priorities of a plurality of interrupt requests 20; a current priority register 52 holding a current priority; a request source information register 53 holding information of an IRQ request source; an interrupt control unit 60; and a processing execution unit 70. The interrupt control unit 60 determines an interrupt request 20 satisfying a predetermined standard as being made from an IRQ request source, writes a priority and a unique identification number of the IRQ request source into the request source information register 53, and if the priority of the request source information register 53 is higher than the current priority, outputs an IRQ 30. The processing execution unit 70, if it receives the IRQ 30, performs processing corresponding to the unique identification number of the IRQ request source held in the request source information register 53. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing device, an integrated circuit device, an electronic device, and the like.

  In an interrupt process for a process execution unit included in an information processing apparatus or the like, there are cases where there are only a single interrupt request signal (hereinafter referred to as “IRQ”) for a process execution unit while there are many interrupt factors. .

  Such a case can be dealt with by checking the interrupt flag register corresponding to the state of the interrupt request by software (program) and executing the interrupt processing according to the priority order. However, when there are a large number of interrupt factors, identifying the interrupt factors only by software and further determining the priority order causes a problem that the time required for a series of processing for the interrupts increases.

  For this reason, for the purpose of shortening the processing time, an interrupt factor and a priority order are also determined by hardware (interrupt control unit). However, since the circuit scale increases with an increase in interrupt factors, certain restrictions arise from the cost aspect.

Therefore, a method has been proposed in which determination processing is performed by hardware only for a part of interrupt factors having a high priority (see Document 1).
JP-A-2005-85056

  However, when hardware processing is performed for some interrupt requests with high priority, it is difficult to flexibly change priority settings during processing for interrupts.

  The object of the present invention has been made in view of the above problems. According to some aspects of the present invention, even when there are a large number of interrupt factors, the increase in the circuit scale of the hardware and the processing burden on the processing execution unit (time required for determination of interrupt factors and the like, setting for each interrupt factor, etc.) It is possible to provide an information processing device, an integrated circuit device, an electronic device, and the like having a flexible interrupt processing function that supports multiple interrupts.

(1) The present invention
An information processing apparatus, an interrupt control unit, a processing execution unit, a priority setting register that holds priority levels of a plurality of interrupt requests in correspondence with unique identification numbers assigned to the interrupt requests, and the processing A current priority register that holds the current priority set by the execution unit; and a request source information register that holds request source information including a unique identification number of the IRQ request source. The interrupt control unit includes the priority control unit Referencing the information in the frequency setting register, determining the IRQ request source based on the priority of the interrupt request requesting the interrupt to the processing execution unit, writing the request source information in the request source information register, If the priority of the IRQ request source is higher than the current priority, an IRQ is output, and when the IRQ is received, the process execution unit is held in the request source information register Serial performs a process corresponding to the IRQ request source of unique identification number.

  According to the present invention, even when there are a large number of interrupt factors, an increase in the hardware circuit scale and the processing load on the processing execution unit can be suppressed, and multiple interrupts can be flexibly handled.

(2) The request source information of this information processing apparatus is
The priority of the IRQ request source may be included. In this case, the interrupt control unit of the information processing apparatus may write the priority of the IRQ request source in the request source information register.

(3) The interrupt control unit of this information processing device
An interrupt request having the highest priority may be determined as the IRQ request source.

(4) The interrupt control unit of this information processing apparatus
The IRQ request source may be determined based on the unique identification number in addition to the priority.

(5) The processing execution unit of this information processing apparatus
When the IRQ is received, the priority of the IRQ request source held in the request source information register may be written in the current priority register.

(6) The processing execution unit of this information processing apparatus
At the end of the process corresponding to the unique identification number of the IRQ request source, the past priority value held in the current priority register before receiving the IRQ that requested the process is written to the current priority register. But you can.

(7) The processing execution unit of this information processing device
The history information of the value held in the current priority register may be stored, and the past priority value may be written in the current priority register based on the history information.

(8) The processing execution unit of this information processing apparatus
A value having a lower priority than any priority value held in the priority setting register may be set in the current priority register.

(9) The present invention
An integrated circuit device including any of the information processing devices described above may be used.

(10) The present invention
An electronic device including the integrated circuit device described above may be used.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments. In addition, the information processing apparatus according to the present invention includes a combination of the following embodiments and modifications.

1. Information processing equipment (integrated circuit equipment)
FIG. 1 is a configuration diagram of an information processing apparatus according to the present embodiment. The information processing apparatus 10 may be included in an integrated circuit device.

  The information processing apparatus 10 includes a priority setting register 51 that holds the priorities of the plurality of interrupt requests 20 in correspondence with the unique identification numbers assigned to the interrupt requests 20 and the current priority set by the processing execution unit 70. , A request source information register 53 that stores request source information including the unique identification number of the IRQ request source, an interrupt control unit 60, and a process execution unit 70. For convenience of explanation, a function hierarchy including the registers 51 to 53 is referred to as a register unit 50.

  The interrupt request 20 is an interrupt request from a plurality of interrupt factors to the processing execution unit 70 and is input to the interrupt control unit 60. An IRQ (Interrupt ReQuest) 30 is output from the interrupt control unit 60 to the processing execution unit 70.

  The register unit 50 may further include an IRQ enable setting register 54 (see FIG. 7D) that sets permission / non-permission of interrupt processing for each of the plurality of interrupt requests 20. In the embodiment described later, the plurality of interrupt requests 20 are premised on maskable (cancellation is possible) interrupts. However, in the present invention, non-maskable (cannot be prohibited) interrupts may be mixed. Note that the register unit 50 may be included in the interrupt control unit 60, and some of the priority setting register 51, the current priority register 52, the request source information register 53, and the IRQ enable setting register 54 are interrupt control units. 60 may be included.

  The priority setting register 51 (see FIG. 7A) indicates the priority of the plurality of interrupt requests 20 (see FIG. 7A) 902 and the unique identification number assigned to the interrupt request 20 (see FIG. 7A). 901). Here, the priority is a numerical value representing the priority of processing for a plurality of interrupt requests 20. As for the priority, as in the embodiment described later, the higher the number, the higher the processing priority may be, and vice versa. (In the description of the embodiments below, the larger number is the higher priority.) Here, when the number of priorities (level) is greater than or equal to the number of interrupt requests 20, the individual number Although different priorities can be given to interrupt requests, the circuit scale of hardware for performing comparison processing with a current priority, which will be described later, comparison processing between a plurality of interrupt requests, and the like increases. Therefore, the number of priorities may be premised on the number of interrupt requests 20 or less. For example, in the embodiment described later, the number of priorities is four. The hardware circuit scale increases as compared with the case where the priority is determined only by software, but the number of priorities can be selected so that the increase is within the allowable range. That is, by selecting a number of priorities that is smaller than the number of interrupt requests 20, it is possible to suppress an increase in hardware scale that accompanies an increase in the number of interrupt factors.

  When a plurality of interrupt requests having the same priority are generated, the IRQ request source may be determined based on, for example, a unique identification number assigned to the interrupt request as described later. The unique identification number is a unique number assigned to each of the plurality of interrupt requests 20 and is used to distinguish a specific interrupt request from other interrupt requests. A unique number as a unique identification number may be attached to each interrupt request, or a unique character or symbol may be used.

  The current priority register 52 (see FIG. 7B) is a register that holds the current priority (see 903 in FIG. 7B) set by the process execution unit 70. Here, the current priority indicates a priority at which the process execution unit 70 permits the current IRQ 30 to be generated. The priority written in this register is the same as that described in the description of the priority setting register 51. The current priority held in the current priority register 52 is used as a judgment material when the interrupt control unit 60 outputs the IRQ 30. The process execution unit 70 may rewrite the current priority held in the current priority register 52 as appropriate. The process execution unit 70 can indirectly control the output / suppression of the IRQ 30 by the interrupt control unit 60 by designating the current priority. As will be described later, for example, if the process execution unit 70 writes “2” in the current priority register 52, the IRQ 30 is generated when the priority of the IRQ request source is “3” or higher, and the priority is “3”. <IRQ30 is suppressed (multiple interrupts). Further, the processing execution unit 70 may not accept the IRQ 30 regardless of the priority by writing the highest priority value held in the priority setting register 51 into the current priority register 52 (multiple interrupts). Ban). In this way, the processing execution unit 70 can flexibly cope with multiple interrupts by rewriting the current priority held in the current priority register 52.

  The request source information register 53 (see FIG. 7C) is a register that holds request source information of an IRQ request source. The request source information includes at least the unique identification number of the IRQ request source (see FIG. 7C) 904. Here, since the priority of the IRQ request source can be obtained from the priority setting register 51, it may not be included in the request source information. However, as in the embodiment described later, when the current priority is written in the current priority register 52, the process execution unit 70 may refer to the priority of the IRQ request source. At this time, rather than the process execution unit 70 obtaining the priority from the priority setting register 51 using the unique identification number as an index, the process is executed when the priority is obtained at the same time when the unique identification number of the IRQ request source is obtained. The processing load on the unit 70 can be reduced. Therefore, the request source information may include the priority of the IRQ request source, and the interrupt control unit 60 may also write the priority of the IRQ request source (see 905 in FIG. 7C) in the request source information register. (In the following description, it is assumed that the request source information includes the priority of the IRQ request source, and the request source information register 53 includes the unique identification number and priority of the IRQ request source.) Incidentally, there are a plurality of IRQ request sources. This interrupt request 20 is determined by the interrupt control unit 60 based on the priority (in addition to the unique identification number if necessary), and indicates a direct cause of the occurrence of the IRQ 30. Since the interrupt control unit 60 writes to the request source information register 53, the processing execution unit 70 may be a read-only register. Since the request source information register 53 holds the unique identification number of the IRQ request source (see FIG. 7 (C) 904), the process execution unit 70 receives the IRQ 30 and immediately executes interrupt processing corresponding to the unique identification number. It can be performed. Further, the processing execution unit 70 does not have to perform the comparison determination work based on the priority order, so that the processing load is reduced. Therefore, the time required for a series of processing for the interrupt is reduced.

  The interrupt control unit 60 refers to the information in the priority setting register 51, determines the IRQ request source based on the priority of the interrupt request 20 requesting the interrupt to the processing execution unit 70, and determines the IRQ request source. The priority and unique identification number are written into the request source information register 53, and if the priority of the request source information register 53 is higher than the current priority, the IRQ 30 is output.

In the determination of the IRQ request source, an interrupt request that satisfies a predetermined criterion using priority may be determined as an IRQ request source from among a plurality of interrupt requests 20 requesting an interrupt to the processing execution unit 70. For example, the predetermined reference may have the highest priority. When there are a plurality of interrupt requests that satisfy a predetermined criterion, another predetermined criterion may be added. For example, the IRQ request source may be determined using a unique identification number assigned to each interrupt request of the plurality of interrupt requests 20. The interrupt request that appears first when the unique identification numbers are arranged in ascending order as in an embodiment to be described later may be determined as the IRQ request source, or in reverse order. (In the description of the following embodiment, when there are a plurality of interrupt requests that satisfy a predetermined criterion in priority, the one that appears first when the unique identification numbers are arranged in ascending order is determined as the IRQ request source. .)
The interrupt control unit 60 writes the determined unique identification number and priority of the IRQ request source in the request source information register 53. The priority and unique identification number of the IRQ request source are obtained from information in the priority setting register 51 when determining the IRQ request source. The timing of writing to the request source information register 53 may be any time, every time the IRQ request source is changed, or in accordance with an instruction from the processing execution unit 70.

The output of the IRQ 30 is determined by comparing the current priority (held in the current priority register 52) with the priority of the IRQ request source (held in the request source information register 53). For example, when the priority of the IRQ request source is higher than the current priority, the IRQ 30 may be output (generated), and when the priority is the same or lower, the IRQ 30 may be suppressed (not generated). If IRQ30 is higher than or equal to the current priority and IRQ30 is output and the priority is low, IRQ30 may be suppressed. (In the description of the following embodiment, it is assumed that the IRQ 30 is output when the priority of the IRQ request source is higher than the current priority as in the former.)
When receiving the IRQ 30, the process execution unit 70 performs a process corresponding to the unique identification number of the IRQ request source held in the request source information register 53. The processing execution unit 70 may be a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). For example, when the process execution unit 70 is a CPU, the process corresponding to the unique identification number of the IRQ request source refers to the interrupt vector when receiving the IRQ 30, and an address corresponding to the identified unique identification number of the IRQ request source. Branching to where the interrupt service routine is executed to return to the original processing.

2. IRQ Occurrence Determination Method FIG. 2 is a diagram illustrating an IRQ occurrence determination method in the information processing apparatus according to the present embodiment. In the IRQ occurrence determination, the interrupt control unit 60 performs the processes of S20 and S30 described later. Further, the interrupt control unit 60 may perform processes of S10A to S10C described later. In the present embodiment, in the determination of the IRQ request source, the predetermined criterion for priority may be that having the highest priority. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  Interrupt requests 20A, 20B, and 20C are interrupt requests issued from different interrupt factors A, B, and C, respectively.

  In the present embodiment, an IRQ enable setting register 54 may be included. The IRQ enable setting register 54 can designate permission (Enable) or non-permission (Disable) of interrupt generation for each of the interrupt requests 20A, 20B, and 20C (see FIG. 7D 907). In the present embodiment, the IRQ enable determinations S10A, S10B, and S10C for the interrupt requests 20A, 20B, and 20C may be performed. The IRQ enable determinations S10A, S10B, and S10C transmit the interrupt request to the subsequent IRQ request source determination S20 if the interrupt generation is permitted from the IRQ enable setting register 54, and if the interrupt generation is not permitted, the subsequent IRQ request source An interrupt request is not transmitted to the determination S20. In the example of FIG. 2, since the interrupt generation is enabled from the IRQ enable setting register 54 for the IRQ enable determinations S10A and S10B, the factor A interrupt request 20A and the factor B interrupt request 20B are changed to the IRQ request source determination S20. To be told. On the other hand, since the IRQ enable determination register S10C is disabled from the IRQ enable setting register 54, the cause C interrupt request 20C is masked and is not transmitted to the IRQ request source determination S20.

  In the present embodiment, the IRQ request source may be determined in the IRQ request source determination S20. When there is an interrupt request, the IRQ request source determination S20 receives the priority of the interrupt request from the priority setting register 51, and determines the IRQ request source according to a predetermined standard. In the example of FIG. 2, the priority (A priority) of the factor A interrupt request 20A read from the priority setting register 51 and the priority (B priority) of the factor B interrupt request 20B are “0” and “ 1 ”. In the IRQ request source determination S20, the IRQ request source is determined to be the factor B interrupt request 20B, assuming that the higher priority is the higher priority.

  After the IRQ request source is determined in the IRQ request source determination S20, the priority of the IRQ request source and the unique identification number in the request source information register 53 are updated when convenient for the information processing apparatus of the present embodiment. In the example of FIG. 2, the priority of the IRQ request source in the request source information register 53 is updated to “1” (B priority) that is the determination result of the IRQ request source determination S20. Further, the unique identification number of the IRQ request source in the request source information register 53 is also updated to “B” which is the determination result of the IRQ request source determination S20.

  In the present embodiment, determination of output / suppression (occurrence / non-occurrence) of the IRQ 30 may be performed in the current priority determination S30. The current priority determination S30 receives the priority of the IRQ request source from the request source information register 53, receives the current priority from the current priority register 52, and compares these to determine output / suppression of the IRQ 30. . In the example of FIG. 2, the priority of the IRQ request source is “1”, and the current priority is “0”. Since the priority of the IRQ request source is higher than the current priority, the IRQ 30 is generated for the processing execution unit 70.

3. IRQ Occurrence Determination Method When Priority is Same FIG. 3 is a diagram showing an IRQ occurrence determination method in the information processing apparatus of the present embodiment. In the IRQ occurrence determination, the interrupt control unit 60 performs the processes of S20 and S30. Further, the interrupt control unit 60 may perform the processes of S10A to S10C. In the present embodiment, the IRQ request source may be determined based on the unique identification number in addition to the priority. The same components as those in FIG. 2 are denoted by the same reference numerals and description thereof is omitted.

  In the example of FIG. 3, since the IRQ enable setting register 54 enables interrupt generation for the IRQ enable determinations S10A, S10B, and S10C, the factor A interrupt request 20A, the factor B interrupt request 20B, and the factor C interrupt are enabled. The request 20C is transmitted to the IRQ request source determination S20.

  When there is an interrupt request, the IRQ request source determination S20 receives the priority of the interrupt request from the priority setting register 51, and determines the IRQ request source according to a predetermined standard. Here, if the predetermined criterion is to have the highest priority, the IRQ request source cannot be determined when there are a plurality of interrupt requests having the highest priority. At this time, in addition to the predetermined reference, an interrupt request whose unique identification number satisfies another predetermined reference may be set as the IRQ request source. The predetermined reference in the unique identification number may be, for example, determining the interrupt request that appears first when the unique identification numbers are arranged in ascending order as the IRQ request source. In the example of FIG. 3, the priority (A priority) of the factor A interrupt request 20A read from the priority setting register 51, the priority (B priority) of the factor B interrupt request 20B, and the factor C interrupt request 20C The priorities (C priorities) are “0”, “1”, and “1”, respectively. In this case, the priority of the factor B interrupt request 20B and the priority of the factor C interrupt request 20C have the same priority, and there is no single IRQ request source. If the interrupt request that appears first when the unique identification numbers are arranged in ascending order is the IRQ request source, the unique identification number “B” of the factor B interrupt request 20B is the unique identification number “C” of the factor C interrupt request 20C. Since it is ahead, the IRQ request source is determined to be the factor B interrupt request 20B.

  For the current priority determination S30, the same determination as in the case of FIG. 2 is performed, but in the example of FIG. 3, the current priority register 52 holds 1 as the value of the current priority. Since the priority of the IRQ request source is not greater than the current priority, the IRQ 30 is suppressed and the IRQ 30 is not generated for the processing execution unit 70.

4). Multiple Interrupts FIG. 4 is a diagram illustrating an example of control of multiple interrupts in the information processing apparatus according to the present embodiment. The process execution unit may control multiple interrupts as in this embodiment. In the case of multiple interrupts, when an interrupt request with a higher priority occurs during the process corresponding to the unique identification number of a certain interrupt request, the process corresponding to the unique identification number of the interrupt request with a higher priority is started. In the present embodiment, when the IRQ is received, the priority of the IRQ request source held in the request source information register may be written in the current priority register. Further, in the present embodiment, at the end of the process corresponding to the unique identification number of the IRQ request source, the past priority value held in the current priority register before receiving the IRQ that requested the process is You may write to the current priority register. At this time, the history information of the value held in the current priority register may be stored, and the past priority value may be written in the current priority register based on the history information. Also, a value having a lower priority than any priority value held in the priority setting register may be set in the current priority register in an initial state of the information processing apparatus or a state where no interrupt request is made.

  In this embodiment, a value having a lower priority than any priority value held in the priority setting register is expressed as “−1” (minus 1). In an actual information processing apparatus, this may be a value in which all the bits are 1 (minus 1 in 2's complement), or an arbitrary number that can be expressed but assigned as a priority is assigned. Also good. In the present embodiment, when “−1” is displayed as the priority of the request source information register, there is no interrupt request. In addition, when “−1” is written in the current priority register, an IRQ is generated regardless of any interrupt request. In the present embodiment, “−1” may also be displayed as the unique identification number of the request source information register when there is no interrupt request. The method of expression in the actual information processing apparatus is the same as in the case of priority.

  In the example of FIG. 4, it is assumed that there are four interrupt requests caused by factors A to D. The four signals from the top of FIG. 4 indicate the implementation status of the processing corresponding to the unique identification numbers (A, B, C, D) of the IRQ request source. The priorities are assumed to be factor A = 0, factor B = 1, factor C = 2, and factor D = 3. A request source information register (separated by unique identification number and priority), a current priority register, and a signal indicating an IRQ occurrence state are shown. In the example of FIG. 4, the unique identification number of the request source information register when there is no interrupt request is expressed by “X” instead of “−1”. The scene where multiple interrupts are executed will be described below.

  Initially, the value of the current priority register is set to “−1” for accepting all interrupt requests (950). The request source information register displays a unique identification number “X” and a priority “−1” indicating that there is no interrupt request.

  Here, when the factor A interrupt request is generated, the value of the request source information register changes to the unique identification number “A” (951) and the priority “0” (952). At this time, since the value of the current priority register is “−1”, the priority of the IRQ request source is higher and an IRQ is generated (I1). Upon receiving the IRQ, the process execution unit starts a process corresponding to the factor A interrupt request. Then, in order to accept only an interrupt request having a higher priority than the factor A currently being processed (priority “0”), the process execution unit writes “0” in the current priority register (953).

  Next, a factor B interrupt request having a higher priority than the factor A currently being processed is generated. Then, IRQ (I2) is generated, and the process execution unit interrupts the process corresponding to the factor A interrupt request and starts the process corresponding to the factor B interrupt request (J1). Then, in order to accept only an interrupt request having a higher priority than the factor B currently being processed (priority “1”), the process execution unit writes “1” in the current priority register (954).

  The same applies when a factor C interrupt request with a higher priority than the factor B currently being processed occurs, and also when a factor D interrupt request occurs during processing corresponding to the factor C interrupt request. (Interrupt occurrence ... I3, I4, change in interrupt processing ... J2, J3).

  As described above, when the process execution unit receives the IRQ, the priority of the interrupt request can be easily considered by simply writing the priority of the IRQ request source held in the request source information register to the current priority register. Multiple interrupts can be performed.

  Then, the processing corresponding to the interrupt request of the factor D having the highest priority is ended first among the interrupt requests of all factors. Then, the process corresponding to the interrupt request of the factor C that was executed before the process corresponding to the interrupt request of the factor D is resumed (J4). At this time, the current priority is 3 due to the interrupt request of the factor D (955). Therefore, it is necessary to set the current priority to 2 so that the processing corresponding to the interrupt request of factor C (priority = 2) allows multiple interrupts.

  The value to be set for the current priority is held in the current priority register before receiving the IRQ requesting the completed interrupt process (process corresponding to the factor D) (during execution of the process corresponding to the factor C). Value (hereinafter referred to as “past priority”). In order to allow multiple interrupts, for example, the process execution unit may read the priority value of the IRQ request source in the request source information register and write it again in the current priority register (W1). However, in order to guarantee a complete return to the state before receiving the IRQ that requested the completed interrupt processing (processing corresponding to the factor D) (during execution of the processing corresponding to the factor C), the past priority May be stored before execution of multiple interrupts, and the value of the past priority may be written to the current priority register at the end of the interrupt process (process corresponding to the factor D) (W2). For example, for the sake of efficiency, the current priority register value is saved (pushed) in the stack area each time multiple interrupts are executed, and the information is taken out (popped) after completion of interrupt processing. It is also possible to have a function of acquiring the past priority value and writing it in the current priority register.

  Similarly, when the process corresponding to the factor C interrupt request is completed, the process corresponding to the factor B interrupt request is resumed (J5), and when the process corresponding to the factor B interrupt request is completed, the factor A interrupt is resumed. Processing corresponding to the request is resumed (J6). When the processing corresponding to all interrupt requests is completed, the values of the request source information register and the current priority register return to the initial state.

  Here, in the example of FIG. 4, the pulse width of the IRQ (I1 to I4) is linked to the time when the priority of the IRQ request source is higher than the value of the current priority register, but can be recognized by the processing execution unit. It may be a pulse having a shorter width in the range, or may be a pulse having a longer width in a range in which multiple interrupts are correctly performed.

  FIG. 8 shows an example of a conventional information processing apparatus 1010 that does not have a current priority register or the like. In order to realize multiple interrupts in this conventional information processing apparatus 1010, it is necessary to set the IRQ enable setting register 1054 for all the interrupt factors before starting the processing corresponding to the interrupt request 1020. Further, since the determination is made by the process execution unit 1070, the load on the process execution unit 1070 is large, resulting in a decrease in processing time. The method for controlling multiple interrupts in the information processing apparatus according to the present embodiment can be dealt with only by rewriting the current priority register without performing special judgment processing even when nesting becomes deep. Further, since the information of the IRQ request source is held in the request source information register, the burden on the processing execution unit is reduced. Therefore, multiple interrupts can be advantageously realized as compared with the conventional information processing apparatus.

5). Multiple Interrupt Disable Operation FIG. 5 is a diagram showing an example of multiple interrupt disable operation in the information processing apparatus of this embodiment. The process execution unit may perform the multiple interrupt prohibition operation as in this embodiment. In the present embodiment, a value having a lower priority than any priority value held in the priority setting register may be set in the current priority register. The same components as those in FIG. 4 are denoted by the same expressions, and description thereof is omitted.

  This embodiment shows that the invention according to the present application supports not only the multiple interrupt control but also the multiple interrupt prohibiting operation.

  The interrupt requests for the factors A to D in FIG. 5 have the uniform priority set to 0 by the priority setting register. Here, the value is not necessarily 0. In the case of the multiple interrupt prohibition operation, other interrupt requests cannot be accepted during the interrupt processing. In order to realize this, the processing execution unit only needs to set the value of the current priority register to 0 after the occurrence of the IRQ (I1) caused by the first factor A interrupt request. Then, at the end of the processing, the value of the current priority register may be returned to “−1” to accept another interrupt request. Hereinafter, the control method is the same for the interrupt requests of factors B to D.

  As described above, even when multiple interrupts are disabled, interrupts can be controlled by writing to the current priority register as in the case of multiple interrupts. Therefore, the invention according to the present application can flexibly cope with multiple interrupts and multiple interrupt prohibition operations.

6). Hereinafter, an electronic device to which the present invention is applied will be described.

  FIG. 6 is a configuration diagram of the electronic device of this embodiment.

  The electronic device 100 includes an image sensor 201, a decoder 202, a pre-processing device 300, an information processing device 10, a post-processing device 400, an LCD controller / video decoder (Liquid Crystal Display Controller / Video Decoder) 500, A display 600 and a storage device 700. Although the present embodiment assumes application to a drive recorder and a surveillance camera, it is also applicable to other applications.

  In the present embodiment, the information processing apparatus 10 may be included in an integrated circuit device.

  The image sensor 201 is, for example, a solid-state image sensor of the NTSC system, the PAL system, or the all-pixel readout system, and the decoder 202 is a video decoder (Video Decoder) compatible with, for example, the NTSC system or the PAL system. The camera module 200 in which the image sensor 201 and the decoder 202 are integrated may be used, or may be omitted when the decoder 202 is not necessary.

  The preprocessing device 300 is a device that performs preprocessing on image data. For example, there are a synchronization device with a system clock, an image size conversion device, and the like. The preprocessing device 300 receives an output signal from the decoder 202 or the camera module 200. If the pre-processing device 300 is unnecessary, it may be omitted.

  For example, the information processing apparatus 10 can have the configuration of the information processing apparatus described in any of FIGS. The information processing apparatus 10 receives an output signal from the preprocessing apparatus 300.

  The post-processing device 400 is a device that performs post-processing on image data. For example, there are an image format conversion device and a contrast correction device. The post-processing device 400 receives an output signal from the information processing device 10. If the post-processing device 400 is unnecessary, it may be omitted.

  The LCD controller / video decoder 500 is an LCD controller or a video decoder. The LCD controller / video decoder 500 receives an output signal from the post-processing device 400, processes it into a signal suitable for the display 600, and outputs it. The display 600 receives the processed signal and displays image data.

  The storage device 700 is a flash memory, for example, and stores a still image output from the information processing device 10.

  In addition, this invention is not limited to this Embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

It is a block diagram which shows an example of the information processing apparatus which concerns on this invention. It is a block diagram which shows an example of the IRQ generation | occurrence | production determination method of the information processing apparatus which concerns on this invention. It is a block diagram which shows an example of the IRQ generation | occurrence | production determination method with respect to the some interrupt request which satisfy | fills the predetermined | prescribed reference | standard regarding a priority of the information processing apparatus which concerns on this invention. It is a block diagram which shows an example of the control method of the multiple interruption of the information processing apparatus which concerns on this invention. It is a block diagram which shows an example of the multiple interrupt prohibition operation | movement of the information processing apparatus which concerns on this invention. It is a block diagram which shows an example of the electronic device to which this invention is applied. 7A to 7D are block diagrams illustrating configuration examples of registers included in the register unit. It is a block diagram which shows an example of the conventional information processing apparatus.

Explanation of symbols

10, 1010 ... Information processing device (integrated circuit device), 20, 20A, 20B, 20C, 1020 ... Interrupt request, 30, 1030 ... IRQ, 50, 1050 ... Register section, 51 ... Priority setting register, 52 ... Current priority Degree register, 53 ... request source information register, 54, 1054 ... IRQ enable setting register, 60, 1060 ... interrupt control unit, 70, 1070 ... processing execution unit, 100 ... electronic device, 200 ... camera module, 201 ... image sensor, 202 ... Decoder, 300 ... Pre-processing device, 400 ... Post-processing device, 500 ... LCD controller / video decoder, 600 ... Display, 700 ... Storage device, 901 ... Unique identification number of priority setting register, 902 ... Priority setting register 903, the current priority of the current priority register, 9 4 ... unique identification number of the request source information register, the priority of 905 ... request source information register, 906 ... unique identification number of the IRQ enable setting register, 907 ... IRQ enable register sets IRQ permission signal

Claims (10)

An interrupt controller;
A process execution unit;
A priority setting register that holds the priority of a plurality of interrupt requests in association with the unique identification number assigned to the interrupt request;
A current priority register that holds the current priority set by the processing execution unit;
A request source information register holding request source information including a unique identification number of the IRQ request source;
Including
The interrupt control unit
Refers to the information in the priority setting register, determines the IRQ request source based on the priority of the interrupt request requesting the interrupt to the processing execution unit, and writes the request source information in the request source information register ,
If the priority of the IRQ request source is higher than the current priority, IRQ is output,
The process execution unit
When the IRQ is received, the information processing apparatus performs processing corresponding to the unique identification number of the IRQ request source held in the request source information register. In claim 1,
The request source information is:
Including the priority of the IRQ requestor;
The interrupt control unit
An information processing apparatus, wherein the priority of the IRQ request source is written in the request source information register. In any one of Claims 1 thru | or 2.
The interrupt control unit
An information processing apparatus, wherein an interrupt request having the highest priority is determined as the IRQ request source. In any one of Claims 1 thru | or 3,
The interrupt control unit
An information processing apparatus that determines the IRQ request source based on a unique identification number in addition to a priority. In any of claims 2 to 4,
The process execution unit
When the IRQ is received, the information processing apparatus writes the priority of the IRQ request source held in the request source information register to the current priority register. In any one of Claims 1 thru | or 5,
The process execution unit
At the end of the process corresponding to the unique identification number of the IRQ request source, the past priority value held in the current priority register before receiving the IRQ that requested the process is written to the current priority register. An information processing apparatus characterized by that. In claim 6,
The process execution unit
An information processing apparatus that stores history information of a value held in the current priority register and writes the value of the past priority in the current priority register based on the history information. In any one of Claims 1 thru | or 7,
The process execution unit
An information processing apparatus, wherein a value having a lower priority than any priority value held in the priority setting register is set in the current priority register.   An integrated circuit device comprising the information processing device according to claim 1.   An electronic apparatus comprising the integrated circuit device according to claim 9.

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