JP2006155048A - Interrupt controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a processing speed in controlling interruption for making it necessary to inhibit interruption, and to reduce stack usage without complicating configurations in an interruption controller to be used for a microprocessor. <P>SOLUTION: In this microprocessor for executing an interrupting program according to an interrupting signal from the outside, an interrupt controller for controlling an interrupting program is provided with a comparator 13 for comparing a data address 14 with an address range in which the interrupting program is inexecutable, and for judging whether or not the data address 14 is included in the address range and an interrupting signal controller 17 for controlling an interrupting signal so that the interrupting program can be made inexecutable when it is judged that the data address 14 is included in the address range by the comparator 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an interrupt control device used for a microprocessor.

  An interrupt control device used in a conventional microprocessor includes an interrupt permission flag. When an interrupt factor occurs, it is determined whether to execute an interrupt program according to the state of the interrupt permission flag.

An interrupt control device provided with a means for setting a predetermined address range so that when the value of the program counter is within the predetermined address range, the interrupt can be forcibly permitted and prohibited regardless of the state of the interrupt permission flag. Has also been proposed (see, for example, Patent Document 1).
JP-A-2-90235

  In a conventional interrupt control device, when a plurality of interrupt programs and tasks access the same variable, it is necessary to make access once in an interrupt disabled state. In practice, a series of processes are required, such as saving the state before disabling interrupts, restoring the saved state after actually disabling interrupts, and enabling interrupts. There was a problem of incurring waste.

  Further, as in Patent Document 1, in an interrupt control device that compares the value of a program counter with a predetermined address range and can forcibly permit or prohibit interrupts, a variable accessed from a plurality of interrupts or tasks When operated at a plurality of locations, a means for setting a predetermined address range and a means for comparing with the value of the program counter are required for the program location for accessing the variable, resulting in a new problem that the configuration becomes complicated. .

  The present invention relates to an interrupt control device that controls an interrupt program in a microprocessor that executes an interrupt program by an external interrupt signal, and compares a data address with an address range in which the interrupt program cannot be executed. And the comparing means for determining whether or not the data address is included in the address range, and the interrupt program is not executed when the comparing means determines that the data address is included in the address range. An interrupt signal control means for controlling the interrupt signal so as to be possible is provided.

  The comparison means sets an address range in which the interrupt program cannot be executed as a range from an address stored in the area start designation storage register to an address stored in the area end designation storage register.

  According to the interrupt control device of the present invention, when it is determined that the data address is included in the address range where the interrupt program cannot be executed, the interrupt is disabled and the interrupt program cannot be executed. Therefore, it is not necessary to perform a series of processing such as saving the state before disabling interrupts, restoring the saved state after actually disabling interrupts, and enabling interrupts. It is possible to improve the processing speed in the control and reduce the stack usage.

  According to the interrupt control device of the present invention, it is possible to improve the processing speed and reduce the stack usage in interrupt control that requires interrupt prohibition without complicating the configuration.

(Embodiment 1)
The interrupt control device according to the present embodiment will be described with reference to FIGS.

  FIG. 1 is a block diagram of an interrupt control device, and FIG. 2 is a block diagram of an interrupt signal control device of the interrupt control device.

  In FIG. 1, 11 is an area start designation storage register, 12 is an area end designation storage register, 13 is a comparison device (comparison means), 14 is a data address, 15 is an interrupt enable flag (IE), and 16 is an interrupt request flag (IR). ), 17 is an interrupt signal control device (interrupt signal control means), and 18 is an interrupt detection flag (ID).

  As shown in FIG. 2, the interrupt signal control device 17 includes a logical product circuit 19 that performs a logical product of the comparison device 13, the interrupt request flag 16, and the interrupt permission flag 15.

  First, a predetermined address range is set in the area start designation storage register 11 and the area end designation storage register 12.

  The comparison device 13 compares the data address 14 with the address range, and outputs 0 when the data address 14 is within the address range, and outputs 1 when the data address 14 is outside the address range.

  In the interrupt signal control device 17, the logical product 19 performs a logical product of the comparison result of the comparison device 13, the interrupt request flag 16, and the interrupt permission flag 15, and stores the logical product result in the interrupt detection flag 18. To do.

  When the data address 14 is within the predetermined address range, the comparator 13 outputs 0, the logical product by the interrupt signal controller 17 is 0, and 0 is stored in the interrupt detection flag 18. When the interrupt detection flag 18 is set to 0, the interrupt is disabled and the interrupt program cannot be executed.

  According to the interrupt control device configured as described above, when it is determined that the data address 14 is included in an address range where the interrupt program cannot be executed, the interrupt program cannot be executed. Therefore, it is not necessary to perform a series of processing such as saving the state before disabling interrupts, restoring the saved state after actually disabling interrupts, and enabling interrupts. It is possible to improve the processing speed in the control and reduce the stack usage. In other words, interrupt prohibition is required by setting a predetermined address range set in the area start designation storage register 11 and the area end designation storage register 12 so that a plurality of interrupts and variables accessed from tasks can be accommodated. It is possible to improve the processing speed and reduce the stack usage in interrupt control.

  In addition, since variables that require atomic processing can be placed in a predetermined address range, the state before interrupts are disabled is saved, the interrupted state is actually restored, the saved state is restored, and interrupts are interrupted. A series of processing such as permitting is unnecessary.

  Further, even when variables accessed from a plurality of interrupts or tasks are operated at a plurality of locations, the region start designation storage register 11, the region end designation storage register 12, and the comparison device 13 are prepared for the program locations that access the variables. It is not necessary and does not cause complication of configuration.

(Embodiment 2)
The interrupt control device according to the present embodiment will be described with reference to FIGS.

  FIG. 3 is a block diagram of the interrupt control device, and FIG. 4 is a block diagram of the interrupt signal control device of the interrupt control device. In addition, the same part as the example shown in FIGS.

  In FIG. 3, 21 is a countdown timer, and 22 is an interrupt signal control device (interrupt signal control means). As shown in FIG. 4, the interrupt signal control device 22 includes a comparison circuit 23 that inputs the value of the countdown timer 21, and a logical product circuit 24 that performs a logical product of the comparison circuit 23, the interrupt request flag 16, and the interrupt permission flag 15. Configured.

  The countdown timer 21 counts down in synchronization with the system clock and other clocks when an initial value is set by a program, and stops counting down when the count value becomes zero. Whether or not the count value of the countdown timer 21 has become 0 is monitored by a monitoring means having a function of switching the output by an input from the countdown timer 21 provided in the interrupt signal control device 22.

  In the interrupt signal control device 22, the value of the interrupt detection flag 18 is set by the value of the countdown timer 21, the interrupt request flag 16, and the interrupt permission flag 15. That is, the comparison circuit 23 outputs 1 when the value of the countdown timer 21 is 0, and outputs 0 when the value of the countdown timer 21 is other than 0. The logical product circuit 24 performs a logical product of the output of the comparison circuit 23, the interrupt request flag 16, and the interrupt permission flag 15, and stores the result of the logical product in the interrupt detection flag 18.

  Until the countdown timer 21 is set to an initial value and starts counting down until the count value becomes 0, the comparison circuit 23 outputs 0, and the result of the logical product by the logical product circuit 24 becomes 0, and an interrupt is detected. 0 is stored in the flag 18. When the interrupt detection flag 18 is set to 0, the interrupt is disabled and the interrupt program cannot be executed. Further, when the time set in the countdown timer 21 elapses and the count value becomes 0, the comparison circuit 23 outputs 1, the result of the logical product by the logical product circuit 24 also becomes 1, and 1 is stored in the interrupt detection flag 18. The interrupt signal is enabled and the interrupt program can be executed.

  According to the interrupt control device configured as described above, the interrupt program cannot be executed until the count value of the countdown timer 21 becomes zero. Therefore, it is not necessary to perform a series of processing such as saving the state before disabling interrupts, restoring the saved state after actually disabling interrupts, and enabling interrupts. It is possible to improve the processing speed in the control and reduce the stack usage.

(Embodiment 3)
The interrupt control apparatus according to this embodiment will be described with reference to FIG.

  FIG. 5 shows a block diagram of the interrupt control device. In addition, the same part as the example shown in FIGS. 1-4 is attached | subjected with the same code | symbol, and the description is abbreviate | omitted.

  In FIG. 5, 31 is a timer initial value setting register (timer initial value storage means), and 32 is a timer initial value transfer control device.

  First, a predetermined address range is set in the area start designation storage register 11 and the area end designation storage register 12.

  The comparison device 13 compares the data address 14 with the address range, and outputs 0 when the data address 14 is within the address range, and outputs 1 when the data address 14 is outside the address range.

  The timer initial value setting register 31 is set by a program. The timer initial value transfer device 32 sets the value of the timer initial value setting register 31 in the countdown timer 21 when the output of the comparison device 13 is 1.

  When an initial value is set, the countdown timer 21 counts down in synchronization with the system clock and other clocks, and stops counting down when the count value reaches zero. Whether or not the count value of the countdown timer 21 has become 0 is monitored by a monitoring means having a function of switching the output by an input from the countdown timer 21 provided in the interrupt signal control device 22.

  In the interrupt signal control device 22, the value of the interrupt detection flag 18 is set by the value of the countdown timer 21, the interrupt request flag 16, and the interrupt permission flag 15. Note that the configuration of the interrupt signal control device 22 is the same as the example shown in FIG.

  When the data address 14 is outside the predetermined address range, the comparison device 13 outputs 1, and the value of the timer initial value setting register 31 is set as the initial value in the countdown timer 21 to start the countdown. Until the count value becomes 0, the result of the logical product by the interrupt signal control device 22 becomes 0, and 0 is stored in the interrupt detection flag 18. When the interrupt detection flag 18 is set to 0, the interrupt is disabled and the interrupt program cannot be executed. When the time set in the countdown timer 21 elapses and the count value becomes 0, 1 is stored in the interrupt detection flag 18, the interrupt signal is validated, and the interrupt program can be executed.

  According to the interrupt control device configured as described above, the interrupt program cannot be executed until the count value of the countdown timer 21 becomes zero. Therefore, it is not necessary to perform a series of processing such as saving the state before disabling interrupts, restoring the saved state after actually disabling interrupts, and enabling interrupts. It is possible to improve the processing speed in the control and reduce the stack usage. Specifically, when executing an interrupt program in which a variable B arranged outside a predetermined address range is added to a variable A arranged within a predetermined address range and stored in the variable A, the data address 14 is predetermined. When the count value of the countdown timer 21 reaches 0, it becomes impossible to execute the interrupt program, and a series of processes for prohibiting and permitting interrupts becomes unnecessary.

(Embodiment 4)
The interrupt control apparatus according to the present embodiment will be described with reference to FIGS.

  6 is a block diagram of the interrupt control device, and FIG. 7 is a block diagram of the interrupt signal control device of the interrupt control device. In addition, the same part as the example shown in FIGS.

  In FIG. 6, 41 is an interrupt prohibition setting number register, 42 is an interrupt prohibition setting register, 43 is an adder, 44 is an interrupt permission setting register, 45 is a subtractor, and 46 is an interrupt signal control device (interrupt signal control means). . As shown in FIG. 7, the interrupt signal control device 46 performs a logical product of a comparison circuit 47 that inputs the value of the interrupt prohibition setting number register 41, a comparison circuit 47, an interrupt request flag 16, and an interrupt permission flag 15. The circuit 48 is used.

  First, when interrupt prohibition setting is performed for the interrupt prohibition setting register 42, the adder 43 adds 1 to the interrupt prohibition setting number register 41. When the interrupt permission setting is performed for the interrupt permission setting register 44, the subtracter 45 subtracts 1 from the interrupt prohibition setting number register 41.

  The interrupt signal controller 46 permits an interrupt when the value of the interrupt prohibition setting number register 41 is 0, and prohibits an interrupt when the value of the interrupt prohibition setting number register 41 is other than 0. That is, the comparison circuit 47 outputs 1 when the value of the interrupt prohibition setting number register 41 is 0, and outputs 0 when the value of the interrupt prohibition setting number register 41 is other than 0. The logical product circuit 48 performs a logical product of the output of the comparison circuit 47, the interrupt request flag 16, and the interrupt permission flag 15, and stores the result of the logical product in the interrupt detection flag 18.

  When the value of the interrupt prohibition setting count register 41 is 0, the comparison circuit 47 outputs 1, the result of the logical product by the logical product circuit 48 is 1, and 1 is stored in the interrupt detection flag 18. When the interrupt detection flag 18 is set to 1, the interrupt program can be executed. When the value of the interrupt prohibition setting number register 41 is other than 0, the comparison circuit 47 outputs 0, the result of the logical product by the logical product circuit 48 is 0, and 0 is stored in the interrupt detection flag 18. When the interrupt detection flag 18 is set to 0, the interrupt is disabled and the interrupt program cannot be executed.

  According to the interrupt control device configured as described above, the interrupt program can be executed when the value of the interrupt prohibition setting number register 41 is 0, and when the value of the interrupt prohibition setting number register 41 is other than 0, the interrupt program can be executed. Execution becomes impossible. Therefore, it is not necessary to perform a series of processing such as saving the state before disabling interrupts, restoring the saved state after actually disabling interrupts, and enabling interrupts. It is possible to improve the processing speed in the control and reduce the stack usage. In particular, it is possible to reduce the amount of stack and the processing time required to disable and enable interrupts in deeply nested functions and recursive functions.

  As shown in FIG. 8, an interrupt prohibition setting register 51 in which the interrupt prohibition setting register and the interrupt permission setting register are combined into one register may be used. That is, when the interrupt prohibition setting is performed for the interrupt prohibition permission setting register 51, the adder 43 adds 1 to the interrupt prohibition setting number register 41. When the interrupt permission setting is performed for the interrupt prohibition permission setting register 51, the subtracter 45 subtracts 1 from the interrupt prohibition setting number register 41. Other configurations are the same as those shown in FIGS.

  The interrupt prohibition permission setting register 51 has a method for distinguishing between prohibition setting and permission setting depending on a value to be written, and a method for distinguishing whether the interrupt prohibition permission setting register 51 is prohibited or permitted depending on whether write access or read access is made. .

  The interrupt control device according to the present invention is useful in various types of microprocessors regardless of the bit length.

Block diagram of interrupt control apparatus according to Embodiment 1 Block diagram of an interrupt signal control device of the interrupt control device according to the first embodiment Block diagram of an interrupt control device according to the second embodiment Block diagram of interrupt signal control device of interrupt control device according to Embodiment 2 Block diagram of interrupt control apparatus according to Embodiment 3 Block diagram of interrupt control apparatus according to Embodiment 4 Block of interrupt signal control device of interrupt control device according to embodiment 4 Block diagram of an interrupt control device according to a modification of the fourth embodiment

Explanation of symbols

11 area start designation storage register 12 area end designation storage register 13 comparison device (comparison means)
14 Data address 15 Interrupt enable flag (IE)
16 Interrupt request flag (IR)
17, 22, 46 Interrupt signal control device (interrupt signal control means)
18 Interrupt detection flag (ID)
21 Countdown timer 31 Timer initial value setting register (timer initial value storage means)
32 Timer initial value transfer control device (timer initial value storage means)
41 Interrupt Disable Setting Count Register 42 Interrupt Disable Setting Register 43 Adder 44 Interrupt Enable Setting Register 45 Subtractor 51 Interrupt Disable Enable Setting Register

Claims (5)

In a microprocessor that executes an interrupt program in response to an external interrupt signal, the interrupt control device controls the interrupt program,
Comparing means for comparing a data address with an address range where the interrupt program cannot be executed to determine whether the data address is included in the address range;
An interrupt control device comprising: an interrupt signal control unit configured to control an interrupt signal so that an interrupt program cannot be executed when the comparison unit determines that the data address is included in the address range.   The comparing means is characterized in that an address range in which the interrupt program cannot be executed is a range from an address stored in an area start designation storage register to an address stored in an area end designation storage register. The interrupt control device according to claim 1. In a microprocessor that executes an interrupt program in response to an external interrupt signal, the interrupt control device controls the interrupt program,
A countdown timer,
Monitoring means for monitoring whether or not the time set in the countdown timer has elapsed;
An interrupt control device comprising: interrupt signal control means for controlling an interrupt signal so that an interrupt program cannot be executed until the set time elapses. In a microprocessor that executes an interrupt program in response to an external interrupt signal, the interrupt control device controls the interrupt program,
Comparing means for comparing a data address with an address range in which the interrupt program can be executed to determine whether the data address is included in the address range;
Timer initial value storage means for storing a predetermined time;
A countdown timer for setting a time stored in the timer initial value storage means when the comparison means determines that the data address is out of the address range;
Monitoring means for monitoring whether or not the time set in the countdown timer has elapsed;
An interrupt control device comprising: interrupt signal control means for controlling an interrupt signal so that an interrupt program cannot be executed until the set time elapses. In a microprocessor that executes an interrupt program in response to an external interrupt signal, the interrupt control device controls the interrupt program,
An interrupt disable setting count register that stores the interrupt disable setting count,
Interrupt disable setting register for interrupt disable setting,
An adder that adds 1 to the number of interrupt prohibition settings stored in the interrupt prohibition setting count register when the interrupt prohibition setting is set in the interrupt prohibition setting register;
Interrupt enable setting register for setting interrupt enable,
A subtractor for subtracting 1 from the interrupt disable setting number stored in the interrupt disable setting number register when interrupt enable is set in the interrupt enable setting register;
An interrupt control device comprising: interrupt signal control means for controlling an interrupt signal so that an interrupt program cannot be executed according to a value of the interrupt prohibition setting number register.

Images