JP2001075819A - Interruption request control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To average the interruption requests by decoding the output of a priority encoder and outputting the decoded value of a channel, and outputting a process request having the decoded value retimed in response to the output. SOLUTION: A priority encoder 24 receives the output signal 39 of a 1st detector 23 and determines a channel 1. On receiving the signal 39, a decoder 26 outputs a signal 42 which is a decoded value as a channel where an interruption process has been performed to a control circuit 20. In response to the output signal 42 of the decoder 26, the decoded value is retimed by a 2nd storage means 27 and a process request of the channel 1 is reported to a host system 53. The host system 53 performs the process and then an interruption request generator 50 turns off the interruption request once, but instantaneously regenerates and turns on the request.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an interrupt request control circuit for controlling an interrupt request in a computer system and other electronic devices.

[0002]

2. Description of the Related Art In computer systems or other electronic devices, interrupt processing is frequently used, and such interrupt processing is generally generated by an interrupt request. When a plurality of such interrupt requests conflict, it is necessary to perform interrupt control for controlling which request is preferentially accepted.

A conventional example of an interrupt request control circuit for performing this type of interrupt request control is disclosed in Japanese Patent Application Laid-Open No. 1-128140. The interrupt request control circuit disclosed in Japanese Patent Application Laid-Open No. 1-128140 discloses a computer system or other electronic device that determines an unprocessed request when determining one to be executed from a plurality of processing requests. The priority is selected so that the acceptance of requests is averaged as a whole.

FIG. 15 is a block diagram showing an example of a conventional interrupt request control circuit disclosed in Japanese Patent Application Laid-Open No. 1-128140, and shows a configuration in which the number of interrupt channels is four.

The input register 1431 receives four peripheral interrupt request signals 1433 supplied from a peripheral I / O (input / output) device or the like by receiving an interrupt sampling signal 1432 from the host system, and receives these as input interrupts. This is a 4-bit latch circuit that holds the request signal 1434.

The unaccepted request priority output circuit 1435 includes an input interrupt request signal 1434 output from the input register 1431 and a received interrupt request signal indicating which of the input interrupt request signals 1434 has already been received by the host system. 1436, the unaccepted interrupt request signal 1434 indicating in the input interrupt request signal 1434 that the host system has not yet been acknowledged.
37. The non-acceptance priority output circuit 1435 includes a first AND circuit 1438, a first OR circuit 1439, and a first switch 1440.

[0007] The priority encoder 1441 is a 4-bit encoder that receives a non-reception interrupt request signal 1437, encodes the signal according to a priority set internally, and outputs a non-reception interrupt request code 1442. The decoder 1443 is a 4-bit decoder to which the unrequested interrupt request code 1442 is inputted, decoded, and outputs an interrupt request signal 1444.

[0008] The accepted request signal generation circuit 1445 includes:
An interrupt request signal 1444 is input, and a received interrupt request signal 1436 is generated based on the input interrupt request signal 1444.
The received request signal generating circuit 1445 includes a second AND circuit 1446,
7, an inverter 1448, a second OR circuit 1449, a second switch 1450, and a register 1451.

The output register 1452 receives the interrupt request signal 1444 and receives an interrupt strobe signal 1453 from the host system. The output register 1452 outputs the interrupt request signal 1444 as an output interrupt request signal 1454 to the host system. Circuit.

Next, the operation of the interrupt request control circuit of FIG. 15 will be described. By receiving the interrupt sampling signal 1432 from the host system, four peripheral interrupt request signals 1433 supplied from a peripheral I / O device or the like are provided.
Is "1001" (an interrupt request is issued to channel 4 and channel 1, and the MSB side is channel 4). The held input interrupt request signal 1434
(“1001”) and the received request signal generation circuit 144
When the signal 1436 (“1111”: the initial value after the release of the power-on reset) supplied from No. 5 is input to the non-reception request priority output circuit 1435, the non-reception request priority output circuit 1435 outputs the non-reception interrupt request signal 1437.
(“1001”) is output. By inputting the unacknowledged interrupt request signal 1437 (“1001”) to the priority encoder 1441, an unacknowledged interrupt request code 1442 (“channel 4”) is output from the priority encoder 1441, and is output to the decoder 14.
Decode at 43, hold in output register 1452,
The output interrupt request signal 1454 (“10
00 ": corresponding to channel 4).

Here, the priority encoder 144
1 indicates that the priority of the interrupt request is increased in descending order of the channel number. Therefore, the value of the first non-accepted interrupt request code 1442 to be output is “4 (indicating channel 4)”. On the other hand, the received request signal generation circuit 14
45 holds an already accepted channel based on an interrupt request signal 1444 (“1000”) indicating the interrupt channel number to be permitted and obtained as a result of decoding the unaccepted interrupt request code 1442, and sets the result signal 1436 to “ 0111 ”.

Next, when selecting an interrupt request, the input register output signal 1434 (“1001”) and the signal 1436 given from the accepted request signal generation circuit 1445 are selected.
(“0111”) is the unaccepted request priority output circuit 143
5, the unaccepted channel signal 1437
(“0001”) is output. Since the interrupt request has already been received for the channel 4, only the channel 1 is notified to the priority encoder 1441. As a result, the signal 1454 includes “0001
(Indicating channel 1) ".

[0013]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Laid-Open Publication No. 1-1
A first problem with the conventional interrupt request control circuit disclosed in Japanese Patent No. 28140 is that there is no scalability.

That is, when the hardware is once commercialized into an LSI (Large Scale Integrated Circuit) or the like, and it is desired to increase the number of interrupt channels by connecting the commercialized LSIs or the like in multiple stages, the invention of the present invention is originally intended. It is impossible to "average the reception of requests as a whole", which was the purpose. If such control is to be realized, the hardware must be redesigned again.

For example, FIG. 16 shows a commercialized LSI in which the number of interrupt channels is four.
Used, and these are subordinately combined to give a total of 7
6 is a configuration example when an attempt is made to implement a channel interrupt request control circuit. Consider a case where the interrupt request control circuit 1 and the interrupt request control circuit 2 are configured using the conventional technology. In this case, since the processing execution ratio of the processing port for each LSI is 1: 1: 1: 1, the processing ratio for each channel as a whole is as follows: channel 1: channel 2: channel 3: channel 4: Since channel 5: channel 6: channel 7 = 4: 4: 4: 1: 1: 1: 1, the processing ratio of each channel is set to 1: 1: 1: 1: 1: 1:
Cannot be 1.

The second problem in the conventional interrupt request control circuit disclosed in Japanese Patent Application Laid-Open No. 1-128140 is as follows.
"Complicated circuit configuration increases gate size."
That's what it means. In the conventional circuit configuration, the received register 1451 and the like have a large feature, and thus the gate scale tends to be large (an example in which a circuit having the same function as that in FIG. 15 is configured using the present invention is shown. Compare with FIG. 14).

A third problem with the conventional interrupt request control circuit disclosed in Japanese Patent Application Laid-Open No. 1-128140 is that, when the host system interrupt sampling signal 1432 is input in FIG. The value of the peripheral interrupt request signal 1433 is fetched, and at that time, the register 1451 holds the accepted information in the previous processing cycle. Therefore, even though the input register 1431 has entered a new processing cycle, the contents of the register 1451 do not shift to the new processing cycle, but retain the values in the old cycle. That is, the register information 1451
In the case where only the reset by turning on the power is performed, the averaging is maintained when the first host system interrupt sampling signal 1432 is received, but the second and third host system interrupt sampling signals 1432 are received. In this case, the input register 1431
Does not correspond to the cycle information held by the output value 1434 of the received register 1451 and the output value 1436 of the accepted register 1451, so that the averaging cannot be maintained. The reason for this is that there is no means for initializing the accepted register 1451 by the host system interrupt sampling signal or the like.

The present invention has been made in view of the above circumstances, and when deciding which one to execute from among a plurality of processing requests, interrupt requests are averaged according to a processing execution ratio set for each channel, Excellent scalability when combining multiple, it is possible to notify the interrupt any number of times,
It is another object of the present invention to provide an interrupt request control circuit having a simple configuration.

[0019]

In order to achieve the above-mentioned object, an interrupt request control circuit according to the present invention comprises a timing signal, a signal indicating that all channels have no interrupt request, and an interrupt request control circuit. A control circuit responsive to the decode value; a first storage means for fetching an interrupt request in response to the output of the control circuit and outputting whether or not there is an unprocessed interrupt request for each channel; A ratio setting circuit for generating a signal corresponding to the ratio of each channel in response to the output of the control circuit; and a channel having an interrupt request in response to the outputs of the first storage means, the control circuit, and the ratio setting circuit. A first detector for outputting a signal for notifying a channel to be processed, and a priority for outputting a signal for notifying a channel to be processed in response to an output of the first detector. A second encoder for outputting a signal indicating that all channel interrupt requests have been eliminated to the control circuit in response to an output of the first encoder, and an output of the priority encoder. A decoder for outputting a decoded value of the channel on which the interrupt processing has been performed to the control circuit; and a second storage means for outputting a processing request in which the decoded value is retimed in response to the output of the decoder.

In the interrupt request control circuit of the present invention,
When deciding which one to execute from among multiple processing requests, interrupt requests are averaged according to the processing execution ratio set for each channel, and processing efficiency can be equalized even if multiple processing requests are combined. It is excellent, can notify an interrupt any number of times, and has a simple configuration.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2
A first embodiment of the interrupt request control circuit according to the present invention will be described with reference to FIG. FIG. 1 shows a configuration of an interrupt request control circuit according to a first embodiment of the present invention, and FIG.
2 shows a specific configuration of a ratio setting circuit in FIG.

The interrupt request control circuit 10 shown in FIG. 1 comprises a control circuit 20, a first storage means 21, a ratio setting circuit 22,
First detector 23, priority encoder 24, second detector 25, decoder 26 and second storage means 2
7 is provided. FIG. 1 shows, in addition to the interrupt request control circuit 10, an interrupt request generator 50, a timing signal generating means 51, a setting means 52, and a processing means 53.

In FIG. 1, an interrupt request control circuit 10
Is based on the setting value given from the setting means 52,
It has a ratio setting circuit 22 that generates a signal 38 that matches the ratio of each channel.

The ratio setting circuit 22 is connected to the control circuit 20 and the setting means 52.
6 and the signal 45, and the signal 3
2 and a signal 33 are received. The signal 36 is a signal indicating operation / non-operation, and the signal 45 is a signal indicating a forced mask release request or a reset request. The signal 32 and the signal 33 are set values for setting the ratio setting circuit 22.

The first storage means 21 is connected to the control circuit 20 and the interrupt request generator 50.
, And a signal 30 from the interrupt request generator 50. The signal 34 is a trigger signal for simultaneously storing the value of the signal 30 indicating the interrupt request given for each channel from the interrupt request generator 50 for all the channels, and the signal 35 is used to erase the storage of the processed channel. This is a signal indicating a clearing request.

The control circuit 20 is connected to the timing signal generating means 51, the second detector 25 and the decoder 26, receives the signal 31 from the timing signal generating means 51, and receives the signal 41 from the second detector 25. Receive. The control circuit 20 further receives a signal 42 from the decoder 26. The signal 31 is a timing signal input every time the interrupt request control circuit 10 operates. The signal 41 is
This signal indicates that interrupt requests for all channels have disappeared. The signal 42 is a decode value indicating the channel on which the interrupt processing has been performed.

The first detector 23 includes a first storage unit 21
, The control circuit 20 and the ratio setting circuit 22, and receives a signal 37 from the first storage means 21 and a signal 44 from the control circuit 20. First detector 23
Receives a signal 38 from the ratio setting circuit 22.
The signal 37 is a signal indicating whether or not there is an unprocessed interrupt request of each channel. The signal 44 is a signal which becomes active during the processing cycle, and keeps the active state until the processing means 53 receives the processing result. The signal 38 is a mask signal indicating ratio setting information set for each channel.

The priority encoder 24 is connected to the first detector 23 and receives a signal 39 from the first detector 23. The signal 39 is a signal for notifying only the channel which must be processed among the channels requesting the interrupt processing.

The second detector 25 is connected to the first detector 23 and receives a signal 39 from the first detector 23. The signal 39 is a signal for notifying only the channel that needs to be processed among the channels requesting the interrupt processing.

The decoder 26 is connected to the priority encoder 24, and the priority encoder 2
4 receives a signal 40. The signal 40 is a signal for notifying one channel that should be processed at that time based on a priority internally set from a plurality of interrupt requests.

The second storage means 27 is connected to the decoder 26 and receives the signal 42 from the decoder 26.
The signal 42 indicates a value obtained by decoding the channel to be processed at that time.

The processing means 53 is connected to the second storage means 27 and receives the signal 43 from the second storage means 27. The signal 43 is a signal obtained by retiming the decoded value.

Next, a specific configuration of the ratio setting circuit 22 will be described with reference to FIG. This ratio setting circuit 22
Can be configured as shown in FIG. 2, for example, by a combination of a counter and a storage means.

In FIG. 2, the ratio setting circuit 22 comprises a counter 70 and third storage means 71. The counter 70 operates with the signal 36 enabled. Third
The storage means 71 outputs the set value previously set by the setting means 52 using the output value of the counter 70 as an address. This set value is supplied to the above-described first detector 23 as a mask signal of each channel.

Instead of the more detailed description of the operation of the interrupt request control circuit according to the first embodiment of the present invention described above, FIGS. 3 and 4 each further show the configuration of FIGS. 1 and 2 respectively. The interrupt request control circuit according to the second embodiment of the present invention will be described in detail. The configuration of the interrupt request control circuit according to the second embodiment of the present invention shown in FIGS. 3 and 4 is different from FIGS. 1 and 2 in that a part is shown as a more specific configuration example. It is.

That is, in the interrupt request control circuit 10 shown in FIG.
It consists of two AND circuits. First storage means 21
Is composed of an AND circuit and a synchronous RS-Flip Flop (clock synchronous set-reset flip-flop) (S / F / F). The first detector 23 is configured by an AND circuit, the second detector 25 is configured by an OR circuit having a negative logic output, that is, a NOR circuit, and the second storage unit 27 is configured by a flip-flop (F / F). It is configured. Further, in the ratio setting circuit 22 shown in FIG. 4, the third storage means 71 is constituted by a memory. The interrupt request generator 50 is a peripheral I / O device that generates an interrupt request, the timing signal generating unit 51 is an interrupt sampling signal of a host system, and the processing unit 53 is a host system.

FIG. 5 shows an example of setting values set in the ratio setting circuit 22 of the interrupt request control circuit shown in FIGS. 3 and 4, and FIG. 6 shows an example of setting the interrupt request control circuit shown in FIGS. 6 is a timing chart of FIG.

Here, in order to facilitate understanding, the number of interrupt channels is three, and the read ratio of each channel is “channel 1: channel 2: channel 3 = 3: 2:
A description will be given of the interrupt processing in the case of “1”.
This is similar to the case of the channel.

In the following, an interrupt request is issued for channel 1 continuously 2
In the following, an example will be described in which the channel I and the channel 2 are two consecutive times, and the channel 3 is two consecutive times, and an interrupt request is supplied from the peripheral I / O device 50. Further, the peripheral I / O device 50 outputs “1” when there is an interrupt request, and the channel on which the host system 50 has executed the processing, or
The peripheral I / O device 50 of the channel to which the host system has given the processing permission stops the interrupt request signal 30 if the interrupt request is satisfied (sets it to "0"), and if not satisfied, supplies again. Yes ("1" or
("1" is held).

First, each storage means is reset to "0" by turning on the power. After turning on the power, setting means 5
From 2, the ratio of each channel is set. The ratio setting circuit 22 shown in FIG. 4 sets the period “5” of the counter 70 as the first set value 32 by the setting means 52. Next, the inside of the memory 71 is set as the second set value 33. In FIG.
A setting example is shown in which an address is a count value, each bit of data is a channel number, a bit width is the number of channels, and when the stored data is “1”, masking is released. The counter 70 starts from “0” when the signal 36 becomes active, and “1”,
“2”, “3”, “4”, “5”, “0”, “1”,
The counting operation is repeated cyclically as “2”, “3”,. Next, since the memory 71 uses an address as a count value and each bit of data as a channel number,
When the count value is "0", "100" is output to the signal 38, when the count value is "1", "010" is output to the signal 38, and when the count value is "2", the signal 38 is output. “00
1 is output, and when the count value is "3", "100" is output to the signal 38. When the count value is "4", the signal 3 is output.
8 is output, and when the count value is "5", "100" is output to the signal 38 (MSB side is channel 1).
And Hereinafter, the MSB side is similarly referred to as channel 1.)

In FIG. 3, the values of the respective units after the power is turned on and the setting of the ratio setting circuit 22 is completed will be described first.
(In the order of cycle 0 in FIG. 6) Synchronous RS flip-flop (SF / F) in first storage means 21
Outputs a signal 37 (“000”). Therefore, the first detector 23 also outputs the output signal 39 (“000”). Next, when there are a plurality of interrupt requests, the priority encoder 24 determines one channel to be processed at that time based on the internally set priority (in this example, the smaller the channel number is, the smaller the channel number is). It will be described as having a higher priority). Then, the first detector 23
, A signal 40 (“no channel”) indicating that there is no corresponding channel is notified to the decoder 26. Upon receiving the notification, the decoder 26 notifies the second storage means 27 and the control circuit 20 of a signal 42 ("000") indicating that there is no corresponding channel. The second storage unit 27 receives the signal 42 (“000”) from the decoder 26 and notifies the host system 53 of a signal 43 (“000”) indicating that there is no interrupt processing execution channel.

The second detector 25 receives the signal 39 (“000”) from the first detector 23 and outputs a signal 41 (“1”) indicating that there is no interrupt request to the control circuit 20.
Notify. The control circuit 20 does not operate because the host system interrupt sampling signal 31 is not input. Therefore, the signal 34, the signal 35, and the signal 36
Outputs “0”.

Next, the operation of the first input of the host system interrupt sampling signal 31 (hereinafter, simply referred to as "sampling signal 31") will be described (FIG. 6).
In the first cycle of the cycle). When the sampling signal 31 is input, the control circuit 20 generates a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed. Since the signal 41 output from the second detector 25 indicates "1", that is, there is no interrupt request, the ratio of the signal 41 to the signal 34 for capturing the interrupt request of the peripheral I / O device 50 is satisfied. The signal 36 for operating the counter 70 of the setting circuit 22 is generated. Peripheral I / O device interrupt request signal 3
Since 0 is "111", the output signal 37 of the first storage means 21 receives the signal 34 and outputs "111". The output signal 38 of the ratio setting circuit 22 is the signal 3
In response to 6, since the count value in the ratio setting circuit 22 becomes 0 (starting from the count value “0” after reset release), “100” is output. Therefore, the output signal 39 of the first detector 23 outputs “100”, and the output signal 41 of the second detector 25 outputs “0”.

The priority encoder 24 receives the output signal 39 (“100”) of the first detector 23 and determines the channel 1. The decoder 26 receives the signal.
Outputs a signal 42 (“100”), and notifies the host system 53 of the processing request of the channel 1 by retiming in the second storage unit 27. Since the host system 53 has executed the processing, the peripheral I / O device 50 turns off the interrupt request once, but instantaneously re-generates the request and turns it on (that is, the signal 30 indicates “ 11
1 ").

Next, the control circuit 20 clears the synchronous RS flip-flop (S / F / F) of the channel 1 in the first storage means 21 of the channel which has just requested the host system 53 to process. A pulse signal 35 is generated. Thereby, the output signal 3 of the first storage unit 21
7 becomes “011” and further notifies the host system 53 of the channel to be processed, so that the signal 44 is turned off. Therefore, the output signal 39 of the first detector 23 is “00”
0 ", and the output signal 41 of the second detector 25 becomes" 1 ".
Becomes

Next, the operation when the sampling signal 31 is input for the second time will be described (the second cycle in FIG. 6). When the sampling signal 31 is input, the control circuit 20 generates a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed. Since the signal 41 output from the second detector 25 indicates "1", that is, there is no interrupt request, the signal 34 for capturing an interrupt request from the peripheral I / O device 50 is output. A signal 36 for operating the counter of the ratio setting circuit is generated. Since the peripheral I / O device interrupt request signal 30 is “111”, the output signal 37 of the first storage unit 21 becomes the signal 3
4 and outputs "111". Further, the output signal 38 of the ratio setting circuit 22 receives the signal 36 and outputs “010” because the count value in the ratio setting circuit 22 becomes 1. Therefore, the output signal 3 of the first detector 23
9 outputs “010”, and the output signal 41 of the second detector 25 outputs “0”.

The priority encoder 24 receives the output signal 39 (“010”) of the first detector 23 and determines the channel 2. Upon receiving the signal, the decoder 26
And outputs the signal 42 (“010”) to the second storage unit 27.
To notify the host system 53 of the processing request for channel 2. The peripheral I / O device 50 stops the interrupt request once due to the processing performed by the host system 53, but the request is instantaneously regenerated (that is, the signal 30 remains “111”).

Next, the control circuit 20 controls the host system 5
3, the synchronous RS flip-flop (S) of the channel 2 in the first storage means 21 of the channel requested to be processed.
-F / F) is generated. Thereby, the output signal 37 of the first storage means 21 becomes
Since it becomes "101" and further notifies the host system 53 of the channel to be processed, the signal 44 is turned off. Therefore, the output signal 39 of the first detector 23 becomes “000”, and the output signal 41 of the second detector 25 becomes “1”.

Next, the operation when the sampling signal 31 is input for the third time will be described (third cycle in FIG. 6). When the sampling signal 31 is input, the control circuit 20 outputs a signal 4 for stretching the signal 43 until the host system 53 receives an interrupt channel to be processed.
4 is generated. Since the signal 41 output from the second detector 25 indicates "1", that is, there is no interrupt request, the signal 34 for capturing an interrupt request from the peripheral I / O device 50 is output. A signal 36 for operating the counter of the ratio setting circuit is generated. Perimeter I
Since the / O device interrupt request signal 30 is “111”, the output signal 37 of the first storage unit 21 becomes the signal 34
Then, "111" is output. Further, the output signal 38 of the ratio setting circuit 22 receives the signal 36 and outputs “001” because the count value in the ratio setting circuit 22 becomes 2. Therefore, the output signal 39 of the first detector 23
Outputs “001”, and the output signal 41 of the second detector 25 outputs “0”.

The priority encoder 24 receives the output signal 39 (“001”) of the first detector 23 and determines the channel 3. Upon receiving the signal, the decoder 26
And outputs the signal 42 (“001”) to the second storage unit 27.
To notify the host system 53 of the processing request for channel 3. Since the host system 53 has executed the processing, the peripheral I / O device 50 turns off the interrupt request once but instantaneously re-generates the request and turns it on (that is, the signal 30 becomes “111”). as it is).

Next, the control circuit 20 clears the synchronous RS flip-flop (SF / F) of the channel 3 in the first storage means 21 of the channel for which the host system 53 has requested processing. A pulse signal 35 is generated. As a result, the output signal 37 of the first storage means 21
Becomes "110", and further notifies the host system 53 of the channel to be processed, so that the signal 44 is turned off. Therefore, the output signal 39 of the first detector 23 is “00”
0 ", and the output signal 41 of the second detector 25 becomes" 1 ".
Becomes

Next, the operation when the input of the sampling signal 31 is the fourth time will be described (the fourth cycle in FIG. 6). When the sampling signal 31 is input, the control circuit 20 outputs a signal 4 for stretching the signal 43 until the host system 53 receives an interrupt channel to be processed.
4 is generated. Since the signal 41 output from the second detector 25 indicates "1", that is, there is no interrupt request, the ratio of the signal 41 to the signal 34 for capturing the interrupt request of the peripheral I / O device 50 is satisfied. A signal 36 for operating the counter of the setting circuit is generated. Peripheral I /
Since the O device interrupt request signal 30 is “111”,
The output signal 37 of the first storage means 21 receives the signal 34 and outputs “111”. The output signal 38 of the ratio setting circuit 22 receives the signal 36 and
Since the count value in is "3", "100" is output. Therefore, the output signal 39 of the first detector 23 is “1”
00 ", and the output signal 41 of the second detector 25 is
Outputs “0”.

The priority encoder 24 receives the output signal 39 (“100”) of the first detector 23 and determines the channel 1. Upon receiving the signal, the decoder 26
And outputs a signal 42 (“100”) to the second storage unit 27.
To notify the host system 53 of the processing request for channel 1. The peripheral I / O device 50 turns off the interrupt request by executing the processing by the host system 53 (that is, the signal 30 changes to “011”).

Next, the control circuit 20 controls the host system 5
3 is the synchronous RS flip-flop (S
-F / F) is generated. Thereby, the output signal 37 of the first storage means 21 becomes
Since "011" has been reached and the channel to be processed has been notified to the host system 53, the signal 44 is turned off. Therefore, the output signal 39 of the first detector 23 becomes “000”, and the output signal 41 of the second detector 25 becomes “1”.

Next, the operation when the input of the sampling signal 31 is the fifth time will be described (the fifth cycle in FIG. 6). When the sampling signal 31 is input, the control circuit 20 outputs a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed.
Generate Since the signal 41 output from the second detector 25 indicates "1", that is, there is no interrupt request, the ratio of the signal 41 to the signal 34 for capturing the interrupt request of the peripheral I / O device 50 is satisfied. A signal 36 for operating the counter of the setting circuit is generated. Peripheral I /
Since the O device interrupt request signal 30 is "011", the output signal 37 of the first storage means 21 receives the signal 34 and outputs "011". Also, the ratio setting circuit 2
The output signal 38 of 2 outputs “010” since the count value in the ratio setting circuit 22 becomes 4 in response to the signal 36. Therefore, the output signal 39 of the first detector 23 is
“010” is output, and the output signal 41 of the second detector 25 is output.
Outputs “0”.

The priority encoder 24 determines the channel 2 in response to the output signal 39 (“010”) of the first detector 23. Upon receiving the signal, the decoder 26
And outputs the signal 42 (“010”) to the second storage unit 27.
To notify the host system 53 of the processing request for channel 2. As a result of the host system 53 executing the processing, the peripheral I / O device 50 turns off the interrupt request (that is, the signal 30 changes to “001”). Next, the control circuit 20 sends the synchronous RS flip-flop (S / F / F) of the channel 2 in the first storage means 21 of the channel which has just requested the host system 53 to process.
A pulse signal 35 for clearing F) is generated. Thereby, the output signal 37 of the first storage unit 21 becomes “0”
01 ", which further informs the host system 53 of the channel to be processed, and turns off the signal 44. Therefore, the output signal 39 of the first detector 23 becomes" 000 ",
The output signal 41 of the second detector 25 becomes "1".

Next, the operation when the input of the sampling signal 31 is the sixth time will be described (the sixth cycle in FIG. 6). When the sampling signal 31 is input, the control circuit 20 outputs a signal 4 for stretching the signal 43 until the host system 53 receives an interrupt channel to be processed.
4 is generated. Since the signal 41 output from the second detector 25 indicates "1", that is, there is no interrupt request, the ratio of the signal 41 to the signal 34 for capturing the interrupt request of the peripheral I / O device 50 is satisfied. A signal 36 for operating the counter of the setting circuit is generated. Peripheral I /
Since the O device interrupt request signal 30 is “001”, the output signal 37 of the first storage means 21 receives the signal 34 and outputs “001”. Further, the output signal 38 of the ratio setting circuit 22 receives the signal 36 and outputs "100" because the count value in the ratio setting circuit 22 becomes 5. Therefore, the output signal 39 of the first detector 23 is “00”
0 ", and the output signal 41 of the second detector 25 is
Outputs “1”.

The priority encoder 24 receives the output signal 39 (“000”) of the first detector 23 and determines that there is no channel. The decoder 26 receives the signal.
Outputs a signal 42 (“000”), notifies the host system 53 of the absence of a channel by retiming in the second storage unit 27. Therefore, the host system 53 ends the processing cycle without executing the interrupt processing. Therefore,
The peripheral I / O device 50 does not turn off the interrupt request in any channel (that is, the signal 30 remains “001”). Also, the output signal 37 of the first storage means 21 is
It remains "001". And the host system 53
, The signal 44 is turned off. Therefore, the output signal 39 of the first detector 23 is “00”
0 ", and the output signal 41 of the second detector 25 becomes" 1 ".
Becomes

Next, the operation when the input of the sampling signal 31 is the seventh time will be described (cycle 7 in FIG. 6).
Order). When the sampling signal 31 is input, the control circuit 20 generates a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed. Then, the signal 4 output by the second detector 25
1 is "1", that is, there is no interrupt request;
Therefore, a signal 34 for capturing an interrupt request from the peripheral I / O device 50 and a signal 36 for operating the counter of the ratio setting circuit are generated. Since the peripheral I / O device interrupt request signal 30 is “001”,
The output signal 37 of the first storage means 21 receives the signal 34 and outputs “001”. The output signal 38 of the ratio setting circuit 22 receives the signal 36 and outputs “100” because the count value in the ratio setting circuit 22 becomes 0. Therefore, the output signal 39 of the first detector 23 is “000”
And the output signal 41 of the second detector 25 is “1”.
Is output.

The priority encoder 24 receives the output signal 39 (“000”) of the first detector 23 and determines that there is no channel. The decoder 26 receives the signal.
Outputs a signal 42 (“000”), notifies the host system 53 of the absence of a channel by retiming in the second storage unit 27. Therefore, the host system 53 ends the processing cycle without executing the interrupt processing. Therefore,
The peripheral I / O device 50 does not turn off the interrupt request in any channel (that is, the signal 30 remains “001”). Also, the output signal 37 of the first storage means 21 is
It remains "001". And the host system 53
, The signal 44 is turned off. Therefore, the output signal 39 of the first detector 23 is “00”
0 ", and the output signal 41 of the second detector 25 becomes" 1 ".
Becomes

Next, the operation when the sampling signal 31 is input for the eighth time will be described (the eighth cycle in FIG. 6). When the sampling signal 31 is input, the control circuit 20 outputs a signal 4 for stretching the signal 43 until the host system 53 receives an interrupt channel to be processed.
4 is generated. Since the signal 41 output from the second detector 25 indicates "1", that is, there is no interrupt request, the ratio of the signal 41 to the signal 34 for capturing the interrupt request of the peripheral I / O device 50 is satisfied. A signal 36 for operating the counter of the setting circuit is generated. Peripheral I /
Since the O device interrupt request signal 30 is “001”, the output signal 37 of the first storage means 21 receives the signal 34 and outputs “001”. Further, the output signal 38 of the ratio setting circuit 22 receives the signal 36 and outputs “010” because the count value in the ratio setting circuit 22 becomes “1”. Therefore, the output signal 39 of the first detector 23 is “00”
0 ", and the output signal 41 of the second detector 25 is
Outputs “1”.

The priority encoder 24 receives the output signal 39 (“000”) of the first detector 23 and determines that there is no channel. The decoder 26 receives the signal.
Outputs a signal 42 (“000”), notifies the host system 53 of the absence of a channel by retiming in the second storage unit 27. Therefore, the host system 53 ends the processing cycle without executing the interrupt processing. Therefore, the peripheral I / O device 50 does not turn off the interrupt request in any channel (that is, the signal 30 remains “001”). Also, the output signal 37 of the first storage means 21 is
It remains "001". And the host system 53
, The signal 44 is turned off. Therefore, the output signal 39 of the first detector 23 is “00”
0 ", and the output signal 41 of the second detector 25 becomes" 1 ".
Becomes

Next, the operation when the input of the sampling signal 31 is the ninth time will be described (cycle 9 in FIG. 6).
Order). When the sampling signal 31 is input, the control circuit 20 outputs a signal 44 for expanding the signal 43 until the host system 53 receives an interrupt channel to be processed.
Generate Since the signal 41 output from the second detector 25 indicates "1", that is, there is no interrupt request, the ratio of the signal 41 to the signal 34 for capturing the interrupt request of the peripheral I / O device 50 is satisfied. A signal 36 for operating the counter of the setting circuit is generated. Peripheral I /
Since the O device interrupt request signal 30 is “001”, the output signal 37 of the first storage means 21 receives the signal 34 and outputs “001”. Further, the output signal 38 of the ratio setting circuit 22 receives the signal 36 and outputs "001" because the count value in the ratio setting circuit 22 becomes 2. Therefore, the output signal 39 of the first detector 23 is “0”
01 ", and the output signal 41 of the second detector 25 is
Outputs “0”.

The priority encoder 24 receives the output signal 39 (“001”) of the first detector 23 and determines the channel 3. Upon receiving the signal, the decoder 26
And outputs the signal 42 (“001”) to the second storage unit 27.
To notify the host system 53 of the processing request for channel 3. The peripheral I / O device 50 turns off the interrupt request by executing the processing by the host system 53 (that is, the signal 30 changes to “000”). Next, the control circuit 20 transmits the synchronous RS flip-flop (S-F) of the channel 3 in the first storage unit 21 of the channel that has just requested the host system 53 to process.
/ F) is generated.
As a result, the output signal 37 of the first storage means 21 becomes “0”
00 "and further notifies the host system 53 of the channel to be processed, so that the signal 44 is turned off. Therefore, the output signal 39 of the first detector 23 becomes" 000 ",
The output signal 41 of the second detector 25 becomes "1".

In the above description, the host system 53 is notified of the absence of the interrupt execution channel in the cycle 6 order. However, if the peripheral I / O device interrupt requests 50 of all the channels are successive interrupt requests, the cycle 6
In order, the channel 1 is notified to the host system 53 as the interrupt execution channel. Also, when the peripheral I / O device interrupt requests 50 of all the channels are successive interrupt requests, looking at the number of times of execution of the interrupt request of each channel from cycle 1 to cycle 6, three times for channel 1 and three times for channel 2 Twice, channel 3 is performed once. From this, when the cycle is set to 6 cycles, the interrupt processing execution ratio of each channel is calculated as follows: channel 1: channel 2: channel 3 =
3: 2: 1 can be generated.

In the interrupt control device according to the first embodiment, the mask signal 38 from the ratio setting circuit 22 becomes valid, despite the fact that the channel 3 has the interrupt processing, and the host system 53 determines that there is no interrupt processing channel. (The section in FIG. 6:
Cycle 6 to cycle 8). Several embodiments of the present invention for avoiding such a situation will be described.

First, the interrupt request control circuit according to the third embodiment of the present invention
The same operation as in the second embodiment is performed, and when there is no channel, the output signal 38 of the ratio setting circuit 22 is immediately forced to "1" for all channels. With such an operation, when there is no interrupt request for a channel having a high ratio, a channel based on the priority in the priority encoder 24 can be preferentially allocated.

FIG. 7 is a detailed block diagram showing a configuration of an interrupt request control circuit according to the third embodiment of the present invention. FIG. 8 is a block diagram showing a specific configuration of the ratio setting circuit in FIG. FIG. FIG. 9 is a timing chart according to the third embodiment.

In the interrupt request control circuit shown in FIG.
3 in that an AND circuit and a synchronous RS flip-flop (SF / F) are added to the control circuit 20. The AND circuit outputs the signal 201 output from the shift register and the output signal 41 of the second detector 25.
Is set, a synchronous RS flip-flop (SF / F) is set, and the synchronous RS flip-flop (SF / F) is reset by a signal 202 output from the shift register. . A forced mask release request signal 45A is provided to the ratio setting circuit 22 as an output of the synchronous RS flip-flop (S-F / F).

In the ratio setting circuit 22 shown in FIG. 8, an OR circuit is further added to the configuration of FIG. The OR circuit ORs the output of the memory 71 and the forced mask release request signal 45A output from the synchronous RS flip-flop (SF / F) of the control circuit 20 to generate a mask signal 38. To the first detector 23.

Hereafter, when the interrupt request is channel 2
The case where the interrupt request is supplied from the peripheral I / O device 50 twice, the channel 2 twice and the channel 3 twice continuously will be described as an example. The first to fifth operations of the sampling signal 31 immediately after the power is turned on are described in the second section.
Since the operation is the same as that described in relation to the embodiment, detailed description thereof will be omitted.

In FIG. 7, the operation when the input of the sampling signal 31 is the sixth time will be described (the sixth cycle in FIG. 9). When the sampling signal 31 is input, the control circuit 20 generates a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed. Since the signal 41 output from the second detector 25 indicates "1", that is, there is no interrupt request, the peripheral I / O device 50
, And a signal 36 for operating the counter of the ratio setting circuit 22 are generated. The peripheral I / O device interrupt request signal 30 is "00
1 ", the output signal 37 of the first storage means 21
Receives the signal 34 and outputs “001”. Also,
The output signal 38 of the ratio setting circuit 22 receives the signal 36 and the count value in the ratio setting circuit 22 becomes 5, so that
"100" is output. Therefore, the first detector 23
Output signal 39 outputs “000”, and the output signal 41 of the second detector 25 outputs “1”. After the counter operation, since the signal 41 is "1" (section in FIG. 9), the signal 45 indicating the forced mask release request to immediately set the output signal 38 of the ratio setting circuit 22 of all channels to "1".
Generate A. Then, the signal 38 becomes (“111”)
And the first detector 23 changes the output signal 39 to “00”.
1 ”.

The priority encoder 24 receives the output signal 39 (“001”) of the first detector 23 and determines the channel 3. The decoder 26 receives the signal.
Outputs a signal 42 (“001”) and notifies the host system 53 of the processing request of the channel 3 by retiming in the second storage unit 27. Due to the processing performed by the host system 53, the peripheral I / O device 50 turns off the interrupt request (that is, the signal 30 becomes “000”).
Changes). Next, the control circuit 20 controls the host system 5 now.
3, the synchronous RS flip-flop (S) of the channel 3 in the first storage unit 21 of the channel requested to be processed.
-F / F) is generated. Thereby, the output signal 37 of the first storage unit 21 is output.
Becomes “000”, and further notifies the host system 53 of the channel to be processed, so that the signal 44 is turned off. Therefore, the output signal 39 of the first detector 23 is “00”
0 ", and the output signal 41 of the second detector 25 becomes" 1 ".
Becomes

As a result, the interrupt processing execution ratio of each channel is set to channel 1: channel 2: channel 3 = 3: 2: 1
If there is no interrupt request for a channel with a high ratio at the same time, another interrupt channel can be assigned as an interrupt request execution channel.

In the interrupt request control circuit 10 according to the above-described third embodiment, when there is no interrupt request of a channel having a high ratio, a priority encoder having a higher priority among other channels is assigned each time. However, in the fourth embodiment, when there is no interrupt request for a channel with a high ratio, when another channel is allocated, an interrupt request channel can be allocated at the set ratio of each channel. FIG. 10 shows a block diagram of an interrupt request control circuit according to the fourth embodiment. FIG. 11 shows a configuration example of the ratio setting circuit 22 at that time. FIG. 13 shows the timing of each signal in the fourth embodiment.

FIG. 10 is different from FIG. 7 in that the control circuit 20 sends a synchronous RS flip-flop (S-
F / F) is removed, and the output signal 45B output from the AND circuit is directly input to the counter of the ratio setting circuit 22 as a counter reset signal. The ratio setting circuit 22 shown in FIG. 11 is different from the configuration of FIG. 4 in that the counter is reset by the output signal 45B output from the AND circuit.

In order to facilitate understanding, an interrupt process when the number of interrupt channels is 3 and the read ratio of each channel is “channel 1: channel 2: channel 3 = 3: 2: 1” will be described. The basic operation is the same for a plurality of channels of three or more.

Hereinafter, when the interrupt request is continuous for channel 1,
The case where the interrupt request is supplied from the peripheral I / O device 50 four times, the channel 2 four times in a row, and the channel 3 three times in a row.

First, each storage means is reset to "0" by turning on the power. After turning on the power, setting means 5
From 2, the ratio of each channel is set. In FIG. 11, a ratio setting circuit 22 outputs a first set value 32
Is set to the counter cycle “7”. Next, the inside of the memory is set as the second set value. FIG. 12 shows a setting example in which an address is set as a count value, each bit of data is set as a channel number, a bit width is set as the number of channels, and “1” is set as unmasked. The counter starts from "0" when the signal 36 becomes active, and "1",
“2”, “3”, “4”, “5”, “6”, “7”,
The operation is repeated as “0”, “1”, “2”, “3”,. Next, since the memory uses the address as the count value and each bit of the data as the channel number, when the count value is “0”, the memory outputs “111” and outputs the count value “1”.
In the case of, "110", and in the case of the count value "2-7",
"100" is output to the signal 39 (MSB side is channel 1. Hereinafter, MSB side is channel 1).

Referring to FIG. 10, the initial values of the respective units after the power is turned on and the setting of the ratio setting circuit 22 is completed will be described first (the order of cycle 0 in FIG. 13). The S / F / F in the first storage unit 21 outputs a signal 37 (“000”). Therefore, the first detector 23 also outputs the signal 39.
(“000”) is output.

Next, the priority encoder 24
When there are a plurality of interrupt requests, one channel to be currently processed is determined based on the internally set priority (in this example, the smaller channel number has the higher priority). Now, the signal 39 (“00”) is output from the first detector.
0 "), a signal 40 (" no channel ") indicating that there is no corresponding channel is notified to the decoder 26. The decoder 2
6 receives the notification, and stores the information in the second storage unit 27 and the control circuit 20.
Is notified of a signal 42 ("000") indicating that there is no corresponding channel. The second storage means 27 receives the signal 42 from the decoder 26, performs retiming, and outputs a signal 43 (“000”) to the host system 53.

The second detector 25 receives the signal 39 (“000”) from the first detector 23 and outputs a signal 41 (“1”) indicating that there is no interrupt request to the control circuit 20.
Notify. The control circuit 20 does not operate because the host system interrupt sampling signal 31 is not input. Therefore, the signal 34, the signal 35, the signal 36, and the signal 45B output “0”. The ratio setting circuit 22 outputs the signal “111” because the count value is “0”.

Next, the operation when the input of the sampling signal 31 is the first time will be described (first cycle in FIG. 13). When the sampling signal 31 is input, the control circuit 20 outputs a signal 4 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed.
4 is generated. Next, since the signal 41 output from the second detector 25 indicates "1", that is, there is no interrupt request, the ratio of the signal 34 for taking in the interrupt request of the peripheral I / O device 50 to the signal 34 is satisfied. A signal 36 for operating the counter of the setting circuit is generated. The first storage unit 21 receives the signal 34 and receives the signal 30 (“111”).
And outputs the signal 37 (“111”). Since the counter in the ratio setting circuit 22 starts from "0" after the power is turned on, the signal 38 outputs "111". Therefore, the output signal 39 of the first detector 23 outputs “111”, and the output signal 41 of the second detector 25 outputs “0”. Here, since the signal 41 is "0" after the counter operation, the control circuit 20 does not generate the signal 45B.

The priority encoder 24 receives the output signal 39 ("111") of the first detector and determines the channel 1 having the smallest channel number. Upon receiving the signal, the decoder 26 outputs a signal 42 (“100”), and notifies the host system 53 of the processing request of the channel 1 by retiming in the second storage unit 27. The peripheral I / O device 50 lowers the interrupt request (that is, the signal 30
Changes to “011”). Next, the control circuit 20 generates a pulse signal 35 for clearing the S / F / F of the channel 1 in the first storage unit 21 of the channel for which the host system 53 has requested processing. Further, since the host system 53 is notified of the channel to be processed, the signal 44 is lowered. The first storage unit 21 receives the signal 35 and clears the SF / F of the channel 1. Therefore, the output signal 37
Becomes “011”.

Next, the operation when the input of the sampling signal 31 is the second time will be described (the second cycle in FIG. 13). When the sampling signal 31 is input, the control circuit 20 outputs a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed.
Generate Next, the signal 37 is "011" and the signal 38
Is “111”, the signal 41 output from the second detector 25 is “0”. That is, since it is notified that the fetched interrupt request is in any channel, the signal 34 for fetching the interrupt request of the peripheral I / O device 50 and the signal 36 for operating the counter of the ratio setting circuit are generated. Cancel generation. Since the first storage means 21 does not receive the signal 34, the signal 30 (“01
1)), the signal 37 becomes the value "01" of the previous state.
1 "is output.

The count value in the ratio setting circuit 22 remains "0" because the signal 36 does not come. Therefore signal 3
8 keeps outputting “111”. Therefore, the output signal 39 of the first detector 23 outputs “011” and the second
The output signal 41 of the detector 25 outputs “0”. Here, the control circuit 20 does not operate the counter,
The signal 45B is not generated regardless of the value of the signal 41. Next, the priority encoder 24 receives the output signal 39 (“011”) of the first detector and determines the channel 2 with the smallest channel number. Upon receiving the signal, the decoder 26 outputs a signal 42 (“010”), and notifies the host system 53 of the processing request of the channel 2 by retiming in the second storage unit 27. As a result of the host system 53 executing the processing, the peripheral I / O device 50
The interrupt request is turned off once, but the request is immediately turned on again (that is, the signal 30 remains "011"). Next, the control circuit 20 controls the host system 53 now.
, The synchronous RS flip-flop (S-
A pulse signal 35 for clearing F / F) is generated. Further, since the host system 53 is notified of the channel to be processed, the signal 44 is turned off. First storage means 2
1 receives a signal 35 and receives a synchronous RS of channel 2
Clear the flip-flop (S-F / F). Therefore, the output signal 37 becomes “001”.

Next, the operation when the input of the sampling signal 31 is the third time will be described (the third cycle in FIG. 13). When the sampling signal 31 is input, the control circuit 20 outputs a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed.
Generate Next, since the signal 37 is “001” and the signal 38 is “111”, the signal 41 output from the second detector 25 is “0”. That is, since it is notified that the fetched interrupt request is in any channel, the signal 34 for fetching the interrupt request of the peripheral I / O device 50 and the signal 36 for operating the counter of the ratio setting circuit are generated. Cancel generation.

In the first storage means 21, since the signal 34 does not come, the signal 30 ("011") is not taken in and the signal 3
7 outputs the value "001" of the previous state. The count value in the ratio setting circuit 22 remains "0" because the signal 36 does not come. Therefore, the signal 38 keeps outputting “111”. Therefore, the output signal 39 of the first detector 23
Outputs “001”, and the output signal 41 of the second detector 25 outputs “0”. Here, the control circuit 20 does not generate the signal 45B regardless of the value of the signal 41 because the counter is not operating.

Next, the priority encoder 24 receives the output signal 39 (“001”) of the first detector and determines the channel 3. Upon receiving the signal, the decoder 26
And outputs the signal 42 (“001”) to the second storage unit 27.
To notify the host system 53 of the processing request for channel 3. Since the host system 53 has executed the processing, the peripheral I / O device 50 lowers the interrupt request once but instantaneously receives the request. (That is, the signal 30 remains “011”).
Is the synchronous R of channel 3 in the first storage means 21 of the channel which has just requested processing to the host system 53.
A pulse signal 35 for clearing the S flip-flop (SF / F) is generated. Also, the host system 53
, The signal 44 is lowered. The first storage means 21 receives the signal 35 and receives a synchronous RS flip-flop (S / F / F) of the channel 3.
Clear Therefore, the output signal 37 becomes “00”.
0 ".

Next, the operation when the input of the sampling signal 31 is the fourth time will be described (the fourth cycle in FIG. 13). When the sampling signal 31 is input, the control circuit 20 outputs a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed.
Generate Next, since the signal 37 is “000” and the signal 38 is “111”, the signal 41 output from the second detector 25 is “1”. That is, since it is notified that there are no interrupt requests, a signal 34 for capturing an interrupt request from the peripheral I / O device 50 and a signal 36 for operating the counter of the ratio setting circuit are generated. The first storage unit 21 receives the signal 34 and receives the signal 3
It holds 0 (“011”) and outputs a signal 37 (“011”). The count value in the ratio setting circuit 22 is a signal 36
In response, it changes to "1". Therefore, the signal 38 is “1”
Thus, the output signal 39 of the first detector 23 outputs "010", and the output signal 41 of the second detector 25 outputs "0". 20
Does not generate the signal 45B because the signal 41 is "0" after the counter operation.

Next, the priority encoder 24 determines the channel 2 in response to the output signal 39 (“010”) of the first detector. Upon receiving the signal, the decoder 26
And outputs the signal 42 (“010”) to the second storage unit 27.
To notify the host system 53 of the processing request for channel 2. The peripheral I / O device 50 lowers the interrupt request once by executing the processing by the host system 53, but instantaneously sets the request (that is, the signal 30 remains "011"). Next, the control circuit 20
Is the synchronous R of channel 2 in the first storage means 21 of the channel that has just requested processing to the host system 53.
A pulse signal 35 for clearing the S flip-flop (SF / F) is generated. Also, the host system 53
, The signal 44 is turned off. The first storage means 21 receives the signal 35 and receives the synchronous RS flip-flop (S-F /
Clear F). Therefore, the output signal 37 becomes "00
1 ".

Next, the operation when the sampling signal 31 is input for the fifth time will be described (the fifth cycle in FIG. 13). When the sampling signal 31 is input, the control circuit 20 outputs a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed.
Generate Next, since the signal 37 is “001” and the signal 38 is “110”, the signal 41 output from the second detector 25 is “1”. That is, since it is notified that there are no interrupt requests, a signal 34 for capturing an interrupt request from the peripheral I / O device 50 and a signal 36 for operating the counter of the ratio setting circuit are generated (section in FIG. 13). ). The first storage means 21 receives the signal 34, holds the signal 30 (“011”), and outputs the signal 37 (“011”). Ratio setting circuit 22
The count value inside changes to “2” in response to the signal 36. Therefore, the signal 38 outputs “100”. Therefore, the output signal 39 of the first detector 23 outputs “000”, and the output signal 41 of the second detector 25 outputs “1”. Here, since the signal 41 is "1" after the counter operation, the control circuit 20 generates the signal 45B (FIG. 1).
Section 3). Therefore, the count value in the ratio setting circuit 22 becomes “0”, and the output signal 38 changes to “111”. Therefore, the output signal 39 of the first detector 23
Changes to “011”.

Next, the priority encoder 24 receives the output signal 39 ("011") of the first detector and determines the channel 2 having the smallest channel number. Upon receiving the signal, the decoder 26 outputs a signal 42 (“010”), and notifies the host system 53 of the processing request of the channel 2 by retiming in the second storage unit 27. The peripheral I / O device 50 turns off the interrupt request once by executing the processing by the host system 53, but immediately turns on the request. (That is, signal 30 is
Next, the control circuit 20 sends the first storage means 21 of the channel which has requested the host system 53 to process.
A pulse signal 35 for clearing a synchronous RS flip-flop (S / F / F) of the channel 2 in the channel 2 is generated. Further, since the host system 53 is notified of the channel to be processed, the signal 44 is turned off. The first storage unit 21 receives the signal 35 and clears the synchronous RS flip-flop (SF / F) of the channel 2.
Therefore, the output signal 37 becomes “001”.

Next, the operation when the sampling signal 31 is input for the sixth time will be described (the sixth cycle in FIG. 13). When the sampling signal 31 is input, the control circuit 20 outputs a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed.
Generate Next, since the signal 37 is “001” and the signal 38 is “111”, the signal 4 output from the second detector 25 is output.
1 is "0". That is, since it is notified that there is an interrupt request somewhere, the generation of the signal 34 for capturing the interrupt request of the peripheral I / O device 50 and the signal 36 for operating the counter of the ratio setting circuit are not performed. The first storage means 21 does not receive the signal 30 (“011”) because the signal 34 does not come. That is, the signal 37 outputs “001”. Ratio setting circuit 22
The count value within remains at "0" since the signal 36 does not come. Therefore, the signal 38 outputs “111”. Therefore, the output signal 39 of the first detector 23 is “00”
1 ", and the output signal 41 of the second detector 25 is
Outputs “0”. Here, the control circuit 20 does not operate the counter.
Do not generate 5B.

Next, the priority encoder 24 determines the channel 3 in response to the output signal 39 (“001”) of the first detector. Upon receiving the signal, the decoder 26
And outputs the signal 42 (“001”) to the second storage unit 27.
To notify the host system 53 of the processing request for channel 3. Since the host system 53 has executed the processing, the peripheral I / O device 50 turns off the interrupt request once but instantaneously turns the request on again (that is, the signal 30 remains “011”). And). Next, the control circuit 20 transmits the synchronous RS flip-flop (S-F / F / F) of the channel 3 in the first storage unit 21 of the channel that has just requested the host system 53 to process.
A pulse signal 35 for clearing F) is generated. Further, since the host system 53 is notified of the channel to be processed, the signal 44 is turned off. The first storage means 21
Upon receiving the signal 35, the synchronous RS flip-flop (S / F / F) of the channel 3 is cleared. Therefore, the output signal 37 becomes “000”.

Next, the operation when the sampling signal 31 is input for the seventh time will be described (the seventh cycle in FIG. 13). When the sampling signal 31 is input, the control circuit 20 outputs a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed.
Generate Next, since the signal 37 is “000” and the signal 38 is “111”, the signal 4 output from the second detector 25 is output.
1 is “1”. That is, since it is notified that there are no interrupt requests, the peripheral I / O device 5
A signal 34 for taking in an interrupt request of 0 and a signal 36 for operating the counter of the ratio setting circuit are generated.
The first storage means 21 receives the signal 34 and receives the signal 30
(“011”) and outputs the signal 37 (“011”). The count value in the ratio setting circuit 22 changes to “1” in response to the signal 36. Therefore, the signal 38 is "11
0 ". Therefore, the output signal 3 of the first detector 23 is output.
9 outputs “010”, and the output signal 41 of the second detector 25 outputs “0”. Here, since the signal 41 is "0" after the counter operation, the control circuit 20 outputs the signal 4
Do not generate 5B.

Next, the priority encoder 24 determines the channel 2 in response to the output signal 39 (“010”) of the first detector. Upon receiving the signal, the decoder 26
And outputs the signal 42 (“010”) to the second storage unit 27.
To notify the host system 53 of the processing request for channel 2. The peripheral I / O device 50 lowers the interrupt request due to the processing performed by the host system 53. (That is, the signal 30 changes to “001”.)
Next, the control circuit 20 checks the channel 2 in the first storage means 21 of the channel that has just requested the host system 53 to process.
A pulse signal 35 for clearing the synchronous RS flip-flop (S / F / F) is generated. Also, since the host system 53 is notified of the channel to be processed,
The signal 44 is turned off. The first storage means 21 stores the signal 3
5 and clears SF / F of channel 2. Therefore, the output signal 37 becomes “001”.

Next, the operation when the input of the sampling signal 31 is the eighth time will be described (the eighth cycle in FIG. 13). When the sampling signal 31 is input, the control circuit 20 outputs a signal 44 for extending the signal 43 until the host system 53 receives an interrupt channel to be processed.
Generate Next, since the signal 37 is “001” and the signal 38 is “110”, the signal 4 output from the second detector 25 is output.
1 is “1”. That is, since it is notified that there are no interrupt requests, the peripheral I / O device 5
A signal 34 for taking in an interrupt request of 0 and a signal 36 for operating the counter of the ratio setting circuit are generated.
The first storage means 21 receives the signal 34 and receives the signal 30
(“001”) and outputs the signal 37 (“001”).

The count value in the ratio setting circuit 22 changes to “2” in response to the signal 36. So signal 38 is
"100" is output. Therefore, the output signal 39 of the first detector 23 outputs “000”, and the output signal 41 of the second detector 25 outputs “1”. Here, since the signal 41 is “1” after the counter operation,
The signal 45B is generated. Therefore, the count value in the ratio setting circuit 22 becomes “0”, and the output signal 38 becomes “111”.
Changes to Therefore, the output signal of the first detector 23 is
It changes to “001”.

Next, the priority encoder 24 determines the channel 3 in response to the output signal 39 (“001”) of the first detector. Upon receiving the signal, the decoder 26
And outputs the signal 42 (“001”) to the second storage unit 27.
To notify the host system 53 of the processing request for channel 3. The peripheral I / O device 50 turns off the interrupt request by executing the processing by the host system 53 (that is, the signal 30 changes to “000”). Next, the control circuit 20 transmits the synchronous RS flip-flop (S-F / F / F) of the channel 3 in the first storage unit 21 of the channel that has just requested the host system 53 to process.
A pulse signal 35 for clearing F) is generated. Further, since the host system 53 is notified of the channel to be processed, the signal 44 is turned off. The first storage means 21
Upon receiving the signal 35, the synchronous RS flip-flop (S / F / F) of the channel 3 is cleared. Therefore, the output signal 37 becomes “000”.

As described above, the interrupt processing execution ratio of each channel is set as follows: channel 1: channel 2: channel 3 = 3:
When there is no interrupt request of a channel having a high ratio at the same time as the interrupt request can be generated at a ratio of 2: 1, another interrupt channel can be allocated as an interrupt request execution channel.

FIG. 14 is a block diagram in the case where the configuration equivalent to that of FIG. 15 described as the prior art is configured by using the present invention. In comparison with FIG. 15, FIG. Is a much simpler configuration.

Therefore, the first effect is that the expandability is improved. This is because even if the number of interrupt processes is increased after the hardware has been commercialized once, the reception of requests can be averaged as a whole.

The second effect is to stabilize the operation of the entire system. This is because it is possible to average the reception of interrupt requests of each channel or to add an arbitrary priority.

The present invention is not limited to the above-described and illustrated embodiments, but can be variously modified and implemented within the scope of the gist.

[0106]

As described above, according to the present invention,
When deciding which processing request to execute from among multiple processing requests, interrupt requests are averaged according to the processing execution rate set for each channel, excellent in scalability when combining multiple processing requests, and interrupt notification is performed many times. And an interrupt request control circuit having a simple configuration can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an interrupt request control circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a ratio setting circuit in the interrupt request control circuit of FIG.

FIG. 3 is a block diagram illustrating a configuration of an interrupt request control circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a ratio setting circuit in the interrupt request control circuit of FIG. 3;

FIG. 5 is a schematic diagram for explaining setting contents in a memory in a ratio setting circuit of the interrupt request control circuit of FIG. 4;

FIG. 6 is a timing chart for explaining the operation of the interrupt request control circuit of FIG. 3;

FIG. 7 is a block diagram illustrating a configuration of an interrupt request control circuit according to a third embodiment of the present invention.

8 is a block diagram showing a configuration of a ratio setting circuit in the interrupt request control circuit of FIG.

FIG. 9 is a timing chart for explaining the operation of the interrupt request control circuit of FIG. 7;

FIG. 10 is a block diagram illustrating a configuration of an interrupt request control circuit according to a fourth embodiment of the present invention.

11 is a block diagram showing a configuration of a ratio setting circuit in the interrupt request control circuit of FIG.

12 is a schematic diagram for explaining setting contents in a memory in a ratio setting circuit of the interrupt request control circuit of FIG. 11;

FIG. 13 is a timing chart for explaining the operation of the interrupt request control circuit of FIG. 10;

FIG. 14 is a schematic block diagram showing a configuration when a configuration equivalent to a conventional interrupt request control circuit is realized by using the present invention.

FIG. 15 is a block diagram showing a configuration of an example of a conventional interrupt request control circuit.

FIG. 16 is a block diagram illustrating a configuration example of an interrupt processing circuit using an interrupt request control circuit.

[Explanation of symbols]

Reference Signs List 10 interrupt control circuit 20 control circuit 21 first storage means 22 ratio setting circuit 23 first detector 24 priority encoder 25 second detector 26 decoder 27 second storage means 50 interrupt request generator (peripheral I / O) Device interrupt request) 51 timing signal generating means (host system interrupt sampling signal) 52 setting means 53 processing means (host system) 70 counter 71 third storage means

Claims (1)

[Claims] 1. A control circuit responsive to a timing signal, a signal indicating that interrupt requests for all channels have disappeared, and a decode value of a channel on which interrupt processing has been performed, and an interrupt request responsive to an output of the control circuit. First storage means for outputting whether or not there is an unprocessed interrupt request for each channel; and a ratio for generating a signal corresponding to the ratio of each channel in response to the output of the control circuit based on a set value. A setting circuit; a first detector that outputs a signal notifying a channel to be processed among channels having an interrupt request in response to outputs of the first storage unit, the control circuit, and the ratio setting circuit; A priority encoder that outputs a signal indicating a channel to be processed in response to an output of the first detector; and a control circuit that instructs the control circuit to respond to an output of the first detector. A second detector that outputs a signal indicating that there has been no longer an interrupt request, a decoder that decodes an output of the priority encoder, and outputs a decoded value of a channel on which an interrupt process has been performed to the control circuit, And a second storage unit for outputting a processing request in which the decoded value is retimed in response to the output of the interrupt request control circuit.