JP5565000B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP5565000B2
JP5565000B2 JP2010047325A JP2010047325A JP5565000B2 JP 5565000 B2 JP5565000 B2 JP 5565000B2 JP 2010047325 A JP2010047325 A JP 2010047325A JP 2010047325 A JP2010047325 A JP 2010047325A JP 5565000 B2 JP5565000 B2 JP 5565000B2
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Prior art keywords
wiring
semiconductor
insulating film
semiconductor device
semiconductor structure
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JP2010047325A
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JP2011181861A (en
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裕康 定別当
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Description

本発明は、半導体装置の製造方法に関する。 The present invention relates to a method of manufacturing a semiconductor device.

従来の半導体装置には、基板にビアホールを形成し、ビアホールに導体を充填することにより基板の一方の面に実装された半導体チップの電極と基板の他方の面に形成された外部電極との電気的接続をとるものがある（特許文献１参照）。   In a conventional semiconductor device, a via hole is formed in a substrate, and a conductor is filled in the via hole, whereby an electrical connection between an electrode of a semiconductor chip mounted on one surface of the substrate and an external electrode formed on the other surface of the substrate. There is a thing which takes a general connection (refer patent document 1).

また、半導体チップが基板上に実装されているため、基板の厚みによって半導体装置全体が厚くなってしまう。そこで、半導体装置を小型化する試みがなされている（例えば非特許文献１参照）。半導体チップを支持基材に支持した状態で半導体チップ及び支持基材上に封止層を形成した後、支持基材を除去する。その後、配線をパターニングする。   Further, since the semiconductor chip is mounted on the substrate, the entire semiconductor device becomes thick depending on the thickness of the substrate. Therefore, attempts have been made to downsize semiconductor devices (see, for example, Non-Patent Document 1). After forming the sealing layer on the semiconductor chip and the support substrate in a state where the semiconductor chip is supported on the support substrate, the support substrate is removed. Thereafter, the wiring is patterned.

特開２００８−４２０６３号公報JP 2008-42063 A

「２００９年度版 日本実装技術ロードマップ」社団法人 電子情報技術産業協会、ｐ．１７２“2009 Japan Implementation Technology Roadmap” Japan Electronics and Information Technology Industries Association, p. 172

しかし、半導体装置をさらに小型化したいという強い市場の要望がある。本発明の課題は、さらに小型化可能な構造の半導体装置の製造方法を提供することである。 However, there is a strong market demand for further downsizing of semiconductor devices. The subject of this invention is providing the manufacturing method of the semiconductor device of the structure which can be further reduced in size.

本発明の態様によれば、
絶縁膜、第１配線及び第２配線が形成されたキャリアーの前記第１配線及び前記第２配線が形成された面に、電極を下に向けて最下部の半導体構成体を接着する第１工程と、
前記最下部の半導体構成体の上部に、電極を上に向けて他の１又は複数の半導体構成体を重ねて接着する第２工程と、
前記第２配線と前記他の１又は複数の半導体構成体の電極とをボンディングワイヤーにより接続する第３工程と、
前記最下部の半導体構成体、前記他の１又は複数の半導体構成体、前記第２配線及び前記ボンディングワイヤーを封止する封止層を前記絶縁膜の上部に形成する第４工程と、
前記絶縁膜、前記第１配線及び前記第２配線を残して前記キャリアーを除去する第５工程と、
前記絶縁膜の下側から前記第１配線及び前記第２配線に向けてレーザーを照射することによって前記第１配線及び前記第２配線まで到達する穴を形成する第６工程と、
前記絶縁膜の下面及び前記穴の内部にそれぞれ第１金属層及び第２金属層を形成し、前記第１金属層を介して前記最下部の半導体構成体の前記電極と前記第１配線とを相互に接続するとともに、前記第２配線と前記第２金属層とを接続する第７工程と、
を含むことを特徴とする半導体装置の製造方法が提供される。 According to an aspect of the invention,
Insulating film, the first wiring and the second wiring is formed the surface of the carrier that the first wiring and the second wiring are formed, a first step of adhering the bottom of the semiconductor structure toward the electrode down When,
A second step of stacking and adhering another one or more semiconductor structures on top of the lowermost semiconductor structure with the electrode facing upward;
A third step of connecting the second wiring and the electrodes of the one or more other semiconductor components by a bonding wire;
A fourth step of forming a sealing layer for sealing the lowermost semiconductor structure, the one or more other semiconductor structures, the second wiring, and the bonding wire on the insulating film;
A fifth step of removing the carrier leaving the insulating film, the first wiring and the second wiring;
A sixth step of forming a hole reaching the first wiring and the second wiring by irradiating a laser from the lower side of the insulating film toward the first wiring and the second wiring;
A first metal layer and a second metal layer are formed on the lower surface of the insulating film and inside the hole, respectively, and the electrode and the first wiring of the lowermost semiconductor structure are connected via the first metal layer. A seventh step of connecting the second wiring and the second metal layer together with each other;
A method for manufacturing a semiconductor device is provided .

本発明によれば、さらに小型化可能な構造の半導体装置の製造方法を提供することができる。 According to the present invention, it is possible to provide a method of manufacturing a semiconductor device miniaturization possible structures.

本発明の第１の実施形態に係る半導体装置１Ａの断面図である。1 is a cross-sectional view of a semiconductor device 1A according to a first embodiment of the present invention. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 本発明の第２の実施形態に係る半導体装置１Ｂの断面図である。It is sectional drawing of the semiconductor device 1B which concerns on the 2nd Embodiment of this invention. 半導体装置１Ｂの製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor device 1B. 半導体装置１Ｂの製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor device 1B. 半導体装置１Ｂの製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor device 1B. 本発明の第３の実施形態に係る半導体装置１Ｃの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 C of semiconductor devices which concern on the 3rd Embodiment of this invention. 本発明の第４の実施形態に係る半導体装置１Ｄの製造方法の説明図である。It is explanatory drawing of the manufacturing method of semiconductor device 1D which concerns on the 4th Embodiment of this invention. （ａ）〜（ｄ）は他の形態の半導体構成体を示す断面図である。(A)-(d) is sectional drawing which shows the semiconductor structure of another form.

以下に、本発明を実施するための好ましい形態について図面を用いて説明する。但し、以下に述べる実施形態には、本発明を実施するために技術的に好ましい種々の限定が付されているが、発明の範囲を以下の実施形態及び図示例に限定するものではない。   Hereinafter, preferred embodiments for carrying out the present invention will be described with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

＜第１実施形態＞
図１は、本発明の第１の実施形態に係る半導体装置１Ａの断面図である。この半導体装置１Ａは、半導体構成体１０、２０を重ねた状態でパッケージしたものである。半導体構成体１０、２０は、それぞれ半導体チップ１１、２１及び複数の電極１２Ａ〜１２Ｄ、２２Ａ、２２Ｂを備える。半導体チップ１１、２１は、シリコン基板の半導体基板に集積回路を設けたものである。複数の電極１２Ａ〜１２Ｄ、２２Ａ、２２Ｂは半導体チップ１１、２１の互いに対向する面の反対側の一方の面に設けられている。電極１２Ａ〜１２Ｄ、２２Ａ、２２Ｂは、Ｃｕからなるものである。なお、電極１２Ａ〜１２Ｄ、２２Ａ、２２Ｂは、配線の一部であってもよい。 <First Embodiment>
FIG. 1 is a cross-sectional view of a semiconductor device 1A according to the first embodiment of the present invention. This semiconductor device 1A is packaged in a state where the semiconductor structural bodies 10 and 20 are stacked. The semiconductor structures 10 and 20 include semiconductor chips 11 and 21 and a plurality of electrodes 12A to 12D, 22A, and 22B, respectively. The semiconductor chips 11 and 21 are obtained by providing an integrated circuit on a semiconductor substrate of a silicon substrate. The plurality of electrodes 12 </ b> A to 12 </ b> D, 22 </ b> A, 22 </ b> B are provided on one surface of the semiconductor chips 11, 21 opposite to the surfaces facing each other. The electrodes 12A to 12D, 22A, and 22B are made of Cu. The electrodes 12A to 12D, 22A, and 22B may be part of the wiring.

図１に示すように、半導体構成体１０の電極１２Ａ〜１２Ｄを下側、半導体構成体２０の電極２２Ａ、２２Ｂを上側に向けた状態で、半導体構成体１０の上面と半導体構成体２０の下面とが接着樹脂層２３により接着されている。また、半導体構成体１０の下面は、接着樹脂層１３により絶縁膜３０の上面に接着されている。接着樹脂層１３、２３は、エポキシ系樹脂といった熱硬化性樹脂からなり、絶縁性を有する。接着樹脂層１３、２３は、繊維強化されていない。接着樹脂層１３には、電極１２Ａ〜１２Ｄと対応する位置にそれぞれビアホール１３Ａ〜１３Ｄが設けられている。   As shown in FIG. 1, the upper surface of the semiconductor structure 10 and the lower surface of the semiconductor structure 20 with the electrodes 12A to 12D of the semiconductor structure 10 facing down and the electrodes 22A and 22B of the semiconductor structure 20 facing up. Are bonded by the adhesive resin layer 23. The lower surface of the semiconductor structure 10 is bonded to the upper surface of the insulating film 30 by the adhesive resin layer 13. The adhesive resin layers 13 and 23 are made of a thermosetting resin such as an epoxy resin, and have insulating properties. The adhesive resin layers 13 and 23 are not fiber reinforced. In the adhesive resin layer 13, via holes 13A to 13D are provided at positions corresponding to the electrodes 12A to 12D, respectively.

絶縁膜３０は、繊維強化樹脂膜である。具体的には、絶縁膜３０は、ガラス布基材エポキシ樹脂、ガラス布基材ポリイミド樹脂その他のガラス布基材絶縁性樹脂複合材からなる。
絶縁膜３０には、導体からなる埋め込み配線４１、４２、４３、４４が上面に設けられている。配線を埋め込むことで、絶縁膜３０の表面を平坦にすることができる。
埋め込み配線４１、４２は、それぞれ一端が電極１２Ａ、１２Ｂと対応する位置に配置されている。当該端部には貫通穴４１Ａ、４２Ｂが設けられている。貫通穴４１Ａ、４２Ｂの大きさはビアホール１３Ａ、１３Ｂの大きさに等しい。
埋め込み配線４３はボンディングワイヤー２４により電極２２Ａと、埋め込み配線４４はボンディングワイヤー２５により電極２２Ｂと、それぞれ接続されている。 The insulating film 30 is a fiber reinforced resin film. Specifically, the insulating film 30 is made of glass cloth base epoxy resin, glass cloth base polyimide resin, or other glass cloth base insulating resin composite.
The insulating film 30 is provided with embedded wirings 41, 42, 43, 44 made of a conductor on the upper surface. By embedding the wiring, the surface of the insulating film 30 can be flattened.
One end of each of the embedded wirings 41 and 42 is disposed at a position corresponding to the electrodes 12A and 12B. Through holes 41A and 42B are provided at the end portions. The sizes of the through holes 41A and 42B are equal to the sizes of the via holes 13A and 13B.
The embedded wiring 43 is connected to the electrode 22A by the bonding wire 24, and the embedded wiring 44 is connected to the electrode 22B by the bonding wire 25.

また、絶縁膜３０の上部には、半導体構成体１０、２０、接着樹脂層１３、２３、及びボンディングワイヤー２４、２５を封止する封止層２９が設けられている。封止層２９は、エポキシ系樹脂、ポリイミド系樹脂その他の絶縁性樹脂からなる。封止層２９は、フィラーを含有した熱硬化性樹脂（例えば、エポキシ樹脂）からなることが好ましい。なお、封止層２９は、ガラス布基材絶縁性樹脂のように繊維強化されたものではないが、繊維強化樹脂からなるものとしてもよい。   Further, a sealing layer 29 for sealing the semiconductor structural bodies 10 and 20, the adhesive resin layers 13 and 23, and the bonding wires 24 and 25 is provided on the insulating film 30. The sealing layer 29 is made of an epoxy resin, a polyimide resin, or other insulating resin. The sealing layer 29 is preferably made of a thermosetting resin (for example, epoxy resin) containing a filler. The sealing layer 29 is not fiber reinforced unlike the glass cloth base insulating resin, but may be made of fiber reinforced resin.

絶縁膜３０には、電極１２Ａ〜１２Ｄと対応する位置にそれぞれスルーホール３１、３２、ビアホール３３、３４が形成されている。また、絶縁膜３０には、埋め込み配線４１の貫通穴４１Ａと反対側の端部に対応する位置にビアホール３５が、埋め込み配線４２の貫通穴４２Ｂと反対側の端部に対応する位置にビアホール３６が、埋め込み配線４３と対応する位置にビアホール３７が、埋め込み配線４４と対応する位置にビアホール３８が、それぞれ設けられている。   Through holes 31 and 32 and via holes 33 and 34 are formed in the insulating film 30 at positions corresponding to the electrodes 12A to 12D, respectively. The insulating film 30 has a via hole 35 at a position corresponding to the end portion of the embedded wiring 41 opposite to the through hole 41A, and a via hole 36 at a position corresponding to the end portion of the embedded wiring 42 opposite to the through hole 42B. However, a via hole 37 is provided at a position corresponding to the embedded wiring 43, and a via hole 38 is provided at a position corresponding to the embedded wiring 44.

ビアホール１３Ａ、スルーホール３１、貫通穴４１Ａには、コンタクト部５１を構成する導体が充填されている。電極１２Ａと配線４１とはコンタクト部５１を介して導通している。同様に、ビアホール１３Ｂ、スルーホール３２、貫通穴４２Ｂには、コンタクト部５２を構成する導体が充填されている。電極１２Ｂと配線４２とはコンタクト部５２を介して導通している。   The via hole 13A, the through hole 31, and the through hole 41A are filled with a conductor constituting the contact portion 51. The electrode 12A and the wiring 41 are electrically connected via the contact portion 51. Similarly, the via hole 13B, the through hole 32, and the through hole 42B are filled with a conductor constituting the contact portion 52. The electrode 12B and the wiring 42 are electrically connected via the contact portion 52.

ビアホール１３Ｃ、３３には、コンタクト部５３を構成する導体が充填されている。コンタクト部５３は電極１２Ｃと導通している。ビアホール１３Ｄ、３４には、コンタクト部５４を構成する導体が充填されている。コンタクト部５４は電極１２Ｄと導通している。
ビアホール３５〜３８には、コンタクト部５５〜５８を構成する導体が充填されている。コンタクト部５５は埋め込み配線４１と、コンタクト部５６は埋め込み配線４２と、コンタクト部５７は埋め込み配線４３と、コンタクト部５８は埋め込み配線４４と、それぞれ導通している。 The via holes 13C and 33 are filled with a conductor constituting the contact portion 53. The contact part 53 is electrically connected to the electrode 12C. The via holes 13D and 34 are filled with a conductor constituting the contact portion 54. The contact part 54 is electrically connected to the electrode 12D.
The via holes 35 to 38 are filled with a conductor constituting the contact portions 55 to 58. The contact portion 55 is electrically connected to the embedded wire 41, the contact portion 56 is electrically connected to the embedded wire 42, the contact portion 57 is electrically connected to the embedded wire 43, and the contact portion 58 is electrically connected to the embedded wire 44.

絶縁膜３０の下面には、ソルダーレジスト６０が設けられる。ソルダーレジスト６０には、コンタクト部５３〜５８を露出させる開口部６３〜６８が設けられる。開口部６３〜６８には、コンタクト部５３〜５８と導通するように半田バンプ７３〜７８が設けられる。
なお、開口部６３〜６８内において、コンタクト部５３〜５８の表面には、メッキ（例えば、金メッキからなる単層メッキ、或いはニッケルメッキ・金メッキからなる二層メッキ等）が形成されていてもよい。 A solder resist 60 is provided on the lower surface of the insulating film 30. The solder resist 60 is provided with openings 63 to 68 that expose the contact parts 53 to 58. Solder bumps 73 to 78 are provided in the openings 63 to 68 so as to be electrically connected to the contact parts 53 to 58.
In the openings 63 to 68, plating (for example, single-layer plating made of gold plating or double-layer plating made of nickel plating / gold plating) may be formed on the surfaces of the contact portions 53 to 58. .

次に、半導体装置１Ａの製造方法について説明する。まず、図２に示すように、金属からなるキャリアー９０上に、絶縁膜３０を積層してから、埋め込み配線４１、４２、４３、４４を積層し、ホットプレス成形により一体化する。
キャリアー９０は、半導体装置１Ａとなる部材、例えば複数の半導体構成体１０を載置、貼着或いは接着して搬送するためのキャリアーであり、具体的には銅箔である。 Next, a method for manufacturing the semiconductor device 1A will be described. First, as shown in FIG. 2, an insulating film 30 is laminated on a carrier 90 made of metal, and then embedded wirings 41, 42, 43, and 44 are laminated and integrated by hot press molding.
The carrier 90 is a carrier for transporting a member to be the semiconductor device 1A, for example, a plurality of semiconductor components 10 by placing, attaching or adhering them, and is specifically a copper foil.

次に、図２に示すように、絶縁膜３０の上面に接着樹脂層１３を塗布し、その上に電極１２Ａ、１２Ｂと貫通穴４１Ａ、４２Ｂとが重なるように、電極１２Ａ〜１２Ｄが形成された面を下にして半導体構成体１０をボンディングする。具体的には、非導電性ペースト（ＮＣＰ；Non-Conductive Paste）を印刷法又はディスペンサ法によって絶縁膜３０に塗布した後、又は非導電性フィルム（ＮＣＦ；Non-Conductive Film）を絶縁膜３０に貼り合わせた後、半導体構成体１０の下面を非導電性ペースト又は非導電性フィルムに向けて下降させて接触させてから、加熱圧着する。非導電性ペースト又は非導電性フィルムが硬化して接着樹脂層１３となる。   Next, as shown in FIG. 2, the adhesive resin layer 13 is applied to the upper surface of the insulating film 30, and the electrodes 12A to 12D are formed so that the electrodes 12A and 12B and the through holes 41A and 42B overlap each other. The semiconductor structure 10 is bonded with the surface facing down. Specifically, a non-conductive paste (NCP; Non-Conductive Paste) is applied to the insulating film 30 by a printing method or a dispenser method, or a non-conductive film (NCF; Non-Conductive Film) is applied to the insulating film 30. After the bonding, the lower surface of the semiconductor structure 10 is lowered and brought into contact with the non-conductive paste or non-conductive film, and then thermocompression bonded. The non-conductive paste or non-conductive film is cured to form the adhesive resin layer 13.

次に、図３に示すように、半導体チップ１１の上面に接着樹脂層２３となる導電性ペースト又は非導電性フィルムを設け、その上に電極２２Ａ、２２Ｂを上側に向けた状態で半導体構成体２０を載置してボンディングする。
次に、図４に示すように、ボンディングワイヤー２４、２５により電極２２Ａ、２２Ｂと埋め込み配線４３、４４とを接続する。このとき、半導体構成体２０の電極２２Ａ、２２Ｂが上向きであるため、ボンディングワイヤー２４、２５により容易に接続することができる。 Next, as shown in FIG. 3, a semiconductor structure is provided with a conductive paste or non-conductive film serving as the adhesive resin layer 23 provided on the upper surface of the semiconductor chip 11 and the electrodes 22 </ b> A and 22 </ b> B facing upward. 20 is mounted and bonded.
Next, as shown in FIG. 4, the electrodes 22 </ b> A and 22 </ b> B and the embedded wirings 43 and 44 are connected by bonding wires 24 and 25. At this time, since the electrodes 22A and 22B of the semiconductor structure 20 are facing upward, they can be easily connected by the bonding wires 24 and 25.

次に、図５に示すように、フィラーを含有した熱硬化性樹脂により封止層２９を形成する。
次に、図６に示すように、キャリアー９０をエッチング（例えば、ウェットエッチング等のケミカルエッチング）或いは物理的な引き剥がしによって除去する。キャリアー９０を除去しても、封止層２９及び絶縁膜３０の積層構造により、十分な強度を確保することができる。 Next, as shown in FIG. 5, the sealing layer 29 is formed with a thermosetting resin containing a filler.
Next, as shown in FIG. 6, the carrier 90 is removed by etching (for example, chemical etching such as wet etching) or physical peeling. Even if the carrier 90 is removed, sufficient strength can be ensured by the laminated structure of the sealing layer 29 and the insulating film 30.

次に、図７に示すように、絶縁膜３０にレーザー光を照射し、ビアホール１３Ａ〜１３Ｄ、スルーホール３１、３２、ビアホール３３〜３８を形成する。このとき、埋め込み配線４１、４２がマスクとなるため、ビアホール１３Ａ、１３Ｂの大きさは貫通穴４１Ａ、４２Ｂの大きさによって定まる。   Next, as shown in FIG. 7, the insulating film 30 is irradiated with laser light to form via holes 13 </ b> A to 13 </ b> D, through holes 31 and 32, and via holes 33 to 38. At this time, since the buried wirings 41 and 42 serve as a mask, the size of the via holes 13A and 13B is determined by the size of the through holes 41A and 42B.

絶縁膜３０が繊維強化樹脂からなるため、高出力のレーザー光を照射するレーザーとしては炭酸ガスレーザー（ＣＯ２レーザー）を用いることが好ましい。なお、スルーホール３１、３２、及びビアホール３３〜３８を形成した後に、紫外線レーザー（ＵＶレーザー）又は低出力のＣＯレーザーによりビアホール１３Ａ〜１３Ｄを形成してもよい。
次に、ビアホール１３Ａ〜１３Ｄ、スルーホール３１、３２、ビアホール３３〜３８内をデスミア処理する。 Since the insulating film 30 is made of a fiber reinforced resin, it is preferable to use a carbon dioxide gas laser (CO 2 laser) as a laser for irradiating a high-power laser beam. In addition, after forming the through holes 31 and 32 and the via holes 33 to 38, the via holes 13A to 13D may be formed by an ultraviolet laser (UV laser) or a low output CO laser.
Next, desmear processing is performed in the via holes 13A to 13D, the through holes 31 and 32, and the via holes 33 to 38.

次に、図８に示すように、メッキ処理を行うことによって、絶縁膜３０の下面全体に金属メッキ膜５０を形成する。金属メッキ膜５０は無電解メッキ処理、電気メッキ処理を順に行うことによって成膜してもよいし、無電解メッキ処理のみによって成膜してもよい。この際、ビアホール１３Ａ〜１３Ｄ、スルーホール３１、３２、ビアホール３３〜３８が金属メッキ膜５０の一部によって埋められる。   Next, as shown in FIG. 8, a metal plating film 50 is formed on the entire lower surface of the insulating film 30 by performing a plating process. The metal plating film 50 may be formed by performing an electroless plating process and an electroplating process in order, or may be formed only by an electroless plating process. At this time, the via holes 13 </ b> A to 13 </ b> D, the through holes 31 and 32, and the via holes 33 to 38 are filled with a part of the metal plating film 50.

次に、図９に示すように、フォトリソグラフィー法及びエッチング法により金属メッキ膜５０をパターニングすることで、金属メッキ膜５０をコンタクト部５１〜５８に加工する。なお、上述のようなサブトラクティブ法によってコンタクト部５１〜５８のパターニングを行うのではなく、セミアディティブ法又はフルアディティブ法によってコンタクト部５１〜５８のパターニングを行ってもよい。   Next, as shown in FIG. 9, the metal plating film 50 is processed into contact parts 51 to 58 by patterning the metal plating film 50 by a photolithography method and an etching method. Instead of patterning the contact portions 51 to 58 by the subtractive method as described above, the contact portions 51 to 58 may be patterned by a semi-additive method or a full additive method.

次に、図１０に示すように、絶縁膜３０の下面に樹脂材料を印刷して、その樹脂材料を硬化させることによって、ソルダーレジスト６０をパターニングする。ソルダーレジスト６０のパターニングにより、開口部６３〜６８が形成され、開口部６３〜６８内でコンタクト部５３〜５８を露出させるが露出している。   Next, as shown in FIG. 10, the solder resist 60 is patterned by printing a resin material on the lower surface of the insulating film 30 and curing the resin material. By patterning the solder resist 60, openings 63 to 68 are formed, and the contact parts 53 to 58 are exposed in the openings 63 to 68, but are exposed.

なお、絶縁膜３０の下面全体にディップコート法又はスピンコート法により感光性樹脂を塗布し、露光・現像することによって、ソルダーレジスト６０をパターニングしてもよい。   Note that the solder resist 60 may be patterned by applying a photosensitive resin to the entire lower surface of the insulating film 30 by dip coating or spin coating, and exposing and developing.

次に、開口部６３〜６８内においてコンタクト部５３〜５８の表面に金メッキ又はニッケルメッキ・金メッキを無電界メッキ法により成長させる端子処理を行う。次に、図１１に示すように、開口部６３〜６８内に半田バンプ７３〜７８を形成する。その後、図１２に示すように、ダイシング処理を行うことで、複数の半導体装置１Ａを切り出すことができる。   Next, terminal processing is performed in which gold plating or nickel plating / gold plating is grown by electroless plating on the surfaces of the contact portions 53 to 58 in the openings 63 to 68. Next, as shown in FIG. 11, solder bumps 73 to 78 are formed in the openings 63 to 68. Thereafter, as shown in FIG. 12, a plurality of semiconductor devices 1A can be cut out by performing a dicing process.

このように製造された半導体装置１Ａでは、半導体構成体１０、２０を重ねた状態でパッケージしているため、さらに小型化をすることができる。   In the semiconductor device 1A manufactured in this way, since the semiconductor structures 10 and 20 are packaged in a stacked state, the size can be further reduced.

＜第２実施形態＞
図１３は、本発明の第２の実施形態に係る半導体装置１Ｂの断面図である。なお、第１実施形態と同様の構成については、下２桁に同符号を付して説明を割愛する。
本実施形態においては、埋め込み配線４１、４２、４３、４４がない。絶縁膜１３０には、半導体構成体１１０の電極１１２Ａ〜１１２Ｄと対応する位置にそれぞれスルーホール１３１〜１３４が形成されている。ビアホール１１３Ａ〜１１３Ｄ及びスルーホール１３１〜１３４にはコンタクト部１５１〜１５４を構成する導体が充填されている。コンタクト部１５１〜１５４により、電極１１２Ａと半田バンプ１７１、電極１１２Ｂと半田バンプ１７２、電極１１２Ｃと半田バンプ１７３、電極１１２Ｄと半田バンプ１７４、がそれぞれ導通している。 Second Embodiment
FIG. 13 is a cross-sectional view of a semiconductor device 1B according to the second embodiment of the present invention. In addition, about the structure similar to 1st Embodiment, the same sign is attached | subjected to the last 2 digits, and description is omitted.
In the present embodiment, there is no embedded wiring 41, 42, 43, 44. Through holes 131 to 134 are formed in the insulating film 130 at positions corresponding to the electrodes 112A to 112D of the semiconductor structure 110, respectively. The via holes 113A to 113D and the through holes 131 to 134 are filled with conductors constituting the contact portions 151 to 154. By the contact portions 151 to 154, the electrode 112A and the solder bump 171, the electrode 112B and the solder bump 172, the electrode 112C and the solder bump 173, and the electrode 112D and the solder bump 174 are electrically connected.

絶縁層１３０の表面に接続パッド１４５、１４６が設けられている。接続パッド１４５はボンディングワイヤー１２４により電極１２２Ａと、接続パッド１４６はボンディングワイヤー１２５により電極１２２Ｂと、それぞれ接続されている。また、絶縁層１３０には接続パッド１４５、１４６と対応する位置にスルーホール１３５、１３６が形成されている。スルーホール１３５、１３６内にはコンタクト部１５５、１５６を構成する導体が充填されている。コンタクト部１５５、１５６により、接続パッド１４５と半田バンプ１７５、接続パッド１４６と半田バンプ１７６、がそれぞれ導通している。   Connection pads 145 and 146 are provided on the surface of the insulating layer 130. The connection pad 145 is connected to the electrode 122A by the bonding wire 124, and the connection pad 146 is connected to the electrode 122B by the bonding wire 125. In addition, through holes 135 and 136 are formed in the insulating layer 130 at positions corresponding to the connection pads 145 and 146. The through holes 135 and 136 are filled with conductors constituting the contact portions 155 and 156. By the contact portions 155 and 156, the connection pad 145 and the solder bump 175, and the connection pad 146 and the solder bump 176 are electrically connected, respectively.

次に、半導体装置１Ｂの製造方法について説明する。まず、図１４に示すように、金属からなる基材１９０上に、絶縁膜１３０、接続パッド１４５、１４６を順に積層し、一体化する。   Next, a method for manufacturing the semiconductor device 1B will be described. First, as shown in FIG. 14, an insulating film 130 and connection pads 145 and 146 are sequentially stacked and integrated on a base material 190 made of metal.

次に、図１４に示すように、絶縁膜１３０の上面に接着樹脂層１１３を塗布し、その上に電極１１２Ａ〜１１２Ｄが形成された面を下にして半導体構成体１１０をボンディングする。   Next, as shown in FIG. 14, the adhesive resin layer 113 is applied to the upper surface of the insulating film 130, and the semiconductor structure 110 is bonded with the surface on which the electrodes 112A to 112D are formed facing down.

次に、図１５に示すように、半導体チップ１１１の上面に接着樹脂層１２３を塗布し、その上に電極１２２Ａ、１２２Ｂを上側に向けた状態で半導体構成体１２０をボンディングする。次に、ボンディングワイヤー１２４、１２５により電極１２２Ａ、１２２Ｂと接続パッド１４５、１４６とを接続する。   Next, as shown in FIG. 15, the adhesive resin layer 123 is applied to the upper surface of the semiconductor chip 111, and the semiconductor structure 120 is bonded with the electrodes 122A and 122B facing upward. Next, the electrodes 122A and 122B and the connection pads 145 and 146 are connected by the bonding wires 124 and 125, respectively.

次に、図１６に示すように、フィラーを含有した熱硬化性樹脂により封止層１２６を形成し、基材１９０をエッチングによって除去する。次に、絶縁膜１３０にレーザー光を照射し、ビアホール１１３Ａ〜１１３Ｄ、スルーホール１３１〜１３６を形成し、デスミア処理する。   Next, as shown in FIG. 16, the sealing layer 126 is formed with a thermosetting resin containing a filler, and the substrate 190 is removed by etching. Next, the insulating film 130 is irradiated with laser light to form via holes 113A to 113D and through holes 131 to 136, and desmear treatment is performed.

以後、第１実施形態と同様に、コンタクト部１５１〜１５６を形成し、ソルダーレジスト１６０をパターニングし、コンタクト部１５１〜１５６の端子処理後、半田バンプ１７１〜１７６を形成し、ダイシング処理する。以上により図１３に示す半導体装置１Ｂが完成する。   Thereafter, as in the first embodiment, the contact portions 151 to 156 are formed, the solder resist 160 is patterned, the solder bumps 171 to 176 are formed after the terminal processing of the contact portions 151 to 156, and the dicing process is performed. Thus, the semiconductor device 1B shown in FIG. 13 is completed.

本実施形態においても、半導体構成体１１０、１２０を重ねた状態でパッケージしているため、より小型の半導体装置１Ｂを得ることができる。   Also in this embodiment, since the semiconductor structures 110 and 120 are packaged in a stacked state, a smaller semiconductor device 1B can be obtained.

＜第３実施形態＞
図１７は本発明の第３実施形態に係る半導体装置１Ｃを示す断面図である。なお、第２実施形態と同様の構成については同符号を付して説明を割愛する。
本実施形態に係る半導体装置１Ｃでは、第１の絶縁層１３０Ａ、コンタクト部１５１Ａ〜１５６Ａに加えて、さらに第２の絶縁層１３０Ｂ、コンタクト部１５１Ｂ〜１５６Ｂが形成されている。また、第２の絶縁層１３０Ｂの下面にソルダーレジスト１６０がパターニングされ、コンタクト部１５１Ｂ〜１５６Ｂに端子処理後、半田バンプ１７１〜１７６が形成されている。 <Third Embodiment>
FIG. 17 is a sectional view showing a semiconductor device 1C according to the third embodiment of the present invention. In addition, about the structure similar to 2nd Embodiment, the same code | symbol is attached | subjected and description is omitted.
In the semiconductor device 1C according to the present embodiment, in addition to the first insulating layer 130A and the contact portions 151A to 156A, a second insulating layer 130B and contact portions 151B to 156B are further formed. Also, a solder resist 160 is patterned on the lower surface of the second insulating layer 130B, and solder bumps 171 to 176 are formed on the contact portions 151B to 156B after terminal processing.

半導体装置１Ｃの製造方法について説明する。まず、第２実施形態と同様に、コンタクト部１５１Ａ〜１５６Ａを形成するまでのプロセスを行う。次に、第２の絶縁膜１３０Ｂを形成し、パターニングする。次に、金属メッキ膜を形成し、パターニングすることでコンタクト部１５１Ｂ〜１５６Ｂを形成する。以後、ソルダーレジスト１６０をパターニングし、コンタクト部１５１Ｂ〜１５６Ｂの端子処理後、半田バンプ１７１〜１７６を形成し、ダイシング処理する。以上により図１７に示す半導体装置１Ｃが完成する。   A method for manufacturing the semiconductor device 1C will be described. First, similarly to the second embodiment, a process until the contact portions 151A to 156A are formed is performed. Next, a second insulating film 130B is formed and patterned. Next, a metal plating film is formed and patterned to form contact portions 151B to 156B. Thereafter, the solder resist 160 is patterned, and after the terminal processing of the contact portions 151B to 156B, solder bumps 171 to 176 are formed and dicing is performed. Thus, the semiconductor device 1C shown in FIG. 17 is completed.

このように、本実施形態によれば、ビルドアップ法により配線を多層化することができ、半導体装置１Ｃの表面における配線の自由度を向上させることができる。   Thus, according to the present embodiment, the wiring can be multilayered by the build-up method, and the degree of freedom of the wiring on the surface of the semiconductor device 1C can be improved.

＜第４実施形態＞
図１８は本発明の第４実施形態に係る半導体装置１Ｄを示す断面図である。なお、第２実施形態と同様の構成については同符号を付して説明を割愛する。
本実施形態に係る半導体装置１Ｄでは、半導体チップ１１１の上面に接着樹脂層１２３Ａが塗布され、その上に電極１２２Ａ、１２２Ｂを上側に向けた状態で半導体構成体１２０Ａがボンディングされている。さらに、半導体構成体１２０Ａの半導体チップ１２１Ａの上部に接着樹脂層１２３Ｂが塗布され、その上に電極１２２Ｃ、１２２Ｄを上側に向けた状態で半導体構成体１２０Ｂの半導体チップ１２１Ｂがボンディングされている。なお、半導体構成体１２０Ａの電極１２２Ａ、１２２Ｂは、隣接する半導体構成体１２０Ｂと重ならないように配置されているので、ボンディングワイヤー１２４、１２５により容易に接続パッド１４５、１４６と接続することができる。 <Fourth embodiment>
FIG. 18 is a sectional view showing a semiconductor device 1D according to the fourth embodiment of the present invention. In addition, about the structure similar to 2nd Embodiment, the same code | symbol is attached | subjected and description is omitted.
In the semiconductor device 1D according to the present embodiment, the adhesive resin layer 123A is applied to the upper surface of the semiconductor chip 111, and the semiconductor structure 120A is bonded on the electrodes 122A and 122B facing upward. Further, an adhesive resin layer 123B is applied to the upper part of the semiconductor chip 121A of the semiconductor structure 120A, and the semiconductor chip 121B of the semiconductor structure 120B is bonded on the electrode 122C and 122D facing upward. Since the electrodes 122A and 122B of the semiconductor structure 120A are arranged so as not to overlap with the adjacent semiconductor structure 120B, they can be easily connected to the connection pads 145 and 146 by the bonding wires 124 and 125.

電極１２２Ｃ、１２２Ｄは絶縁膜１３０に設けられた接続パッド１４７、１４８とボンディングワイヤー１２６、１２７により接続されている。接続パッド１４７、１４８はそれぞれコンタクト部１５７、１５８により、半田バンプ１７７、１７８と導通している。半導体装置１Ｄの製造プロセスは第２実施形態に係る半導体装置１Ｂと同様である。   The electrodes 122C and 122D are connected to connection pads 147 and 148 provided on the insulating film 130 by bonding wires 126 and 127, respectively. The connection pads 147 and 148 are electrically connected to the solder bumps 177 and 178 through contact portions 157 and 158, respectively. The manufacturing process of the semiconductor device 1D is the same as that of the semiconductor device 1B according to the second embodiment.

本実施形態においては、半導体構成体１１０、１２０Ａ、１２０Ｂを重ねた状態でパッケージしているため、さらに集積した半導体装置１Ｄを得ることができる。   In the present embodiment, since the semiconductor structures 110, 120A, 120B are packaged in an overlapping state, a further integrated semiconductor device 1D can be obtained.

上記の第１〜第４実施形態において、封止される前の半導体構成体は、図１９（ａ）〜（ｄ）のいずれかの形状としてもよい。
すなわち、図１９（ａ）に示すように、半導体チップ１１の下面に形成された複数の電極１２Ａ、１２Ｂを、絶縁コート１４により覆ってもよい。
また、図１９（ｂ）に示すように、複数の電極１２Ａ、１２Ｂに、ギャップや厚さの調整をするために、金属パッド１５Ａ、１５Ｂを設けてもよい。さらに、図１９（ｃ）に示すように、電極１２Ａ、１２Ｂ及び金属パッド１５Ａ、１５Ｂを絶縁コート１４により覆ってもよい。 In said 1st-4th embodiment, the semiconductor structure before sealing is good also as the shape in any one of Fig.19 (a)-(d).
That is, as shown in FIG. 19A, the plurality of electrodes 12 </ b> A and 12 </ b> B formed on the lower surface of the semiconductor chip 11 may be covered with the insulating coat 14.
Further, as shown in FIG. 19B, metal pads 15A and 15B may be provided in the plurality of electrodes 12A and 12B in order to adjust the gap and thickness. Further, as shown in FIG. 19C, the electrodes 12A and 12B and the metal pads 15A and 15B may be covered with an insulating coat 14.

あるいは、図１９（ｄ）に示すように、ウエハＷ上に半導体素子や集積回路、金属パッド１５Ａ、１５Ｂを形成した後、絶縁膜１６によるパッケージング工程等の後工程を行ったウエハレベルＣＳＰを用いてもよい。   Alternatively, as shown in FIG. 19D, after forming semiconductor elements, integrated circuits, and metal pads 15A and 15B on the wafer W, a wafer level CSP obtained by performing a post-process such as a packaging process using the insulating film 16 is formed. It may be used.

１Ａ、１Ｂ、１Ｃ、１Ｄ 半導体装置
１０、２０、１１０、１２０、１２０Ａ、１２０Ｂ 半導体構成体
１１、２１、１１１、１２１ 半導体チップ
１２Ａ〜１２Ｄ、２２Ａ、２２Ｂ、１２２Ａ〜１２２Ｄ 電極
１３、２３、１１３、１２３、１２３Ａ、１２３Ｂ 接着樹脂層
１３Ａ〜１３Ｄ、３３〜３８ ビアホール
２４、２５ ボンディングワイヤー
２９ 封止層
３０、１３０、１３０Ａ、１３０Ｂ 絶縁層
３１、３２、１３１〜１３４ スルーホール
４１〜４４ 埋め込み配線
４１Ａ、４２Ｂ 貫通穴
５０ 金属メッキ膜
５１〜５８、１５１〜１５６、１５１Ａ〜１５６Ａ、１５１Ｂ〜１５６Ｂ コンタクト部
６０ ソルダーレジスト
６３〜６８ 開口部
７３〜７８、１７１〜１７８ 半田バンプ
９０ 基材
１４５〜１４８ 接続パッド
1A, 1B, 1C, 1D Semiconductor device 10, 20, 110, 120, 120A, 120B Semiconductor structure 11, 21, 111, 121 Semiconductor chips 12A-12D, 22A, 22B, 122A-122D Electrodes 13, 23, 113, 123, 123A, 123B Adhesive resin layers 13A-13D, 33-38 Via holes 24, 25 Bonding wires 29 Sealing layers 30, 130, 130A, 130B Insulating layers 31, 32, 131-134 Through holes 41-44 Embedded wiring 41A, 42B Through-hole 50 Metal plating films 51-58, 151-156, 151A-156A, 151B-156B Contact part 60 Solder resist 63-68 Opening 73-78, 171-178 Solder bump 90 Base material 145-148 Connection pad

Claims (3)

絶縁膜、第１配線及び第２配線が形成されたキャリアーの前記第１配線及び前記第２配線が形成された面に、電極を下に向けて最下部の半導体構成体を接着する第１工程と、
前記最下部の半導体構成体の上部に、電極を上に向けて他の１又は複数の半導体構成体を重ねて接着する第２工程と、
前記第２配線と前記他の１又は複数の半導体構成体の電極とをボンディングワイヤーにより接続する第３工程と、
前記最下部の半導体構成体、前記他の１又は複数の半導体構成体、前記第２配線及び前記ボンディングワイヤーを封止する封止層を前記絶縁膜の上部に形成する第４工程と、
前記絶縁膜、前記第１配線及び前記第２配線を残して前記キャリアーを除去する第５工程と、
前記絶縁膜の下側から前記第１配線及び前記第２配線に向けてレーザーを照射することによって前記第１配線及び前記第２配線まで到達する穴を形成する第６工程と、
前記絶縁膜の下面及び前記穴の内部にそれぞれ第１金属層及び第２金属層を形成し、前記第１金属層を介して前記最下部の半導体構成体の前記電極と前記第１配線とを相互に接続するとともに、前記第２配線と前記第２金属層とを接続する第７工程と、
を含むことを特徴とする半導体装置の製造方法。 Insulating film, the first wiring and the second wiring is formed the surface of the carrier that the first wiring and the second wiring are formed, a first step of adhering the bottom of the semiconductor structure toward the electrode down When,
A second step of stacking and adhering another one or more semiconductor structures on top of the lowermost semiconductor structure with the electrode facing upward;
A third step of connecting the second wiring and the electrodes of the one or more other semiconductor components by a bonding wire;
A fourth step of forming a sealing layer for sealing the lowermost semiconductor structure, the one or more other semiconductor structures, the second wiring, and the bonding wire on the insulating film;
A fifth step of removing the carrier leaving the insulating film, the first wiring and the second wiring;
A sixth step of forming a hole reaching the first wiring and the second wiring by irradiating a laser from the lower side of the insulating film toward the first wiring and the second wiring;
A first metal layer and a second metal layer are formed on the lower surface of the insulating film and inside the hole, respectively, and the electrode and the first wiring of the lowermost semiconductor structure are connected via the first metal layer. A seventh step of connecting the second wiring and the second metal layer together with each other;
A method for manufacturing a semiconductor device, comprising: 前記最下部及び最上部の半導体構成体を除いた中間部の半導体構成体の電極は、当該中間部の半導体構成体上の半導体構成体と重ならないように配置されていることを特徴とする請求項１に記載の半導体装置の製造方法。The electrodes of the intermediate semiconductor structure excluding the lowermost and uppermost semiconductor structures are arranged so as not to overlap with the semiconductor structure on the intermediate semiconductor structure. Item 14. A method for manufacturing a semiconductor device according to Item 1. 前記第１配線及び前記第２配線は、前記絶縁膜の前記半導体構成体が固定される面に埋め込まれていることを特徴とする請求項１または２に記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 1, wherein the first wiring and the second wiring are embedded in a surface of the insulating film to which the semiconductor structure is fixed.
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