JP5563641B2 - Manufacturing method of substrate structure - Google Patents

Description

  The present invention relates to a method for manufacturing a substrate structure, and more particularly to a method for manufacturing a substrate structure having excellent structural reliability.

  In general, many circuit structures of multilayer circuit boards are manufactured using a laminated method or a build-up method, so that the circuit wiring density is high and the wiring interval is reduced. . In the lamination method, multilayer circuit layers are respectively formed on multilayer dielectric layers to form an inner layer circuit board and an outer layer circuit board, and the completed inner layer circuit board, outer layer circuit board, and glass fiber resin plastic film for bonding are aligned. Then, the multilayer circuit board is formed by performing the lamination once.

  When a multilayer circuit board is manufactured using a lamination method, it is generally used only for manufacturing an even layer circuit (for example, four layers, six layers, or six layers or more). Can be used to produce odd or even layers of circuits according to different circuit requirements. However, since the requirement for alignment accuracy is very high and the operation time is long, it is directly reflected in the cost and disadvantageous for mass production. When a circuit board is manufactured by adopting the single area layer method, the circuit board and the dielectric layer are asymmetric, so that the circuit board after lamination is easily bent, and thus the reliability is low. Therefore, one of the major issues to be overcome at present is to improve the structural reliability by solving the problem that the substrate after lamination is curved when the dielectric layer is a single area layer and by increasing the manufacturing time of the multilayer circuit board. is there.

  The present invention provides a method for manufacturing a substrate structure that can solve the problem that a substrate after lamination is curved when a known insulating layer is formed as a single area layer.

  The present invention provides a method for manufacturing a substrate structure including the following steps. A substrate is provided. The substrate has a core layer and a first patterned copper foil layer and a second patterned copper foil layer on the first surface and the second surface of the core layer facing each other. A first conductive layer and a first conductive layer overlying the first insulating layer are thermally laminated on the first patterned copper foil layer. The first insulating layer has a central block and a peripheral block surrounding the central block. The central block and the surrounding block of the first insulating layer are both semi-solidified. A heating and pressurizing step is performed on the surrounding block of the first insulating layer, and the surrounding block of the first insulating layer is completely solidified. The second insulating layer and the second conductive layer overlying the second insulating layer are thermally laminated on the second patterned copper foil layer, and all the central blocks of the second insulating layer and the semi-solidified first insulating layer are all A completely solidified state is obtained in the same manner as the surrounding block of the first insulating layer.

  In the embodiment of the present invention, the temperature at which the first insulating layer and the first conductive layer described above are thermally laminated is between 80 ° C. and 160 ° C., and the time is between 1 minute and 30 minutes.

  In the embodiment of the present invention, the temperature for thermally laminating the second insulating layer and the second conductive layer described above is between 120 ° C. and 250 ° C., and the time is 30 minutes to 240 minutes.

  In the embodiment of the present invention, the temperature at which the heating and pressing step is performed on the peripheral block of the first insulating layer described above is between 150 ° C. and 300 ° C., and the time is 0.5 minutes to 20 minutes. is there.

  In the embodiment of the present invention, the above-described method for manufacturing the substrate structure further includes thermally laminating the second insulating layer and the second conductive layer, and then the first conductive layer, the first insulating layer, and the first patterned copper foil layer. Forming a conductive through hole penetrating the core layer, the second patterned copper foil layer, the second insulating layer and the second conductive layer, and performing a patterning step on the first conductive layer and the second conductive layer Forming a first patterned conductive layer and a second patterned conductive layer, and a conductive through hole connecting the first patterned conductive layer and the second patterned conductive layer; and a first solder resist layer and a second A solder resist layer is formed on the first patterned conductive layer and the second patterned conductive layer, respectively, and the first solder resist layer and the second solder resist layer are part of the first patterned conductive layer and part of the first patterned conductive layer, respectively. Second patterned conductive layer of Performing the surface treatment on the first patterned conductive layer and the second patterned conductive layer from which the first solder resist layer and the second solder resist layer are exposed, at least one first pad and at least one Forming a second pad.

  The present invention submits a method for manufacturing a substrate structure including the following manufacturing steps. A core layer and first and second copper foil layers on the first and second surfaces of the core layer facing each other are provided. A thermal lamination step is performed, and the core layer, the first copper foil layer, and the second copper foil layer are integrally bonded to form a base material. The core layer has a central block and a surrounding block surrounding the central block. The central block and the surrounding block of the core layer are both semi-solidified. A heating and pressurizing step is performed on the surrounding block of the core layer, and the surrounding block of the core layer is completely solidified. A patterned conductive layer is formed on the first copper foil layer. An insulating layer and a third copper foil layer overlying the insulating layer are formed on the patterned conductive layer, and the central block of the insulating layer and the semi-solid state core layer are all completely the same as the surrounding blocks of the core layer. Solidify.

  In the embodiment of the present invention, the temperature constituting the substrate by the above-described thermal lamination step is between 80 ° C. and 160 ° C., and the time is 1 minute to 30 minutes.

  In the embodiment of the present invention, the temperature for performing the heating and pressing step on the peripheral block of the core layer described above is between 150 ° C. and 300 ° C., and the time is 0.5 minutes to 20 minutes.

  In the embodiment of the present invention, the temperature at which the insulating layer and the third copper foil layer described above are thermally laminated is between 120 ° C. and 250 ° C., and the time is between 30 minutes and 240 minutes.

  In the embodiment of the present invention, in the method for manufacturing a substrate structure described above, after the insulating layer and the third copper foil layer are thermally laminated, the third copper foil layer is irradiated with laser light, and the third copper foil layer is used. Forming at least one blind hole extending into the patterned conductive layer; filling the blind hole with a conductive material to connect the third copper foil layer and the patterned conductive layer with the conductive material; A patterning step is performed on the copper foil layer to form a third patterned copper foil layer, a solder resist layer is formed on the third patterned copper foil layer, and the solder resist layer is partially Exposing the third patterned copper foil layer and subjecting the third patterned copper foil layer from which the solder resist layer is exposed to surface treatment to form at least one pad.

  In the embodiment of the present invention, the above-described surface treatment layer may be an electroless nickel-gold layer, an electroless nickel-palladium layer, an electroless palladium-gold layer, or an electroless nickel-palladium-gold layer with a solder resist layer exposed. Forming on the third patterned copper foil layer.

  As described above, according to the present invention, first, the peripheral block of the semi-solidified first insulating layer is completely solidified to increase the bonding force between the first insulating layer and the substrate, and then the second insulation. The central block of the second insulating layer and the semi-solidified first insulating layer is completely solidified in the same manner as the surrounding blocks of the first insulating layer by thermally laminating the layer and the second conductive layer thereover To. Therefore, even if a single-sided insulating layer and a conductive layer thereover are stacked on a base material, the base material is difficult to bend, and further, the reliability of a substrate structure to be completed later can be increased.

  In order to make the above and other objects, features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described below.

It is a section schematic diagram showing a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a section schematic diagram showing a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a section schematic diagram showing a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a section schematic diagram showing a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a section schematic diagram showing a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a section schematic diagram showing a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a section schematic diagram showing a part of step of a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a section schematic diagram showing a part of step of a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a section schematic diagram showing a part of step of a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a cross-sectional schematic diagram which shows the manufacturing method of the board | substrate structure which concerns on another embodiment of this invention. It is a cross-sectional schematic diagram which shows the manufacturing method of the board | substrate structure which concerns on another embodiment of this invention. It is a cross-sectional schematic diagram which shows the manufacturing method of the board | substrate structure which concerns on another embodiment of this invention. It is a cross-sectional schematic diagram which shows the manufacturing method of the board | substrate structure which concerns on another embodiment of this invention. It is a section schematic diagram showing a part of step of a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a section schematic diagram showing a part of step of a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a section schematic diagram showing a part of step of a manufacturing method of a substrate structure concerning an embodiment of the present invention. It is a section schematic diagram showing a part of step of a manufacturing method of a substrate structure concerning an embodiment of the present invention.

  1A to 1F are schematic cross-sectional views illustrating a method for manufacturing a substrate structure according to an embodiment of the present invention. In the substrate structure manufacturing method of the present embodiment, first, referring to FIG. 1A, a substrate 110 is provided. The substrate 110 includes a core layer 112, a first copper foil layer 114, and a second copper foil layer 116. In the present embodiment, the core layer 112 has a first surface 111 and a second surface 113 that face each other, and the first copper foil layer 114 and the second copper foil layer 116 are the first surface 111 and the second surface 113 of the core layer 112, respectively. Arranged on the second surface 113. Here, the material of the core layer 112 is, for example, a resin.

  Subsequently, referring to FIG. 1B, a patterning step is performed on the first copper foil layer 114 to form a first patterned copper foil layer 114 ′ on the first surface 111 of the core layer 112. Here, in the patterning step, first, a photoresist layer (not shown) is applied on the first copper foil layer 114, and then the photoresist layer is exposed and developed to form a patterned photoresist layer ( (Not shown) and the mask is etched with the patterned photoresist layer, and the first copper foil layer 114 outside the patterned photoresist layer is etched to form the first patterned copper foil layer 114 ′. Including doing.

  1C, the first insulating layer 120 and the first conductive layer 130 on the first insulating layer 120 are thermally stacked on the first patterned copper foil layer 114 '. Here, the first insulating layer 120 includes a central block C and a peripheral block P surrounding the central block C. The temperature at which the second insulating layer 120 and the first conductive layer 130 are thermally laminated is between 80 ° C. and 160 ° C., and the time is between 1 minute and 30 minutes. In particular, the central block C and the surrounding block P of the first insulating layer 120 at this time are both semi-solidified.

  Subsequently, referring to FIG. 1D, a heating and pressing step is performed on the surrounding block P of the first insulating layer 120 to bring the surrounding block P of the first insulating layer 120 into a completely solidified state. Here, the temperature at which the heating and pressing step is performed on the peripheral block P of the first insulating layer 120 is between 150 ° C. and 300 ° C., and the time is between 0.5 minutes and 20 minutes.

  Thereafter, referring to FIG. 1E, a patterning step is performed on the second copper foil layer 116 to form a second patterned copper foil layer 116 ′ on the second surface 113 of the core layer 112. Here, in the patterning step, first, a photoresist layer (not shown) is applied on the second copper foil layer 116, and then the photoresist layer is exposed and developed to form a patterned photoresist layer ( (Not shown), the mask is etched with the patterned photoresist layer, and the second copper foil layer 116 outside the patterned photoresist layer is etched to form the second patterned copper foil layer 116 ′. Including doing. At this time, the core layer 112, the first patterned copper foil layer 114 ', and the second patterned copper foil layer 116' constitute the substrate 110 '.

  Here, as should be explained, in the present embodiment, first, the base 110 having the first copper foil layer 114 and the second copper foil layer 116 is provided, and the first insulating layer 120 and the first insulating layer 120 thereon are provided. For the first time before and after laminating the conductive layer 130, the first patterned copper foil layer 114 ′ and the second patterned copper foil layer 116 ′ are formed by the patterning step method. First, a substrate 110 ′ having a first patterned copper foil layer 114 ′ and a second patterned copper foil layer 116 ′ is directly provided, and then the first insulating layer 120 and the first conductive layer 130 thereon are provided. Lamination and subsequent steps may be performed. That is, the form of the substrate 110 in FIG. 1A is merely described by way of example, and does not limit the present invention.

  Finally, referring to FIG. 1F, the second insulating layer 140 and the second conductive layer 150 overlying the second insulating layer 140 are thermally stacked on the second patterned conductive layer 116 ′ to form the second insulating layer. 140 and the central block C of the semi-solidified first insulating layer 120 are completely solidified in the same manner as the peripheral block P of the first insulating layer 120. That is, after the second insulating layer 140 and the second conductive layer 150 thereon are thermally laminated, the second insulating layer 140 and the central block C of the semi-solidified first insulating layer 120 are both in a completely solidified state. become. Here, the temperature at which the second insulating layer 140 and the second conductive layer 150 are thermally laminated is between 120 ° C. and 250 ° C., and the time is between 30 minutes and 240 minutes. Thus far, the manufacturing method of the substrate structure 100a is completed.

  In the present embodiment, first, the peripheral block P of the semi-solidified first insulating layer 120 is completely solidified to increase the bonding force between the first insulating layer 120 and the substrate 110 ′, and then the second insulation. The central block C of the second insulating layer and the semi-solidified first insulating layer 120 is all the same as the peripheral block P of the first insulating layer 120 by thermally laminating the layer 140 and the second conductive layer 150 thereon. So that it is completely solidified. Therefore, when the single-sided first insulating layer 120 and the first conductive layer 130 thereover are stacked on the base 110 ′, the central block C of the first insulating layer 120 is in a semi-solidified state. The material 110 ′ is not easily bent, and the reliability of the substrate structure 100 a to be completed later can be increased.

  2A to 2C are schematic cross-sectional views illustrating some steps of a method for manufacturing a substrate structure according to an embodiment of the present invention. Since this embodiment uses the constituent element codes and part of the contents of the above-described embodiment, the same or similar constituent elements are displayed using the same display codes, and the same technical contents are not described. . For the description of the omitted part, the above-described embodiment can be referred to, and therefore, the description is not repeated in this embodiment.

  Referring to FIG. 2C, the main difference between the substrate structure 100b of the present embodiment and the substrate structure 100a of the above-described embodiment is that the substrate structure 100b of the present embodiment further includes a conductive through hole 160 and a first pattern. A patterned conductive layer 132, a second patterned conductive layer 152, a first solder resist layer 170, a second solder resist layer 175, a first pad 180, and a second pad 185.

  In the manufacturing process, the substrate structure 100b of the present embodiment can employ substantially the same manufacturing method as the substrate structure 100a of the above-described embodiment, and further after the step of FIG. 1F, that is, the second insulating layer 140 and After thermally laminating the second conductive layer 150 thereon onto the second patterned copper foil layer 116 ′, referring to FIG. 2A, the first conductive layer 130, the first insulating layer 120, the first patterned copper. Conductive through-holes 160 penetrating the foil layer 114 ′, the core layer 112, the second patterned copper foil layer 116 ′, the second insulating layer 140, and the second conductive layer 150 are formed.

  Subsequently, referring to FIG. 2B, a patterning step is performed on the first conductive layer 130 and the second conductive layer 150 to form the first patterned conductive layer 132 and the second patterned conductive layer 152. The conductive through hole 160 connects the first patterned conductive layer 132 and the second patterned conductive layer 152, and the conductive through hole 160 includes the first patterned conductive layer 132, the first patterned copper foil layer 114 ′, The second patterned copper foil layer 116 ′ and the second patterned conductive layer 152 are electrically connected. Thereafter, referring to FIG. 2C, a first solder resist layer 170 and a second solder resist layer 175 are formed on the first patterned conductive layer 132 and the second patterned conductive layer 152, respectively. The first solder resist layer 170 and the second solder resist layer 175 expose a part of the first patterned conductive layer 132 and a part of the second patterned conductive layer 152, respectively. Finally, referring to FIG. 2C again, surface treatment is performed on the first patterned conductive layer 132 and the second patterned conductive layer 152 where the first solder resist layer 170 and the second solder resist layer 175 are exposed, and at least One first pad 180 and at least one second pad 185 are formed. Here, the surface treatment is performed, for example, on the first patterned conductive layer 132 and the second patterned conductive layer 152 on which the first solder resist layer 170 and the second solder resist layer 175 are exposed. Forming. Of course, in other embodiments not shown, an electroless nickel-palladium layer, an electroless palladium-gold layer, or an electroless nickel-palladium-gold layer is formed by the first solder resist layer 170 and the second solder resist layer 175. It may be formed on the exposed first patterned conductive layer 132 and second patterned conductive layer 152, and the present invention is not limited thereto. Thus far, the manufacture of the substrate structure 100b is completed.

  3A to 3D are schematic cross-sectional views illustrating a method for manufacturing a substrate structure according to another embodiment of the present invention. First, referring to FIG. 3A, the substrate structure manufacturing method of the present embodiment will be described with reference to the core layer 212, the first copper foil layer 214 on the first surface 211 and the second surface 213 of the core layer 212 facing each other, and A second copper foil layer 216 is provided. Subsequently, referring to FIG. 3A again, a thermal lamination step is performed, and the core layer 212, the first copper foil layer 214, and the second copper foil layer 216 are integrally bonded to form the base material 210. The core layer 212 includes a central block C ′ and a surrounding block P ′ surrounding the central block C ′. At this time, both the central block C ′ and the surrounding block P ′ of the core layer 212 are in a semi-solidified state. Here, the temperature which performs the heat | fever lamination step and comprises the base material 210 is between 80 degreeC-160 degreeC, and time is between 1 minute-30 minutes.

  Subsequently, referring to FIG. 3B, a heating / pressing step is performed on the peripheral block P ′ of the core layer 212 to completely solidify the peripheral block P ′ of the core layer 212. Here, the temperature for performing the heating and pressing step on the peripheral block P ′ of the core layer 212 is between 150 ° C. and 300 ° C., and the time is between 0.5 minutes and 20 minutes.

  Thereafter, referring to FIG. 3C, a patterned conductive layer 220 is formed on the first copper foil layer 214.

  Finally, referring to FIG. 3D, the insulating layer 230 and the third copper foil layer 240 overlying the insulating layer 230 are thermally laminated on the patterned conductive layer 220 to form the insulating layer 230 and the semi-solidified core layer. The central block C ′ of 212 is completely solidified in the same manner as the peripheral block P ′ of the core layer 212. That is, after thermally insulating the insulating layer 230 and the third copper foil layer 240 thereon, the insulating layer 230 and the central block C ′ of the semi-solidified third copper foil layer 240 are all in a completely solidified state. . Here, the temperature at which the insulating layer 230 and the third copper foil layer 240 are thermally laminated is between 120 ° C. and 250 ° C., and the time is between 30 minutes and 240 minutes. Thus far, the manufacture of the substrate structure 200a is completed.

  In this embodiment, first, the peripheral block P ′ of the semi-solidified core layer 212 is completely solidified, and the bonding force between the core layer 212 and the first copper foil layer 214 and the second copper foil layer 216 is increased. After that, by thermally laminating the insulating layer 230 and the third copper foil layer 240 thereover, the central block C ′ of the insulating layer 230 and the semi-solidified core layer 212 is entirely removed from the peripheral block P ′ of the core layer 212. Just as in the case of complete solidification. Therefore, when the single-sided insulating layer 230 and the third copper foil layer 240 thereon are laminated on the base material 210, the central block C ′ of the core layer 212 is in a semi-solidified state. It is difficult to bend, and the reliability of the substrate structure 200a to be completed later can be increased.

  4A to 4D are schematic cross-sectional views illustrating some steps of the method for manufacturing a substrate structure according to the embodiment of the present invention. Since this embodiment uses the constituent element codes and part of the contents of the above-described embodiment, the same or similar constituent elements are displayed using the same display codes, and the same technical contents are not described. . For the description of the omitted part, the above-described embodiment can be referred to, and therefore, the description is not repeated in this embodiment.

  Referring to FIG. 4C, the main difference between the substrate structure 200b of this embodiment and the substrate structure 200a of the above-described embodiment is that the substrate structure 200b of this embodiment further includes a blind hole B and a blind hole B. A filling material 250 filled therein, a third patterned copper foil layer 242, a solder resist layer 260, an electroless nickel-gold layer 270, and a pad 280.

  In the manufacturing process, the substrate structure 200b of the present embodiment can adopt substantially the same manufacturing method as the substrate structure 200a of the above-described embodiment, and further, after the step of FIG. 3D, that is, the insulating layer 230 and above it. After the third copper foil layer 240 is thermally laminated on the patterned conductive layer 220, referring to FIG. 4A, the third copper foil layer 240 is irradiated with a laser beam to form a pattern from the third copper foil layer 240. At least one blind hole B extending in the conductive layer 220 is formed (two are schematically shown in FIG. 4A). Subsequently, referring to FIG. 4B, the conductive material 250 is filled into the blind hole B, and the third copper foil layer 240 and the patterned conductive layer 220 are connected by the conductive material 250. Thereafter, referring to FIG. 4C, a patterning step is performed on the third copper foil layer 240 to form a third patterned copper foil layer 242. The third patterned copper foil layer 242 is electrically connected to the patterned conductive layer 220 through the conductive material 250 in the blind hole B. Finally, referring to FIG. 4D, a solder resist layer 260 is formed on the third patterned copper foil layer 242. The solder resist layer 260 exposes part of the third patterned copper foil layer 242. Subsequently, after the solder resist layer 260 is exposed, the third patterned copper foil layer 242 is subjected to a surface treatment to form at least one pad 280 (two are schematically shown in FIG. 4A). Here, the surface treatment includes, for example, forming the electroless nickel-gold layer 270 on the third patterned copper foil layer 242 from which the solder resist layer 260 is exposed. Of course, in another embodiment not shown, a third patterned copper foil layer in which the electroless nickel-palladium layer, electroless palladium-gold layer, or electroless nickel-palladium-gold layer is exposed with the solder resist layer 260 exposed. However, the present invention is not limited to these. Thus far, the manufacture of the substrate structure 200b is completed.

  As described above, according to the present invention, first, the peripheral block of the semi-solidified first insulating layer is completely solidified to increase the bonding force between the first insulating layer and the substrate, and then the second insulation. The central block of the second insulating layer and the semi-solidified first insulating layer is completely solidified in the same manner as the surrounding blocks of the first insulating layer by thermally laminating the layer and the second conductive layer thereover To. Therefore, even if a single-sided insulating layer and a conductive layer thereover are stacked on a base material, the base material is difficult to bend, and further, the reliability of a substrate structure to be completed later can be increased.

  As described above, the present invention has been disclosed by the embodiments. However, the present invention is not intended to limit the present invention, and is within the scope of the technical idea of the present invention so that those skilled in the art can easily understand. Therefore, the scope of patent protection should be defined based on the scope of claims and the equivalent area.

  The present invention provides a method for manufacturing a substrate structure that has an excellent structural reliability and is difficult to bend even when a single insulating layer is laminated on the substrate.

100a, 100b, 200a, 200b Substrate structure 110, 110 ′, 210 Base material 111, 211 First surface 112, 212 Core layer 113, 213 Second surface 114, 214 First copper foil layer 114 ′ First patterned copper foil Layer 116, 216 Second copper foil layer 116 ′ Second patterned copper foil layer 120 First insulating layer 130 First conductive layer 132, 220 First patterned conductive layer 140 Second insulating layer 150 Second conductive layer 152 Second Patterned conductive layer 160 First conductive through hole 170 First solder resist layer 175 Second solder resist layer 180 First pad 185 Second pad 190, 270 Electroless nickel-gold layer 230 Insulating layer 240 Third copper foil layer 242 First Three patterned copper foil layers 250 Filling material 260 Solder resist layer 280 Pad C, C ′ Central block P P 'around the block

Claims (11)

Providing a substrate having a core layer and a first patterned copper foil layer and a second patterned copper foil layer on the first and second surfaces of the core layer facing each other;
A first insulating layer and a first conductive layer overlying the first insulating layer are thermally laminated on the first patterned copper foil layer, the first insulating layer surrounding a central block and the central block Each of the central block and the surrounding block of the first insulating layer is in a semi-solidified state,
Performing a heating and pressing step on the surrounding block of the first insulating layer to bring the surrounding block of the first insulating layer into a completely solidified state;
A second conductive layer and a second conductive layer overlying the second insulating layer are thermally laminated on a second patterned copper foil layer, and the second insulating layer and the semi-solidified first insulating layer are Making all the central blocks completely solidified like the surrounding blocks of the first insulating layer;
A method of manufacturing a substrate structure including:   2. The method of manufacturing a substrate structure according to claim 1, wherein a temperature at which the first insulating layer and the first conductive layer are thermally laminated is between 80 ° C. and 160 ° C., and the time is between 1 minute and 30 minutes.   2. The method for manufacturing a substrate structure according to claim 1, wherein the temperature at which the second insulating layer and the second conductive layer are thermally laminated is between 120 ° C. and 250 ° C., and the time is between 30 minutes and 240 minutes.   The temperature at which the heating and pressing step is performed on the surrounding block of the first insulating layer is between 150 ° C. and 300 ° C., and the time is between 0.5 minutes and 20 minutes. A method for manufacturing a substrate structure. After thermally laminating the second insulating layer and the second conductive layer, the first conductive layer, the first insulating layer, the first patterned copper foil layer, the core layer, and the second patterned copper foil layer Forming a conductive through hole penetrating the second insulating layer and the second conductive layer;
A patterning step is performed on the first conductive layer and the second conductive layer to form a first patterned conductive layer and a second patterned conductive layer, and the conductive through hole is formed in the first patterned conductive layer. And connecting the second patterned conductive layer;
A first solder resist layer and a second solder resist layer are respectively formed on the first patterned conductive layer and the second patterned conductive layer, and the first solder resist layer and the second solder resist layer are respectively Exposing a portion of the first patterned conductive layer and a portion of the second patterned conductive layer;
A surface treatment is performed on the first patterned conductive layer and the second patterned conductive layer from which the first solder resist layer and the second solder resist layer are exposed, and at least one first pad and at least one first The method for manufacturing a substrate structure according to claim 1, further comprising: forming two pads. Providing a core layer and first and second copper foil layers on the first and second surfaces of the core layer facing each other;
A thermal lamination step is performed to integrally bond the core layer, the first copper foil layer, and the second copper foil layer to form a base material, and the core layer surrounds the central block and the central block The central block of the core layer and the peripheral block are both in a semi-solid state, and a heating and pressing step is performed on the peripheral block of the core layer, and the peripheral layer of the core layer is Making the block completely solidified,
Forming a patterned conductive layer on the first copper foil layer;
An insulating layer and a third copper foil layer overlying the insulating layer are formed on the patterned conductive layer, and the central block of the insulating layer and the semi-solidified core layer are all surrounded by the periphery of the core layer; A method for producing a substrate structure, comprising: making a solidified state in the same way as a block.   The method for manufacturing a substrate structure according to claim 6, wherein a temperature constituting the base material by the thermal lamination step is between 80 ° C and 160 ° C, and a time is between 1 minute and 30 minutes.   The substrate structure according to claim 6, wherein a temperature at which the heating and pressing step is performed on the peripheral block of the core layer is between 150 ° C. and 300 ° C., and a time is 0.5 minutes to 20 minutes. Manufacturing method.   The method for manufacturing a substrate structure according to claim 6, wherein a temperature at which the insulating layer and the third copper foil layer are thermally laminated is between 120C and 250C, and the time is between 30 minutes and 240 minutes. After thermally laminating the insulating layer and the third copper foil layer, the third copper foil layer is irradiated with laser light, and at least one blind hole extending from the third copper foil layer to the patterned conductive layer is formed. Forming,
Filling the blind hole with a conductive material, and connecting the third copper foil layer and the patterned conductive layer with the conductive material;
Performing a patterning step on the third copper foil layer to form a third patterned copper foil layer;
Forming a solder resist layer on the third patterned copper foil layer, the solder resist layer exposing a part of the third patterned copper foil layer;
The method for manufacturing a substrate structure according to claim 6, further comprising: performing a surface treatment on the third patterned copper foil layer from which the solder resist layer is exposed to form at least one pad. The third patterned copper in which the surface treatment layer is an electroless nickel-gold layer, an electroless nickel-palladium layer, an electroless palladium-gold layer, or an electroless nickel-palladium-gold layer with the solder resist layer exposed. The method of manufacturing a substrate structure according to claim 10, comprising forming on a foil layer.

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