JP5562603B2 - Display device - Google Patents

Description

The present invention relates to a display device having an inverted staggered thin film transistor in a driver circuit and a pixel portion.

As a kind of field effect transistor, a thin film transistor in which a channel formation region is formed using a semiconductor layer formed over a substrate having an insulating surface is known. A technique using amorphous silicon, microcrystalline silicon, or polycrystalline silicon as a semiconductor layer used in a thin film transistor is disclosed. A typical application example of a thin film transistor is a liquid crystal television device, which is put into practical use as a switching transistor of each pixel constituting a display screen.

In order to reduce the cost of the display device, there is a display device in which the number of external components is reduced and the gate driver is formed of a thin film transistor using amorphous silicon or microcrystalline silicon (see Patent Document 1).

JP 2005-049832 A

A thin film transistor in which a channel formation region is formed using an amorphous silicon layer has a problem of low field-effect mobility and on-state current. Further, there is a problem that the thin film transistor deteriorates due to long-term use, the threshold voltage shifts, and the on-current decreases. When a driving circuit such as a gate driver is formed using a thin film transistor in which a channel formation region is formed using an amorphous silicon layer, the threshold voltage is increased by increasing the width of the channel formation region and the area of the thin film transistor. Even if the on-current is reduced due to the shift, a sufficient on-current is secured.

Alternatively, the number of thin film transistors included in the driver circuit is increased to shorten the operation time of each thin film transistor, so that deterioration of the thin film transistor is reduced and sufficient on-state current is ensured.

For this reason, in a display device in which a driver circuit is formed using a thin film transistor in which a channel formation region is formed using an amorphous silicon layer, the area occupied by the driver circuit is large, which hinders the narrowing of the display device, and the pixel serving as the display region The area of a part will become small.

On the other hand, a thin film transistor in which a channel formation region is formed using a microcrystalline silicon layer has improved field-effect mobility but higher off-state current than an amorphous silicon thin film transistor, and thus has sufficient switching characteristics. There is a problem that it is not possible.

A thin film transistor in which a polycrystalline silicon layer serves as a channel formation region has characteristics that field effect mobility is significantly higher than that of the two types of thin film transistors, and a high on-state current can be obtained. Due to the above-described characteristics, this thin film transistor can constitute not only a switching transistor provided in a pixel but also a driver circuit that requires high-speed operation.

However, a thin film transistor in which a channel formation region is formed of a polycrystalline silicon layer requires a semiconductor layer crystallization step as compared with a case where a thin film transistor is formed of an amorphous silicon layer, which increases the manufacturing cost. ing. For example, a laser annealing technique necessary for manufacturing a polycrystalline silicon layer has a problem that a large area liquid crystal panel cannot be efficiently produced with a small laser beam irradiation area.

In view of the above, an object of one embodiment of the present invention is to provide a display device that can reduce manufacturing costs and has excellent image display characteristics. Another object of one embodiment of the present invention is to provide a display device that can reduce manufacturing cost and can have a narrow frame.

The present invention includes a driver circuit portion and a pixel portion, the driver circuit portion is a display device having a logic circuit portion and a switch portion or a buffer portion, and the inverted staggered TFT constituting the driver circuit portion and the pixel portion is Inverted staggered TFTs with the same polarity, the switch part or the buffer part is composed of inverted staggered TFTs that can flow a large amount of on-current, and the logic circuit part is a depletion type TFT and an enhancement type TFT. And an inverter circuit (hereinafter referred to as an EDMOS circuit).

As a TFT capable of flowing a large amount of on-state current, a dual gate type inverted staggered TFT or a depletion type inverted staggered TFT is used.

The EDMOS circuit has two or more inverted staggered TFTs having different threshold voltages, typically a depletion type TFT and an enhancement type TFT. A depletion type TFT includes a first gate electrode, a first gate insulating layer, a semiconductor layer formed on the first gate insulating layer, and a second gate insulating layer formed on the semiconductor layer. The threshold voltage is controlled and an EDMOS circuit can be formed by forming a dual gate type inverted staggered TFT in which the second gate electrode is formed on the second gate insulating layer.

Alternatively, as a depletion type TFT, an inverted staggered TFT having a semiconductor layer to which an impurity element serving as a donor is added to a channel formation region is used, and as an enhancement type TFT, an impurity element serving as a donor is not added to the channel formation region. By using a semiconductor layer, an EDMOS circuit can be configured.

Alternatively, as a depletion type TFT, an inverted staggered TFT having a semiconductor layer to which no acceptor impurity element is added is used in the channel formation region, and as an enhancement type TFT, an acceptor impurity element is added to the channel formation region. By using a semiconductor layer, an EDMOS circuit can be configured.

The inverted staggered TFT manufactured in the display device of the present invention includes a gate electrode, a gate insulating layer formed over the gate electrode, a semiconductor layer formed over the gate insulating layer, and a semiconductor layer. The semiconductor layer formed over the gate insulating layer includes an impurity semiconductor layer functioning as a source region and a drain region, and a wiring. The semiconductor layer is formed over the first microcrystalline semiconductor layer and the first microcrystalline semiconductor layer. A second microcrystalline semiconductor layer having a plurality of conical projections formed on the substrate, and a pair of amorphous semiconductor layers formed over the second microcrystalline semiconductor layer. Further, the second microcrystalline semiconductor layer is in contact with the insulating layer between the pair of amorphous semiconductor layers. For this reason, the off current can be suppressed while increasing the on current of the inverted staggered TFT.

Note that the on-state current refers to a current that flows between a source electrode and a drain electrode when a transistor is on. For example, in the case of an n-type transistor, the current flows between the source electrode and the drain electrode when the gate voltage is higher than the threshold voltage of the transistor.

An off-state current is a current that flows between a source electrode and a drain electrode when a transistor is off. For example, in the case of an n-type transistor, the current flows between the source electrode and the drain electrode when the gate voltage is lower than the threshold voltage of the transistor.

Note that a display device in this specification means an image display device, a light-emitting device, or a light source (including a lighting device). Also, a connector, for example, a module with a FPC (Flexible printed circuit) or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package), a module with a printed wiring board at the end of a TAB tape or TCP, or a display It is assumed that the display device includes all modules in which an IC (integrated circuit) is directly mounted on the element by a COG (Chip On Glass) method.

According to the present invention, image display characteristics can be improved while reducing manufacturing cost of a display device. Further, the frame of the display device can be narrowed, and the display area in the display device can be enlarged.

1 is a block diagram illustrating an entire display device according to an embodiment of the present invention. 4A and 4B each illustrate an arrangement of wirings, input terminals, and the like in a display device according to an embodiment of the present invention. FIG. 11 is a block diagram illustrating a structure of a shift register circuit. FIG. 11 illustrates an example of a flip-flop circuit. The figure which shows the layout figure (top view) of a flip-flop circuit. FIG. 6 is a timing chart for explaining the operation of a shift register circuit. FIG. 6 is a cross-sectional view illustrating a display device according to an embodiment of the present invention. 4A and 4B are a cross-sectional view and a top view illustrating a display device according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a thin film transistor in a display device according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a display device according to an embodiment of the present invention. 4A and 4B are a cross-sectional view and a top view illustrating a display device according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a driver circuit in a display device according to an embodiment of the present invention. 8A and 8B are a cross-sectional view and a top view illustrating a method for manufacturing a display device according to one embodiment of the present invention. 8A and 8B are a cross-sectional view and a top view illustrating a method for manufacturing a display device according to one embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. 4A and 4B illustrate a multi-tone mask which can be used in a method for manufacturing a display device according to one embodiment of the present invention. FIG. 6 is a plan view illustrating a method for manufacturing a display device according to one embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. FIG. 6 is an equivalent circuit diagram illustrating a protection circuit applied to the display device according to one embodiment of the present invention. 4A and 4B illustrate a terminal portion of a display device according to an embodiment of the present invention. 4A and 4B illustrate a terminal portion of a display device according to an embodiment of the present invention. 4A and 4B illustrate an example of a liquid crystal display device according to an embodiment of the present invention. 4A and 4B illustrate an example of a light-emitting display device according to an embodiment of the present invention. 8A and 8B each illustrate an example of an electronic device to which the present invention is applied according to an embodiment;

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments and examples. Note that in describing the structure of the present invention with reference to the drawings, the same portions are denoted by the same reference numerals in different drawings.

(Embodiment 1)
In this embodiment, a display device which is one embodiment of the present invention will be described with reference to a block diagram and the like.

FIG. 1A illustrates an example of a block diagram of an active matrix liquid crystal display device. A liquid crystal display device illustrated in FIG. 1A includes a pixel portion 101 having a plurality of pixels each provided with a display element over a substrate 100, a scan line driver circuit 102 that controls a scan line connected to the gate electrode of each pixel, and And a signal line driver circuit 103 for controlling input of a video signal to the selected pixel.

FIG. 1B illustrates an example of a block diagram of an active matrix light-emitting display device to which the present invention is applied. A light-emitting display device illustrated in FIG. 1B includes a first scan line driver that controls a pixel portion 111 including a plurality of pixels each including a display element over a substrate 110 and a scan line connected to a gate electrode of each pixel. A circuit 112 and a second scan line driver circuit 113; and a signal line driver circuit 114 which controls input of a video signal to a selected pixel. When two switching TFTs (Thin Film Transistors, hereinafter referred to as TFTs) and current control TFTs are arranged in one pixel, in the light emitting display device shown in FIG. 1B, the gate electrode of the switching TFT is used. A signal input to the connected first scan line is generated by the first scan line driver circuit 112, and a signal input to the second scan line connected to the gate electrode of the current control TFT is second. Are generated by the scanning line driving circuit 113. However, the signal input to the first scan line and the signal input to the second scan line may be generated by one scan line driver circuit. Further, for example, a plurality of first scanning lines used for controlling the operation of the switching element may be provided in each pixel depending on the number of TFTs included in the switching element. In this case, all signals input to the plurality of first scanning lines may be generated by one scanning line driving circuit, or a plurality of scanning line driving circuits may be provided and generated by each of them. .

Note that although the scan line driver circuit 102, the first scan line driver circuit 112, the second scan line driver circuit 113, and the signal line driver circuits 103 and 114 are formed in a display device here, scanning is performed. Part of the line driver circuit 102, the first scan line driver circuit 112, or the second scan line driver circuit 113 may be mounted using a semiconductor device such as an IC. Further, part of the signal line driver circuits 103 and 114 may be mounted using a semiconductor device such as an IC.

FIG. 2 is a diagram for explaining a positional relationship between a signal input terminal, a scanning line, a signal line, a protection circuit including a nonlinear element, and a pixel portion included in the display device. On the substrate 120 having an insulating surface, the scanning lines 123 and the signal lines 124 are arranged so as to intersect with each other, so that a pixel portion 127 is formed. Note that the pixel portion 127 corresponds to the pixel portion 101 and the pixel portion 111 illustrated in FIG.

The pixel portion 127 includes a plurality of pixels 128 arranged in a matrix. The pixel 128 includes a pixel TFT 129 connected to the scanning line 123 and the signal line 124, a storage capacitor portion 130, and a pixel electrode 131.

In the pixel configuration shown here, in the storage capacitor portion 130, one electrode and the pixel TFT 129 are connected, and the other electrode and the capacitor line 132 are connected. The pixel electrode 131 constitutes one electrode for driving a display element (a liquid crystal element, a light emitting element, a contrast medium (electronic ink), or the like). The other electrode of these display elements is connected to the common terminal 133.

The protection circuit is provided between the pixel portion 127 and the signal line input terminal 122. Further, it is disposed between the scan line driver circuit and the pixel portion 127. In this embodiment mode, a plurality of protection circuits are provided so that a surge voltage is applied to the scanning line 123, the signal line 124, and the capacitor wiring 137 due to static electricity or the like, and the pixel TFT 129 and the like are not destroyed. For this reason, the protection circuit is configured to release charges to the common wiring when a surge voltage is applied.

In this embodiment mode, an example in which a protection circuit 134 for the scanning line 123, a protection circuit 135 for the signal line 124, and a protection circuit 136 for the capacitor wiring 137 are provided. However, the position of the protection circuit is not limited to this. In the case where the scan line driver circuit is not mounted using a semiconductor device such as an IC, the protection circuit 134 is not necessarily provided on the scan line 123 side.

Using the TFT of the present invention in each of these circuits has the following advantages.

The pixel TFT preferably has high switching characteristics. By increasing the switching characteristics of the pixel TFT, the contrast ratio of the display device can be increased. In order to improve the switching characteristics, it is effective to increase the on current and reduce the off current. Since the pixel TFT to which the present invention is applied has a large on-state current and a small off-state current, the pixel TFT can have high switching characteristics and a thin film transistor with a high contrast ratio can be realized.

The drive circuit is roughly divided into a logic circuit part and a switch part or a buffer part. The TFT provided in the logic circuit portion may have a structure capable of controlling the threshold voltage. On the other hand, the TFT provided in the switch portion or the buffer portion preferably has a large on-current. With this configuration, the threshold voltage of the TFT provided in the logic circuit portion can be controlled, and the on-current of the TFT provided in the switch portion or the buffer portion can be increased. Furthermore, the area occupied by the drive circuit is reduced, which contributes to a narrow frame.

Since the protective circuit is provided at the periphery of the pixel portion, it has been a factor that hinders narrowing of the frame. However, since the display device described in this specification can reduce the area of the protection circuit, it can suppress the narrowing of the frame.

(Embodiment 2)
In this embodiment, circuit diagrams and the like of the driver circuit of the display device described in Embodiment 1 will be described with reference to FIGS.

First, a shift register circuit included in the scan line driver circuit described in Embodiment 1 is described.

The shift register circuit illustrated in FIG. 3 includes a plurality of flip-flop circuits 201, and includes a control signal line 202, a control signal line 203, a control signal line 204, a control signal line 205, a control signal line 206, and a reset line 207.

As shown in the shift register circuit of FIG. 3, in the flip-flop circuit 201, the start pulse SSP is input to the input terminal IN of the first stage via the control signal line 202, and the flip-flop of the previous stage is input to the input terminal IN of the subsequent stage. The output signal terminal S _OUT of the circuit 201 is connected. The reset terminal RES of the N-th stage (N is a natural number.) Are connected via the (N + 3) output signal terminal S _out and the reset line 207 of the flip-flop circuit of the stage. Assuming that the first clock signal CLK1 is input to the clock terminal CLK of the Nth stage flip-flop circuit 201 via the control signal line 203, the clock terminal of the (N + 1) th stage flip-flop circuit 201 is assumed. The second clock signal CLK2 is input to CLK through the control signal line 204. The third clock signal CLK 2 is input to the clock terminal CLK of the (N + 2) -th stage flip-flop circuit 201 via the control signal line 205. The fourth clock signal CLK 4 is input to the clock terminal CLK of the (N + 3) -th stage flip-flop circuit 201 through the control signal line 206. The first clock signal CLK 1 is input to the clock terminal CLK of the (N + 4) -th stage flip-flop circuit 201 through the control signal line 203. The Nth flip-flop circuit 201 outputs the output SRoutN of the Nth flip-flop circuit from the gate output terminal _Gout .

Although connection between the flip-flop circuit 201 and a power supply and a power supply line is not shown, a power supply potential Vdd and a power supply potential GND are supplied to each flip-flop circuit 201 via the power supply line.

Note that the power supply potential described in this specification corresponds to a potential difference in a case where the reference potential is 0V. Therefore, the power supply potential is sometimes called a power supply voltage.

Note that in this specification, A and B are connected to each other, including A and B being directly connected, as well as those being electrically connected. Here, A and B are electrically connected when A and B have an object having some electrical action, and A and B are substantially identical through the object. It shall represent the case of becoming a node. Specifically, A and B are connected via a switching element such as a TFT, and when A and B are approximately at the same potential due to conduction of the switching element, or A and B are connected via a resistance element. Are connected to each other and A and B are connected to the same node when considering circuit operation, such as when the potential difference generated at both ends of the resistance element does not affect the operation of the circuit including A and B. It represents the case where it can be understood as.

Next, FIG. 4 illustrates one mode of the flip-flop circuit 201 included in the shift register circuit illustrated in FIG. A flip-flop circuit 201 illustrated in FIG. 4 includes a logic circuit portion 211 and a switch portion 212. The logic circuit portion 211 includes TFTs 213 to 218. The switch unit 212 includes TFTs 219 to 222. Note that the logic circuit portion is a circuit for switching a signal to be output to the switch portion 212 which is a subsequent circuit in accordance with a signal input from the outside. The switch unit 212 is a circuit for switching on or off a TFT serving as a switch in accordance with a signal input from the outside and the logic circuit unit 211 and outputting a current corresponding to the size and structure of the TFT. is there.

In the flip-flop circuit 201, the input terminal IN is connected to the gate terminal of the TFT 214 and the gate terminal of the TFT 217. The reset terminal is connected to the gate terminal of the TFT 213. The clock terminal CLK is connected to the first terminal of the TFT 219 and the first terminal of the TFT 221. A power supply line to which the power supply potential Vdd is supplied is connected to the first terminal of the TFT 214 and the gate terminal and the second terminal of the TFT 216. A power supply line to which the power supply potential GND is supplied is connected to the second terminal of the TFT 213, the second terminal of the TFT 215, the second terminal of the TFT 217, the second terminal of the TFT 218, the second terminal of the TFT 220, and the second terminal of the TFT 222. ing. The first terminal of the TFT 213, the second terminal of the TFT 214, the first terminal of the TFT 215, the gate terminal of the TFT 218, the gate terminal of the TFT 219, and the gate terminal of the TFT 221 are connected to each other. The first terminal and the gate terminal of the TFT 216 are connected to the gate terminal of the TFT 215, the first terminal of the TFT 217, the first terminal of the TFT 218, the gate terminal of the TFT 220, and the gate terminal of the TFT 222. The gate output terminal G _out is connected to the second terminal of the TFT 219 and the first terminal of the TFT 220. The output signal terminal S _out is connected to the second terminal of the TFT 221 and the first terminal of the TFT 222.

Note that here, a case where the TFTs 213 to 222 are all N-type TFTs will be described. However, the TFTs 213 to 222 may be P-type TFTs.

Note that a TFT is an element having at least three terminals including a gate, a drain, and a source, has a channel formation region between the drain region and the source region, and the drain region, the channel formation region, and the source region. A current can be passed through. Here, since the source and the drain may be interchanged depending on the structure or operating conditions of the TFT, it is difficult to specify which is the source and which is the drain. Therefore, regions functioning as a source and a drain are not referred to as a source or a drain, but are referred to as a first terminal and a second terminal, for example. In this case, a terminal functioning as a gate is referred to as a gate terminal.

Next, an example of a layout diagram of the flip-flop circuit 201 illustrated in FIG. 4 is illustrated in FIG.

5 includes a power supply line 231 to which a power supply potential Vdd is supplied, a reset line 232, a control signal line 203, a control signal line 204, a control signal line 205, a control signal line 206, a control signal line 233, a power supply potential. A power supply line 234 to which GND is supplied, a logic circuit portion 211, and a switch portion 212 are included. The logic circuit portion 211 includes TFTs 213 to 218. The switch unit 212 includes TFTs 219 to 222. FIG. 5 also shows a wiring connected to the gate output terminal _Gout and a wiring connected to the output signal terminal _Sout .

In FIG. 5, the semiconductor layer 235, the first wiring layer 236, the second wiring layer 237, the third wiring layer 238, and the contact hole 239 are shown. Note that the first wiring layer 236 is formed by a layer for forming a gate electrode, the second wiring layer 237 is formed by a layer for forming a source electrode or a drain electrode of the TFT, and the third wiring layer 238 is formed by A layer for forming a pixel electrode in the pixel portion may be used. However, the present invention is not limited to this. For example, the third wiring layer 238 may be formed as a wiring layer different from the layer for forming the pixel electrode.

The connection relationship between the circuit elements in FIG. 5 is as described in FIG. Note that FIG. 5 illustrates the flip-flop circuit to which the first clock signal is input; therefore, connection with the control signal line 204 to the control signal line 206 is not illustrated.

In this embodiment mode, the EDMOS circuit 223 can be formed by controlling the threshold voltage of the TFT 216 or the TFT 217 included in the logic circuit portion 211 in the layout diagram of the flip-flop circuit in FIG. Typically, the TFT 216 is a depletion type and the TFT 217 is an enhancement type EDMOS circuit 223, and the TFTs 219 to 222 included in the switch unit 212 are dual gate TFTs or depletion type TFTs. One.

The channel formation region of the depletion type TFT 216 is a semiconductor layer having an impurity element serving as a donor, and the channel formation region of the enhancement type TFT 217 is a semiconductor layer to which an impurity element serving as a donor is not added, whereby the EDMOS circuit 223 is formed. Can be formed.

Alternatively, the channel formation region of the depletion type TFT 216 is a semiconductor layer to which an acceptor impurity element is not added, and the channel formation region of the enhancement type TFT 217 is a semiconductor layer having an acceptor impurity element, whereby the EDMOS circuit 223 is formed. Can be formed.

Alternatively, the depletion type TFT 216 or the enhancement type TFT 217 can be formed by forming the depletion type TFT 216 or the enhancement type TFT 217 with a dual gate type TFT and controlling the potential of the back gate electrode. A circuit 223 can be formed.

Therefore, the TFT of the display device can be formed using only one polarity TFT, such as an n-channel TFT or a p-channel TFT.

Further, the TFT 216 in the logic circuit portion 211 is a TFT for passing a current in accordance with the power supply potential Vdd, and the performance is lowered by increasing the flowing current by using the dual gate TFT or the TFT 216 as a depletion type TFT. Therefore, the TFT can be reduced in size.

Further, in the TFT constituting the switch unit 212, since the amount of current flowing through the TFT can be increased and switching between on and off can be performed at high speed, the area occupied by the TFT can be reduced without reducing the performance. it can. Therefore, the area occupied by the circuit constituted by the TFT can be reduced. Note that the TFTs 219 to 222 in the switch portion 212 may be laid out so that the semiconductor layer 235 is sandwiched between the first wiring layer 236 and the third wiring layer 238 as shown in the figure to form a dual gate TFT.

In FIG. 5, the dual gate TFT includes a semiconductor layer 235 connected to the first wiring layer 236 and a third wiring layer 238 that is connected to the first wiring layer 236 through the contact hole 239 and has the same potential. However, the present invention is not limited to this configuration. For example, a separate control signal line may be provided for the third wiring layer 238 so that the potential of the third wiring layer 238 is controlled independently from the first wiring layer 236. By controlling the threshold voltage of the TFT by the third wiring layer 238 and increasing the amount of current flowing through the TFT, the area occupied by the TFT and the circuit constituted by the TFT can be obtained without degrading the performance. The area occupied by can be reduced.

Note that in the layout diagram of the flip-flop circuit illustrated in FIG. 5, the shape of the channel formation region of the TFTs 213 to 222 may be a U shape (a U shape or a horseshoe shape). In FIG. 5, the size of each TFT is made equal, but the size of each TFT connected to the output signal terminal S _out or the gate output terminal G _out is appropriately changed according to the size of the subsequent load. May be.

Next, operation of the shift register circuit illustrated in FIG. 3 is described with reference to a timing chart illustrated in FIG. 6 illustrates the start pulse SSP, the first clock signal CLK1 to the fourth clock signal CLK4, and the first to fifth stages supplied to the control signal line 202 to the control signal line 206 shown in FIG. It shows the Sout1 to Sout5 outputted from the output signal terminal _{S out} of the flip-flop circuit. In the description of FIG. 6, the reference numerals attached to the elements in FIGS. 4 and 5 are used.

FIG. 6 is a timing chart in the case where each TFT included in the flip-flop circuit is an N-type TFT. The first clock signal CLK1 and the fourth clock signal CLK4 are shifted by a quarter wavelength (one section divided by a dotted line) as shown in the figure.

First, in the period T1, the start pulse SSP is input to the first flip-flop circuit at the H level, and the logic circuit portion 211 turns on the TFT 219 and the TFT 221 in the switch portion and turns off the TFT 220 and the TFT 222. At this time, since the first clock signal CLK1 is at L level, Sout1 is at L level.

Note that in the period T1, since no signal is input to the IN terminal of the second and subsequent flip-flop circuits, the L level is output without being operated. In the initial state, each flip-flop circuit of the shift register circuit will be described as outputting L level.

Next, in the period T2, in the flip-flop circuit in the first stage, the logic circuit portion 211 controls the switch portion 212 as in the period T1. In the period T2, since the first clock signal CLK1 is at the H level, Sout1 is at the H level. In the period T2, Sout1 is input to the IN terminal at the H level in the second-stage flip-flop circuit, the logic circuit portion 211 turns on the TFT 219 and the TFT 221 in the switch portion, and turns off the TFT 220 and the TFT 222. At this time, since the second clock signal CLK2 is at L level, Sout2 is at L level.

Note that in the period T2, since no signal is input to the IN terminal in the third and subsequent flip-flop circuits, the L level is output without being operated.

Next, in the period T3, in the flip-flop circuit in the first stage, the logic circuit unit 211 controls the switch unit 212 so as to maintain the state in the period T2. Therefore, in the period T3, the first clock signal CLK1 is at an H level and Sout1 is at an H level. Further, in the period T3, in the flip-flop circuit in the second stage, the logic circuit unit 211 controls the switch unit 212 as in the period T2. In the period T3, since the second clock signal CLK2 is at the H level, Sout2 is at the H level. In addition, in the third-stage flip-flop circuit in the period T3, Sout2 is input to the IN terminal at the H level, the logic circuit portion 211 turns on the TFTs 219 and 221 in the switch portion, and turns off the TFTs 220 and 222. At this time, since the third clock signal CLK3 is at L level, Sout3 is at L level.

Note that in the period T3, no signal is input to the IN terminal of the fourth and subsequent flip-flop circuits, and thus the L level is output without operation.

Next, in the period T4, the first clock signal CLK1 is at the L level, and Sout1 is at the L level. In the period T4, in the second-stage flip-flop circuit, the logic circuit unit 211 controls the switch unit 212 so that the state of the period T3 is maintained. Therefore, in the period T4, the second clock signal CLK2 is at an H level and Sout2 is at an H level. In the period T4, in the third-stage flip-flop circuit, the logic circuit unit 211 controls the switch unit 212 as in the period T3. In the period T4, since the third clock signal CLK3 is at the H level, Sout3 is at the H level. In addition, in the fourth flip-flop circuit in the period T4, Sout3 is input to the IN terminal at the H level, the logic circuit portion 211 turns on the TFT 219 and the TFT 221 of the switch portion 212, and turns off the TFT 220 and the TFT 222. At this time, since the fourth clock signal CLK4 is at L level, Sout4 is at L level.

Note that in the period T4, since no signal is input to the IN terminal of the fifth and subsequent flip-flop circuits, the L level is output without operation.

Next, in the period T5, in the flip-flop circuit in the first stage, the logic circuit unit 211 controls the switch unit 212 so as to maintain the state in the period T4. Therefore, in the period T5, the first clock signal CLK1 is at the L level and Sout1 is at the L level. In the period T5, in the second-stage flip-flop circuit, the logic circuit unit 211 controls the switch unit 212 as in the period T4. In the period T5, since the second clock signal CLK2 is at the L level, Sout2 is at the L level. In the period T5, in the flip-flop circuit at the third stage, the logic circuit unit 211 controls the switch unit 212 so that the state of the period T4 is maintained. Therefore, in the period T5, the third clock signal CLK3 is at an H level, and Sout3 is at an H level. In the period T5, the logic circuit portion 211 controls the switch portion 212 in the fourth flip-flop circuit as in the period T4. In the period T5, since the fourth clock signal CLK4 is at the H level, Sout4 is at the H level. The fifth and subsequent flip-flop circuits have the same wiring relationship as the first to fourth flip-flop circuits, and the timing of the input signals is also the same, and thus description thereof is omitted.

As shown in the shift register circuit of FIG. 3, Sout4 also serves as a reset signal for the first-stage flip-flop circuit. In the period T5, Sout4 becomes H level, and this signal is input to the reset terminal RES of the first-stage flip-flop circuit. When the reset signal is input, the TFT 219 and the TFT 221 of the switch unit 212 are turned off, and the TFT 220 and the TFT 222 are turned on. Then, Sout1 of the first-stage flip-flop circuit outputs an L level until the next start pulse SSP is input.

With the operation described above, the flip-flop circuits in the second and subsequent stages also reset the logic circuit portion based on the reset signal output from the flip-flop circuit in the subsequent stage, and as shown in Sout1 to Sout5, A shift register circuit that outputs a signal having a waveform shifted by ¼ wavelength can be obtained.

Further, as the flip-flop circuit, the logic circuit unit 211 is configured by providing the logic circuit unit 211 with a TFT of an EDMOS circuit in which an enhancement type and a depletion type are combined, and the switch unit 212 with a dual gate TFT. The amount of current flowing through the TFT can be increased, and the area occupied by the TFT and the area occupied by the circuit constituted by the TFT can be reduced without reducing the performance. Further, in the TFT constituting the switch unit 212, since the amount of current flowing through the TFT can be increased and switching between on and off can be performed at high speed, the area occupied by the TFT without degrading the performance, and further the TFT The area occupied by the circuit constituted by can be reduced. Accordingly, it is possible to reduce the frame size, size, and performance of the display device.

Further, a latch circuit, a level shifter circuit, or the like can be provided in the signal line driver circuit described in Embodiment 1. A buffer unit is provided at the final stage for transmitting a signal from the signal line driver circuit to the pixel unit, and a signal obtained by amplifying the current amount is transmitted from the signal line driver circuit to the pixel unit. Therefore, by providing a TFT having a large on-current, typically a dual gate TFT or a depletion TFT, in the buffer portion, the area of the TFT can be reduced, and the signal line driver circuit occupies it. The area can be reduced. Accordingly, it is possible to reduce the frame size, size, and performance of the display device. Note that a shift register which is part of the signal line driver circuit is required to operate at high speed, and thus is preferably mounted on a display device using an IC or the like.

(Embodiment 3)
In this embodiment, a structure of a thin film transistor in a logic circuit portion, a switch portion, and a pixel portion in the display device described in Embodiments 1 and 2 is described. A thin film transistor used for a display device has higher carrier mobility in an n-type than in a p-type. In addition, it is preferable that all thin film transistors formed over the same substrate have the same polarity because the number of steps can be reduced. Therefore, in this embodiment, an n-type thin film transistor is described.

7A and 7B are cross-sectional views of one mode (structure 1) of the logic circuit portion 391, the switch portion 393, and the pixel portion 395 of the display device according to this embodiment.

In the logic circuit portion 391 of the display device shown in FIG. 7, an EDMOS circuit is shown, and one of a depletion type TFT or an enhancement type TFT of the EDMOS circuit is formed by a dual gate type TFT 300a having a gate electrode 303 and a back gate electrode 373. Is done. The other of the depletion type TFT or the enhancement type TFT is formed by the TFT 300b. Note that the cross-sectional view CD of the logic circuit portion 391 illustrated in FIG. 7 and the cross-sectional view CE of the logic circuit portion 391 illustrated in FIG. 8A are CDs in the top view of FIG. It corresponds to each of C-E.

In the switch portion 393 of the display device illustrated in FIG. 7, a dual-gate TFT 300 c including the gate electrode 305 and the back gate electrode 374 is formed.

A switching element in the pixel of the pixel portion 395 of the display device illustrated in FIG. 7 is formed of a TFT 300d. Further, the capacitor 300 e is formed by the second gate insulating layer 379, the wiring 353, and the wiring 375.

The TFT 300a includes a gate electrode 303, a first semiconductor layer 333a, a second semiconductor layer 333b, a pair of third semiconductor layers 363a and 363b, a gate electrode 303, and a first semiconductor layer over a substrate 301. A first gate insulating layer 309 provided between the first semiconductor layer 333a, impurity semiconductor layers 355 and 356 functioning as a source region and a drain region in contact with the pair of third semiconductor layers 363a and 363b, and a wiring 346 in contact with the impurity semiconductor layer. 347. Further, the first semiconductor layer 333a, the second semiconductor layer 333b, the pair of third semiconductor layers 363a and 363b, the first gate insulating layer 309, the impurity semiconductor layers 355 and 356, and the impurity semiconductor layers are provided. A second gate insulating layer 379 is formed to cover the wirings 346 and 347 in contact therewith, and a back gate electrode 373 is provided in a region facing the gate electrode 303 with the second gate insulating layer interposed therebetween.

The TFT 300b includes a gate electrode 304, a first semiconductor layer 333a, a second semiconductor layer 333b, a pair of third semiconductor layers 363b and 363c, a gate electrode 304, and a first semiconductor layer over a substrate 301. A first gate insulating layer 309 provided between the first semiconductor layer 333a, impurity semiconductor layers 356 and 357 functioning as a source region and a drain region in contact with the pair of third semiconductor layers 363b and 363c, and a wiring 347 in contact with the impurity semiconductor layer. 348.

As shown in FIG. 8A, the gate electrode 303 of the TFT 300a and the wiring 347 of the TFT 300a and the TFT 300b are connected by a wiring 384 formed over the insulating layer 381 simultaneously with the pixel electrode 383.

The TFT 300c includes a gate electrode 305, a first semiconductor layer 334a, a second semiconductor layer 334b, a pair of third semiconductor layers 364a and 364b, a gate electrode 305, and a first semiconductor layer over a substrate 301. A first gate insulating layer 309 provided between the first semiconductor insulating layer 334a, impurity semiconductor layers 358 and 359 functioning as a source region and a drain region in contact with the pair of third semiconductor layers 364a and 364b, and a wiring 349 in contact with the impurity semiconductor layer. , 350. In addition, the first semiconductor layer 334a, the second semiconductor layer 334b, the pair of third semiconductor layers 364a and 364b, the first gate insulating layer 309, the impurity semiconductor layers 358 and 359, the wiring 349, A second gate insulating layer 379 is formed so as to cover 350, and a back gate electrode 374 is provided in a region facing the gate electrode 305 with the second gate insulating layer 379 interposed therebetween.

The TFT 300d includes a gate electrode 306, a first semiconductor layer 335a, a second semiconductor layer 335b, a pair of third semiconductor layers 365a and 365b, a gate electrode 306, and a first semiconductor layer over a substrate 301. A first gate insulating layer 309 provided between 335a, impurity semiconductor layers 360 and 361 functioning as a source region and a drain region in contact with the third semiconductor layer 365, and wirings 351 and 352 in contact with the impurity semiconductor layer. Have.

The capacitor 300e includes a second gate insulating layer 379, a wiring 353, and a wiring 375.

As the substrate 301, a glass substrate, a ceramic substrate, a plastic substrate having heat resistance enough to withstand the processing temperature in the manufacturing process, or the like can be used. In the case where the substrate does not require translucency, a metal substrate such as a stainless alloy provided with an insulating layer on the surface may be used. As the glass substrate, for example, an alkali-free glass substrate such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass may be used. Further, as the substrate 301, the third generation (550 mm × 650 mm), the 3.5th generation (600 mm × 720 mm, or 620 mm × 750 mm), the fourth generation (680 mm × 880 mm, or 730 mm × 920 mm), the fifth generation (1100 mm). × 1300mm), 6th generation (1500mm × 1850mm), 7th generation (1870mm × 2200mm), 8th generation (2200mm × 2400mm), 9th generation (2400mm × 2800mm, 2450mm × 3050mm), 10th generation (2950mm × A glass substrate such as 3400 mm) can be used.

The gate electrodes 303 to 306 and the capacitor wiring 307 are formed of a single layer or stacked layers using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing these as a main component. Can be formed. Alternatively, a semiconductor layer typified by polycrystalline silicon doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used.

For example, as a two-layer structure of the gate electrodes 303 to 306 and the capacitor wiring 307, a two-layer structure in which a molybdenum layer is stacked on an aluminum layer, or a two-layer structure in which a molybdenum layer is stacked on a copper layer, Alternatively, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked is preferable. The three-layer structure is preferably a stack in which a tungsten layer or a tungsten nitride layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer are stacked. When a metal layer functioning as a barrier layer is stacked over a layer with low electrical resistance, electrical resistance is low and diffusion of a metal element from the metal layer to the semiconductor layer can be prevented.

The first gate insulating layer 309 can be formed using a single layer or stacked layers of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer by a CVD method, a sputtering method, or the like. In addition, by forming the first gate insulating layer 309 using silicon oxide or silicon oxynitride, when the first semiconductor layers 333a to 335a are microcrystalline semiconductor layers, variation in threshold voltage of the thin film transistor can be reduced. it can.

Note that in this specification, silicon oxynitride has a higher oxygen content than nitrogen as a composition, and preferably Rutherford Backscattering Spectroscopy (RBS) and hydrogen forward scattering. When measured by the method (HFS: Hydrogen Forward Scattering), the composition ranges from 50 to 70 atomic% for oxygen, 0.5 to 15 atomic% for nitrogen, 25 to 35 atomic% for silicon, and 0.1 for hydrogen. The thing contained in the range of -10 atomic%. In addition, silicon nitride oxide has a composition containing more nitrogen than oxygen, and preferably has a composition range of 5 to 30 atomic% when measured using RBS and HFS. Nitrogen is contained in the range of 20 to 55 atomic%, silicon is contained in the range of 25 to 35 atomic%, and hydrogen is contained in the range of 10 to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.

The first semiconductor layers 333a to 336a are formed using a microcrystalline semiconductor layer. A microcrystalline semiconductor is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). A microcrystalline semiconductor is a semiconductor having a third state which is stable in terms of free energy, is a crystalline semiconductor having a short-range order and lattice distortion, and has a crystal grain size of 2 nm to 200 nm, preferably 10 nm. Columnar crystals or needle-like crystals having a thickness of 80 nm or more and more preferably 20 nm or more and 50 nm or less grow in the normal direction with respect to the substrate surface. For this reason, a crystal grain boundary may be formed at the interface between the columnar crystal or the needle crystal.

Microcrystalline silicon which is a typical example of a microcrystalline semiconductor has a Raman spectrum shifted to a lower wave number side than 520 cm ⁻¹ indicating single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520 cm ⁻¹ indicating single crystal silicon and 480 cm ⁻¹ indicating amorphous silicon. In addition, at least 1 atomic% or more of hydrogen or halogen is contained to terminate dangling bonds (dangling bonds). Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote the lattice distortion, the stability can be improved and a good microcrystalline semiconductor can be obtained. A description of such a microcrystalline semiconductor is disclosed in, for example, US Pat. No. 4,409,134.

The concentration of oxygen and nitrogen contained in the first semiconductor layers 333a to 336a measured by secondary ion mass spectrometry is less than 1 × 10 ¹⁸ atoms / cm ³ , whereby the first semiconductor layer 333a The crystallinity of ˜336a can be increased, which is preferable.

The pair of third semiconductor layers 363a to 365a, 363b to 365b, and the third semiconductor layer 366 are formed using an amorphous semiconductor layer, an amorphous semiconductor layer containing halogen, or an amorphous semiconductor layer containing nitrogen. Is done. Nitrogen contained in the amorphous semiconductor layer containing nitrogen may exist as, for example, an NH group or an NH ₂ group. The amorphous semiconductor layer is formed using amorphous silicon.

FIG. 9 shows an enlarged view of the TFTs 300a to 300d in FIG.

As shown in FIG. 9, the third semiconductor layers 363a to 365a, 363b to 365b are in contact with the second semiconductor layers 333b to 335b between the impurity semiconductor layers 355 to 361 and the first semiconductor layers 333a to 335a. Is provided.

The pair of third semiconductor layers 363a to 365a and the third semiconductor layers 363b to 365b are formed using an amorphous semiconductor layer with low electrical conductivity and high resistivity, an amorphous semiconductor layer containing halogen, or nitrogen. By forming the amorphous semiconductor layer, the off-state current of the thin film transistor can be reduced. In addition, when the pair of third semiconductor layers 363a to 365a and the third semiconductor layers 363b to 365b are formed using an amorphous semiconductor layer containing nitrogen, the band gap of the band gap of the amorphous semiconductor layer is compared. The slope becomes steep, the band gap becomes wide, and the tunnel current hardly flows. As a result, the off-state current of the thin film transistor can be reduced.

The second semiconductor layers 333b to 335b are formed using a microcrystalline semiconductor layer having a plurality of conical protrusions (convex portions). Here, the conical shape is a convex shape whose tip is narrowed from the first gate insulating layer 309 toward the third semiconductor layers 363a to 365a and 363b to 365b, and includes a needle shape. Note that the first gate insulating layer 309 may have a convex shape whose width increases from the third semiconductor layers 363a to 365a and 363b to 365b. Since the second semiconductor layers 333b to 335b are formed of conical microcrystalline semiconductor layers, resistance in the vertical direction (film thickness direction) when a voltage is applied to the wiring while the thin film transistor is on, that is, the first The resistance between one semiconductor layer 333a to 336a and the source region or the drain region can be reduced, and the on-state current of the thin film transistor can be increased.

In addition, the second semiconductor layers 333b to 335b preferably contain nitrogen. This is because nitrogen, typically, is present at the interface between crystal grains included in the second semiconductor layers 333b to 335b and at the interfaces between the second semiconductor layers 333b to 335b and the third semiconductor layers 363a to 365a and 363b to 365b. This is because defects are reduced when NH groups or NH ₂ groups are bonded to dangling bonds of silicon atoms. Therefore, the nitrogen concentration of the second semiconductor layers 333b to 335b is set to 1 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less, 1 × 10 ²⁰ atoms / cm ^{3 to} 1 × 10 ²¹ atoms / cm. ^By setting it to ³ , dangling bonds of silicon atoms can be easily cross-linked with nitrogen, preferably NH groups, and carriers can easily flow. Alternatively, the dangling bonds of the semiconductor atoms at the interface described above are terminated with NH ₂ groups, and the defect level disappears. As a result, resistance in the vertical direction (thickness direction) when a voltage is applied between the source electrode and the drain electrode in the on state is reduced. That is, the field effect mobility and the on-current of the thin film transistor are increased.

In addition, by reducing the oxygen concentration of the second semiconductor layers 333b to 335b, the second semiconductor layers 333b to 335b, the pair of third semiconductor layers 363a to 365a, and the third semiconductor layers 363b to 365b Bonds that inhibit the movement of carriers at the interface or between crystal grains can be reduced.

Note that the first semiconductor layers 333a to 335a and the second semiconductor layers 333b to 335b may have different contents of nitrogen or hydrogen. This is because film formation conditions of the first semiconductor layers 333a to 335a and the second semiconductor layers 333b to 335b are different, and the second semiconductor layers 333b to 335b contain more nitrogen or hydrogen.

The total thickness of the first semiconductor layers 333a to 335a and the second semiconductor layers 333b to 335b, that is, from the interface of the first gate insulating layer 309, the tips of the convex portions of the second semiconductor layers 333b to 335b By setting the distance to 3 nm to 80 nm, preferably 5 nm to 30 nm, the off-state current of the TFT can be reduced.

A first insulating layer 348a is formed on the surfaces of the first semiconductor layers 333a to 335a and the second semiconductor layers 333b to 335b. In addition, second insulating layers 348 b and 348 c are formed on the side surfaces of the third semiconductor layers 363 a to 365 a and 363 b to 365 b and the side surfaces of the impurity semiconductor layers 355 to 361. In addition, third insulating layers 348d and 348e are formed on the side surfaces of the wirings 346 to 352.

The first insulating layer 348a includes an oxide layer obtained by oxidizing the first semiconductor layers 333a to 335a and the second semiconductor layers 333b to 335b, or the first semiconductor layers 333a to 335a and the second semiconductor layers 333b to 335b. It is formed of a nitride layer obtained by nitriding.

The second insulating layers 348b and 348c are oxide layers obtained by oxidizing the side surfaces of the third semiconductor layers 363a to 365a and 363b to 365b and the impurity semiconductor layers 355 to 361, or the third semiconductor layers 363a to 365a, 363b to 363b. The side surface of 365b and the nitride layer formed by nitriding the impurity semiconductor layers 355 to 362 are formed.

The third insulating layers 348d and 348e are formed of an oxide layer obtained by oxidizing the wirings 346 to 352 or a nitride layer obtained by nitriding the wirings 346 to 352.

The amorphous semiconductor layer has a weak n-type. In addition, the density is lower than that of the microcrystalline semiconductor layer. Therefore, an insulating layer obtained by oxidizing or nitriding an amorphous semiconductor layer is also a low-density, sparse insulating layer and has low insulating properties. However, in the TFT described in this embodiment, the first insulating layer 348a obtained by oxidizing the second semiconductor layers 333b to 335b formed using a microcrystalline semiconductor layer is formed on the back channel side. Since the microcrystalline semiconductor layer has a higher density than the amorphous semiconductor layer, the first insulating layer 348a also has a higher density and higher insulating properties. Further, since the second semiconductor layers 333b to 335b have a plurality of conical protrusions, the surfaces thereof are uneven. For this reason, the distance of the leak path from the source region to the drain region is long. From these results, the leakage current and off-current of the TFT can be reduced.

The impurity semiconductor layers 355 to 362 are formed using amorphous silicon to which phosphorus is added, microcrystalline silicon to which phosphorus is added, or the like. Note that in the case where a p-channel thin film transistor is formed as the thin film transistor, the impurity semiconductor layers 355 to 362 are formed of microcrystalline silicon to which boron is added, amorphous silicon to which boron is added, or the like. Note that when the second semiconductor layers 333b to 336b or the pair of third semiconductor layers 363a to 365a, 363b to 365b, the third semiconductor layer 366, and the wirings 346 to 353 are in ohmic contact, the impurity semiconductor layer 355 to 362 need not be formed.

In the case where the impurity semiconductor layers 355 to 362 are formed using microcrystalline silicon to which phosphorus is added or microcrystalline silicon to which boron is added, the second semiconductor layers 333b to 336b or the pair of third semiconductor layers By forming a microcrystalline semiconductor layer, typically a microcrystalline silicon layer, between the semiconductor layers 363a to 365a, 363b to 365b, the third semiconductor layer 366, and the impurity semiconductor layers 355 to 362, the characteristics of the interface can be improved. Can be improved. As a result, resistance generated at the interface between the impurity semiconductor layers 355 to 362 and the pair of third semiconductor layers 363a to 365a, 363b to 365b, and the third semiconductor layer 366 can be reduced. As a result, the amount of current flowing through the source region, the semiconductor layer, and the drain region of the thin film transistor can be increased, and the on-current and field effect mobility can be increased.

The wirings 346 to 352 can be formed of a single layer or a stacked layer using aluminum, copper, titanium, neodymium, scandium, molybdenum, chromium, tantalum, tungsten, or the like. Alternatively, an aluminum alloy to which a hillock prevention element is added (eg, an Al—Nd alloy that can be used for the gate electrodes 303 to 306 and the capacitor wiring 307) may be used. Crystalline silicon to which an impurity element which serves as a donor is added may be used. The layer on the side in contact with the crystalline silicon to which the impurity element to be a donor is added is formed of titanium, tantalum, molybdenum, tungsten, or nitride of these elements, and a laminated structure in which aluminum or an aluminum alloy is formed thereon Also good. Furthermore, a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched between titanium, tantalum, molybdenum, tungsten, or nitrides of these elements may be employed.

The second gate insulating layer 379 can be formed in a manner similar to that of the first gate insulating layer 309.

The back gate electrodes 373 and 374 and the wiring 375 can be formed in a manner similar to that of the wirings 346 to 353.

The insulating layer 381 can be formed using an inorganic insulating layer or an organic resin layer. As the inorganic insulating layer, silicon oxide, silicon oxynitride, silicon nitride oxide, carbon typified by DLC (diamond-like carbon), or the like can be used. For the organic resin layer, for example, acrylic, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or the like can be used. Moreover, a siloxane polymer can be used.

The wiring 384 and the pixel electrode 383 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, and indium zinc oxide. Or indium tin oxide to which silicon oxide is added can be used.

The wiring 384 and the pixel electrode 383 can be formed using a conductive composition including a light-transmitting conductive high molecule (also referred to as a conductive polymer). The wiring 384 and the pixel electrode 383 preferably have a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be given.

The dual gate TFT can control the threshold voltage by changing the potential of each of the gate electrode 303 and the back gate electrode 373. Therefore, in the logic circuit portion 391, a depletion type TFT or An EDMOS circuit can be formed by using one of the enhancement type TFTs as a dual gate TFT 300a and the other of the depletion type TFT or the enhancement type TFT as a TFT 300b shown in FIG.

Further, in the case of a dual gate TFT, the channel through which carriers flow is two locations near the interface on the first gate insulating layer 309 side and the interface near the second gate insulating layer 379 side, so that the amount of carrier movement Increases, and the on-state current of the thin film transistor can be increased. For this reason, the area of the TFT can be reduced by forming the dual gate type TFT 300c capable of increasing the on-current in the TFT formed in the switch portion 393, and the drive circuit of the display device can be reduced. The area can be reduced.

Next, cross-sectional views of one embodiment (structure 2) of the logic circuit portion 391, the switch portion 393, and the pixel portion 395 of the display device according to this embodiment are illustrated in FIGS.

10 shows an EDMOS circuit of the logic circuit portion 391 of the display device shown in FIG. 10, and a TFT having a first semiconductor layer to which an impurity element imparting one conductivity type is added to a channel formation region as a depletion type TFT 401a of the EDMOS circuit Is formed. Further, an enhancement type TFT 401b is formed. Note that a cross-sectional view CD of the logic circuit portion 391 illustrated in FIG. 10 and a cross-sectional view CE of the logic circuit portion 391 illustrated in FIG. 11A are CDs in the top view of FIG. It corresponds to each of C-E.

In the switch portion 393 of the display device illustrated in FIG. 10, a TFT in which a first semiconductor layer to which an impurity element imparting one conductivity type is added is formed in a channel formation region, in this case, an impurity element to be a donor is added A depletion type TFT 401c having a first semiconductor layer is formed.

The TFT 401a includes a gate electrode 303, a first semiconductor layer 427a to which an impurity element imparting one conductivity type is added, a second semiconductor layer 427b, a pair of third semiconductor layers 469a, 469b, a first gate insulating layer 309 provided between the gate electrode 303 and the first semiconductor layer 427a to which an impurity element imparting one conductivity type is added, and the pair of third semiconductor layers 469a and 469b Impurity semiconductor layers 459 and 460 functioning as a source region and a drain region in contact with each other, and wirings 451 and 452 in contact with the impurity semiconductor layers 459 and 460 are provided.

The TFT 401b includes a gate electrode 304, a first semiconductor layer 454a, a second semiconductor layer 454b, a pair of third semiconductor layers 470a and 470b, a gate electrode 304, and a first semiconductor layer 454a over a substrate 301. The first gate insulating layer 309, the impurity semiconductor layers 461 and 462 that function as source and drain regions in contact with the pair of third semiconductor layers 470a and 470b, and the impurity semiconductor layers 461 and 462. Wiring 452 and 453 are included.

11A, the gate electrode 303 of the TFT 401a and the wiring 452 of the TFT 401a and the TFT 401b are connected by a wiring 384 formed over the insulating layer 381.

The TFT 401c includes a gate electrode 305, a first semiconductor layer 428a and a second semiconductor layer 428b to which an impurity element imparting one conductivity type is added, and a pair of third semiconductor layers 471a and 471b over a substrate 301. A first gate insulating layer 309 provided between the gate electrode 305 and the first semiconductor layer 428a, and an impurity semiconductor layer 463 functioning as a source region and a drain region in contact with the pair of third semiconductor layers 471a and 471b. 464 and wirings 454 and 455 which are in contact with the impurity semiconductor layers.

The TFT 401d includes a gate electrode 306, a first semiconductor layer 455a, a second semiconductor layer 455b, a pair of third semiconductor layers 472a and 472b, a gate electrode 306, and a first semiconductor layer 455a over a substrate 301. A first gate insulating layer 309 provided between the impurity semiconductor layers 465 and 466 functioning as a source region and a drain region in contact with the pair of third semiconductor layers 472a and 472b, a wiring 456 in contact with the impurity semiconductor layer, 457.

Here, the first semiconductor layers 427a and 428a to which an impurity element imparting one conductivity type is added have an impurity element which serves as a donor here. The impurity element that serves as a donor is an element belonging to Group 15 of the periodic table, and typically includes phosphorus, arsenic, antimony, and the like. Here, as the first semiconductor layer 427a to which an impurity element imparting one conductivity type is added, a microcrystalline semiconductor layer to which phosphorus that is an impurity element serving as a donor is added is formed.

The first semiconductor layers 454a to 456a can be formed in a manner similar to that of the first semiconductor layers 333a to 335a shown in the “Structure 1”.

The second semiconductor layers 427b, 428b, 454b to 456b can be formed in a similar manner to the second semiconductor layers 333b to 336b shown in the “Structure 1”.

The pair of third semiconductor layers 469a to 472a, 469b to 472b, and the third semiconductor layer 473 are the same as the pair of third semiconductor layers 363a to 365a, 363b to 365b, and the third semiconductor layer shown in the “Structure 1”. It can be formed in the same manner as 366.

The impurity semiconductor layers 459 to 467 can be formed in a manner similar to that of the impurity semiconductor layers 355 to 362 shown in the above “Structure 1”.

The wirings 451 to 458 can be formed in a manner similar to that of the wirings 346 to 353 described in the above “Structure 1”.

Note that in FIG. 10, a TFT in which a first semiconductor layer to which an impurity element imparting one conductivity type is added is formed in a channel formation region is used as a depletion type TFT 401a of an EDMOS circuit. A channel formation region of the TFT 401a is formed in a manner similar to that of the first semiconductor layer 454a of the TFT 401b, and an impurity element imparting one conductivity type, typically an impurity element serving as an acceptor, is added to the channel formation region of the enhancement type TFT 401b. A first semiconductor layer to which is added may be formed. The impurity element that serves as an acceptor is an element belonging to Group 13 of the periodic table, and typically includes boron and the like.

Here, in the logic circuit portion 391, an EDMOS circuit is formed by using a semiconductor layer to which an impurity element imparting one conductivity type is added in one channel formation region of a depletion type TFT or an enhancement type TFT. be able to.

In addition, since the threshold voltage of the depletion type TFT shifts to minus, it is possible to increase the current in the on state, so that the on current can be increased in the TFT formed in the switch portion 393. By forming a depletion type TFT, the area of the TFT can be reduced, and the area of the drive circuit of the display device can be reduced.

Next, a cross-sectional view of one embodiment (structure 3) of the logic circuit portion 391, the switch portion 393, and the pixel portion 395 of the display device according to this embodiment is described with reference to FIGS.

12 shows an EDMOS circuit of the logic circuit portion 391 of the display device shown in FIG. 12, and an impurity element imparting one conductivity type is added to the channel formation region shown in the “configuration 2” as a depletion type TFT 401a of the EDMOS circuit. A TFT 401a having the first semiconductor layer is formed. Further, as the enhancement type TFT 401b, the TFT 401b shown in the above "Configuration 2" is formed. Note that a cross-sectional view CD of the logic circuit portion 391 illustrated in FIG. 12 and a cross-sectional view CE of the logic circuit portion 391 illustrated in FIG. 13A are CDs in the top view of FIG. It corresponds to each of C-E.

In the switch portion 393 of the display device illustrated in FIG. 12, a dual-gate TFT 403c having a gate electrode 305 and a back gate electrode 482 is formed.

A switching element in the pixel of the pixel portion 395 of the display device illustrated in FIG. 12 is formed of a TFT 401d. In addition, the pixel element 481 connected to the wiring of the TFT 401d, the wiring 458, and the second gate insulating layer 379 form a capacitor 403e.

Compared with the TFT 401a shown in FIG. 10, the TFT 401a shown in FIG. 12 includes a gate electrode 303 and a wiring 452 connecting the TFT 401a and the TFT 401b over the second gate insulating layer 379, as shown in FIG. Are connected by a wiring 483 formed simultaneously with the pixel electrode 481.

The TFT 403c includes a gate electrode 305, a first semiconductor layer 428a to which an impurity element imparting one conductivity type is added, a second semiconductor layer 428b, a pair of third semiconductor layers 471a, 471b, a first gate insulating layer 309 provided between the gate electrode 305 and the first semiconductor layer 428a, impurity semiconductor layers 463 and 464 functioning as a source region and a drain region in contact with the third semiconductor layer 471, And wirings 454 and 455 which are in contact with the impurity semiconductor layers 463 and 464, respectively. In addition, a back gate electrode 482 is provided in a region facing the gate electrode 305 with the second gate insulating layer 379 interposed therebetween. The back gate electrode 374 can be formed at the same time as the pixel electrode 481.

Note that instead of the TFT 403c, a dual-gate TFT 300c shown in the above "Structure 1" may be formed.

A pixel electrode 481 connected to the TFT 401d is formed over the second gate insulating layer 379.

In the display device illustrated in FIGS. 12A and 12B, the back gate electrode 482, the gate electrode 303, and the wiring 483 that connect the wiring 452 can be formed at the same time as the pixel electrode 481, so that the number of photomasks can be reduced. is there.

Next, FIG. 14 shows a cross-sectional view (structure 4) of an embodiment of an EDMOS circuit applicable to the “structure 1” to “structure 3”.

FIG. 14A shows an EDMOS circuit of the logic circuit portion 391 of the display device. A depletion type TFT 480a of the EDMOS circuit is provided in a channel formation region as shown in the above “structure 2” and “structure 3”. A TFT having a first semiconductor layer to which an impurity element imparting a conductivity type is added is formed. Further, the enhancement type TFT 480b is formed with a structure similar to that of the TFT 300b shown by “Structure 1”. Note that a cross-sectional view CD of the logic circuit portion 391 illustrated in FIG. 14A corresponds to CD in the top view of FIG.

In the EDMOS circuit illustrated in FIG. 14, the gate electrode 486 of the depletion type TFT 480 a is directly connected to the wiring 485 that connects the depletion type TFT 480 a and the enhancement type TFT 480 b and the opening formed in the first gate insulating layer 309. Connecting.

Therefore, since the gate electrode 486 and the wiring 485 are directly connected to each other, the contact resistance of the gate electrode 486 and the wiring 485 can be reduced as compared with the EDMOS circuits illustrated in FIGS.

Note that when the field effect mobility of the TFT is lower than 5 cm ² / V · sec, typically, in the case of 0.5 to ³ cm ² / V · sec, “Structure 1” to “Structure 3” As shown, the number of masks is reduced by connecting the depletion-type TFT and the enhancement-type TFT to the gate electrode of the depletion-type TFT simultaneously with the back gate electrode or the pixel electrode. It is possible. On the other hand, when the field effect mobility of the TFT is 5 cm ² / V · sec or more, as shown in FIG. 14, the wiring connecting the depletion type TFT and the enhancement type TFT is connected to the first gate insulating layer 309. Since the increase in contact resistance can be reduced by directly connecting to the gate electrode of the depletion type TFT in the opening formed in the TFT, high-speed operation of the TFT can be maintained.

Note that the TFTs shown in the EDMOS circuits of “Structure 1” to “Structure 4” can be applied to an inverter, a shift register, a buffer circuit, a protection circuit, a diode, and the like as appropriate.

In the display device described above, the TFT formed in the driver circuit and the pixel portion is an inverted staggered TFT, and the polarity of each TFT can be formed as one of n-channel and p-channel polarities. In addition, since part of the driver circuit is formed over the substrate, the cost of the display device can be reduced. Further, by providing a dual gate TFT or a depletion type TFT to a TFT which requires a large amount of current, the area of the TFT can be reduced, so that the display device can be narrowed and the display area can be reduced. Can be enlarged. In addition, in the pixel portion, a TFT with a high on-state current and a low off-state current is used as a switching element of each pixel, so that a display device with high contrast and good image quality is obtained.

(Embodiment 4)
Here, a method for manufacturing the display device illustrated in FIGS. 7A to 7C is described with reference to FIGS. In this embodiment, a method for manufacturing an n-type thin film transistor (“method 1”) will be described.

As shown in FIG. 13A, gate electrodes 303 to 306 and a capacitor wiring 307 are formed over a substrate 301. Next, a first gate insulating layer 309 and a first semiconductor layer 311 are formed so as to cover the gate electrodes 303 to 306 and the capacitor wiring 307.

As the substrate 301, the substrate 301 described in Embodiment 3 can be used as appropriate.

The gate electrodes 303 to 306 and the capacitor wiring 307 are formed by appropriately using the materials shown in the gate electrodes 303 to 306 and the capacitor wiring 307 described in Embodiment 3. For the gate electrodes 303 to 306 and the capacitor wiring 307, a conductive layer is formed using the above-described material on the substrate 301 by a sputtering method or a vacuum evaporation method, and a mask is formed on the conductive layer by a photolithography method, an inkjet method, or the like. The conductive layer can be formed by etching using the mask. Alternatively, a conductive nano paste such as silver, gold, or copper can be formed by discharging onto a substrate by an ink jet method and baking. Note that a nitride layer of the above metal material is used for the substrate 301 and the gate electrodes 303 to 306 as a barrier metal for preventing adhesion to the gate electrodes 303 to 306 and the capacitor wiring 307 and the substrate 301 and preventing diffusion to the base. Alternatively, the capacitor wiring 307 may be provided. Here, a conductive layer is formed over the substrate 301 and etched with a resist mask formed using a photomask.

Note that side surfaces of the gate electrodes 303 to 306 and the capacitor wiring 307 are preferably tapered. This is because an insulating layer, a semiconductor layer, and a wiring layer are formed over the gate electrode 303 in a later step, so that no break is caused at the level difference. In order to taper the side surfaces of the gate electrodes 303 to 306 and the capacitor wiring 307, etching may be performed while retracting the resist mask.

In addition, a gate wiring (scanning line) and a capacitor wiring can be formed at the same time by the process of forming the gate electrodes 303 to 306. Note that a scanning line refers to a wiring for selecting a pixel, and a capacitor wiring refers to a wiring connected to one electrode of a storage capacitor of the pixel. However, the present invention is not limited to this, and one or both of the gate wiring and the capacitor wiring may be provided separately from the gate electrodes 303 to 306.

The first gate insulating layer 309 can be formed using any of the materials for the first gate insulating layer 309 described in Embodiment 3 as appropriate. The first gate insulating layer 309 can be formed by a CVD method, a sputtering method, or the like. The first gate insulating layer 309 may be formed using a microwave plasma CVD apparatus with a high frequency (1 GHz or more). When the first gate insulating layer 309 is formed with a high frequency using a microwave plasma CVD apparatus, the breakdown voltage between the gate electrode, the drain electrode, and the source electrode can be improved; thus, a highly reliable thin film transistor can be manufactured. Can be obtained. In addition, by forming a silicon oxide layer by a CVD method using an organosilane gas as the first gate insulating layer 309, the hydrogen content of the first gate insulating layer can be reduced. Variations in threshold voltage can be reduced. Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), and octamethylcyclotetrasiloxane. It is possible to use a silicon-containing compound such as (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ). it can.

The first semiconductor layer 311 is formed using microcrystalline silicon, microcrystalline silicon germanium, microcrystalline germanium, or the like. The first semiconductor layer 311 is formed with a thickness of 1 nm to 20 nm, preferably 3 nm to 10 nm.

The first semiconductor layer 311 is formed by glow discharge plasma by mixing a deposition gas containing silicon or germanium with hydrogen in a reaction chamber of a plasma CVD apparatus. Alternatively, a deposition gas containing silicon or germanium, hydrogen, and a rare gas such as helium, neon, or krypton are mixed and formed by glow discharge plasma. The flow rate of hydrogen is diluted 10 to 2000 times, preferably 10 to 200 times the flow rate of the deposition gas containing silicon or germanium to form microcrystalline silicon, microcrystalline silicon germanium, microcrystalline germanium, or the like. .

Typical examples of the deposition gas containing silicon or germanium include SiH ₄ , Si ₂ H ₆ , GeH ₄ , and Ge ₂ H ₆ .

Note that before the first semiconductor layer 311 is formed, a deposition gas containing silicon or germanium is introduced while evacuating the processing chamber of the CVD apparatus to remove impurity elements in the processing chamber, thereby forming the first semiconductor layer 311 later. The impurity element at the interface between the first gate insulating layer 309 and the first semiconductor layer of the thin film transistor to be formed can be reduced, and the electrical characteristics of the thin film transistor can be improved.

Next, as illustrated in FIG. 15B, the second semiconductor layer 313 and the third semiconductor layer 315 are formed over the first semiconductor layer 311. Here, the second semiconductor layer 313 and the third semiconductor layer 315 are formed under a condition in which crystals are partially grown from the first semiconductor layer 311. Note that a deposition gas containing silicon or germanium and hydrogen are mixed in a reaction chamber of a plasma CVD apparatus and formed by glow discharge plasma. At this time, the second semiconductor is formed by reducing the flow rate of hydrogen with respect to the deposition gas containing silicon or germanium, that is, by reducing the crystal growth compared to the formation conditions of the first semiconductor layer 311. As crystal growth in the layer 313 is suppressed and a film is deposited, a third semiconductor layer 315 that does not include a microcrystalline semiconductor region can be formed.

Further, in the reaction chamber of the plasma CVD apparatus, a deposition gas containing silicon or germanium, a gas containing hydrogen and nitrogen are mixed, and the second semiconductor layer 313 and the third semiconductor layer 315 are formed by glow discharge plasma. Form. At this time, the flow rate of hydrogen with respect to the deposition gas containing silicon or germanium is reduced more than the film formation conditions of the first semiconductor layer 311, and the gas in the second semiconductor layer 313 is mixed with a gas containing nitrogen. The third semiconductor layer 315 whose growth is suppressed and does not include a microcrystalline semiconductor region can be formed.

In this embodiment, in the initial deposition of the second semiconductor layer 313, the first semiconductor layer 311 is used as a seed crystal to deposit a film as a whole. Thereafter, the crystal growth is partially suppressed, and a conical microcrystalline semiconductor region grows (mid-deposition). Further, crystal growth of the conical microcrystalline semiconductor region is suppressed, and a third semiconductor layer 315 (late deposition stage) not including the microcrystalline semiconductor region is formed. Thus, the first semiconductor layer described in Embodiment 3 corresponds to the first semiconductor layer 311 described in this embodiment. In addition, the second semiconductor layer described in Embodiment 3 includes a film formed in the initial deposition of the second semiconductor layer 313 described in this embodiment and a cone formed in the middle of the deposition of the second semiconductor layer 313. This corresponds to a microcrystalline semiconductor region and an amorphous semiconductor region. In addition, the third semiconductor layer described in Embodiment 3 corresponds to the third semiconductor layer 315 formed in the later stage of deposition described in this embodiment.

Next, as illustrated in FIG. 15C, a semiconductor layer to which an impurity imparting one conductivity type is added (hereinafter referred to as an impurity semiconductor layer 317) is formed over the third semiconductor layer 315. A conductive layer 319 is formed over the impurity semiconductor layer 317.

The impurity semiconductor layer 317 is formed by glow discharge plasma by mixing a deposition gas containing silicon or germanium, hydrogen, and phosphine (hydrogen dilution or silane dilution) in a reaction chamber of a plasma CVD apparatus. A deposition gas containing silicon or germanium is diluted with hydrogen, and amorphous silicon to which phosphorus is added, microcrystalline silicon to which phosphorus is added, amorphous silicon germanium to which phosphorus is added, and microcrystalline silicon germanium to which phosphorus is added Amorphous germanium to which phosphorus is added is formed as microcrystalline germanium to which phosphorus is added.

For the conductive layer 319, the material and stacked structure of the wirings 346 to 353 described in Embodiment 3 can be used as appropriate. The conductive layer 319 is formed by a CVD method, a sputtering method, or a vacuum evaporation method. Alternatively, the conductive layer 319 may be formed by discharging a conductive nanopaste of silver, gold, copper, or the like using a screen printing method, an inkjet method, or the like, and baking.

Next, as illustrated in FIG. 16A, second resist masks 321 to 324 are formed over the conductive layer 319.

The resist masks 321 to 323 have regions having different thicknesses. Such a resist mask can be formed using a multi-tone mask. It is preferable to use a multi-tone mask because the number of photomasks to be used is reduced and the number of manufacturing steps is reduced. In this embodiment mode, a multi-tone mask can be used in a step of forming a pattern of a semiconductor layer and a step of separating a source region and a drain region.

A multi-tone mask is a mask that can be exposed with multiple levels of light, and typically, exposure is performed with three levels of light: an exposed area, a half-exposed area, and an unexposed area. By using a multi-tone mask, a resist mask having a plurality of thicknesses (typically two types) can be formed by one exposure and development process. Therefore, the number of photomasks can be reduced by using a multi-tone mask.

19A-1 and 19B-1 are cross-sectional views of typical multi-tone masks. FIG. 19A-1 shows a gray tone mask 490, and FIG. 19B-1 shows a halftone mask 495.

A gray-tone mask 490 illustrated in FIG. 19A-1 includes a light-blocking portion 492 formed using a light-blocking film over a light-transmitting substrate 491, and a diffraction grating portion 493 provided using a pattern of the light-blocking film. ing.

The diffraction grating portion 493 controls the light transmittance by having slits, dots, meshes, or the like provided at intervals less than the resolution limit of light used for exposure. Note that the slits, dots, or mesh provided in the diffraction grating portion 493 may be periodic or non-periodic.

As the substrate 491 having a light-transmitting property, quartz or the like can be used. The light-shielding film constituting the light-shielding portion 492 and the diffraction grating portion 493 may be formed using metal, and is preferably provided with chromium, chromium oxide, or the like.

When light for exposure is applied to the gray tone mask 490, as shown in FIG. 19A-2, the light transmittance in the region overlapping with the light shielding portion 492 becomes 0%, and the light shielding portion 492 or the diffraction grating portion. The transmittance in a region where the 493 is not provided is 100%. Further, the light transmittance in the diffraction grating portion 493 is approximately in the range of 10 to 70%, and can be adjusted by the interval of slits, dots or meshes of the diffraction grating.

A halftone mask 495 illustrated in FIG. 19B-1 includes a semi-transparent portion 497 formed using a semi-transparent film over a light-transmitting substrate 496 and a light-shielding portion 498 formed using a light-shielding film. Has been.

The semi-translucent portion 497 can be formed using a film of MoSiN, MoSi, MoSiO, MoSiON, CrSi or the like. The light shielding portion 188 may be formed using the same metal as the light shielding film of the gray tone mask, and is preferably provided with chromium, chromium oxide, or the like.

When light for exposure is applied to the halftone mask 495, the light transmittance in the region overlapping the light shielding portion 498 is 0% as shown in FIG. The light transmittance in the region where the portion 497 is not provided is 100%. The translucency in the semi-translucent portion 497 is generally in the range of 10 to 70%, and can be adjusted by the type of material to be formed, the film thickness to be formed, or the like.

By performing exposure and development using a multi-tone mask, a resist mask having regions with different thicknesses can be formed.

Next, the first semiconductor layer 311, the second semiconductor layer 313, the third semiconductor layer 315, the impurity semiconductor layer 317, and the conductive layer 319 are etched using the resist masks 321 to 324. Through this step, the first semiconductor layer 311, the second semiconductor layer 313, the third semiconductor layer 315, the impurity semiconductor layer 317, and the conductive layer 319 are separated for each element, and the first semiconductor layers 333 a to 336 a, Second semiconductor layers 333b to 336b, third semiconductor layers 333c to 336c, impurity semiconductor layers 329 to 332, and conductive layers 325 to 328 are formed (see FIG. 16B).

Next, the resist masks 321 to 324 are retracted to form separated resist masks 337 to 344 and a retracted resist mask 345. For the receding of the resist mask, ashing using oxygen plasma may be used. Here, the resist masks 337 to 344 can be formed by ashing the resist masks 321 to 323 so as to be separated on the gate electrode (see FIG. 16C).

Next, the conductive layers 325 to 328 are etched using the resist masks 337 to 345 to form wirings 346 to 353 (see FIG. 17A). Etching of the conductive layers 325 to 328 is preferably performed by wet etching. The conductive layers 325 to 328 are isotropically etched by wet etching. As a result, the wirings 346 to 353 are retracted inward from the resist masks 337 to 345. The wirings 346 to 352 function not only as source and drain electrodes but also as signal lines. However, the present invention is not limited to this, and the signal line, the source electrode, and the drain electrode may be provided separately.

Next, part of the impurity semiconductor layers 329 to 332 is etched using the resist masks 337 to 345. Here, dry etching is used. Up to this step, impurity semiconductor layers 355 to 362 functioning as buffer layers are formed (see FIG. 17A). Thereafter, the resist masks 337 to 345 are removed.

Next, the third semiconductor layers 333c to 336c are etched to expose the second semiconductor layers 333b to 336b and to form a pair of third semiconductor layers 363a to 365a, 363b to 365b, and a semiconductor layer 366. To do. Here, conditions for selectively etching the amorphous semiconductor layers which are the third semiconductor layers 333c to 336c by wet etching or dry etching to expose the second semiconductor layers 333b to 336b which are microcrystalline semiconductors are used. Is used as appropriate. Typically, etchants for wet etching include hydrazine, dilute hydrofluoric acid (DHF), and the like. As the dry etching, the amorphous semiconductor layer can be selectively etched using hydrogen. After that, the resist masks 337 to 346 are removed, and the surfaces of the second semiconductor layers 333b to 3336b are oxidized or nitrided to form the insulating layer 348a shown in FIG. 9, and the insulating layers 348b to 348e are formed. The Note that the cross-sectional view of the pixel portion 395 in FIG. 17B corresponds to a cross-sectional view along AB in the plan view of the pixel portion shown in FIG.

Note that here, after etching the conductive layers 325 to 328, the third semiconductor layers 333 c to 336 c are etched to expose the second semiconductor layers 333 b to 336 b, but the second conductive layers 325 to 328 are etched. Then, after forming the wirings 346 to 353, the resist masks 337 to 345 are removed, and part of the impurity semiconductor layers 329 to 332 and the third semiconductor layers 333c to 336c are dry-etched, and further the second semiconductor layer Plasma treatment for oxidizing or nitriding the surfaces of 333b to 336b may be performed. In this case, since the impurity semiconductor layers 329 to 332 and the third semiconductor layers 333c to 336c are etched using the wirings 346 to 353 as a mask, the side surfaces of the wirings 346 to 353 and the impurity semiconductor functioning as a source region and a drain region are etched. The side surfaces of the layers 355 to 362 are matched.

As described above, after the second semiconductor layers 333b to 336b having conical unevenness are exposed, an insulating layer is formed on the surface of the second semiconductor layers 333b to 336b by plasma treatment, whereby the source region and the drain are formed. The distance of the leak path between the regions can be increased, and an insulating layer is formed. For this reason, the off current of the TFT can be reduced.

Through the above process, a thin film transistor can be manufactured.

Next, a second gate insulating layer 371 is formed. Next, on the first gate insulating layer 309, the back gate electrode 373 is formed in a region where the dual gate TFT 300 a of the logic circuit portion 391, the dual gate TFT 300 c of the switch portion 393, and the capacitor element of the pixel portion 395 are formed. To 374 and a wiring 375 are formed (see FIG. 17B).

The second gate insulating layer 371 can be formed in a manner similar to that of the first gate insulating layer 309.

The back gate electrodes 373 to 374 and the wiring 375 can be formed using the materials and manufacturing methods shown by the wirings 346 to 353 as appropriate.

Next, as illustrated in FIG. 18A, an insulating layer 372 is formed. The insulating layer 372 can be formed using the insulating layer 381 described in Embodiment 3 as appropriate.

Next, part of the insulating layer 372 and the second gate insulating layer 371 are etched to connect the dual gate TFT 300a and the TFT 300b in the logic circuit portion 391, the wiring 347, the gate electrode 303 of the dual gate TFT 300a, An opening that exposes the wiring 352 of the pixel portion 395 is formed. This opening can be formed by a photolithography method. After that, the wiring 347 connecting the dual-gate TFT 300a and the TFT 300b and the wiring 384 connecting the gate electrode 303 and the wiring 384 (the wiring 347 and the gate electrode 303 are formed over the insulating layer 372 so as to be connected through the opening. 8A and 18B), a pixel electrode 383 connected to the wiring 352 of the pixel portion 395 is formed (see FIG. 16B). Note that the cross-sectional view of the pixel portion 395 in FIG. 18A corresponds to a cross-sectional view taken along a line AB in the plan view of the pixel portion illustrated in FIG.

The wiring 384 and the pixel electrode 383 can be formed by forming a thin film using the material described in Embodiment 3 by a sputtering method and then etching the thin film using a resist mask formed by a photolithography process. Alternatively, the conductive composition containing a light-transmitting conductive polymer can be applied or printed, and then fired. Note that the cross-sectional view of the pixel portion 395 in FIG. 17A corresponds to a cross-sectional view along AB in the plan view of the pixel portion shown in FIG.

By connecting the gate electrode 303 to the wiring 347 connecting the dual gate TFT 300a and the TFT 300b of the logic circuit portion 391 with the wiring 384, an EDMOS circuit including the TFT 300a and the TFT 300b can be formed.

Through the above steps, a display device as shown in FIG. 8 can be manufactured.

Here, a method for manufacturing the display device illustrated in FIG. 10 (“method 2”) is described with reference to FIGS.

As shown in FIG. 21A, gate electrodes 303 to 306 and a capacitor wiring 307 are formed over a substrate 301. Next, a first gate insulating layer 309 and a first semiconductor layer 411 to which an impurity element imparting one conductivity type is added are formed so as to cover the gate electrodes 303 to 306 and the capacitor wiring 307.

As the substrate 301, the substrate 301 described in Embodiment 3 can be used as appropriate.

The gate electrodes 303 to 306, the capacitor wiring 307, and the first gate insulating layer 309 can be formed in the same manner as in the “Method 1”.

The first semiconductor layer 411 to which an impurity element imparting one conductivity type is added is formed by adding an impurity element serving as a donor or an impurity element serving as an acceptor to the first semiconductor layer 311. The impurity element that serves as a donor is an element belonging to Group 15 of the periodic table, and typically includes phosphorus, arsenic, antimony, and the like. An impurity element that serves as an acceptor is an element belonging to Group 13 of the periodic table, and typically includes boron and the like. Here, a method for manufacturing a microcrystalline semiconductor layer to which phosphorus that is an impurity element serving as a donor is added as the first semiconductor layer 411 to which an impurity element imparting one conductivity type is added is described.

A gas containing an impurity element imparting one conductivity type is mixed with a source gas of the first semiconductor layer 411 to which an impurity element imparting one conductivity type is added, so that a semiconductor layer is formed. Typically, a deposition gas containing silicon or germanium, hydrogen, and phosphine are mixed in a reaction chamber of a plasma CVD apparatus and formed by glow discharge plasma. Alternatively, a deposition gas containing silicon or germanium, hydrogen, phosphine, and a rare gas such as helium, neon, or krypton are mixed and formed by glow discharge plasma. As the first semiconductor layer 411 to which an impurity element imparting one conductivity type is added, microcrystalline silicon containing phosphorus, microcrystalline silicon germanium containing phosphorus, microcrystalline germanium containing phosphorus, or the like is formed.

Alternatively, after the surface of the first gate insulating layer 309 is exposed to a gas containing an impurity element imparting one conductivity type and then a microcrystalline semiconductor layer is formed, the impurity element imparting one conductivity type is finely captured. A crystalline semiconductor layer is formed. Typically, phosphorus is adsorbed on the surface of the first gate insulating layer 309 by exposing the surface of the first gate insulating layer 309 to phosphine. After that, a microcrystalline semiconductor layer is formed by a method similar to that of the first semiconductor layer 311 described in “Method 1”, so that microcrystalline silicon containing phosphorus, microcrystalline silicon germanium containing phosphorus, and microcrystalline silicon containing phosphorus Crystal germanium or the like can be formed.

Alternatively, after the microcrystalline semiconductor layer is formed over the first gate insulating layer 309, plasma is generated in a gas atmosphere containing an impurity element imparting one conductivity type, so that the one conductivity type is imparted to the microcrystalline semiconductor layer. By exposing to plasma containing an impurity element, the first semiconductor layer 411 to which an impurity element imparting one conductivity type is added can be formed. Typically, after a microcrystalline semiconductor layer is formed by a method similar to that of the first semiconductor layer 311 described in the above “Method 1”, phosphorus plasma is exposed to the microcrystalline semiconductor layer, whereby microcrystalline silicon containing phosphorus is formed. Microcrystalline silicon germanium containing phosphorus, microcrystalline germanium containing phosphorus, or the like can be formed.

Next, after forming the second semiconductor layer 413, the third semiconductor layer 415, and the impurity semiconductor layer 417 over the first semiconductor layer 411, resist masks 419 and 420 are formed over the impurity semiconductor layer 417. (See FIG. 21B).

Here, the second semiconductor layer 413, the third semiconductor layer 415, and the impurity semiconductor are formed in the same manner as the second semiconductor layer 313, the third semiconductor layer 315, and the impurity semiconductor layer 317 described in “Method 1”. Layer 417 is formed.

Note that the impurity semiconductor layer 417 is thinned by an etching process of the fourth semiconductor layer 431, the fifth semiconductor layer 433, the sixth semiconductor layer 435, and the impurity semiconductor layer 437, and thus the thickness of the impurity semiconductor layer 417 is reduced. It is preferable to increase the thickness, and typically the thickness is about 30 to 150 nm.

The resist masks 419 and 420 are formed in regions to be the TFT 401a of the logic circuit portion 391 and the TFT 401c of the switch portion 393 later.

Next, the first semiconductor layer 411, the second semiconductor layer 413, the third semiconductor layer 415, and the impurity semiconductor layer 417 are etched using the resist masks 419 and 420. Through this step, the first semiconductor layer 411, the second semiconductor layer 413, the third semiconductor layer 415, and the impurity semiconductor layer 417 are separated for each element, and the first semiconductor layers 427a and 428a and the second semiconductor layer are separated. Layers 427b and 428b, third semiconductor layers 425 and 426, and impurity semiconductor layers 423 and 424 are formed. After that, the resist masks 419 and 420 are removed (see FIG. 21C).

Next, as illustrated in FIG. 22A, a fourth semiconductor layer 431, a fifth semiconductor layer 433, a sixth semiconductor layer 435, and an impurity semiconductor layer 437 are formed, and a resist is formed over the impurity semiconductor layer 437. Masks 439 and 440 are formed.

The fourth semiconductor layer 431, the fifth semiconductor layer 433, the sixth semiconductor layer 435, and the impurity semiconductor layer 437 are the first semiconductor layer 311 and the second semiconductor layer 313 described in “Method 1”, respectively. The third semiconductor layer 315 and the impurity semiconductor layer 317 can be formed in a similar manner.

The resist masks 439 and 440 are formed in regions to be the TFT 401b of the logic circuit portion 391 and the TFT 401d of the pixel portion 395 later.

Next, the fourth semiconductor layer 431, the fifth semiconductor layer 433, the sixth semiconductor layer 435, and the impurity semiconductor layer 437 are etched using the resist masks 439 and 440. Through this step, the fourth semiconductor layer 431, the fifth semiconductor layer 433, the sixth semiconductor layer 435, and the impurity semiconductor layer 437 are separated for each element, and the fourth semiconductor layers 448a to 450a and the fifth semiconductor are separated. Layers 449b to 450b, sixth semiconductor layers 448c to 450c, and impurity semiconductor layers 444, 446, and 447 are formed. Note that in this etching, the impurity semiconductor layers 423 and 424 are also etched, so that impurity semiconductor layers 443 and 445 with reduced thickness are formed. This is because the fourth semiconductor layer 431, the fifth semiconductor layer 433, the sixth semiconductor layer 435, and the impurity semiconductor layer 437 are sufficiently etched to leave no etching residue. After etching is over, overetching is performed. As a result, the impurity semiconductor layers 423 and 424 are also etched in the overetching (see FIG. 22B). Thereafter, the resist masks 439 and 440 are removed.

Next, as illustrated in FIG. 22C, a conductive layer 319 is formed.

Next, a resist mask is formed over the conductive layer 319. Next, the conductive layer 319 is etched using the resist mask in the same manner as in the “Method 1”, so that the wirings 451 to 458 are formed.

Next, part of the impurity semiconductor layers 443 to 447 is etched using the resist mask in the same manner as in the “Method 1”, so that impurity semiconductor layers 459 to 467 are formed. Next, the third semiconductor layers 425, 426, 448c, and 449c are etched to expose the second semiconductor layers 427b, 428b, 454b to 456b, and the pair of third semiconductor layers 469a to 472a, 469b to A third semiconductor layer 473 is formed 472b. After that, the resist mask is removed, and plasma treatment for oxidizing or nitriding the surfaces of the second semiconductor layers 427b, 428b, 454b to 456b is performed.

Next, in the same manner as in the “method 1”, the second gate insulating layer 475 and the insulating layer 476 are formed. The second gate insulating layer 475 can be formed in a manner similar to that of the second gate insulating layer 379. The insulating layer 476 can be formed in a manner similar to that of the insulating layer 381 (see FIG. 23A).

Through the above process, a thin film transistor can be manufactured.

Next, the second gate insulating layer 475 and part of the insulating layer 476 are etched to form openings that expose the wiring 452 of the TFT 401a of the logic circuit portion 391, the gate electrode 303, and the wiring 457 of the pixel portion 395. . This opening can be formed by a photolithography method. After that, a pixel electrode connected to the wiring 384 connecting the wiring 452 and the gate electrode 303 of the TFT 401a of the logic circuit portion 391 and the wiring 457 of the pixel portion 395 over the insulating layer 476 so as to be connected through the opening. 383 is formed (see FIG. 11A for connection of the wiring 384 and the gate electrode 303; see FIG. 23B).

By connecting the wiring 452 of the TFT 401a of the logic circuit portion 391 and the gate electrode 303 with the wiring 384, an EDMOS circuit including the TFT 401a and the TFT 401b can be formed.

(Embodiment 5)
In this embodiment, a protection circuit provided in a display device which is one embodiment of the present invention will be described with reference to drawings. An example of a specific circuit configuration of the protection circuit used in the protection circuits 134 to 136 in FIG. 2 of Embodiment 1 will be described with reference to FIG. In the following description, only the case where an n-type transistor is provided will be described, but the present invention is not limited to this.

A protection circuit illustrated in FIG. 24A includes protection diodes 501 to 504 each using a plurality of thin film transistors. The protective diode 501 has an n-type thin film transistor 501a and an n-type thin film transistor 501b connected in series. One of the source electrode and the drain electrode of the n-type thin film transistor 501a is connected to the gate electrodes of the n-type thin film transistor 501a and the n-type thin film transistor 501b and is kept at the potential V _ss . The other of the source electrode and the drain electrode of the n-type thin film transistor 501a is connected to one of the source electrode and the drain electrode of the n-type thin film transistor 501b. The other of the source electrode and the drain electrode of the n-type thin film transistor 501 b is connected to the protection diode 502. Similarly to the protection diode 501, the other protection diodes 502 to 504 each have a plurality of thin film transistors connected in series, and one end of each of the plurality of thin film transistors connected in series is connected to the gate electrodes of the plurality of thin film transistors. It is connected.

Note that in the present invention, the number and polarity of thin film transistors included in each of the protection diodes 501 to 504 are not limited to the structure illustrated in FIG. For example, the protection diode 501 may be configured by three thin film transistors connected in series.

The protective diodes 501 to 504 are sequentially connected in series, and the protective diode 502 and the protective diode 503 are connected to the wiring 505. Note that the wiring 505 is electrically connected to a semiconductor element to be protected. Note that the wiring connected to the wiring 505 is not limited to the wiring between the protection diode 502 and the protection diode 503. That is, the wiring 505 may be connected between the protection diode 501 and the protection diode 502, or may be connected between the protection diode 503 and the protection diode 504.

One end of the protection diode 504 is kept at the power supply potential V _dd . In addition, each of the protection diodes 501 to 504 is connected so that a reverse bias voltage is applied.

Note that in the protection circuit illustrated in FIG. 24A, the protection diodes 501 and 502 can be replaced with the protection diode 506 and the protection diodes 503 and 504 can be replaced with the protection diode 507 as illustrated in FIG. is there.

A protection circuit illustrated in FIG. 24C includes a protection diode 510, a protection diode 511, a capacitor 512, a capacitor 513, and a resistor 514. Resistance element 514 is a two-terminal resistor, its one end is potential _{V in} is supplied from the wiring 515, the other end potential _{V ss} is supplied. Resistance element 514 is provided to the potential of the wiring 515 when the potential V _in is not supplied to the V _ss, the resistance value is set to be sufficiently larger than the wiring resistance of the wiring 515 . For the protection diode 510 and the protection diode 511, diode-connected n-type thin film transistors are used.

Note that the protective diode illustrated in FIG. 24C may be formed by further connecting a plurality of thin film transistors in series.

In the protection circuit illustrated in FIG. 24D, the protection diode 510 and the protection diode 511 are each replaced with two n-type thin film transistors.

Note that in the protection circuits illustrated in FIGS. 24C and 24D, diode-connected n-type thin film transistors are used as protection diodes; however, this embodiment is not limited to this structure.

In addition, the protection circuit illustrated in FIG. 24E includes protection diodes 520 to 527 and a resistance element 528. The resistance element 528 is connected in series between the wiring 529A and the wiring 529B. Each of the protection diodes 520 to 523 uses a diode-connected n-type thin film transistor, and each of the protection diodes 520 to 527 uses a diode-connected n-type thin film transistor.

Protection diode 520 and the protection diode 521 are connected in series, one end of which is kept at the potential _{V ss,} the other end is connected to the wiring 529A potential _{V in.} Protection diode 523 and the protection diode 522 are connected in series, one end of which is kept at the potential _{V dd,} and the other end thereof is connected to the wiring 529A potential _{V in.} The protective diode 524 and the protective diode 525 are connected in series, one end is held at the potential V _ss and the other end is connected to the wiring 529B having the potential V _out . The protective diode 526 and the protective diode 527 are connected in series, one end is held at the potential V _dd and the other end is connected to the wiring 529B having the potential V _out .

In addition, the protection circuit illustrated in FIG. 24F includes a resistance element 530, a resistance element 531, and a protection diode 532. In FIG. 24F, a diode-connected n-type thin film transistor is used as the protective diode 532; however, this embodiment is not limited to this structure. A plurality of diode-connected thin film transistors may be used. The resistance element 530, the resistance element 531, and the protection diode 532 are connected in series to the wiring 533.

The resistor 530 and the resistor 531 can alleviate rapid fluctuations in the potential of the wiring 533 and prevent deterioration or destruction of the semiconductor element. In addition, the protection diode 532 can prevent a reverse bias current from flowing through the wiring 533 due to potential fluctuation.

Note that in the case where only the resistance element is connected in series to the wiring, a rapid change in the potential of the wiring can be reduced, and the semiconductor element can be prevented from being deteriorated or destroyed. Further, when only the protective diode is connected in series to the wiring, it is possible to prevent a reverse current from flowing through the wiring due to potential fluctuation.

Here, consider a case where the protection circuit shown in FIG. 24 operates. At this time, in the source and drain electrodes of the protection diodes 501, 502, 506, 511, 520, 521, 524 and 525, the side held at the potential V _ss is the drain electrode. The other is a source electrode. Of the source and drain electrodes of the protective diodes 503, 504, 507, 510, 522, 523, 526, and 527, the side held at the potential _Vdd is used as the source electrode, and the other is used as the drain electrode. Further, the threshold voltage of the thin film transistor constituting the protective diode is denoted as _Vth .

The protective diode 501,502,506,511,520,521,524,525 takes a reverse bias voltage when the potential _{V in} is higher than the potential _{V ss,} hardly current flows. On the other hand, the protection diode 503,504,507,510,522,523,526,527, the potential _{V in} it takes a reverse bias voltage when lower than the potential _{V dd,} current does not easily flow.

Here, the operation of the protection circuit potential V _out is generally provided so as to be between the potential V _ss and the potential V _dd.

First, consider the case where the potential _{V in} is higher than the potential _{V dd.} If the potential _{V in} is higher than the potential _{V dd,} the gate electrode and the source electrode of the protection diode 503,504,507,510,522,523,526,527 potential difference _V gs ₌ V _in -V dd _{of> V th} of Sometimes the n-type thin film transistor is turned on. Here, it is assumed the case where V _in is abnormally high, the n-channel thin film transistors are turned on. At this time, the n-type thin film transistors included in the protection diodes 501, 502, 506, 511, 520, 521, 524, and 525 are turned off. Then, the potentials of the wirings 505, 508, 515, 529A, and 529B become V _dd through the protective diodes 503, 504, 507, 510, 522, 523, 526, and 527. Therefore, even when the potential _{V in} is unusually higher than the potential _{V dd} due to noise or the like, wiring 505,508,515,529A, the potential of 529B does not become higher than the potential _{V dd.}

On the other hand, when the potential _{V in} is lower than the potential _{V ss} is the potential difference _V gs _{= V} ss -V between the gate electrode and the source electrode of the protection diode 501,502,506,511,520,521,524,525 _{When in} > _Vth , the n-type thin film transistor is turned on. Here, it is assumed the case where V _in is unusually low, n-channel thin film transistors are turned on. At this time, the n-type thin film transistors included in the protection diodes 503, 504, 507, 510, 522, 523, 526, and 527 are turned off. Then, the potentials of the wirings 505, 508, 515, 529A, and 529B become V _ss through the protective diodes 501, 502, 506, 511, 520, 521, 524, and 525. Therefore, due to noise or the like, even when the potential _{V in} is unusually lower than the potential _{V ss,} wiring 505,508,515,529A, the potential of 529B does not become lower than the potential _{V ss.} Further, a capacitor 512 and 513 reduce pulsed noise of the input potential V _in, to relieve a steep change in the potential due to noise.

The potential _{V in} is _the case between V ss _{-V th} of _V dd _{+ V th} is, n-type thin film transistor in which all of the protection diode having turns off, the potential _{V in} is output as the potential _{V out.}

By disposing the protective circuit as described above, the potentials of the wirings 505, 508, 515, 529 A, and 529 B are generally maintained between the potential V _ss and the potential V _dd . Accordingly, it is possible to prevent the wirings 505, 508, 515, 529A, and 529B from having a potential greatly deviating from this range. That is, the wirings 505, 508, 515, 529 A, and 529 B are prevented from becoming an abnormally high potential or an abnormally low potential, the subsequent circuit of the protection circuit is prevented from being destroyed or deteriorated, and the subsequent circuit Can be protected.

Further, as shown in FIG. 24C, by providing a protective circuit having a resistance element 514 at the input terminal, the potentials of all wirings to which signals are supplied are constant (here) Then, the potential V _ss ). In other words, when a signal is not input, it also has a function as a short ring that can short-circuit the wires. Therefore, electrostatic breakdown due to a potential difference generated between the wirings can be prevented. In addition, since the resistance value of the resistance element 514 is sufficiently larger than the wiring resistance, it is possible to prevent a signal applied to the wiring from dropping to the potential V _ss when a signal is input.

Here, as an example, a case where an n-type thin film transistor having a threshold voltage V _th = 0 is used for the protection diode 510 and the protection diode 511 in FIG.

First, when V _in > V _dd , the protection diode 510 is turned on because V _gs = V _in −V _dd > 0. The protection diode 511 is turned off. Accordingly, the potential of the wiring 515 is V _dd and V _out = V _dd .

On the other hand, when V _in <V _ss , the protection diode 510 is turned off. The protection diode 511 is turned on because V _gs = V _ss −V _in > 0. Accordingly, the potential of the wiring 515 is V _ss and V _out = V _ss .

As described above, even when V _in <V _ss or V _dd <V _in , the operation can be performed in the range of V _ss <V _out <V _dd . Therefore, even if V _in is excessive or small, it is possible to prevent V _{out from} becoming excessive or excessive. Thus, for example, due to noise or the like, even when the potential V _in is lower than the potential V _ss, the potential of the wiring 515 does not become much lower than the potential V _ss. Further, the capacitor 512 and the capacitor 513 have a function of dampening pulsed noise included _in the input potential Vin and reducing a steep change in potential.

By arranging the protection circuit as described above, the potential of the wiring 515 is generally kept between the potential V _ss and the potential V _dd . Therefore, the wiring 515 can be prevented from having a potential greatly deviated from this range, and a circuit subsequent to the protection circuit (a circuit in which the input portion is electrically connected to _Vout ) is protected from destruction or deterioration. can do. Further, by providing a protection circuit at the input terminal, the potentials of all wirings to which signals are _supplied can be kept constant (here, the potential V _ss ) when no signal is input. That is, when a signal is not input, it also has a function as a short ring that can short-circuit the wirings. Therefore, electrostatic breakdown due to a potential difference generated between the wirings can be prevented. In addition, since the resistance value of the resistance element 514 is sufficiently large, a decrease in the potential of a signal supplied to the wiring 515 can be prevented when a signal is input.

Note that the protection circuit used in the present invention is not limited to the configuration shown in FIG. 24, and the design can be changed as appropriate as long as the circuit configuration has the same function.

In addition, as a protection diode included in the protection circuit of the present invention, a diode-connected thin film transistor can be used. By using the thin film transistor of the present invention for the protection circuit, the area occupied by the protection circuit can be reduced, and the display device can be narrowed in frame, downsized, and improved in performance.

(Embodiment 6)
In this embodiment mode, a terminal portion of the display device of the present invention will be described with reference to FIG.

25A and 25B respectively show a cross-sectional view and a top view of the gate wiring terminal portion. FIG. 25A corresponds to a cross-sectional view taken along line X1-X2 in FIG. In FIG. 25A, a transparent conductive layer 545 over a protective insulating layer 544 formed by stacking is a connection terminal electrode that functions as an input terminal. In FIG. 25A, in the terminal portion, the first terminal 540 formed using the same material as the gate wiring and the connection electrode 543 formed using the same material as the source wiring are provided with the gate insulating layer 542 interposed therebetween. Overlap, they are connected (at least electrically) via a transparent conductive layer 545. In addition, a semiconductor layer 546 (an intrinsic semiconductor layer and a semiconductor layer including one conductivity type impurity element) is provided between the gate insulating layer 542 and the connection electrode 543.

25C and 25D respectively show a cross-sectional view and a top view of the source wiring terminal portion. FIG. 25C corresponds to a cross-sectional view taken along line Y1-Y2 in FIG. In FIG. 25C, the transparent conductive layer 545 over the protective insulating layer 544 formed by stacking is a terminal electrode that functions as an input terminal. In FIG. 25C, in the terminal portion, an electrode 547 formed of the same material as the gate wiring is formed below the second terminal 541 that is electrically connected (at least electrically) to the source wiring. Overlap with the insulating layer 542 interposed therebetween. The electrode 547 is not directly or electrically connected to the second terminal 541. If the electrode 547 is set to a potential different from that of the second terminal 541, for example, floating, GND, 0V, etc., it is used for noise countermeasures. Capacitance or capacitance for static electricity can be formed. The second terminal 541 is connected (at least electrically) to the transparent conductive layer 545. In addition, a semiconductor layer 546 (an intrinsic semiconductor layer and a semiconductor layer including an impurity element of one conductivity type) is provided between the gate insulating layer 542 and the second terminal 541.

A plurality of gate wirings, source wirings, and capacitor wirings are provided depending on the pixel density. In the terminal portion, a plurality of first terminals having the same potential as the gate wiring, second terminals having the same potential as the source wiring, third terminals having the same potential as the capacitor wiring, and the like are arranged. Each terminal may be provided in an arbitrary number, and may be determined appropriately by the practitioner.

The terminal portion and the FPC terminal portion described in this embodiment are connected through an anisotropic conductive paste or the like. As a result, external signals and power can be supplied.

Note that FIG. 25 shows a terminal portion when a halftone mask is used, but the present invention is not limited to this as described in the above embodiment. FIG. 26 shows a diagram of a terminal portion when manufactured without using a halftone mask. The terminal portion illustrated in FIG. 26 has a structure without a semiconductor layer.

FIGS. 26A and 26B are a cross-sectional view and a top view, respectively, of a gate wiring terminal portion when manufactured without using a halftone mask. FIG. 26A corresponds to a cross-sectional view taken along line X3-X4 in FIG. In FIG. 26A, a transparent conductive layer 545 over the protective insulating layer 544 is a terminal electrode that functions as an input terminal. In FIG. 26A, in the terminal portion, the first terminal 540 formed of the same material as the gate wiring and the connection electrode 543 formed of the same material as the source wiring are connected to each other with the gate insulating layer 542 interposed therebetween. Overlap, they are connected (at least electrically) via a transparent conductive layer 545. In addition, a connection electrode 543 is provided in contact with the gate insulating layer 542, and FIGS. 26A and 26B have a structure in which a semiconductor layer is not provided.

26C and 26D respectively show a cross-sectional view and a top view of the source wiring terminal portion when manufactured without using a halftone mask. FIG. 26C corresponds to a cross-sectional view taken along line Y3-Y4 in FIG. In FIG. 26C, the transparent conductive layer 545 over the protective insulating layer 544 is a terminal electrode that functions as an input terminal. In FIG. 26C, an electrode 547 formed of the same material as the gate wiring is formed in the terminal portion below the second terminal 541 connected (at least electrically) to the source wiring. Overlap through. The electrode 547 is not connected to the second terminal 541. If the electrode 547 is set to a potential different from that of the second terminal 541, for example, floating, GND, 0V, etc., the capacitor for noise countermeasure or the countermeasure for static electricity Capacity can be formed. Further, the second terminal 541 is connected to the transparent conductive layer 545. In addition, a second terminal 541 is provided in contact with the gate insulating layer 542, and FIGS. 26C and 26D have a structure in which a semiconductor layer is not provided. That is, the terminal portion illustrated in FIG. 26 has a structure without a semiconductor layer.

(Embodiment 7)
Next, one mode of a display panel or a light-emitting panel mounted on the liquid crystal display device and the light-emitting display device described in the above embodiment is described with reference to drawings (cross-sectional views).

The appearance of a liquid crystal display device and a light-emitting device which are one embodiment of the present invention is described with reference to FIGS. FIG. 27A illustrates a panel in which a thin film transistor 610 and a liquid crystal element 613 each including a microcrystalline semiconductor layer formed over a first substrate 601 are sealed with a sealant 605 between the second substrate 606 and the thin film transistor. A top view is shown. FIG. 27B corresponds to a cross-sectional view taken along a line KL in FIG.

The liquid crystal display device has a liquid crystal element in each pixel. A liquid crystal element is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal, and includes a pair of electrodes and liquid crystal. Note that the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Liquid crystal elements and their driving modes include nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal (also referred to as lyotropic liquid crystal), low molecular liquid crystal, polymer liquid crystal, ferroelectric liquid crystal, Antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) ) Mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) ment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid A Crystal mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a guest host mode, and the like can be used. However, the present invention is not limited to this, and various liquid crystal elements can be used.

The liquid crystal layer may be formed using a liquid crystal exhibiting a blue phase without using an alignment film. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, it is applied to the liquid crystal layer 174 using a liquid crystal composition in which 5% by weight or more of a chiral agent is mixed. A liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent has a response speed as short as 10 μs to 100 μs, is optically isotropic, and therefore does not require alignment treatment and has a small viewing angle dependency.

A sealant 605 is provided so as to surround the pixel portion 602 and the scan line driver circuit 604 provided over the first substrate 601. A second substrate 606 is provided over the pixel portion 602 and the scan line driver circuit 604. Therefore, the pixel portion 602 and the scan line driver circuit 604 are sealed together with the liquid crystal layer 608 by the first substrate 601, the sealant 605, and the second substrate 606. In addition, a signal line driver circuit 603 is also provided in a region surrounded by the sealant 605 on the first substrate 601. Note that the signal line driver circuit 603 may be provided using a thin film transistor having a polycrystalline semiconductor layer over a separately prepared substrate. Note that a signal line driver circuit may be formed using a thin film transistor including a single crystal semiconductor and then bonded.

The pixel portion 602 provided over the first substrate 601 includes a plurality of thin film transistors. FIG. 27B illustrates a thin film transistor 610 included in the pixel portion 602. The scan line driver circuit 604 also includes a plurality of thin film transistors. FIG. 27B illustrates the thin film transistor 609 included in the signal line driver circuit 603. The thin film transistor 610 corresponds to a thin film transistor using a microcrystalline semiconductor layer.

In addition, the pixel electrode 612 included in the liquid crystal element 613 is electrically connected to the thin film transistor 610 through a wiring 618. Further, the wiring 618 is electrically connected to the lead wiring 614. The counter electrode 617 of the liquid crystal element 613 is provided over the second substrate 606. A portion where the pixel electrode 612, the counter electrode 617, and the liquid crystal layer 608 overlap corresponds to the liquid crystal element 613.

Note that as a material of the first substrate 601 and the second substrate 606, glass, metal (typically stainless steel), ceramic, plastic, or the like can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, an acrylic resin film, or the like can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or polyester films may be used.

The spacer 611 is a bead spacer and is provided to control the distance (cell gap) between the pixel electrode 612 and the counter electrode 617 to be constant. Note that a spacer (post spacer) obtained by selectively etching the insulating layer may be used instead of the bead spacer of the spacer 611.

In addition, various signals (potentials) supplied to the signal line driver circuit 603, the scan line driver circuit 604, and the pixel portion 602 are supplied from an FPC 607 (Flexible Printed Circuit) through a lead wiring 614.

In this embodiment mode, the connection terminal 616 is formed using the same conductive layer as the pixel electrode 612 included in the liquid crystal element 613. The lead wiring 614 is formed of the same conductive layer as the wiring 618.

A terminal included in the connection terminal 616 and the FPC 607 is electrically connected through an anisotropic conductive layer 619.

Although not illustrated, the liquid crystal display device described in this embodiment includes an alignment film and a polarizing plate, and may further include a color filter, a light-shielding layer, and the like.

Further, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be provided as appropriate on the emission surface of the light emitting element. Further, an antireflection layer may be provided on the polarizing plate or the circularly polarizing plate.

FIG. 28 illustrates an example of a light-emitting device which is one embodiment of the present invention. In FIG. 28, only parts different from those in FIG. As the light emitting device, a light emitting element using electroluminescence is used. A light-emitting element utilizing electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. In general, the former is called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, when a voltage is applied to the light emitting element, carriers (electrons and holes) are injected from the pair of electrodes to the layer containing the light emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state and emits light when the carrier returns from the excited state to the ground state. Such a light-emitting element is called a current-excitation light-emitting element because of its mechanism.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. A thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between a pair of electrodes, and the light-emission mechanism is localized light emission that utilizes inner-shell electron transition of metal ions.

Note that description is made here using an organic EL element as a light-emitting element. A thin film transistor to which the manufacturing method described in the above embodiment is applied is described as a thin film transistor for controlling driving of the light-emitting element.

First, thin film transistors 621 and 622 are formed over a substrate. An insulating layer functioning as a protective layer is formed over the thin film transistors 621 and 622. The insulating layer may be formed by stacking an insulating layer 623 formed using an inorganic material and an insulating layer 624 formed using an organic material, and the top surface may be planarized with a layer formed using an organic material. Here, as the inorganic material, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like may be used. As the organic material, an organic resin such as acrylic, polyimide, or polyamide, or siloxane may be used.

A conductive layer is provided over the insulating layer 624 formed using an organic material. This conductive layer is referred to as a first conductive layer 625. The first conductive layer 625 functions as a pixel electrode. When the thin film transistor of the pixel is an n-type thin film transistor, it is preferable to form a cathode as the pixel electrode, but in the case of a p-type thin film transistor, it is preferable to form an anode. When forming a cathode as a pixel electrode, a material having a low work function, such as Ca, Al, MgAg, AlLi, or the like may be used.

Next, a partition 626 is formed over the side surface (end portion) of the first conductive layer 625 and the insulating layer 624 formed using an organic material. The partition 626 has an opening, and the first conductive layer 625 is exposed in the opening. The partition wall 626 is formed using an organic resin layer, an inorganic insulating layer, or organic polysiloxane. Particularly preferably, a partition wall is formed using a photosensitive material, and the partition wall 626 on the first conductive layer 625 is exposed to form an opening so that the side wall of the opening has a continuous curvature. It is preferable to form it so as to be an inclined surface to be formed.

Next, a light-emitting layer 627 is formed so as to be in contact with the first conductive layer 625 in the opening portion of the partition wall 626. The light emitting layer 627 may be composed of a single layer or may be composed of a plurality of layers stacked.

Then, a second conductive layer 628 is formed so as to cover the light-emitting layer 627. The second conductive layer 628 is called a common electrode. In the case where the first conductive layer 625 is formed using a cathode material, the second conductive layer 628 is formed using an anode material. The second conductive layer 628 can be formed using a light-transmitting conductive layer using a light-transmitting conductive material. As the second conductive layer 628, a titanium nitride layer or a titanium layer may be used. Here, indium tin oxide (ITO) is used as the second conductive layer. In the opening of the partition wall, the first conductive layer 625, the light-emitting layer 627, and the second conductive layer 628 overlap with each other, whereby the light-emitting element 630 is formed. After that, a protective layer is preferably formed over the partition wall 626 and the second conductive layer 628 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 630. As the protective layer, a silicon nitride layer, a silicon nitride oxide layer, a DLC layer, or the like can be used. More preferably, it is further packaged (enclosed) with a protective film (such as an ultraviolet curable resin film) or a cover material that is highly airtight and less degassed so as not to be exposed to the outside air.

In order to extract light emission, the light-emitting element 630 may have at least one of an anode and a cathode that is transparent. Then, thin film transistors 621 and 622 and a light emitting element 630 are formed over the substrate, a top emission structure for extracting light from a surface opposite to the substrate, a bottom emission structure for extracting light from a surface on the substrate side, and the substrate side and the substrate There is a light emitting element having a dual emission structure in which light emission is extracted from both sides of the opposite side. Any of the above-described emission structures can be applied to the light-emitting device that is one embodiment of the present invention.

Note that in the light-emitting element 630 having a top emission structure, a light-emitting layer and an anode are sequentially stacked over a cathode. The cathode may be formed of a conductive material (eg, Ca, Al, MgAg, AlLi, etc.) that has a small work function and reflects light. When the light emitting layer is composed of a plurality of layers, for example, the electron injecting layer, the electron transporting layer, the light emitting layer, the hole transporting layer, or the hole injecting layer are stacked in this order on the cathode. Note that it is not necessary to provide all of these layers. The anode is formed using a light-transmitting conductive material that transmits light. For example, the anode includes indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, and titanium oxide. A light-transmitting conductive layer such as indium tin oxide, indium tin oxide (ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added may be used. Light generated from the light emitting layer is emitted to the anode side.

In the light emitting element 630 having a bottom emission structure, a light emitting layer and an anode are sequentially stacked on a cathode. Note that in the case where the anode has a light-transmitting property, a light-blocking layer for reflecting or shielding light is preferably provided so as to cover the anode. As in the case of the top emission structure, the cathode may be a conductive layer formed of a material having a low work function, and a known material may be used. However, the thickness is set so as to transmit light (preferably, about 5 nm to 30 nm). For example, aluminum having a thickness of 20 nm can be used as the cathode. And the light emitting layer may be comprised by the single layer similarly to the case of a top emission structure, and may be comprised by laminating | stacking several layers. The anode does not need to transmit light, but can be formed using a light-transmitting conductive material as in the case of the top emission structure. The light shielding layer may be, for example, a metal layer that reflects light or a resin to which a black pigment is added. Light generated from the light emitting layer is emitted to the cathode side.

Note that the pixel electrode included in the light-emitting element 630 is electrically connected to the source electrode or the drain electrode of the thin film transistor 622 through a wiring. In this embodiment mode, the common electrode of the light-emitting element 630 and the light-transmitting conductive material layer are electrically connected.

The structure of the light-emitting element 630 is not limited to the structure described in this embodiment. The structure of the light-emitting element 630 can be changed as appropriate depending on the direction of light extracted from the light-emitting element 630, the polarity of the thin film transistor 622, and the like.

Note that in the case where the light-emitting element 630 has a top emission structure, the second substrate which is a substrate positioned in a direction in which light is extracted from the light-emitting element 630 must be a light-transmitting substrate. In that case, a substrate made of a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

As the filler 631 disposed between the two substrates, an inert gas such as nitrogen or argon, an ultraviolet curable resin, a thermosetting resin, or the like can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy Resin, silicon resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) is used.

Note that although an example in which the thin film transistor 622 (driving transistor) that controls driving of the light emitting element 630 and the light emitting element are directly connected is described in this embodiment mode, the thin film transistor for driving and the light emitting element are connected to each other. A current control thin film transistor may be connected to the capacitor.

Note that the light-emitting device described in this embodiment is not limited to the illustrated structure, and various modifications based on a technical idea are possible.

This embodiment can be implemented in combination with any structure described in the other embodiments.

(Embodiment 8)
The semiconductor device including the thin film transistor according to the present invention can be applied to various electronic devices (including game machines). Examples of the electronic apparatus include a television device (also referred to as a television or a television receiver), a computer monitor, electronic paper, a digital camera, a digital video camera, a digital photo frame, a mobile phone (a mobile phone, a mobile phone device). Also, large game machines such as portable game machines, portable information terminals, sound reproducing devices, and pachinko machines can be given.

The semiconductor device including the thin film transistor according to the present invention can be applied to electronic paper. Electronic paper can be used for electronic devices in various fields as long as they display information. For example, electronic paper can be used for electronic books (electronic books), posters, advertisements in vehicles such as trains, and displays on various cards such as credit cards. An example of the electronic device is illustrated in FIG.

FIG. 29A illustrates an example of an electronic book. An electronic book illustrated in FIG. 29A includes two housings, a housing 700 and a housing 701. The housing 700 and the housing 701 are integrated with a hinge 704 and can be opened and closed. With such a configuration, an operation like a paper book can be performed.

A display portion 702 is incorporated in the housing 700, and a display portion 703 is incorporated in the housing 701. The display unit 702 and the display unit 703 may be configured to display a continued screen or may be configured to display different screens. By adopting a configuration in which different screens are displayed, for example, a sentence is displayed on the right display unit (display unit 702 in FIG. 29A) and an image is displayed on the left display unit (display unit 703 in FIG. 29A). Can be displayed.

FIG. 29A illustrates an example in which the housing 700 is provided with an operation portion and the like. For example, the housing 700 includes a power input terminal 705, operation keys 706, a speaker 707, and the like. A page can be turned with the operation keys 706. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, an external connection terminal (such as an earphone terminal, a USB terminal, and a terminal that can be connected to various cables such as a USB cable), a recording medium insertion portion, and the like may be provided on the back and side surfaces of the housing. Further, the electronic book illustrated in FIG. 29A may have a function as an electronic dictionary.

The electronic book illustrated in FIG. 29A may have a structure capable of transmitting and receiving information wirelessly. It is also possible to purchase and download desired book data from an electronic book server by wireless communication.

FIG. 29B illustrates an example of a digital photo frame. For example, in a digital photo frame illustrated in FIG. 29B, a display portion 712 is incorporated in a housing 711. The display unit 712 can display various images. For example, by displaying image data captured by a digital camera or the like, the display unit 712 can function in the same manner as a normal photo frame.

Note that the digital photo frame illustrated in FIG. 29B includes an operation portion, an external connection terminal (a terminal that can be connected to various types of cables such as a USB terminal and a USB cable), a recording medium insertion portion, and the like. These configurations may be incorporated on the same surface as the display portion, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, a memory storing image data captured by a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to capture the image data, and the captured image data can be displayed on the display unit 712.

In addition, the digital photo frame illustrated in FIG. 29B may have a structure in which information can be transmitted and received wirelessly. A configuration may be employed in which desired image data is captured and displayed wirelessly.

FIG. 29C illustrates an example of a television device. In the television device illustrated in FIG. 29C, a display portion 722 is incorporated in a housing 721. The display portion 722 can display an image. Here, a configuration in which the housing 721 is supported by the stand 723 is shown. The display device described in Embodiment 7 can be applied to the display portion 722.

The television device illustrated in FIG. 29C can be operated with an operation switch included in the housing 721 or a separate remote controller. Channels and volume can be operated with operation keys provided in the remote controller, and an image displayed on the display portion 722 can be operated. Further, the remote controller may be provided with a display unit that displays information output from the remote controller.

Note that the television set illustrated in FIG. 29C is provided with a receiver, a modem, and the like. General TV broadcasts can be received by the receiver, and connected to a wired or wireless communication network via a modem, so that one-way (sender to receiver) or two-way (sender and receiver) It is also possible to perform information communication between each other or between recipients.

FIG. 29D illustrates an example of a mobile phone. A cellular phone illustrated in FIG. 29D includes an operation button 733, an operation button 737, an external connection port 734, a speaker 735, a microphone 736, and the like in addition to the display portion 732 incorporated in the housing 731.

In the mobile phone illustrated in FIG. 29D, the display portion 732 is a touch panel, and the display content of the display portion 732 can be operated by touching a finger or the like. In addition, making a call or creating a mail can be performed by touching the display portion 732 with a finger or the like.

There are mainly three screen modes of the display portion 732. The first is a display mode mainly for displaying images, and the second is an input mode mainly for inputting information such as characters. The third is a display + input mode in which the display mode and the input mode are mixed.

For example, when making a call or creating a mail, the display unit 732 may be set to a character input mode mainly for inputting characters, and an operation for inputting characters displayed on the screen may be performed. In this case, it is preferable to display a keyboard or number buttons using most of the screen of the display unit 732.

In addition, by providing a detection device provided with a sensor for detecting the inclination of a gyroscope, an acceleration sensor, or the like inside the mobile phone shown in FIG. 29D, the orientation (vertical or horizontal) of the mobile phone is determined, The display information on the display unit 732 can be switched automatically.

The screen mode is switched by touching the display portion 732 or operating the operation button 737 of the housing 731. In addition, a configuration in which switching is performed depending on the type of image displayed on the display portion 732 may be employed. For example, the display mode can be switched if the image signal to be displayed on the display unit is moving image data, and the input mode can be switched if it is text data.

In addition, in the input mode, when a signal detected by the optical sensor of the display unit 732 is detected and there is no input by a touch operation on the display unit 732 for a certain period, the screen mode is switched from the input mode to the display mode. You may control.

The display portion 732 can also function as an image sensor. For example, the user authentication can be performed by touching the display unit 732 with a palm or a finger and capturing an image of a palm print, a fingerprint, or the like with an image sensor. In addition, if a backlight that emits near-infrared light or a sensing light source that emits near-infrared light is used for the display portion, finger veins, palm veins, and the like can be imaged.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

Claims (5)

A switch unit or a buffer unit, a logic circuit unit, and a pixel unit,
The pixel portion includes a first inverted staggered thin film transistor and a pixel electrode connected to a wiring of the first inverted staggered thin film transistor,
The switch unit or buffer unit includes a second inverted staggered thin film transistor,
The logic circuit unit includes an inverter circuit including a third inverted staggered thin film transistor and a fourth inverted staggered thin film transistor,
The first reverse staggered thin film transistor to the fourth reverse staggered thin film transistor have the same polarity,
The first reverse staggered thin film transistor to the fourth reverse staggered thin film transistor are:
A gate electrode;
A first gate insulating layer on the gate electrode;
A first microcrystalline semiconductor layer over the first gate insulating layer;
A second microcrystalline semiconductor layer having a plurality of cone-shaped protrusions on the first microcrystalline semiconductor layer;
A pair of amorphous semiconductor layers on the second microcrystalline semiconductor layer;
A pair of impurity semiconductor layers on the pair of amorphous semiconductor layers;
The second inverted staggered thin film transistor is:
A second gate insulating layer over the second microcrystalline semiconductor layer and the pair of amorphous semiconductor layers;
A back gate electrode overlapping with the gate electrode and in contact with the second gate insulating layer;
A display device comprising: Oite to claim 1,
The third inverted staggered thin film transistor is:
A second gate insulating layer over the second microcrystalline semiconductor layer and the pair of amorphous semiconductor layers;
And a back gate electrode overlapping with the gate electrode and in contact with the second gate insulating layer. In claim 1 or claim 2,
The display device, wherein the third inverted staggered thin film transistor is a depletion type thin film transistor. In claim 1 or claim 2,
The display device, wherein the third inverted staggered thin film transistor is an enhancement type thin film transistor. In any one of Claims 1 thru | or 4 ,
The second microcrystalline semiconductor layer having a plurality of conical protrusions included in the first inverted staggered thin film transistor to the fourth inverted staggered thin film transistor has one surface in contact with the first microcrystalline semiconductor layer and the other The display device is characterized in that the surface thereof is in contact with the insulating layer.

Images