JP5555864B2 - Insulated gate semiconductor device and insulated gate semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a structure of an insulated gate semiconductor element having radiation resistance and an insulated gate semiconductor integrated circuit using the insulated gate semiconductor element.

  Solid-state imaging devices are roughly classified into CCD types and CMOS types. When these solid-state imaging devices are used in a radiation-intensive environment such as a satellite-mounted camera, the CCD type that performs multi-stage charge transfer operation is susceptible to transfer deterioration due to the influence of radiation, so a CMOS that does not involve multi-stage charge transfer operation. The mold is more advantageous. However, the CMOS type is also affected variously by irradiation. Specifically, the increase in dark current and white defects in the light receiving unit, the increase in leakage current in the transistor, and the latch-up. Among these, the leakage current of the transistor is generated in the transistor in the pixel or the transistor in the analog circuit used in the readout circuit system, and it is important to take measures against the radiation-resistant design of the CMOS type solid-state imaging device. It becomes one of the points.

With reference to FIG. 10, it will be described that a general MOS transistor causes an increase in leakage current when irradiated with radiation. In the MOS transistor shown in FIG. 10, a gate electrode 24P is formed on a semiconductor layer 11 that is a p-type substrate via a gate insulating film 22 made of a silicon oxide film, and the periphery is surrounded by a thick element isolation insulating film 21. This region is used as an active region 21B, and an n-type drain region 12 and a source region 13 are formed in the active region 21B. A current flows from the drain region 12 to the source region 13 through the channel below the gate electrode 24P. FIG. 11 shows a potential distribution in the depth direction of the MOS transistor shown in FIG. MOS transistors have low mobility after electron-hole pairs are generated in an insulating film when irradiated with high-energy light such as X-rays or gamma rays, or ionizing radiation such as charged particles of high energy. Holes are left behind and accumulate in many traps near the interface with the semiconductor. As a result, even if the gate voltage Vg does not change, the channel potential (electrons) has a deep potential from Vs0 to Vs1, and the channel cannot be turned off even if the gate voltage Vg is normally off (cut off). In other words, the threshold voltage at which the gate is turned on (conducted) shifts in the negative direction. Since this effect is proportional to the square of the thickness of the oxide film, it becomes significant when the oxide film is thick. As shown in FIG. 10A, a leak path is formed at both ends along the length direction of the channel at the time of off. Current _Ia flows.

  As one method for preventing this, as shown in FIG. 12, the gate electrode 81 is formed in a ring shape, a region 82 surrounded by the gate electrode 81 is a source or drain, and a region 83 around the gate electrode 81 is a drain or source. It is known (see Non-Patent Document 1). This eliminates the thick oxide sidewall between the source and drain and prevents leakage current. However, this method increases the transistor size.

  As another method, as shown in FIG. 13, it is proposed to increase the width of the channel 86 under the gate electrode 88 and increase the edge length of the side wall portion from a thick oxide film from y to 2x + y (Patent Document). 1). This increases the channel length near the side wall and makes it difficult for leakage current to flow, but this method also increases the gate size.

Special table 2009-516361

G. Anelli et al., “Radiation Tolerant VLSI Circuits in Standard Deep Submicron CMOS Technologies for the LHC Experiments: Practical Design Aspects), American Institute of Electrical and Electronics Engineers (IEEE), Transactions on Nuclear Science, Volume 46, pp. 1690-1696, December 1999

  The present invention relates to an insulated gate semiconductor device capable of reducing a leakage current between a source and a drain due to radiation without increasing the size, and an insulated gate semiconductor integration using the insulated gate semiconductor device An object is to provide a circuit.

  In order to achieve the above object, according to a first aspect of the present invention, there is provided: (a) a first conductivity type semiconductor layer at least partially forming a channel region; and (b) at least surrounding the channel region, (C) a first main electrode region of a second conductivity type provided in one of the active regions and injecting carriers into the channel region via a carrier injection port; and (d) ) A second main electrode region of a second conductivity type provided on the other side of the active region and having a carrier discharge port for discharging carriers from the channel region; and (e) a gate insulating film provided on the surface of the active region; (f) Provided on the gate insulating film, electrostatically control the carrier flow, and on the plane pattern, the main control unit orthogonal to the carrier flow path, and to form a π-shape in this main control unit There are two guard parts that intersect, and a gage surrounding three sides of the second main electrode region. (G) on the active region, on the planar pattern, on both ends in the gate width direction of the second main electrode region, with two guard portions, respectively, in contact with the guard portion and the element isolation insulating film The gist of the present invention is that each of the gate electrodes is an insulated gate semiconductor element having a first conductivity type and a leak prevention region having a higher impurity density than the semiconductor layer.

  According to a second aspect of the present invention, there is provided: (a) a first conductivity type semiconductor layer at least partially forming a channel region; and (b) an element isolation that surrounds at least the channel region and defines an active region above the semiconductor layer. An insulating film; (c) a first main electrode region of a second conductivity type provided on one end side of the active region and injecting carriers into the channel region via a carrier injection port; and (d) an active region A second main electrode region of the second conductivity type provided on the other end side and having a carrier discharge port for discharging carriers from the channel region; and (e) a gate insulating film provided on the surface of the active region; (f) a first main controller provided on the gate insulating film and orthogonal to the carrier flow path; and two first guard portions intersecting the first main controller so as to form a π-shape. A first gate electrode surrounding three sides of the first main electrode region; and (g) a first guard portion and an element in the active region. A pair of first conductivity types inserted between the isolation insulating films and having a higher impurity density than the semiconductor layer; and (h) a first gate electrode facing the gate insulating film. A second main control section that is perpendicular to the carrier flow path, and two second guard sections that intersect with the second main control section so as to form a π-shape. A second gate electrode that surrounds the first gate electrode; and (i) a pair of first conductivity types respectively inserted between the second guard portion of the active region and the element isolation insulating film, and a second impurity having a higher impurity density than the semiconductor layer. (J) located between the first and second gate electrodes of the active region, and is of a second conductivity type, functions as a second main electrode region with respect to the first main electrode region, It is an insulated gate semiconductor integrated circuit comprising a first main electrode region and a common main electrode region that functions with respect to the main electrode region. To.

  According to a third aspect of the present invention, there is provided: (a) a first conductivity type semiconductor layer at least partially forming a channel region; and (b) an element isolation that surrounds at least the channel region and defines an active region above the semiconductor layer. An insulating film; (c) a first main electrode region of a second conductivity type provided on one end side of the active region and injecting carriers into the channel region via a carrier injection port; and (d) an active region A second main electrode region of the second conductivity type provided on the other end side and having a carrier discharge port for discharging carriers from the channel region; and (e) a gate insulating film provided on the surface of the active region; (f) a first main controller provided on the gate insulating film and orthogonal to the carrier flow path; and two first guard portions intersecting the first main controller so as to form a π-shape. A first gate electrode surrounding three sides of the first main electrode region; and (g) a first guard portion and an element in the active region. A pair of first conductivity types inserted between the isolation insulating films and having a higher impurity density than the semiconductor layer; and (h) a first gate electrode facing the gate insulating film. A second main control section that is perpendicular to the carrier flow path, and two second guard sections that intersect with the second main control section so as to form a π-shape. A second gate electrode that surrounds the first gate electrode; and (i) a pair of first conductivity types respectively inserted between the second guard portion of the active region and the element isolation insulating film, and a second impurity having a higher impurity density than the semiconductor layer. A leakage prevention region; (j) a plurality of intermediate gate electrodes spaced apart between the first gate electrode and the second gate electrode; and (k) a first gate electrode and a plurality of intermediate gate electrodes. Between each of the plurality of intermediate gate electrodes, between each of the plurality of intermediate gate electrodes and the second A gist of the present invention is an insulated gate semiconductor integrated circuit including a plurality of second conductive type common main electrode regions that are located between the gate electrodes and are provided in the active region and spaced apart from the element isolation insulating film. .

  According to the present invention, an insulated gate semiconductor element capable of reducing a leakage current between the source and the drain due to radiation without increasing the size, and an insulated gate type using the insulated gate semiconductor element A semiconductor integrated circuit can be provided.

FIG. 1A is a plan view showing an insulated gate semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a first view seen from the IA-IA direction of FIG. FIG. 1C is a schematic cross-sectional view showing a part of an insulated gate semiconductor device according to the first embodiment, and FIG. 1C is an insulated gate according to the first embodiment as viewed from the IB-IB direction in FIG. FIG. 1D shows a part of the insulated gate semiconductor device according to the first embodiment as viewed from the IC-IC direction of FIG. It is typical sectional drawing. FIG. 2A is a plan view showing an insulated gate semiconductor device according to the second embodiment of the present invention, and FIG. 2B is a plan view seen from the IIA-IIA direction of FIG. It is typical sectional drawing which shows a part of insulated gate semiconductor element which concerns on 2 embodiment. FIG. 3A is a plan view showing an insulated gate semiconductor device according to the third embodiment of the present invention, and FIG. 3B is a plan view seen from the IIIB-IIIB direction of FIG. It is typical sectional drawing which shows a part of insulated gate semiconductor element which concerns on 3 embodiment. It is an example of the top view of the insulated gate semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. It is an example of the top view of the insulated gate semiconductor integrated circuit which concerns on the 5th Embodiment of this invention. It is an example of the top view of the insulated gate semiconductor integrated circuit which concerns on the 6th Embodiment of this invention. The circuit diagram which shows the example of the circuit structure of each pixel of the amplification type image sensor to which the insulated gate semiconductor device which concerns on the 7th Embodiment of this invention, and the insulated gate semiconductor integrated circuit which concerns on 8th Embodiment are applied. It is. It is an example of the top view of the insulated gate semiconductor element which concerns on the 7th Embodiment of this invention used for a part of circuit diagram shown in FIG. It is an example of the top view of the insulated gate semiconductor integrated circuit which concerns on the 8th Embodiment of this invention used for a part of circuit diagram shown in FIG. FIG. 10A is a plan view for explaining the path of the main current of the conventional insulated gate semiconductor device, and FIG. 10B is a diagram illustrating the on-state of the channel portion of the insulated gate semiconductor device of FIG. It is a typical sectional view showing a potential profile at the time of conduction) and off (cut off). It is a figure which compares the potential change of the channel of the conventional insulated gate semiconductor element with the potential distribution of the channel of the insulated gate semiconductor element before and after irradiation of a radiation. It is a top view explaining the conventional insulated gate semiconductor element which has radiation resistance. It is a top view explaining the conventional insulated gate semiconductor element which has radiation resistance.

  Next, first to eighth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the following first to eighth embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is a material of a component. The shape, structure, arrangement, etc. are not specified as follows. The technical idea of the present invention can be variously modified within the technical scope described in the claims.

(First embodiment)
As shown in FIG. 1, the insulated gate semiconductor device according to the first embodiment of the present invention is composed of a first conductivity type (p-type) silicon (Si), and at least a part of the first gate gate region forms a channel region. The conductive type semiconductor layer 11 and at least one of the channel region and the element isolation insulating film 21 defining the active region 21B on the semiconductor layer 11 are provided on one side of the active region 21B, and the channel region is provided with a carrier injection port. A second conductive type (n-type) for injecting carriers (electrons), a rectangular first main electrode region 12 having three sides in contact with the element isolation insulating film 21, and the active region 21B. A second main electrode region 13 having a second conductivity type (n-type) having a carrier discharge port for discharging carriers and having one side in contact with the other end of the element isolation insulating film 21, and an active region Provided on the surface of 21B The gate insulating film 22 is provided on the gate insulating film 22, and the flow of carriers is electrostatically controlled, so that the plane pattern is formed between the first main electrode region 12 and the second main electrode region 13. The main control unit orthogonal to the flow path of the carrier flowing in the channel region, and the main control unit have two guard portions 241 and 242 that intersect with the main control unit so as to surround three sides of the second main electrode region 13. The two guard portions 241 and 242 are separated from each other in the gate width direction of the second main electrode region 13 on the planar pattern on the gate electrode 24 having a π-shape and the active region 21B on the planar pattern. The guard portions 241 and 242 and the element isolation insulating film 21 are formed so as to be in contact with each other, and are provided with leak prevention regions 61 and 62 of the first conductivity type (p ⁺ type) and having a higher impurity density than the semiconductor layer 11.

  The first main electrode region 12 has a side close to the gate electrode 24 as a carrier injection port, and the second main electrode region 13 has a side close to the first main electrode region 12 as a carrier discharge port. The carrier flow path connecting the carrier injection port of the first main electrode region 12 and the carrier discharge port of the second main electrode region 13 is provided apart from the leak path generated by radiation. The leak path has a lower potential for electrons than the surroundings, and is formed along the element isolation insulating film 21 in the active region 21B. An interlayer insulating film 25 is provided on the gate electrode 24, and a first main electrode wiring 23 is formed in the first main electrode region 12 and a second main electrode region through a contact hole opened in the interlayer insulating film 25. A second main electrode wiring 27 is connected to 13.

  In FIG. 1B to FIG. 1D, the case where a semiconductor substrate (Si substrate) of the first conductivity type (p-type) is used as the “semiconductor layer 11” is illustrated, but instead of the semiconductor substrate, An epitaxial growth layer of a first conductivity type having a lower impurity density than the semiconductor substrate may be formed on the semiconductor substrate of the first conductivity type, and the epitaxial growth layer may be adopted as the semiconductor layer 11. The first conductive type (p-type) epitaxial growth layer may be formed on the semiconductor substrate, and the epitaxial growth layer may be adopted as the semiconductor layer 11. The first conductive type semiconductor layer (SOI layer) having the SOI structure may be used. May be employed as the semiconductor layer 11. As the element isolation insulating film 21, various structures and insulating films of various materials can be adopted as long as they have an element isolation function. For example, a thick oxide film used for a trench isolation structure such as shallow trench isolation (STI), which is advantageous for miniaturized integrated circuits, is suitable as the element isolation insulating film 21. As long as the element isolation insulating film 21 surrounds at least the upper portion of the semiconductor layer 11, various structures can be adopted, and a structure surrounding the bottom and side surfaces of the semiconductor layer 11 like an island structure may be adopted. Absent.

  In the description of the present specification and claims, the “first main electrode region” is either a source region or a drain region of a field effect transistor (FET), a static induction transistor (SIT), or the like. It means a semiconductor region. The “second main electrode region” means a semiconductor region such as an FET, SIT, etc., which is either the source region or the drain region that is not the first main electrode region. That is, if the first main electrode region is a source region, the second main electrode region is a drain region, and if the first main electrode region is a drain region, the second main electrode region is a source region. In the following description, for the sake of convenience, the case where the first main electrode region is the drain region and the second main electrode region is the source region will be described, but which is called the drain region and which is called the source region is an insulated gate type. Of course, this is merely a selection problem determined by the bias relationship of the semiconductor element, and the drain region and the source region may be interchanged.

  In the description of the present specification and claims, the term “rectangle” does not mean a complete rectangle (rectangle). In other words, the expression “the rectangular first main electrode region 12” and “the rectangular second main electrode region 13” means only the first main electrode region 12 and the second main electrode region 13 which are completely rectangular (rectangular). However, for the reason of photolithography and other processes, the case where the corner portion of the planar shape of the first main electrode region 12 or the second main electrode region 13 becomes a rounded rectangle occurs. It should be noted that such incomplete rectangular topologies are also tolerated. In particular, in a structure that has been miniaturized, the planar shape of the first main electrode region 12 and the second main electrode region 13 can be a planar shape close to a circle, but in the description of the present specification and claims. These are also referred to as “rectangular first main electrode region 12” and “rectangular second main electrode region 13” including their planar shapes.

  In FIG. 1A, the first main electrode region 12 is provided only on the planar pattern on the gate electrode 24, and the second main electrode region 13 is provided only on the planar pattern on the lower side of the gate electrode 24. The structure was illustrated. However, the first main electrode region 12 may slightly protrude from the first main electrode region 12 side directly below the gate electrode 24 on the plane pattern, at least with a Debye length or longer. May slightly protrude from the second main electrode region 13 side directly below the gate electrode 24 on the plane pattern. Actually, in consideration of the heat treatment process in the process, the first main electrode region 12 is arranged in the horizontal direction (in FIG. 1A) directly below the gate electrode 24 from the first main electrode region 12 side on the plane pattern. The structure in which the second main electrode region 13 diffuses in the lateral direction (upward in FIG. 1A) immediately below the gate electrode 24 from the second main electrode region 13 side can be easily realized. Therefore, as an actual structure, in the structure shown in FIG. 1A, the first main electrode region 12 slightly protrudes downward from the first main electrode region 12 side directly below the gate electrode 24 on the plane pattern. The second main electrode region 13 slightly protrudes upward from the second main electrode region 13 side directly below the gate electrode 24.

The gate electrode 24 may be formed of a polycrystalline silicon (hereinafter referred to as “doped polysilicon”) film doped with a second conductivity type (n-type) impurity such as phosphorus (P) or arsenic (As). The boundary between the gate electrode 24 and the first main electrode region 12 and the boundary between the gate electrode 24 and the second main electrode region 13 can be determined in a self-aligning manner. Alternatively, if the gate electrode 24 is formed of a multilayer structure such as a doped polysilicon film and a tungsten silicide (WSi ₂ ) film, the resistance value of the gate electrode 24 can be reduced and high-speed operation can be achieved. As the silicide film, a metal silicide film such as a cobalt silicide (CoSi ₂ ) film, a titanium silicide (TiSi ₂ ) film, and a molybdenum silicide (MoSi ₂ ) film can be used in addition to a tungsten silicide (WSi ₂ ) film. Instead of the silicide film, a refractory metal such as tungsten (W), cobalt (Co), titanium (Ti), and molybdenum (Mo) may be used. Furthermore, the gate electrode 24 is formed of a polycide film using these silicide films. It may be configured. Instead of the silicide film, a metal film having a high conductivity such as aluminum (Al) or copper (Cu) may be disposed on the doped polysilicon film, such as a tungsten nitride (WN) film, a titanium nitride ( Any one or a plurality of laminated films of (TiN, Ti ₂ N) film may be arranged on the doped polysilicon film instead of the silicide film to constitute the gate electrode 24.

The insulated gate semiconductor device according to the first embodiment is not limited to a simple MOS transistor using a silicon oxide film as the gate insulating film 22. That is, as the gate insulating film 22 of the insulated gate semiconductor device according to the first embodiment, in addition to a silicon oxide film, a strontium oxide (SrO) film, a silicon nitride (Si ₃ N ₄ ) film, an aluminum oxide (Al ₂ O ₃ ) film, magnesium oxide (MgO) film, yttrium oxide (Y ₂ O ₃ ) film, hafnium oxide (HfO ₂ ) film, zirconium oxide (ZrO ₂ ) film, tantalum oxide (Ta _A MIS transistor may be formed using any one single layer film of ₂ O ₅ ) film, bismuth oxide (Bi ₂ O ₃ ) film, or a composite film in which a plurality of these films are stacked. However, these gate insulating film materials are premised on being resistant to radiation.

  When ionizing radiation is irradiated to the insulated gate semiconductor device according to the first embodiment, the threshold voltage of the gate shifts in the negative direction in the regions PA and PB near the device isolation insulating film 21 below the gate electrode 24. . However, since one end of each of the regions PA and PB is the leakage prevention regions 61 and 62 made of a layer having a conductivity type opposite to the channel charge, the current path through the leakage prevention regions 61 and 62 is blocked. Therefore, even when ionizing radiation is irradiated, it is possible to almost completely prevent the leakage current from flowing.

(Second Embodiment)
In the insulated gate semiconductor device according to the first embodiment, the structure in which three sides are in contact with the element isolation insulating film 21 as the first main electrode region 12 has been described, but the inner sides of the three sides in contact with the element isolation insulating film 21 are described. The two sides may be separated from the element isolation insulating film 21.

  That is, in the insulated gate semiconductor device according to the second embodiment, as shown in FIG. 2, the first main electrode region 12a is separated from two sides parallel to the carrier flow path of the first main electrode region 12a. The second embodiment is different from the first embodiment in that a distance q is provided between the insulating film 21 and the insulating film 21 in a direction (gate width direction) orthogonal to the carrier flow path. Since the other structure is the same as that of the insulated gate semiconductor device according to the first embodiment, a duplicate description is omitted.

  When ionizing radiation is irradiated to the insulated gate semiconductor device according to the second embodiment, the threshold voltage of the gate shifts in the negative direction in the regions PA and PB near the device isolation insulating film 21 below the gate electrode 24. To do. However, since one end of each of the regions PA and PB is the leakage prevention regions 61 and 62 made of a layer having a conductivity type opposite to that of the channel charge, the current path through these portions is blocked. Furthermore, in the insulated gate semiconductor device according to the second embodiment, the carrier flow of the first main electrode region 12a is avoided so that the first main electrode region 12a avoids a leak path formed in the vicinity of the element isolation insulating film 21. Since the two sides parallel to the path and the element isolation insulating film 21 are provided so as to be separated from each other, it is possible to prevent leakage current from flowing more reliably even when ionizing radiation is irradiated.

(Third embodiment)
As shown in FIG. 3, the insulated gate semiconductor device according to the third embodiment of the present invention includes a second main electrode region in the active region 21B below the π-shaped gate electrode 24 in the same direction as the channel width. 13 differs from the first embodiment in that an n ⁻ type buried region 15 having a width comparable to 13 is formed. The insulated gate semiconductor device according to the third embodiment is a normally-on (depletion) insulated gate transistor in which carriers are injected into the channel at a gate voltage of 0 V. The potential for carriers (electrons) is deeply formed. The impurity density of the buried region 15 is lower than that of the first main electrode region 12 and the second main electrode region 13, but is about the same as that of the p-type semiconductor layer 11 or larger than that of the p-type semiconductor layer 11. It is.

  When the insulated gate semiconductor device according to the third embodiment is irradiated with ionizing radiation, the threshold voltage of the gate shifts in the negative direction in the regions PA and PB near the device isolation insulating film 21 below the gate electrode 24. To do. However, since one end of each of the regions PA and PB is the leakage prevention regions 61 and 62 made of a layer having a conductivity type opposite to the channel charge, the current path through the leakage prevention regions 61 and 62 is blocked. Furthermore, the insulated gate semiconductor device according to the third embodiment has an n − type active region 21B below the gate electrode 24 and having an approximately the same width as the second main electrode region 13 in the same direction as the channel width. Since the buried region 15 is formed, the carrier flow path is restricted by the buried region 15, and even when ionizing radiation is irradiated, leakage current can be further prevented.

(Fourth embodiment)
As shown in FIG. 4, the insulated gate semiconductor integrated circuit according to the fourth embodiment shares the first main electrode region 12 with the insulated gate semiconductor element according to the first embodiment shown in FIG. As the electrode region, two insulated gate semiconductor elements are connected in series so as to face each other.

That is, the insulated gate semiconductor integrated circuit according to the fourth embodiment is made of first conductivity type (p-type) Si, and at least a part of which forms a channel region, and at least surrounds the channel region. The element isolation insulating film 21 defining the active region 21B is formed on the upper side of the layer 11, and is provided on one end side of the active region 21B. The second conductivity type (n is injected into the channel region via the carrier injection port). Type) rectangular first main electrode region 12 and the second conductivity type (n type) rectangular on the other end side of the active region 21B and having a carrier discharge port for discharging carriers from the channel region. A second main electrode region 13, a gate insulating film (not shown) provided on the surface of the active region 21B, a first main controller provided on the gate insulating film and orthogonal to the carrier flow path, 1 Main control unit A first gate electrode 24a that has two first guard portions 241a and 242a that intersect in a π-shape, surrounds three sides of the first main electrode region 12, and a first guard portion 241a of the active region 21B. , 242a and the element isolation insulating film 21 and a pair of first conductivity type (p ⁺ type) first impurity blocking regions 61a, 62a having a higher impurity density than the semiconductor layer 11, and a gate insulating film A second main control unit provided opposite to the first gate electrode 24a and orthogonal to the carrier flow path, and two second guards intersecting the second main control unit so as to form a π-shape. Having a portion 241b, 242b and inserted between the second gate electrode 24b surrounding three sides of the second main electrode region 13 and the second guard portions 241b, 242b of the active region 21B and the element isolation insulating film 21, respectively. a pair of first conductivity type (p ⁺ ) Is located between the second leakage prevention regions 61b and 62b having a higher impurity density than the semiconductor layer 11 and the first gate electrode 24a and the second gate electrode 24b in the active region 21B, and has the second conductivity type ( n-type), and a common main electrode region 14 that functions as the second main electrode region 13 for the first main electrode region 12 and functions as the first main electrode region 12 for the second main electrode region 13. .

  When ionizing radiation is irradiated to the insulated gate semiconductor integrated circuit according to the fourth embodiment, regions PAa and PBa near the element isolation insulating film 21 below the first gate electrode 24a and the second gate electrode 24b, respectively. The threshold voltage of the gate shifts in the negative direction at PAb and PBb. However, since one end of each of the regions PAa, PBa; PAb, PBb is a leakage prevention region 61a, 62a; 61b, 62b made of a layer having a conductivity type opposite to the channel charge, the leakage prevention regions 61a, 62a; 61b, 62b are interposed. The current path is blocked. Therefore, even when ionizing radiation is irradiated, it is possible to almost completely prevent the leakage current from flowing.

(Fifth embodiment)
The insulated gate semiconductor integrated circuit according to the fourth embodiment shown in FIG. 4 has a common main portion between the π-shaped first gate electrode 24a and the π-shaped second gate electrode 24b on the plane pattern. Although the electrode region 14 is disposed and the two transistors are connected in series, a plurality of transistors may be connected in series by using a plurality of common main electrode regions and a plurality of gate electrodes.

As shown in FIG. 5, the insulated gate semiconductor integrated circuit according to the fifth embodiment of the present invention includes a semiconductor layer 11 made of Si of the first conductivity type (p-type) and at least part of which forms a channel region. The element isolation insulating film 21 that at least surrounds the channel region and defines the active region 21B above the semiconductor layer 11, and is provided on one end side of the active region 21B, and carriers are supplied to the channel region via a carrier injection port. A second conductivity type (n-type) first main electrode region 12 to be injected and a second conductivity type (on the other end side of the active region 21B) and having a carrier discharge port for discharging carriers from the channel region ( n-type) second main electrode region 13, a gate insulating film (not shown) provided on the surface of the active region 21B, and a first main control provided on the gate insulating film and orthogonal to the carrier flow path. Part, this first The control unit has two first guard portions 241a and 242a that intersect in a π-shape, and includes a first gate electrode 24a that surrounds three sides of the first main electrode region 12, and a first of the active region 21B. A pair of first conductivity type ( ^{p.sup. +} Type) inserted between the guard portions 241a and 242a and the element isolation insulating film 21 and having a higher impurity density than the semiconductor layer 11, and first leakage prevention regions 61a and 62a; A second main control unit that is provided on the gate insulating film so as to face the first gate electrode 24a, and intersects the second main control unit so as to form a π-shape. A second gate electrode 24b that has second guard portions 241b and 242b and surrounds three sides of the second main electrode region 13, and between the second guard portions 241b and 242b of the active region 21B and the element isolation insulating film 21. A pair of first conductivity types, each inserted A plurality of (p ⁺ -type) second leak blocking regions 61b and 62b having a higher impurity density than the semiconductor layer 11 and spaced apart between the first gate electrode 24a and the second gate electrode 24b. Intermediate gate electrodes 26 _{-1 to} 26 _-m (m is a positive integer), a plurality of intermediate gate electrodes 26 _{-1 to} 26 _-m between the first gate electrode 24 a and the intermediate gate electrode 26 _-1 . A plurality of second conductivity types (n-type) are provided between the intermediate gate electrode 26- _m and the second gate electrode 24b, respectively, and are provided in the active region 21B apart from the element isolation insulating film 21. And a common main electrode region 141 to form a series circuit of a plurality of insulated gate semiconductor elements.

  When ionizing radiation is irradiated to the insulated gate semiconductor integrated circuit according to the fifth embodiment, regions PAa and PBa near the element isolation insulating film 21 below the first gate electrode 24a and the second gate electrode 24b, respectively. The threshold voltage of the gate shifts in the negative direction at PAb and PBb. However, since one end of each of the regions PAa, PBa; PAb, PBb is a leakage prevention region 61a, 62a; 61b, 62b made of a layer having a conductivity type opposite to the channel charge, the leakage prevention regions 61a, 62a; 61b, 62b are interposed. The current path is blocked. Therefore, even when ionizing radiation is irradiated, it is possible to almost completely prevent the leakage current from flowing.

  Furthermore, in the insulated gate semiconductor integrated circuit according to the fifth embodiment, since the plurality of common main electrode regions 141 are provided separately from the element isolation insulating film 21, the carrier is the element isolation insulating film 21. By avoiding the region PAc in which a leak path is formed in the vicinity, it is possible to prevent leakage current from flowing more reliably.

(Sixth embodiment)
In the insulated gate semiconductor integrated circuit according to the fifth embodiment shown in FIG. 5, the plurality of common main electrode regions 141 are separated from the element isolation insulating film 21 so that the carriers are in the vicinity of the element isolation insulating film 21. In the region adjacent to the element isolation insulating film 21 below each of the plurality of intermediate gate electrodes 26 _{-1 to} 26 _-m , the first conductivity having a concentration higher than that of the semiconductor layer 11 is prevented. By providing the mold region, it is possible to prevent leakage current between the two π-shaped gate electrodes.

As shown in FIG. 6, the insulated gate semiconductor integrated circuit according to the sixth embodiment of the present invention is made of Si of the first conductivity type (p-type), and at least a part forms channel regions of a plurality of transistors. An element isolation insulating film 21 that at least surrounds the semiconductor layer 11 and a channel region of each transistor above the semiconductor layer 11 and defines an active region 21B common to a plurality of transistors above the semiconductor layer 11; Provided on one end side of the region 21B, injects carriers into the channel region via a carrier injection port, and is of the second conductivity type (n-type), with only one side contacting one end of the element isolation insulating film. The first main electrode region 12 having a rectangular shape and the other end side of the active region 21B have a carrier discharge port for discharging carriers from the channel region, and are of the second conductivity type (n-type). A rectangular second main electrode region 13 having only one side in contact with the other end portion of the separation insulating film, a gate insulating film (not shown) provided on the surface of the active region 21B, and a carrier above the gate insulating film Of the first main electrode region 12 in contact with one side of the first main electrode region 12 between the first main electrode region 12 and the second main electrode region 13 on the plane pattern. Two first guard portions extending in a direction orthogonal to the flow path of carriers flowing in the channel region between the first main electrode region 13 and the second main electrode region 13 and further extending so as to surround three sides of the first main electrode region 12 Pi-shaped first gate electrode 24a having 241a, 242a, active region 21B, planar pattern, both ends of first main electrode region 12 in the gate width direction, and the first gate electrode 24a The first guard portion 241a, 242a is separated from the first The carrier flow is electrostatically controlled above the first conductivity type (p ⁺ type) first leak prevention regions 61a and 62a in contact with the guard portions 241a and 242a and the element isolation insulating film 21 and the gate insulating film. Then, on the plane pattern, the first main electrode region 12 and the second main electrode region 13 are in contact with one side of the second main electrode region 13 so as to face the first gate electrode 24a, and the second main electrode Two second guard portions 241b and 242b that further extend so as to surround the three sides of the region 13 are provided. Between the first gate electrode 24a and the second gate electrode 24b with respect to the first gate electrode 24a. Π-shaped second gate electrode 24b disposed mirror-image-symmetrically with respect to the center line along the channel width direction, and the active region 21B on the planar pattern on both ends in the gate width direction of the second main electrode region 13 And the second game The second guard portion 241b of the electrode 24b, at a 242b, second guard portion 241b, a first conductivity type in contact with 242b and the isolation insulating film 21 ^{(p +} -type) of the second leakage blocking region 61b, and 62b, The carrier flow is electrostatically controlled above the gate insulating film, and is arranged on the plane pattern so as to be spaced apart from each other between the first gate electrode 24a and the second gate electrode 24b. electrodes 24a, (the m positive integer) multiple of the intermediate gate electrode 26 _-1 ~ 26 _-m for extending parallel to each other between the second gate electrode 24b and, in the active region 21B, a plurality of intermediate gate electrode 26 _{- 1} ~ 26 _-m of being respectively formed in a region near each of the element isolation insulating film 21 of the lower, the leak blocking regions 18, 19 prevents the leakage path in the vicinity of the element isolation insulating film 21 is formed, On the surface pattern, the first gate electrode 24a, a plurality of intermediate gate electrode 26 _-1 ~ 26 _-m, located between the respective second gate electrode 24b, the second conductivity type provided on the active region 21B ( n-type) common main electrode regions 14 and a series circuit of a plurality of insulated gate semiconductor elements.

Leakage prevention regions 18 and 19 are of the first conductivity type (p ⁺ type) having a higher impurity density than that of semiconductor layer 11, and the main current flows in regions below each of the plurality of intermediate gate electrodes 26 _{−1 to} 26 _−m . The potential at the peripheral portion is made lower than the potential at the central portion forming the path (current path).

  When ionizing radiation is applied to the insulated gate semiconductor integrated circuit according to the sixth embodiment, regions PAa and PBa near the element isolation insulating film 21 below the first gate electrode 24a and the second gate electrode 24b, respectively. The threshold voltage of the gate shifts in the negative direction at PAb and PBb. However, since one end of each of the regions PAa, PBa; PAb, PBb is a leakage prevention region 61a, 62a; 61b, 62b made of a layer having a conductivity type opposite to that of the channel charge, the current path through these portions is blocked. . Therefore, even when ionizing radiation is irradiated, it is possible to almost completely prevent the leakage current from flowing.

Furthermore, in the insulated gate semiconductor integrated circuit according to the sixth embodiment, the potential of the central portion forming the main current path (current path) in each of the regions below the plurality of intermediate gate electrodes 26 _{-1 to} 26 _-m. Since the potential at the peripheral portion is lower, carriers can avoid the region PAc where a leak path is formed in the vicinity of the element isolation insulating film 21 and prevent leakage current from flowing more reliably.

(Seventh embodiment)
FIG. 7 is a diagram illustrating an example of a four-transistor pixel configuration including four MOS transistors in each pixel 5 of an amplification type image sensor (APS: Active Pixel Sensor). The cathode region of the embedded photodiode PD _ij that is the light receiving portion of each pixel 5 of the amplification type image sensor is common to the source region of the transfer transistor TT _ij . The floating drain (FD) region of the transfer transistor TT _ij is connected to the gate electrode of the signal readout transistor (amplification transistor) TA _ij constituting the amplifier circuit shown in the F part of FIG. 7 and the source electrode of the reset transistor TR _ij. Yes. The drain electrode of the reset transistor TR _{ij and} the drain electrode of the signal readout transistor (amplification transistor) TA _ij are connected to the power supply VDD, respectively, and the source electrode of the signal readout transistor (amplification transistor) TA _ij is the switching transistor TS _ij for pixel selection. Connected to the drain electrode. The source electrode of the pixel selection switching transistor TS _ij is connected to the _j vertical signal line B _j, and the vertical selection signal S _i of the horizontal line of i rows is driven to the timing generation circuit (not shown) by the gate electrode. And supplied from a vertical shift register (vertical scanning circuit) (not shown).

The insulated gate semiconductor device according to the seventh embodiment is a semiconductor device in which the transfer transistor TT _ij and the embedded photodiode PD _ij shown in part E of FIG. 7 are integrated. FIGS. 8A and 8B are a plan view and a cross-sectional view corresponding to part E in FIG. 7, respectively.

As shown in FIG. 8, the insulated gate semiconductor device according to the seventh embodiment of the present invention includes a semiconductor layer 51 made of Si of the first conductivity type (p-type), at least a part of which forms a channel region, An element isolation insulating film 21 that at least surrounds a region to be a channel region above the semiconductor layer 51 and defines an active region 21B above the semiconductor layer 51, and is provided on one end side of the active region 21B. apart from the configure photodiode PD _ij, via a carrier injection port injecting the photodiode PD _ij is generated carriers (electrons) to the channel region, the second conductivity type (n-type), from the device isolation insulating film 21 The rectangular surface-buried region (first main electrode region) 52 and the other end side of the active region 21B are provided, and carriers (electrons) are discharged from the channel region to be of the second conductivity type (n-type). ,element A rectangular charge detection part (second main electrode region) 53 having only one side in contact with the other end of the separation insulating film 21, a gate insulating film 22 provided on the surface of the active region 21B, and the gate insulating film 22 The carrier flow is electrostatically controlled to form a channel pattern between the surface buried region 52 and the charge detection region 53 and a channel region between the surface buried region 52 and the charge detection region 53 on the plane pattern. A π-shaped gate having two guard portions 241 and 242 extending in a direction orthogonal to the flow path of the carrier flowing through and further extending so as to surround three sides of the charge detection region (second main electrode region) 53 And an electrode (transfer gate electrode) 24.

The buried photodiode PD _ij has a semiconductor layer 51 as an anode region and a surface buried region 52 as a cathode region, and a first conductivity type (p ⁺ -type) pinning layer 54 is formed on each surface buried region 52. Is formed.

From the surface buried region 52 of the light receiving portion that functions as a source region of the transfer transistor TT _ij (first main electrode region), a charge detection functioning as a floating drain of the transfer transistor TT _ij (FD) region (second main electrode region) By applying a high (H) level signal as the control signal T to the gate electrode (transfer gate electrode) 24 of the transfer transistor TT _ij , the region 53 passes through the first conductivity type (p-type) semiconductor layer 51. Thus, the signal charge is transferred. In the charge detection region 53, the gate electrode of the signal readout transistor (amplification transistor) TA _ij and the source electrode of the reset transistor TR _ij are formed by surface wiring through a contact plug (not shown) provided in the gate insulating film 22. It is connected. The reset signal R _{i is set} to the high (H) level (R _i = “1”) to the reset gate electrode of the reset transistor TR _ij , and the charges accumulated in the charge detection region 53 are discharged, respectively. Reset.

  When ionizing radiation is irradiated to the insulated gate semiconductor device according to the seventh embodiment, the threshold voltage of the gate shifts in the negative direction in the regions PA and PB near the device isolation insulating film 21 below the gate electrode 24. To do. However, since one end of each of the regions PA and PB is the leakage prevention regions 61 and 62 made of a layer having a conductivity type opposite to the channel charge, the current path through the leakage prevention regions 61 and 62 is blocked. Therefore, even when ionizing radiation is irradiated, it is possible to almost completely prevent the leakage current from flowing.

(Eighth embodiment)
Of the configuration of each pixel 5 of the amplification type image sensor described in the seventh embodiment, the configuration of the present invention can be applied to elements other than the insulated gate semiconductor device according to the seventh embodiment. As shown in FIG. 9, the insulated gate semiconductor integrated circuit according to the eighth embodiment of the present invention includes an n ⁺ -type first main electrode region 12, an n ⁺ -type first common main electrode region 14a, The reset transistor TR _ij shown in the F section of FIG. 7, the signal readout transistor (amplification transistor) TA _ij, and the switching, each including the second common main electrode region 14 b and the n ⁺ -type second main electrode region 13. This is an integrated circuit in which the transistor TS _ij is integrated.

That is, the insulated gate semiconductor integrated circuit according to the eighth embodiment of the present invention is made of Si of the first conductivity type (p-type) as shown in FIG. And an element isolation insulating film (illustrated) defining at least a region to be a channel region of each transistor above the semiconductor layer 11 and defining an active region 21B common to a plurality of transistors above the semiconductor layer 11. And is provided on one end side of the active region 21B, injects carriers into the channel region via a carrier injection port, and is of the second conductivity type (n-type) and one end portion of the element isolation insulating film. The first main electrode region 12 having a rectangular shape in contact with only one side of the active region 21B and a carrier discharge port for discharging carriers from the channel region are provided on the other end side of the active region 21B. A rectangular second main electrode region 13 having only one side in contact with the other end portion of the element isolation insulating film, a gate insulating film (not shown) provided on the surface of the active region 21B, and a gate insulating film The flow of carriers is electrostatically controlled above the upper surface of the first main electrode region 12 in contact with one side between the first main electrode region 12 and the second main electrode region 13 on the plane pattern. Two lines extending in a direction orthogonal to the flow path of carriers flowing in the channel region between the first main electrode region 12 and the second main electrode region 13 and further extending so as to surround three sides of the first main electrode region 12 The π-shaped first gate electrode 24 a having the first guard portions 241 a and 242 a and the carrier flow is electrostatically controlled above the gate insulating film, and the first main electrode region 12 is formed on the planar pattern. Between the first main electrode region 13 and the second main electrode region 13. Two second guard portions 241b and 242b extending further to surround three sides of the second main electrode region 13 in contact with one side of the second main electrode region 13, and the first gate electrode 24a The carrier flows above the gate insulating film and the π-shaped second gate electrode 24b arranged in mirror symmetry with respect to the center line along the channel width direction between the gate electrode 24a and the second gate electrode 24b. The first gate electrode 24a and the second gate electrode 24b are electrostatically controlled and arranged on the plane pattern so as to be separated from each other between the first gate electrode 24a and the second gate electrode 24b. And the intermediate gate electrode 26 extending in parallel with each other and the carrier injection port and the channel which are located between the first gate electrode 24a and the intermediate gate electrode 26 on the plane pattern and inject carriers into the channel region. The second conductive type (n-type) first common main electrode region 14a having a carrier discharge port for discharging carriers from the region and the plane pattern is located between the intermediate gate electrode 26 and the second gate electrode 24b. A second common main electrode region 14b of the second conductivity type (n-type) having a carrier injection port for injecting carriers into the channel region and a carrier discharge port for discharging carriers from the channel region. An amplifying circuit in which a reset transistor TR _ij , a signal reading transistor (amplifying transistor) TA _ij, and a switching transistor TS _ij are integrated is configured.

The floating drain (FD) region of the transfer transistor TT _ij shown in FIG. 7 includes an intermediate gate electrode 26 that is a gate electrode of a signal readout transistor (amplification transistor) TA _ij and a first main electrode that is a source electrode of a reset transistor TR _ij. Connected to region 12. The first common main electrode region 14a functions as a region common to the drain region of the reset transistor _{TRij and} the drain region of the signal readout transistor (amplification transistor) _TAij , and is connected to the power supply VDD. The second common main electrode region 14b functions as a region common to the source region of the signal readout transistor (amplification transistor) _{TAij and} the drain region of the pixel selection switching transistor _TSij . The second main electrode region 13 which is a source region of the pixel selection switching transistor TS _ij is connected to _j vertical signal lines B _j , and i rows of horizontal lines are connected to the second gate electrode 24b which is a gate electrode. The vertical selection signal S _i is driven by a timing generation circuit (not shown) and supplied from a vertical shift register (vertical scanning circuit) (not shown).

  When the insulated gate semiconductor device according to the eighth embodiment is irradiated with ionizing radiation, regions PAa and PBa near the device isolation insulating film 21 below the first gate electrode 24a and the second gate electrode 24b, respectively; The threshold voltage of the gate shifts in the negative direction at PAb and PBb. However, since one end of each of the regions PAa, PBa; PAb, PBb is a leakage prevention region 61a, 62a; 61b, 62b made of a layer having a conductivity type opposite to the channel charge, the leakage prevention regions 61a, 62a; 61b, 62b are interposed. The current path is blocked. Therefore, even when ionizing radiation is irradiated, it is possible to almost completely prevent the leakage current from flowing.

(Other embodiments)
As described above, the present invention has been described according to the first to eighth embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In FIG. 4, two insulated gate semiconductor devices according to the first embodiment are opposed to each other by sharing the first main electrode region 12 as an insulated gate semiconductor integrated circuit according to the fourth embodiment of the present invention. Although the configuration has been described, two insulated gate semiconductor devices according to the second or third embodiment may be arranged in series instead of the insulated gate semiconductor device according to the first embodiment. .

In the description of the insulated gate semiconductor integrated circuit according to the fifth and sixth embodiments, as shown in FIGS. 5 and 6, the π-shaped first gate electrode 24a and the π-shaped second gate are used. a gate electrode disposed between the gate electrode 24b, is described as a plurality of intermediate gate electrode 26 _-1 ~ 26 _-m, intermediate gate electrode is not necessarily a multiple may be one.

Further, as an integrated circuit in which the reset transistor TR _ij shown in the F portion of the amplification type image sensor of FIG. 7, the signal readout transistor (amplification transistor) TA _ij, and the switching transistor TS _ij are integrated, an eighth circuit shown in FIG. In the insulated gate semiconductor integrated circuit according to the fifth embodiment, the insulated gate semiconductor integrated circuit according to the fifth and sixth embodiments shown in FIGS. 5 and 6 is used instead of the configuration shown in FIG. A single intermediate gate electrode may be used. In these cases, across one of the intermediate gate electrode 26 is the gate electrode of the signal reading transistor (amplification transistor) TA _ij, the first common main electrode region 14a and the second common main electrode region 14b In the meantime, carriers can avoid the region PAc in which a leak path is formed in the vicinity of the element isolation insulating film 21, and more reliably prevent a leak current from flowing.

  In the description of the first to eighth embodiments already described, the first conductivity type is p-type, the second conductivity type is n-type, and each insulated gate semiconductor element is an nMOS transistor. However, even when the first conductivity type is n-type and the second conductivity type is p-type, and each insulated gate semiconductor element is a pMOS-type transistor, the same effect can be obtained by reversing the electrical polarity. It will be easy to understand.

  In addition, the semiconductor integrated circuit can be applied to various semiconductor integrated circuits such as a semiconductor memory device, a miniaturized logic integrated circuit, and a system LSI other than the solid-state imaging device. It will be easy to understand.

  Furthermore, in the description of the first to eighth embodiments, the case of Si as the semiconductor material of the semiconductor layer 11 has been described. However, other than germanium (Ge), silicon carbide (SiC), diamond, gallium arsenide (GaAs), and the like. In this case, the technical idea of the present invention can be similarly applied. The semiconductor layer 11 is formed of Si, and the drain region (first main electrode region) 12 or the source region (second main electrode). It may be a Si-Ge heterojunction in which the (region) 13 is formed in Ge.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 5 ... Pixel 11, 51 ... Semiconductor layer 12, 12a ... 1st main electrode area | region 13 ... 2nd main electrode area | region 14, 141 ... Common main electrode area | region 14a ... 1st common main electrode area | region 14b ... 2nd common main electrode Region 15 ... Embedded region 18, 19 ... Leak prevention region 21 ... Element isolation insulating film 21B ... Active region 22 ... Gate insulating film 23 ... First main electrode wiring 24 ... Gate electrode 24P ... Gate electrode 24a ... First gate electrode 24b ... second gate electrode 25 ... interlayer insulation film 26 _-1 ~ 26 _-m ... intermediate gate electrode 27 ... second main electrode wiring 52 ... surface-buried region (first main electrode region)
53 ... Charge detection region (second main electrode region)
54 ... Pinning layer 61, 62, 61a, 62a, 61b, 62b ... Leakage prevention region 81 ... Gate electrode 82 ... Source / drain region 83 ... Drain / source region 86 ... Channel 88 ... Gate electrode 241, 242, 241a, 242a, 241b, 242b ... guard part

Claims (5)

A first conductivity type semiconductor layer at least partially forming a channel region;
An element isolation insulating film that at least surrounds the channel region and defines an active region above the semiconductor layer;
A first main electrode region of a second conductivity type provided in one of the active regions and injecting carriers into the channel region via a carrier injection port;
A second main electrode region of a second conductivity type provided on the other side of the active region and having a carrier discharge port for discharging the carriers from the channel region;
A gate insulating film provided on the surface of the active region;
A second main electrode region provided on the gate insulating film, having a main control portion orthogonal to the carrier flow path and two guard portions intersecting the main control portion so as to form a π-shape; A gate electrode surrounding three sides of
Between the guard part of the active region and the element isolation insulating film, a region separated from the first main electrode region via a region immediately below the main control unit, and immediately below the two guard portions the through spaced apart from said second main electrode region, are inserted respectively, the first conductivity type of the pair, and a leakage blocking region of high impurity concentration than the semiconductor layer, by the leakage preventing region, the element An insulated gate semiconductor device, wherein a current path from the first main electrode region to the second main electrode region formed in the vicinity of the isolation insulating film is blocked .   2. The insulated gate semiconductor device according to claim 1, wherein the first main electrode region is provided apart from the device isolation insulating film in a gate width direction.   Provided below the gate electrode is spaced apart from the element isolation insulating film, and further includes a second conductivity type buried region having a lower impurity density than the first main electrode region and the second main electrode region. The insulated gate semiconductor device according to claim 1, wherein: A first conductivity type semiconductor layer at least partially forming a channel region;
An element isolation insulating film that at least surrounds the channel region and defines an active region above the semiconductor layer;
A first main electrode region of a second conductivity type provided on one end side of the active region and injecting carriers into the channel region via a carrier injection port;
A second conductive type second main electrode region provided on the other end side of the active region and having a carrier discharge port for discharging the carriers from the channel region;
A gate insulating film provided on the surface of the active region;
A first main control unit provided on the gate insulating film and orthogonal to the carrier flow path; and two first guard units intersecting the first main control unit so as to form a π-shape; A first gate electrode surrounding three sides of the first main electrode region;
A second main control unit that is provided on the gate insulating film so as to face the first gate electrode and intersects the carrier flow path so as to form a π shape with the second main control unit 2 A second gate electrode having three second guard portions and surrounding three sides of the second main electrode region;
The active region is located between the first and second gate electrodes, is of a second conductivity type, functions as a second main electrode region with respect to the first main electrode region, and is formed in the second main electrode region. On the other hand, a common main electrode region that functions as the first main electrode region ;
Between the first guard part of the active region and the element isolation insulating film, the space is separated from the common main electrode region through a region immediately below the first main control unit, and the two first guard units A pair of first conductivity types that are spaced apart from the first main electrode region via a region immediately below the first main electrode region and have a higher impurity density than the semiconductor layer;
A space between the second guard portion of the active region and the element isolation insulating film is separated from the common main electrode region via a region immediately below the second main control portion, and the two second guard portions A pair of first conductivity types and a second leakage prevention region having a higher impurity density than the semiconductor layer, spaced apart from the second main electrode region via a region immediately below the first main electrode region , And the second leakage prevention region blocks a current path from the first main electrode region formed in the vicinity of the element isolation insulating film to the second main electrode region via the common main electrode region. A feature of an insulated gate semiconductor integrated circuit. A first conductivity type semiconductor layer at least partially forming a channel region;
An element isolation insulating film that at least surrounds the channel region and defines an active region above the semiconductor layer;
A first main electrode region of a second conductivity type provided on one end side of the active region and injecting carriers into the channel region via a carrier injection port;
A second conductive type second main electrode region provided on the other end side of the active region and having a carrier discharge port for discharging the carriers from the channel region;
A gate insulating film provided on the surface of the active region;
A first main control unit provided on the gate insulating film and orthogonal to the carrier flow path; and two first guard units intersecting the first main control unit so as to form a π-shape; A first gate electrode surrounding three sides of the first main electrode region;
A second main control unit that is provided on the gate insulating film so as to face the first gate electrode and intersects the carrier flow path so as to form a π shape with the second main control unit 2 A second gate electrode having three second guard portions and surrounding three sides of the second main electrode region;
A plurality of intermediate gate electrodes arranged respectively apart from between the first gate electrode and the second gate electrode,
Positioned between the first gate electrode and any of the plurality of intermediate gate electrodes, between each of the plurality of intermediate gate electrodes, and between any of the plurality of intermediate gate electrodes and the second gate electrode. A plurality of second conductive type common main electrode regions provided apart from the element isolation insulating film in the active region ;
A space between the first guard portion of the active region and the element isolation insulating film is spaced from the common main electrode region via a region immediately below the first main control unit, and two first guard portions A pair of first conductivity types that are spaced apart from the first main electrode region via a region directly below, respectively, and a first leakage prevention region having a higher impurity density than the semiconductor layer;
A space between the second guard portion of the active region and the element isolation insulating film is separated from the common main electrode region via a region immediately below the second main control portion, and the two second guard portions A pair of first conductivity types and a second leakage prevention region having a higher impurity density than the semiconductor layer, spaced apart from the second main electrode region via a region immediately below the first main electrode region , And a second leakage prevention region blocks a current path from the first main electrode region formed in the vicinity of the element isolation insulating film to the second main electrode region via the plurality of common main electrode regions. An insulated gate semiconductor integrated circuit.