JP5552521B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, a non-volatile semiconductor memory device that can hold data by accumulating electric charges in a gate insulating film and that can hold data and can be rewritten. It relates to a manufacturing method.

  Semiconductor memories are broadly classified into volatile types in which information is lost when the power is erased and non-volatile types in which information is retained even when the power is turned off. As a typical example of the latter nonvolatile memory, a flash memory is known in which data erasure is performed all at once to shorten the rewriting time.

In recent years, multi-value cell structures having a MNOS (Metal (gate) -Nitride-Oxide-Silicon) structure and a SONOS (Silicon (gate) -Oxide-Nitride-Oxide-Silicon) structure have been proposed as new cell structures of nonvolatile memories. Has been. In these structures, an ON (Oxide-Nitride) structure or ONO (Oxide-Nitride-Oxide) structure is adopted as the structure of the gate insulating film directly under the gate electrode, and a nitride film (near the source / drain of the transistor) The charge accumulated in the (Si ₃ N ₄ film) is localized and accumulated in different regions in the film, thereby increasing the number of values, thereby increasing the capacity of the cell and reducing the bit cost. For example, when two charge localized regions in the Si ₃ N ₄ film are provided, it is possible to store 2-bit (2 bits / cell) data in one cell.

  The floating gate structure employed in the conventional nonvolatile memory is a structure in which electric charges are accumulated by sandwiching conductive polycrystalline silicon between insulating films such as a silicon oxide film. Since it is a conductor, there may be a problem that data is lost due to leakage of charges, whereas in the MNOS structure or SONOS structure, charges are accumulated in the nitrogen compound of the insulating layer, so that such a problem does not occur. There is a big advantage.

  1A and 1B are cross-sectional views of a memory for explaining a conventional example of a method for manufacturing a multi-value cell memory having a gate portion of a SONOS structure and a source / drain portion of a buried bit line structure. FIG. The core region, FIG. 1B, illustrates the memory periphery.

  In the core region of the memory, for example, n-type diffusion regions 102 provided as bit lines by As diffusion, for example, are provided at predetermined intervals on the main surface of the p-type semiconductor substrate 100. A space between the n-type diffusion regions 102 is a channel region. A tunnel oxide film 103 having a uniform thickness is formed on the channel region and the n-type diffusion region 102. A nitride film 104, an upper oxide film 105, and a control gate (not shown) are sequentially stacked on the tunnel oxide film 103, and a gate portion is constituted by these four layers. The nitride film 104 is an electrically insulating film, and electrons injected through the tunnel oxide film 103 are accumulated in the nitride film 104.

  In the conventional memory using the floating gate of the conductor, the electrons injected through the tunnel oxide film are spatially distributed so as to have a uniform electric field distribution in the floating gate. As a result, only one bit is formed for one cell. On the other hand, in a memory having a gate portion of an MNOS structure or a SONOS structure, electrons injected into the nitride film 104 as an insulating film are localized and accumulated in the nitride film 104 without being diffused, thereby increasing the number of bits. (Multi-value). Note that channel ion implantation 101 is performed on the p-type semiconductor substrate 100 in the core region for the purpose of adjusting the threshold value of each bit.

  On the other hand, in the memory peripheral portion (peripheral circuit portion), well regions 106 are provided on the main surface of the semiconductor substrate 100 at predetermined intervals. Between these well regions 106, a thinly formed oxide film 108 is locally thickened to form a LOCOS 107 for element isolation. Note that a nitride film 104 and an upper oxide film 105 are sequentially stacked on the oxide film 108 and the LOCOS 107.

  Such a multi-value cell can be manufactured by the following procedure, for example. First, a thin oxide film is formed on the main surface of the semiconductor substrate 100, and a well region 106 is formed in the peripheral circuit portion by ion implantation. More specifically, for example, a resist is applied to a thin oxide film formed on the surface of the semiconductor substrate 100 and patterned, and the well region 106 is formed by ion implantation using the resist pattern as a mask.

  Next, a LOCOS 107 for element isolation is formed in the peripheral circuit portion. For example, a SiN film is formed on the semiconductor substrate 100, a resist is coated thereon and patterned to form a resist pattern for forming an element isolation LOCOS, and the SiN film is etched using this as a mask. Then, the semiconductor substrate 100 is locally oxidized through the opening to form the LOCOS 107, and the SiN film remaining in the core region after removing the resist is removed.

  Further, a resist is applied and patterned, and ions are implanted into the opening using the resist pattern as a mask. Thereby, channel ion implantation 101 for adjusting the threshold value into the core region is executed.

  Subsequently, the resist and the thin oxide film are removed to form the tunnel oxide film 103 and the charge storage nitride film 104, and only the portion where the n-type diffusion region 102 (bit line diffusion layer) is formed by resist patterning. And an n-type diffusion region 102 is formed by ion implantation.

  Finally, the resist is removed and an upper oxide film 105 is deposited on the nitride film 104.

  Writing to a multi-value cell having such a SONOS structure is performed independently for each of a plurality of bits provided in one cell, so that the capacity of the cell and the bit cost can be reduced. It will be.

  However, in a multi-value cell having a conventional structure having an MNOS structure or a SONOS structure, since the tunnel oxide film is uniformly formed with a uniform thickness, the charge depends on the electron injection position determined by the potential gradient of the source region and the drain region. The storage location is determined. However, as data writing progresses and the amount of charge accumulated in each bit increases, the bit region that accumulates a large amount of charge tends to gradually spread from the vicinity of the drain to the center of the channel in the nitride film. Such a bit area spread acts in the same way as other bits that store only a small amount of charge in the same way that charges exceeding the actual charge storage amount are stored, and the threshold value of that bit. As a result, there is a problem that a data read error occurs.

  The present invention has been made in view of such a problem, and the object of the present invention is to perform normal write operation on a plurality of bits provided in the same cell without depending on the write amount to other bits. Furthermore, another object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that enable further miniaturization of a SONOS structure cell without impairing write / read characteristics.

  In order to solve such a problem, the present invention provides a gate unit including a substrate having a pair of first diffusion regions, an oxide film formed on the substrate, and a charge storage layer formed on the oxide film; And the charge storage layer is an electrical insulating film having a plurality of bit regions spaced apart from each other in the charge storage layer, and the oxide film has a portion corresponding to each of the bit regions formed by tunnel oxidation. The semiconductor device includes a thin film portion having a thickness that acts as a film, and a thick film portion having a thickness in which a portion located between the bit regions suppresses charge transport due to a tunnel effect.

  In the semiconductor device, each of the pair of first diffusion regions is a source / drain region which becomes a source region or a drain region according to a bias condition, and the pair of first diffusion regions is symmetrical to both ends of the channel region. It is preferable to be provided.

  In the semiconductor device, it is preferable that a threshold adjustment region for adjusting a threshold value of the bit region is provided on the substrate.

  In the semiconductor device, a second diffusion region may be provided over the entire surface vicinity region of the substrate. The second diffusion region may be provided between the pair of first diffusion regions. In this case, it is preferable that the second diffusion region is provided independently of the pair of first diffusion regions. The second diffusion region is preferably spaced from the pair of first diffusion regions, and is provided only in the center of the channel region. The second diffusion region is preferably provided extending vertically downward from the surface of the substrate.

  The threshold adjustment region described above is preferably a region formed by ion implantation.

  Furthermore, the first diffusion region may have a buried bit line structure, and a plurality of the pair of first diffusion regions may be arranged.

  In the semiconductor device, for example, the substrate may be silicon, the oxide film may be a silicon oxide film, and the charge storage layer may be a silicon nitride film. In this case, the gate unit has, for example, an MNOS structure or a SONOS structure.

  In the semiconductor device, for example, the dopant in the second diffusion region is boron, and the dopant in the first diffusion region is arsenic.

  The present invention also includes a first step of forming a tunnel oxide film having a uniform thickness on the substrate surface, and a second step of forming a pair of first diffusion regions on the substrate surface below the tunnel oxide film. And a third step of depositing a surface protective film on the pair of first diffusion regions and on the tunnel oxide film, and reoxidizing the substrate surface exposed through the surface protective film. And a fourth step of forming, by self-alignment, an oxide film having a thickness that suppresses charge transport due to the tunnel effect.

  In this manufacturing method, the oxidation in the first and fourth steps is performed by, for example, thermal oxidation or plasma oxidation.

  Moreover, it can be set as the structure provided with the 5th step which forms the 2nd diffusion area | region which extends perpendicularly | vertically from the said substrate surface in the said board | substrate between said pair of 1st diffusion areas. In this case, it is preferable that the fifth step is executed by self-alignment using a sidewall of the first surface protective film. The second diffusion region is preferably formed by ion implantation.

  In the manufacturing method, the second step includes a step of forming a patterned resist having a window provided with a sidewall, and the pair of first diffusion regions are self-aligned using the sidewall. Preferably it is formed. In this case, the first diffusion region is preferably formed by ion implantation.

  The tunnel oxide film included in the semiconductor device of the present invention is formed so as to have both end portions formed thin so as to perform data writing / erasing and a channel center portion formed thick so as not to tunnel electrons. ing. As a result, the threshold value of each bit arranged across the center of the channel is not affected by the amount of charge accumulated in other bits, and the threshold value fluctuation (rise) of each bit does not occur. Can solve the problem of read error. In addition, the write / erase operation for each bit provided in the same cell can be normally executed without depending on the charge accumulation amount of other bits.

  In addition, since the semiconductor device of the present invention forms the ion implantation region for threshold adjustment using the sidewall nitride film as a mask, ions of any energy and / or dose amount can be used as channel adjustment channel ions. It is possible to accurately inject only into the injection region, and it is possible to improve the write characteristics and the read characteristics.

  Furthermore, in the semiconductor device of the present invention, since the diffusion region is formed using the sidewall nitride film as a mask, the diffusion region can be formed with high positional accuracy, and the write characteristics and read characteristics can be improved. Further miniaturization can be achieved without loss.

1A is a cross-sectional view of a core region of a memory for explaining a conventional example of a method for manufacturing a multi-value cell memory having a gate portion of a SONOS structure and a source / drain portion of a buried bit line structure, and FIG. FIG. 5 is a cross-sectional view of a peripheral region of a memory for explaining a conventional example of a method for manufacturing a multi-value cell memory having a gate portion of a SONOS structure and a source / drain portion of a buried bit line structure. 2A is a cross-sectional view of a cell for explaining an example of the basic structure of the semiconductor device of the present invention, and FIG. 2B is a schematic cross-sectional view of a core region for explaining the operating principle of the semiconductor device of the present invention. FIG. 2C is a schematic cross-sectional view of the peripheral region of the cell for explaining the operation principle of the semiconductor device of the present invention. 3A is a cross-sectional view of a core region for explaining a first configuration example of a semiconductor device of the present invention having a gate portion of a SONOS structure and a source / drain portion of a buried bit line structure, and FIG. 1 is a cross-sectional view of a peripheral region of a cell for explaining a first configuration example of a semiconductor device of the present invention having a gate portion of a SONOS structure and a source / drain portion of a buried bit line structure. 4A to 4C are diagrams for explaining a manufacturing process of the semiconductor device shown in FIGS. 3A and 3B. FIGS. 5D to 5F are views for explaining a manufacturing process of the semiconductor device shown in FIGS. 3A and 3B. FIGS. 6G to 6I are views for explaining a manufacturing process of the semiconductor device shown in FIGS. 3A and 3B. FIG. 7A is a cross-sectional view of a core region for explaining a second configuration example of the semiconductor device of the present invention having a gate portion of a SONOS structure and a source / drain portion of a buried bit line structure, and FIG. FIG. 6 is a cross-sectional view of a peripheral region of a cell for explaining a second configuration example of a semiconductor device of the present invention having a gate portion of a SONOS structure and a source / drain portion of a buried bit line structure. 8A to 8C are views for explaining a manufacturing process of the semiconductor device shown in FIGS. 7A and 7B. FIGS. 9A to 9D are diagrams for explaining a process of forming an n-type diffusion region according to the third embodiment.

  The basic configuration of the semiconductor device of the present invention will be described below with reference to the drawings. In the following description, the structure of the gate portion is mainly described as a SONOS structure. However, the gate portion may be formed by stacking an oxide film, a charge storage layer, and a gate electrode, and may be a gate having another structure such as a MONS structure. It is good also as a part. In the following description, it is assumed that the semiconductor substrate is silicon, the oxide film is a silicon oxide film, and the charge storage layer is a silicon nitride film.

  2A is a cross-sectional view of a cell for explaining an example of the basic structure of the semiconductor device of the present invention, and FIGS. 2B and 2C are schematic cross-sectional views of the cell for explaining the operating principle of the semiconductor device of the present invention.

  In this semiconductor device, for example, n-type diffusion regions 6 a and 6 b provided by, for example, As diffusion on the main surface of a p-type semiconductor substrate 1 are provided at predetermined intervals. A channel region is formed between the n-type diffusion regions 6a and 6b. A tunnel oxide film 2 having a thick central portion 2b and thin end portions 2a is formed on the channel region, and both end portions 2a are formed on the n-type diffusion regions 6a and 6b. positioned. The tunnel oxide film 2 has both end portions 2a having a thin film thickness acting as a tunnel oxide film and a central portion 2b having a film thickness for suppressing charge transport due to the tunnel effect. Call it 2.

  On the tunnel oxide film 2, a nitride film 3, a silicon oxide film 4 and a control gate 5 are sequentially laminated, and a gate portion is constituted by these four layers. The nitride film 3 is an electrically insulating film, and has a plurality of bit regions that are spaced apart from each other in the charge storage layer. Electrons injected through the tunnel oxide film are accumulated in the nitride film 3.

  In a conventional device using a floating gate of a conductor, electrons injected through the tunnel oxide film 2a are spatially distributed so as to have a uniform electric field distribution in the floating gate. As a result, only one bit is formed for one cell, whereas in a semiconductor device having a SONOS structure gate as shown in FIG. 2A, implantation is performed on the nitride film 3 as an insulating film. The electrons thus accumulated are localized and accumulated in the nitride film 3 without diffusing.

  Specifically, when the n-type diffusion region 6a is a source region and the n-type diffusion region 6b is a drain region (see FIG. 2B), electrons (indicated by black circles in the figure) are emitted from the right end 2a of the tunnel oxide film 2. And are accumulated in the charge accumulation region 3b. Conversely, when the n-type diffusion region 6b is the source region and the n-type diffusion region 6a is the drain region (see FIG. 2C), electrons are injected through the left end 2a of the tunnel oxide film 2. And stored in the charge storage region 3a. That is, each of the pair of n-type diffusion regions provided apart from each other by a predetermined interval is a source / drain region that becomes a source region or a drain region depending on the bias condition.

  As described above, it is possible to form the two charge storage regions 3a and 3b in one cell. As a result, two bits are formed per cell, and the capacity of the cell is increased and the bit cost is reduced. Figured. In addition to such a basic configuration, an ion implantation region may be provided in the channel region for threshold adjustment of each bit.

  Here, in the semiconductor device of the present invention, since the film thickness of the channel central region of the tunnel oxide film 2 is set larger than the film thickness of the write region near the drain, the electric field in the gate direction at the channel central portion is set. Becomes weaker, and writing in that part is not performed. As a result, the region where writing is performed is limited to the drain region where the tunnel oxide film is thinly formed, and the charge accumulation amount between a plurality of charge accumulation regions (bits) provided in the same cell is reduced. It is possible to eliminate the threshold fluctuation caused and to realize a normal read operation.

  By the way, in Japanese Patent Publication No. 2001-148430, the thickness of the tunnel oxide film provided under the floating gate is not uniform, and a thick convex part is provided at the center part and the film thickness is provided at both ends thereof. An invention of a nonvolatile semiconductor memory device having a thin end portion is disclosed. With such a tunnel oxide film shape, it can be performed without reducing the speed of data writing and erasing at the edge where the oxide film is thin, while other regions, that is, charge injection and extraction. Since the thickness of the oxide film is increased in the central part where it does not contribute, the leakage of charges in the floating gate can be suppressed to a very small level even when a potential difference occurs between the well region and the control gate. It is described that the charge retention characteristics can be improved without impairing the injection and extraction characteristics.

  The configuration of the semiconductor device described in the above publication differs greatly from the configuration of the semiconductor device of the present invention in the following points.

  First, the semiconductor device described in the above publication is a non-volatile semiconductor memory device such as a flash memory having a floating gate, and the charge accumulated in this device is distributed over the entire conductive floating gate. The cell has one charge storage region. On the other hand, in the semiconductor device of the present invention, the gate insulating film has an ONO structure (or ON structure), and charges are accumulated in the nitride film of the insulator constituting the gate insulating film. The cell has two or more charge storage areas.

  Secondly, in the nonvolatile semiconductor memory device having the floating gate described in the above publication, one of two diffusion regions forming a channel therebetween is a source region and the other is a drain region. In this semiconductor device, both of the two diffusion regions forming the channel are both the source region and the drain region.

  Third, the shape (and effect) of the tunnel oxide film differs due to the difference in the configuration of the semiconductor device, which is the first difference. Specifically, the convex shape at the center of the tunnel oxide film described in the above publication is a shape for better holding the charge accumulated in the floating gate, which is a conductive layer, and the effect of improving the holding characteristics by this shape. It plays. On the other hand, according to the present invention, a thin film portion having a film thickness in which a portion corresponding to each of a plurality of bit regions positioned separately in a charge storage layer which is an insulating film acts as a tunnel oxide film, The portion located between the regions has a thick film portion with a film thickness that suppresses the charge transport due to the tunnel effect. With this configuration, between the plurality of charge accumulation regions (bits) provided in the same cell There is an effect of eliminating the threshold fluctuation caused by the amount of accumulated charges and realizing a normal read operation.

  Due to such a difference in configuration and effect, the manufacturing methods of these semiconductor devices inevitably differ. That is, when forming the tunnel oxide film convex portion of the semiconductor device described in the above publication, a region in which nitrogen is implanted into the surface of the silicon substrate by a mask process in advance and a region in which nitrogen is not implanted are provided, and the difference in nitrogen concentration in the silicon crystal is provided. A thick oxide film portion formed in a region where nitrogen is not implanted using the difference in the oxide film growth rate caused by the above is a convex portion. Therefore, the positional accuracy of the formed convex portion is limited to about +/− 40 nm which is the alignment accuracy of the stepper.

  On the other hand, in the semiconductor device of the present invention, since both of the two diffusion regions forming the channel are the source region and the drain region, the film thickness is high-precision at the center of the tunnel oxide film. It is necessary to form a thick part. Therefore, the thick part of the tunnel oxide film is formed by self-alignment without depending on the mask process. Thereby, a thick region of the tunnel oxide film is formed at an equal distance from the source / drain diffusion region. A specific example of the method for manufacturing a semiconductor device according to the present invention will be described in detail in the embodiments described later.

Hereinafter, the best mode for carrying out the present invention will be described by way of examples.
Example 1
3A and 3B are cross-sectional views of a cell for explaining a first configuration example of a semiconductor device of the present invention having a gate portion of a SONOS structure and a source / drain portion of a buried bit line structure, and FIG. 3A shows a core FIG. 3B illustrates the state of the cell peripheral region. A plurality of cells are arranged in the core region, and each of these cells has the basic configuration shown in FIG. 2A and performs the operation described based on FIGS. 2B and 2C.

  4A to 6I are diagrams for explaining the manufacturing process of the semiconductor device. The left diagram shows the core region and the right diagram shows the cell peripheral region.

  In this core region, for example, n-type diffusion regions 12 provided as bit lines by, for example, As implantation are provided at predetermined intervals on the main surface of the p-type semiconductor substrate 10. Acts as a source / drain region. Further, a channel region is formed between the n-type diffusion regions 12.

  A tunnel oxide film 13 is provided on the channel region and the n-type diffusion region 12, and the tunnel oxide film 13 on the n-type diffusion region 12 is formed thin enough to write data by the tunnel effect. On the other hand, the tunnel oxide film 13 on the channel region is formed thick so as to suppress charge transport due to the tunnel effect (13b). The thickness of the thin portion 13a of the tunnel oxide film 13 is, for example, about 7 nm.

  On the tunnel oxide film 13, a charge storage nitride film 14, an upper oxide film 15, and a control gate (not shown) are sequentially stacked, and a gate portion is constituted by these four layers. The nitride film 14 is an electrically insulating film, and has a thickness of, for example, about 12 nm. Electrons injected through the thin portion 13a of the tunnel oxide film are accumulated locally in the nitride film 14 and accumulated in multiple bits. It is planned. Further, for example, channel ion implantation 11 of B ions is performed on the semiconductor substrate 10 in the core region for the purpose of adjusting the threshold value of each bit.

  On the other hand, well regions 16 are provided on the main surface of the semiconductor substrate 10 at predetermined intervals in the cell peripheral region (peripheral circuit portion). A thinly formed oxide film 18 is locally thickened between the well regions 16 to form a LOCOS 17 for element isolation. A nitride film 14 and an upper oxide film 15 are sequentially stacked on the oxide film 18 and the LOCOS 17.

  Such a multi-value cell can be manufactured by the following procedure, for example. First, a thin oxide film 18 (thickness of about 7 nm) is uniformly formed on the main surface of the semiconductor substrate 10, and a resist is coated on the oxide film 18 to provide an opening at a predetermined position in the peripheral area of the cell. To pattern. Then, ion implantation is performed using this resist pattern as a mask to form the well region 16.

  Next, after forming a SiN film (not shown) on the semiconductor substrate 10 and forming a resist pattern having an opening at a predetermined position in the cell peripheral region thereon, the SiN film is etched from the opening using this as a mask, The LOCOS 17 is formed by locally oxidizing the semiconductor substrate 10 through the opening. After the LOCOS 17 is formed, the resist pattern is peeled off and the SiN film remaining in the core region is removed (FIG. 4A).

Following the formation of the LOCOS 17, a resist pattern having an opening in the core region is formed, B is ion-implanted (40 keV) at a desired dose (for example, 6 × 10 ¹² cm ⁻² ), and channel ion implantation 11 for threshold adjustment is performed. Run.

After the resist is peeled off, a polysilicon layer of 200 nm is deposited on the entire surface, and a part of the polysilicon layer 19 in the core region is etched away by photolithography using the resist pattern for bit line formation as a mask, and the remaining polysilicon layer 19 is used as a mask. A desired dose (for example, 2 × 10 ¹⁵ cm ⁻² ) of As is ion-implanted (70 keV) from the opening to provide an n-type diffusion region 12 as a bit line (FIG. 4B).

  Further, a first sidewall nitride film 20 is deposited to a thickness of 300 nm (FIG. 4C), and this sidewall nitride film 20 is etched until the surface of the polysilicon 19 is exposed (FIG. 5D). The polysilicon 19 is etched away so as to leave only. Thereby, the polysilicon 19 in the cell peripheral region is almost completely removed (FIG. 5E).

  Next, a second sidewall nitride film 21 is deposited to a thickness of 100 nm to cover the entire surface (FIG. 5F), and the sidewall nitride film 21 (and a part of 20) is etched to obtain a final sidewall nitride film 22. (FIG. 6G). At this time, by controlling the final thickness of the sidewall nitride film 22, the width of the opening to be provided between the sidewall nitride films 22 can be set.

  Following this, the oxide film 18 located in the opening between the sidewall nitride films 22 is etched to expose the surface of the semiconductor substrate 10, and this portion has an appropriate film thickness enough to suppress charge transport due to the tunnel effect. Oxidize to become As a result, the portion of the oxide film 18 that remains without being etched becomes the thin film portion 13a (thickness of about 7 nm) of the tunnel oxide film 13, and the thickly oxidized portion becomes the thick film portion 13b of the tunnel oxide film 13. In this manner, the tunnel oxide film 13 included in the semiconductor device of the present invention is formed in the core region (FIG. 6H). The oxidation at this time may be normal thermal oxidation, or may be based on low-temperature, low-damage plasma oxidation.

  Finally, the sidewall nitride film 22 is removed, and the nitride film 14 and the upper oxide film 15 are sequentially formed on the entire surface of the core region and the peripheral portion. The nitride film 14 at this time is a film having a film thickness of, for example, 12 nm formed by the CVD method, and serves as a charge accumulation region in the core region. The thickness of the upper oxide film 15 is, for example, 11.5 nm, and is formed by a CVD method or a plasma oxidation method with low temperature and low damage (FIG. 6I).

In this way, the semiconductor device of the present invention illustrated in FIGS. 3A and 3B is obtained.
(Example 2)
7A and 7B are cell cross-sectional views for explaining a second structural example of the semiconductor device of the present invention. FIG. 7A shows a core region and FIG. 7B shows a cell peripheral region. 8A to 8C are diagrams for explaining the manufacturing process of the semiconductor device, in which the left diagram shows the state of the core region and the right diagram shows the cell peripheral region.

  The structure of the cell peripheral region of this semiconductor device is the same as the first configuration example shown in FIG. 3B. In addition, the structure of the core region is that the threshold adjustment ion implantation 11 is performed on the entire surface of the semiconductor substrate 10 in the first configuration example shown in FIG. As shown in FIG. 7A, the difference is that the threshold adjustment ion implantation 11 is provided only in the channel region located between the n-type diffusion regions 12. This is because the threshold adjustment ion-implanted region 11 shown in the first embodiment is formed by ion-implanting B into the entire surface of the substrate in the core region, so that the n-type diffusion region 12 formed by diffusing As. It is a device for solving the problem that the donor is compensated.

  That is, in this semiconductor device, n-type diffusion regions 12 provided as bit lines by As implantation are provided on the main surface of the p-type semiconductor substrate 10 at predetermined intervals. A channel ion implantation of B ions is performed in the channel region between them for the purpose of adjusting the threshold value of each bit, and a threshold adjustment ion implantation region 11 extending in the vertical direction from the surface of the semiconductor substrate 10 is provided.

  Such a multi-value cell can be manufactured by the following procedure, for example. Note that the steps until the well region 16 is formed in the periphery of the cell are the same as those in the first embodiment, and thus the description thereof is omitted.

  In this embodiment, after the n-type diffusion region 12 is formed in the core region, the threshold adjustment ion implantation region 11 is formed. Specifically, polysilicon 19 is deposited, and a polysilicon mask for forming a bit line is formed by photolithography. Then, As is ion-implanted from the opening of the polysilicon mask to form the n-type diffusion region 12 (FIG. 8A). The As ion implantation conditions are the same as in Example 1.

Next, a nitride film sidewall 22 is formed by a process similar to that of the first embodiment, and B is ion-implanted from an opening between the sidewalls 22 to provide a threshold adjustment ion-implanted region 11 (FIG. 8B). Since the bit line is covered with a nitride film having a thickness of about 200 nm, B implanted at an acceleration voltage of 80 keV or less does not pass through this nitride film. Therefore, it is possible to ion-implant B having a dose of 6 × 10 ¹² cm ⁻² only in the vicinity of the channel center of the core region with an acceleration voltage of 40 keV. In addition, since ion implantation is performed by self-alignment using the nitride film sidewalls 22 without depending on the mask process, the threshold adjustment ion implantation region 11 to be formed can be positioned with high accuracy.

  By controlling the thickness of the sidewall nitride film 22, the width of the opening provided between the sidewall nitride films 22 can be set, thereby reducing the width of the threshold adjustment ion implantation region 11. It is possible to control.

  The subsequent processes are the same as those described in the first embodiment, and the oxide film 18 located in the opening of the sidewall nitride film 22 is removed and re-oxidized, whereby the thin film portion 13a (film thickness of about 7 nm) is obtained. After the tunnel oxide film 13 formed of the thick film portion 13b is formed and the sidewall nitride film 22 is removed, an insulator nitride film 14 for charge storage and an upper oxide film 15 are sequentially stacked on the tunnel oxide film 13. (FIG. 8C).

  In this way, the semiconductor device of the present invention illustrated in FIGS. 7A and 7B is obtained.

In the semiconductor device of this embodiment, the threshold adjustment ion implantation region 11 is formed by using the sidewall nitride film 22 as a mask, so that ions of any energy and / or dose amount can be supplied to the threshold adjustment channel. It is possible to accurately implant only into the ion implantation region 11, and it is possible to improve the write characteristics and the read characteristics.
(Example 3)
The configuration of the semiconductor device of this embodiment is the same as that shown in FIGS. 7A and 7B, but the formation process of the n-type diffusion region is different.

  9A to 9D are diagrams for explaining the formation process of the n-type diffusion region of the present embodiment. In each figure, the left diagram shows the core region and the right diagram shows the cell peripheral region.

  First, a thin oxide film 18 (film thickness of about 7 nm) is uniformly formed on the main surface of the semiconductor substrate 10, and after depositing a polysilicon 19 on the oxide film 18, a part of the polysilicon 19 is formed by photolithography. The region is etched to form openings with a predetermined interval (FIG. 9A).

  Next, after a nitride film is uniformly deposited, etching is performed to form sidewall nitride films 23 on both sides of the polysilicon 19 provided on the thin oxide film 18 at regular intervals. Then, As is ion-implanted from the opening between the sidewalls to form an n-type diffusion region 12 that is a bit line (FIG. 9B). Here, by controlling the film thickness of the sidewall nitride film 23, the width of the opening provided between the sidewall nitride films 23 can be set, thereby controlling the width of the bit line. Is possible.

  Subsequently, a nitride film sidewall 22 is formed by the same process as in Examples 1 and 2, and B is ion-implanted from the opening between the sidewalls 22 to provide a threshold adjustment ion implantation region 11. The oxide film 18 located in the opening of the sidewall nitride film 22 is removed and reoxidized to form the tunnel oxide film 13 composed of the thin film portion 13a and the thick film portion 13b (FIG. 9C).

  Finally, the sidewall nitride film 22 is removed, and a nitride film 14 and an upper oxide film 15 of a charge storage insulator are sequentially stacked on the tunnel oxide film 13 (FIG. 9D).

  The threshold adjustment ion implantation region 11 may be formed before or after the above-described bit line formation process.

  In the semiconductor device of this embodiment, the n-type diffusion region 12 which is a bit line is formed using the sidewall nitride film 23 as a mask, so that the n-type diffusion region can be formed with high positional accuracy. Therefore, further miniaturization can be achieved without impairing the write characteristics and the read characteristics.

  According to the present invention, a write operation to each of a plurality of bits provided in the same cell is normally executed without depending on the charge accumulation amount of other bits, and moreover, multi-value without impairing write / read characteristics. A semiconductor device and a method for manufacturing the same are provided.

Claims (6)

A first step of forming a uniform thickness tunnel oxide on the substrate surface;
A second step of forming a pair of first diffusion regions on the substrate surface under the tunnel oxide film;
A third step of depositing a surface protection film on the pair of first diffusion regions and on the tunnel oxide film;
A fourth step of self-aligning an oxide film having a thickness that suppresses charge transport due to a tunnel effect by reoxidizing the substrate surface exposed through the surface protective film, and
The second step includes forming a patterned resist having a window provided with sidewalls;
The pair of first diffusion region, a method of manufacturing a semiconductor device that will be formed in self-alignment with the side wall.   The method of manufacturing a semiconductor device according to claim 1, wherein the oxidation in the first and fourth steps is performed by thermal oxidation or plasma oxidation.   3. The semiconductor device manufacturing method according to claim 1, further comprising a fifth step of forming a second diffusion region extending perpendicularly from a surface of the substrate in the substrate between the pair of first diffusion regions. Method.   The method of manufacturing a semiconductor device according to claim 3, wherein the fifth step is performed by self-alignment using a sidewall of the surface protective film.   The method of manufacturing a semiconductor device according to claim 3, wherein the second diffusion region is formed by ion implantation. The first diffusion region, a method of manufacturing a semiconductor device according to any one of claims 1 5 which is formed by ion implantation.

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