JP5549820B2 - Triplexa - Google Patents

Description

  The present invention relates to a triplexer, and more particularly to a circuit configuration of a triplexer and an arrangement structure of circuit elements in a chip.

  In recent years, wireless communication devices, particularly portable wireless communication devices such as mobile phones, smartphones, and notebook personal computers, have been provided that can support a plurality of communication frequency bands with the progress of high functionality and multi-function. For example, in addition to the 800 MHz band, 1.7 GHz band, and 2 GHz band used in mobile phones, GPS (Global Positioning System) 1.5 GHz band, wireless LAN 2.4 GHz band, high-speed wireless LAN 5 GHz band, etc. This is a device that can simultaneously use a telephone call, data communication, GPS function, etc. using different frequency bands.

  In such a multiband device, a triplexer is used to separate a high-frequency signal received from an antenna into each frequency band. This triplexer combines a high-pass filter (hereinafter referred to as “HPF”), a low-pass filter (hereinafter referred to as “LPF”), and a band-pass filter (hereinafter referred to as “BPF”). Is divided into signals of three different frequency bands and output, and is generally provided as a single chip component using a multilayer substrate.

  As a circuit configuration of the triplexer, for example, as shown in FIG. 13, three matching lines 51, 52, 53 and three filters 54, 55, 56 are connected in parallel, or two filters as shown in FIGS. Conventionally, a method of connecting diplexers 63, 66, 73, and 76, which are a combination of 61 to 62, 64 to 65, 71 to 72, and 74 to 75, in two stages in series has been adopted.

  Further, there is the following patent document as a disclosure of a triplexer.

JP 2003-198309 A JP 2006-108824 A Japanese Patent No. 4428292 Japanese Patent No. 4442056 Japanese Patent No. 4842245

  By the way, the conventional triplexer leaves room for further improvement in that a small size and a low profile and good characteristics (low insertion loss and high demultiplexing performance in each frequency band) are realized at the same time.

  Specifically, the circuit configuration shown in FIG. 13 includes matching lines 51, 52, and 53 for each of the filters 54 to 56 in addition to the three filters 54, 55, and 56. It is difficult to realize a tall chip. On the other hand, in the configuration example shown in FIG. 14, the first output P1 and the second output P2 are shown, and in the configuration example shown in FIG. 15, the second output P2 and the third output P3 are shown as the filter 61, respectively. , 64, 65, 72, 74, and 75 are stacked in two stages, so that the insertion loss is inevitably increased.

  14 and 15 use two diplexers 63, 66; 73, 76, so that the number of elements increases, which is disadvantageous in terms of small size and low profile as in the case of FIG. When two diplexers 63, 66; 73, 76 are arranged in one chip component, the inductors and capacitors constituting the diplexers 63, 66; 73, 76 come close to each other or are on the same conductor layer. Therefore, it is difficult to obtain high isolation characteristics (demultiplexing performance) due to coupling between elements. Furthermore, the invention described in the patent document includes the same problems, and these problems cannot be solved.

  Therefore, the object of the present invention is to simplify the circuit configuration of the triplexer, and further devise the arrangement of each element in the chip, so that the insertion loss is small and low in profile, and high isolation characteristics are provided for each frequency band. The point is to realize a triplexer.

  In order to solve the above problems and achieve the object, a triplexer according to the present invention is a triplexer that separates an input signal into signals of three different frequency bands and outputs the signals separately from each other, and is capable of inputting the input signal. A first port that outputs a signal in a first frequency band, a second port that outputs a signal in a second frequency band higher than the first frequency band, and a second port higher than the second frequency band. A third port that outputs a signal of the third frequency band, a first filter that passes the signal of the first frequency band, a second filter that passes the signal of the second frequency band, and the third filter A third filter for passing a signal in the frequency band; and a signal in the first frequency band and a signal in the second frequency band are allowed to pass while the third filter is open. The first filter is connected between the input port and the first port via the matching line, and the second filter is connected to the input port via the matching line. The third filter is connected between the input port and the third port. The third filter is connected between the input port and the third port.

  The pass frequency band (first frequency band) of the first filter is f1, the pass frequency band (second frequency band) of the second filter is f2, and the pass frequency band (third frequency band) of the third filter is In the case of f3 (f1 <f2 <f3), in the triplexer of the present invention, the matching line passes the signals of f1 and f2 input from the input port, while the third filter The signals of f1 and f2 are blocked, and transmission to the third port side is blocked.

  Further, the first filter passes the signal of f1 that has passed through the matching line, but the second filter blocks the signal of f1. Therefore, the signal of f1 input from the input port passes through the matching line and the first filter and is output from the first port.

  Further, for the signal of f2 that has passed through the matching line, the second filter passes the signal, but the first filter blocks the signal of f2. Therefore, the signal of f2 input from the input port is output from the second port through the matching line and the second filter.

  Further, for the signal of f3, the third filter passes the signal, but when the matching line is f3, the third filter is in an open state (input impedance is infinite), and the signal of f3 is cut off (first port) And transmission to the second port side). Therefore, the signal f3 input from the input port passes through the third filter and is output from the third port.

  In this way, in the triplexer of the present invention, the signal input from the input port can be separated and output from the first port to the third port corresponding to each frequency band of f1 to f3. In the triplexer of the present invention, as described above, the signal transmission from the input port to each output port (the first port, the second port, and the third port) has only one stage of filter, or a matching line and one stage of filter. Therefore, the insertion loss can be kept low. Furthermore, since only one matching line is required and only three filters are required, the circuit can be simplified as compared with the prior art, and a compact and low-profile triplexer can be realized by reducing the number of components. I can do it.

  The first filter can be constituted by LPF (low-pass filter), the second filter can be constituted by HPF (high-pass filter), and the third filter can be constituted by HPF (high-pass filter). Any one, two, or all of the first to third filters may be configured by a BPF (band pass filter).

  Further, in one aspect of the present invention, each of the filters (first filter, second filter, and third filter) and each port (input port, first port, second port, and third port) are provided in a laminated substrate, A laminated chip triplexer configured as one chip component is configured. In this case, it is preferable to adopt the following laminated structure from the viewpoint of increasing the isolation for each frequency band f1 to f3 and obtaining good characteristics.

  That is, in this aspect, each of the first filter, the second filter, and the third filter includes one or more inductors and one or more capacitors, and these inductors and capacitors are stacked with an insulating layer interposed therebetween. Provided in a multilayer substrate having a conductor layer equal to or more than one layer, the inductor included in the first filter and the second filter and the matching line are disposed in an upper layer portion of the multilayer substrate, and the inductor included in the third filter is disposed on the multilayer substrate. Place in the lower layer.

  With such a laminated structure, the third filter inductor having the highest frequency and the most likely coupling is isolated in the lower layer of the chip (multilayer substrate), and other components (the first filter and the first filter having a relatively low frequency are separated). Can be placed away from the inductor and matching line that make up the second filter, avoiding coupling between the inductor of the third filter and other inductors and matching lines, and providing good attenuation in the high frequency range. As a result, it is possible to minimize the characteristic deterioration (decrease in isolation) due to the coupling between the constituent elements of the triplexer as a whole.

  In a more preferred aspect, the multilayer substrate has three or more conductor layers, and a capacitor included in the first filter, the second layer is disposed in an intermediate layer portion located between the upper layer portion and the lower layer portion. One or more of a capacitor included in the filter and a capacitor included in the third filter are disposed.

  Thus, if a capacitor is arranged between the lower layer part in which the inductor constituting the third filter is arranged and the upper layer part in which other inductors (first and second filters) and matching lines are arranged (middle layer part) The capacitor can better cut off the coupling between the inductor of the third filter and the other inductors and the matching line. For the same reason, a ground electrode may be further disposed in the middle layer portion.

  The upper layer portion, middle layer portion, and lower layer portion described above may include one layer, two layers, or three or more conductor layers, and are included in each of these portions (upper layer portion, middle layer portion, and lower layer portion). Components such as inductors and capacitors are appropriately arranged in one or more conductor layers, and connections between elements or element portions arranged in different conductor layers are via holes (hereinafter referred to as “vias”) or the outer periphery of the multilayer substrate. What is necessary is just to carry out by interlayer connection conductors, such as a side electrode formed in the surface. Further, in the above aspect of the present invention, the laminated substrate or the triplexer chip is composed of only two portions of the upper layer portion and the lower layer portion, or is composed of only three portions of the upper layer portion, the middle layer portion, and the lower layer portion. For example, a conductor layer or an insulating layer further above the upper layer portion, between the upper layer portion and the middle layer portion, between the middle layer portion and the lower layer portion, or further below the lower layer portion. Of course, it is possible to further include parts and elements constituting the triplexer such as a conductor pattern and a terminal electrode.

  Further, in the present invention, the first filter and the second filter are collectively grasped as one diplexer that separates the signal of the first frequency band (f1) and the signal of the second frequency band (f2) (first It is also possible to provide a diplexer instead of the first filter and the second filter, and it can be understood as the following invention.

  That is, the triplexer according to the present invention is a triplexer that separates an input signal into signals of three frequency bands different from each other and outputs the signals separately, and a common input port capable of inputting the input signal and a signal of the first frequency band A second port that outputs a signal in a second frequency band higher than the first frequency band, and a second port that outputs a signal in a third frequency band higher than the second frequency band. Three ports, the first frequency band signal and the second frequency band signal are separated to output the first frequency band signal to the first port and the second frequency band signal A diplexer that outputs a signal to the second port, a filter that passes the signal in the third frequency band, a signal in the first frequency band, and a signal in the second frequency band. A matching line that is open in the third frequency band, and the diplexer is connected between the input port and the first port and the second port via the matching line. The filter is connected between the input port and the third port.

  Also in such a triplexer, preferably, each of the diplexer and the filter includes one or more inductors and one or more capacitors, and the inductors and capacitors are laminated with three or more conductor layers stacked via an insulating layer. The inductor included in the diplexer and the matching line are disposed in an upper layer portion of the multilayer substrate, the inductor included in the filter is disposed in a lower layer portion of the multilayer substrate, and the upper layer portion. One or more of a capacitor included in the diplexer and a capacitor included in the filter are disposed in a middle layer portion of the multilayer substrate positioned between the lower layer portion and the lower layer portion.

  According to the present invention, it is possible to obtain a triplexer that has a simplified triplexer circuit configuration, a small size and a low profile, low insertion loss, and high isolation characteristics.

  Other objects, features, and advantages of the present invention will become apparent from the following description of embodiments of the present invention described with reference to the drawings. In addition, in each figure, the same code | symbol shows the same or an equivalent part.

FIG. 1 is a block diagram showing a triplexer according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing the triplexer according to the embodiment. FIG. 3 is a conceptual diagram showing the arrangement structure of the triplexer on the multilayer substrate according to the embodiment. FIG. 4 is an exploded perspective view showing a conductor pattern constituting the triplexer of the embodiment. FIG. 5A is a plan view showing first to twelfth layers of a multilayer substrate constituting the triplexer of the embodiment. FIG. 5B is a plan view showing the 13th to 24th layers of the multilayer substrate constituting the triplexer of the embodiment. FIG. 6 is a diagram showing frequency characteristics (first frequency band) of the triplexer according to the embodiment. FIG. 7 is a diagram showing frequency characteristics (second frequency band) of the triplexer according to the embodiment. FIG. 8 is a diagram showing the frequency characteristic (third frequency band) of the triplexer according to the embodiment. FIG. 9A is a diagram showing frequency characteristics (insertion loss in the first frequency band) of the triplexer according to the embodiment. FIG. 9B is a diagram showing frequency characteristics (VSWR in the first frequency band) of the triplexer according to the embodiment. FIG. 10A is a diagram showing frequency characteristics (insertion loss in the second frequency band) of the triplexer according to the embodiment. FIG. 10B is a diagram showing a frequency characteristic (VSWR in a second frequency band) of the triplexer according to the embodiment. FIG. 11A is a diagram showing frequency characteristics (insertion loss in a third frequency band) of the triplexer according to the embodiment. FIG. 11B is a diagram showing a frequency characteristic (VSWR in a third frequency band) of the triplexer according to the embodiment. FIG. 12 is a block diagram showing a modification of the triplexer according to the embodiment. FIG. 13 is a block diagram illustrating a configuration example of a conventional triplexer. FIG. 14 is a block diagram showing another configuration example of a conventional triplexer. FIG. 15 is a block diagram showing still another configuration example of a conventional triplexer.

  As shown in FIG. 1, the triplexer according to the embodiment of the present invention has an input port P0 for receiving a received signal from an antenna and f1, f2, and f3 in ascending order of frequency (f1 <f2 <f3). The first port P1 that outputs a signal in the first frequency band f1, the second port P2 that outputs a signal in the second frequency band f2, and the third port P3 that outputs a signal in the third frequency band f3 A first filter 11 having a pass band at f1, a second filter 12 having a pass band at f2, a third filter 13 having a pass band at f3, and a matching line 10.

  The matching line 10 has one end connected to the input port P0 and the other end connected to the first filter 11 and the second filter 12, and allows the signals of f1 and f2 to pass through, while being open at f3 (the input impedance is substantially reduced). The line is formed to be (infinite). The first filter 11 is connected between the matching line 10 and the first port P1, and the second filter 12 is connected between the matching line 10 and the second port P2. Further, the third filter 13 is connected between the input port P0 and the third port P3.

  Each filter 11, 12, 13 is an LC filter comprising an inductor and a capacitor. The first filter 11 is composed of LPF or BPF, the second filter 12 is composed of HPF or BPF, and the third filter 13 is composed of HPF or BPF. I can do it.

  FIG. 2 illustrates a circuit configuration of each of the filters 11, 12, and 13. As shown in the figure, the first filter 11 includes an inductor L1 connected so as to be inserted in series between the input end and the output end of the filter 11, a capacitor C1 connected in parallel to the inductor L1, The capacitor C1 includes a capacitor C2 connected so as to branch to the ground between the connection point on the output end side of the capacitor C1 and the output end of the first filter 11.

  The second filter 12 includes a capacitor C3 connected in series so as to be inserted between the input end and the output end of the second filter 12, and a branch path that branches from between the capacitor C3 and the output end to the ground. And an inductor L2 and a capacitor C4 connected in series.

  The third filter 13 further includes a first capacitor C5, a second capacitor C6, and a first inductor L3 connected in series on a transmission line connecting the input end to the output end of the third filter 13. Further, one end of the second capacitor C6 and the first inductor L3 is connected in parallel with the first capacitor C5 and the second capacitor C6 (that is, one end between the input terminal and the first capacitor C5). The other end of the third capacitor C7 is connected in parallel with the first inductor L3 (that is, one end is connected between the second capacitor C6 and the first inductor L3, the first inductor L3). A second capacitor L8 connected between the first and second capacitors C5 and C6 to the ground, and a second inductor L4 connected between the first and second capacitors C5 and C6. two A fifth capacitor C9 connected on the branch path branched from the space between the capacitor C6 and the first inductor L3 to the ground, and a sixth capacitor connected on the branch path branched to the ground from the gap between the first inductor L3 and the output terminal. Capacitor C10.

  In the present embodiment, a multilayer chip triplexer is configured by disposing the circuit elements (inductors L1 to L4, capacitors C1 to C10, and the matching line 10) on the internal conductor layer of the multilayer substrate. As the multilayer substrate, for example, an LTCC (Low Temperature Co-fired Ceramics) substrate is used, and a conductor pattern or ground that constitutes each circuit element on the inner conductor layer (the surface of the ceramic green sheet) of the substrate. The electrodes, vias for electrically connecting these conductor patterns and the like are formed, and these are stacked and fired to be integrated.

  The arrangement of the conductor pattern and the like on the multilayer substrate is as shown in FIGS. 3 to 4 and FIGS. 5A to 5B. In addition, the said multilayer substrate laminates | stacks 24 ceramic green sheets, and FIG. 5A-FIG. 5B have shown each layer of the said multilayer substrate from the upper layer to the lower layer in order.

  As shown in FIG. 3, in this embodiment, the inductors L1 and L2 of the first filter 11 and the second filter 12 and the matching line 10 are provided in the substrate upper layer portion 21, and the inductors L3 and L3 of the third filter 13 are provided in the substrate lower layer portion 23. L4 is disposed, and each of the filters 11 and 12 is arranged on the substrate middle layer portion 22 which is a portion between the substrate upper layer portion 21 and the lower layer portion 23 and the substrate bottom surface portion 24 which is a lower layer portion of the substrate lower layer portion 23. , 13 capacitors C1 to C10 and the ground electrode G are arranged.

  More specifically with reference to FIG. 4 and FIGS. 5A to 5B, the inductor L1 of the first filter 11 is formed by dividing a loop-shaped conductor into a second layer and a third layer, and the conductor formed in each of these layers. The inductor L1 is connected by the via V. Similarly, the inductor L2 of the second filter 12 forms an inductor L2 by forming loop-shaped conductors in the second to sixth layers and connecting these conductors with vias V. Further, conductor lines are formed in the second layer, the fourth layer, and the sixth layer, and these conductor lines are connected by the vias V to form the matching line 10. On the other hand, the inductors L3 and L4 of the third filter 13 are formed as inductors L3 and L4 by connecting the conductors formed in the 18th and 19th layers with vias V.

  Further, the capacitor C1 of the first filter 11, the capacitors C3 and C4 of the second filter 12, and the capacitors C5, C6 and C7 of the third filter 13 are formed in the ninth layer and the eleventh to fourteenth layers. Arrange the electrodes. Furthermore, the electrodes forming the capacitor C2 of the first filter 11, the electrodes forming the capacitors C8, C9, and C10 of the third filter 13 and the ground electrode G are disposed on the 22nd to 24th layers.

  Also, external connection terminals (input port P0, first port P1, second port P2, third port P3, ground (GND) terminal) are formed on the back surface of the multilayer substrate (the back surface side of the 24th layer). Yes (not shown), and the connection to these is performed via side electrodes (not shown) formed on the outer peripheral surface of the laminated substrate so as to extend in the vertical direction (stacking direction). In FIG. 5A and FIG. 5B, “to P0” “to P1” “to P2” “to P3” “to GND” represents this.

  The triplexer of the present embodiment assumes a 1.5 GHz band (f1), a 2.4 GHz band (f2), and a 5 GHz band (f3) as operating frequency bands. FIGS. 6 to 8 respectively show frequency characteristics (the solid line is the pass characteristic and the broken line is the reflection characteristic) of the triplexer of the present embodiment, and FIGS. 9A, 10A, and 11A are related to f1, f2, and f3, respectively. 9B, FIG. 10B, and FIG. 11B show VSWR (voltage standing wave ratio) for f1, f2, and f3, respectively. As shown in these figures, it is understood that good pass / attenuation characteristics can be obtained in the three frequency bands f1, f2, and f3.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these, It is clear to those skilled in the art that a various change can be made within the range as described in a claim. .

  For example, the numerical value of the used frequency band is an example, and it is possible to configure a triplexer having various used frequency bands based on the present invention. The circuit configurations of the first filter 11, the second filter 12, and the third filter 13 shown in FIG. 2 are examples, and the configurations of the filters 11 to 13 are not limited thereto. .

  Further, in the present invention, as shown in FIG. 12, the first filter 11 and the second filter 12 of the embodiment are replaced with a diplexer 14 (a diplexer 14 is provided instead of the first filter 11 and the second filter 12 shown in FIG. 1). It is also possible. Also in this case, as in the above embodiment, the inductor included in the diplexer 14 is disposed in the upper layer portion 21 of the multilayer substrate together with the matching line 10, and the inductor included in the third filter 13 is disposed in the lower layer portion of the substrate. good.

  Further, the constituent material of the insulating layer can be made different in the laminated substrate. Specifically, the green sheets (substrate middle layer portion 22 and substrate bottom surface portion 24) on which capacitors are disposed are made of a material having a high dielectric constant, and green sheets (substrate upper layer portion 21 and substrate lower layer portion 23) on which inductors are disposed. If a material having a low dielectric constant is used, it is advantageous in obtaining good characteristics. In particular, in the preferred aspect and embodiment of the present invention, since the inductor and the capacitor are arranged in different layers, the structure in which the constituent material (dielectric constant) of the insulating layer is changed in the multilayer substrate as described above is easily applied. I can do it.

C1, C2, C3, C4, C5, C6, C7, C8, C9, C10 Capacitor L1, L2, L3, L4 Inductor P0 Input port P1 First port P2 Second port P3 Third port G Ground electrode V Via hole 10, 51, 52, 53 Matching line 11 First filter 12 Second filter 13 Third filter 14, 63, 66, 73, 76 Diplexer 21 Substrate upper layer 22 Substrate middle layer 23 Substrate lower layer 24 Substrate bottom 54, 55, 56 , 61, 62, 64, 65, 71, 72, 74, 75 filter

Claims (3)

A triplexer that separates an input signal into signals of three different frequency bands and outputs them separately,
A common input port capable of inputting the input signal;
A first port that outputs a signal in a first frequency band;
A second port for outputting a signal in a second frequency band higher than the first frequency band;
A third port for outputting a signal in a third frequency band higher than the second frequency band;
A first filter that passes the signal of the first frequency band;
A second filter that passes the signal of the second frequency band;
A third filter that passes the signal of the third frequency band;
While passing the first frequency band signal and the second frequency band signal, the matching line that is open in the third frequency band,
With
The first filter is connected between the input port and the first port via the matching line,
The second filter is connected between the input port and the second port via the matching line,
The third filter is connected between the input port and the third port ;
Each of the first filter, the second filter, and the third filter includes one or more inductors and one or more capacitors,
These inductors and capacitors are provided on a multilayer substrate having three or more conductor layers laminated via an insulating layer,
While placing the inductor included in the first filter and the matching line in the upper layer portion of the multilayer substrate,
An inductor included in the third filter is disposed in a lower layer portion of the multilayer substrate,
Among the capacitor included in the first filter, the capacitor included in the second filter, and the capacitor included in the third filter in the middle layer portion of the multilayer substrate located between the upper layer portion and the lower layer portion A triplexer characterized by arranging one or more of the above . A triplexer that separates an input signal into signals of three different frequency bands and outputs them separately,
A common input port capable of inputting the input signal;
A first port that outputs a signal in a first frequency band;
A second port for outputting a signal in a second frequency band higher than the first frequency band;
A third port for outputting a signal in a third frequency band higher than the second frequency band;
The first frequency band signal and the second frequency band signal are separated to output the first frequency band signal to the first port, and the second frequency band signal is output to the first port. A diplexer that outputs to two ports;
A filter that passes the signal of the third frequency band;
While passing the first frequency band signal and the second frequency band signal, the matching line that is open in the third frequency band,
With
The diplexer is connected between the input port and the first port and the second port via the matching line,
The filter is connected between the input port and the third port ;
Each of the diplexer and the filter includes one or more inductors and one or more capacitors,
These inductors and capacitors are provided on a multilayer substrate having three or more conductor layers laminated via an insulating layer,
While arranging the inductor and the matching line included in the diplexer on the upper layer portion of the multilayer substrate,
An inductor included in the filter is disposed in a lower layer portion of the multilayer substrate,
A triplexer , wherein one or more of a capacitor included in the diplexer and a capacitor included in the filter are arranged in an intermediate layer portion of the multilayer substrate positioned between the upper layer portion and the lower layer portion . Triplexer according to claim 1 or 2 was placed ground electrode on the middle layer.

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