JP5543184B2 - Wiring board material, laminated board, multilayer board and wiring board - Google Patents

Description

  The present invention relates to a circuit board material suitable for a core material of a printed board, a probe card, a package build-up board, and the like.

  Circuit boards, especially circuit boards that use thermosetting resins, have recently become increasingly finer, more precise, thinner, or have increased process temperatures, resulting in board materials (usually thermal expansion coefficient of 10 to 30 ppm / ° C). The difference in thermal expansion coefficient between silicon and silicon (thermal expansion coefficient = 3 to 4 ppm / ° C.) is a problem. That is, if the coefficient of thermal expansion is large, for example, when used for a probe card, the deviation of the evaluation position becomes large due to the difference in thermal expansion between the card and the silicon substrate to be inspected, and accurate inspection becomes impossible. . On the other hand, when used for a package, there is a problem that distortion stress is generated by heat such as solder reflow when bonding the substrate and the silicon chip, and the bonded portion is easily peeled off.

  In order to solve this problem, a thermosetting resin (for example, thermal expansion coefficient of epoxy resin = 60 to 80 ppm / ° C.) and an inorganic filler having a relatively small thermal expansion coefficient, for example, natural or synthetic quartz ingots have been crushed so far. A composition filled with a large amount of square silica powder as it is, Si, Ca, Al, B of general alkali glass or low thermal expansion glass mainly composed of oxides such as Na, Ca, Mg, etc. E glass (thermal expansion coefficient = 5.4 to 5.6 ppm / ° C.) containing oxides such as Si, B, etc., or D glass (thermal expansion coefficient = 3. 1 ppm / ° C.), NE glass (thermal expansion coefficient = 3.4 ppm / ° C.) such as NE glass mainly composed of oxides of Si, B, Al, and the like.

In addition, when the above glass cloth is used, it is a filament having an average diameter of 20 μm or more, or the opening ratio of the cloth is 20% or less or 70% or more from the viewpoint of cost, manufacturing difficulty, and ease of lamination. Alternatively, a glass cloth having a cloth basis weight of 100 g / m ² or more has been used. However, it has been difficult to realize a coefficient of thermal expansion of 10 ppm / ° C. or less by these methods. That is, if a large amount of pulverized silica powder is filled in the thermosetting resin for the purpose of reducing the coefficient of thermal expansion, the fluidity is lost and it is difficult to process a wiring board or a laminated board.

Further, when glass cloth is used in combination, the coefficient of thermal expansion of the obtained product is inevitably large unless the coefficient of thermal expansion of the glass cloth is small. Even in the case of E glass having a relatively small coefficient of thermal expansion, when the average diameter of the filament is too large, the opening ratio of the cloth is too small, or the cloth basis weight is 100 g / m ² or more, a thermosetting resin and an inorganic filler are used. The cloth was not uniformly impregnated and adhered, and the amount of adhesion was small, and the thermal expansion coefficient was in-plane nonuniform, and it was difficult to reduce the thermal expansion coefficient to near that of silicon.

  On the other hand, Patent Document 1 describes a laminate obtained by surface-treating quartz glass cloth with a silane coupling agent, then impregnating with an epoxy resin to form a prepreg, and laminating the prepreg. However, the laminate described in Patent Document 1 has a problem that it is expensive because the raw material used is a tubular body.

JP 2006-27960 A

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit board material having a low coefficient of thermal expansion and excellent high-frequency characteristics, heat resistance, and the like.

In order to solve the above problems, a wiring board material of the present invention includes a thermosetting resin, an inorganic filler, and quartz cloth (thermal expansion coefficient = 0.5 to 0.6 ppm / ° C.). Because
The cloth weight of the quartz cloth is 100 g / m ² or less,
Blending 50 to 700 parts by mass of the inorganic filler with respect to 100 parts by mass of the thermosetting resin;
The thermosetting resin is at least one selected from the group consisting of an epoxy resin, a bismaleimide triazine resin and a polyimide resin;
The inorganic filler is mainly composed of spherical silica having an average particle size of 0.1 to 20 μm,
The quartz cloth is formed using a fiber bundle in which 15 to 200 quartz filaments having an average diameter of 20 μm or less are bundled; and the opening ratio of the quartz cloth is 20 to 70%.
Including
Silicon chip (thermal expansion coefficient) with a low thermal expansion coefficient , excellent high frequency characteristics and heat resistance characteristics , and a low thermal expansion coefficient laminated board molded from the wiring board material due to the low thermal expansion coefficient. 3-6ppm / ° C), when solder reflow, after heating up to the solder melting temperature, even if the temperature dropped, the solder joint part was not peeled off due to the difference in thermal expansion. Features.

  In the wiring board material of the present invention, the thermosetting resin is preferably at least one selected from the group consisting of an epoxy resin, a bismaleimide triazine resin and a polyimide resin. When the thermosetting resin is an epoxy resin, a bismaleimide triazine resin, or a polyimide resin, a material for a wiring board having a relatively low cost and good workability can be obtained.

  In the wiring board material of the present invention, it is preferable that the inorganic filler is mainly composed of spherical silica having an average particle diameter of 0.1 to 20 μm. When the inorganic filler contains spherical silica having an average particle size of 0.1 to 20 μm as a main component, even a wiring board material highly filled with silica has good fluidity and can be easily laminated.

  In the wiring board material of the present invention, the quartz cloth is preferably formed using a fiber bundle in which 15 to 200 quartz filaments having an average diameter of 20 μm or less are bundled. When the quartz cloth is a fiber bundle in which 15 to 200 quartz filaments having an average diameter of 20 μm or less are bundled, a laminate obtained by molding can be made thinner, smooth and high in strength.

  In the wiring board material of the present invention, it is preferable that the aperture ratio of the quartz cloth is 20 to 70%.

  The prepreg of the present invention is formed using the wiring board material of the present invention.

  The laminated board of the present invention is formed by using the wiring board material of the present invention as it is or after making a prepreg, and then laminating the required number of sheets, and if necessary, superposing the metal foil on one side or both sides, and heating and pressing. It is characterized by doing.

  The multilayer board of the present invention is characterized in that the laminated board of the present invention is used as a core material, and if necessary, a printed board having a circuit formed on one side or both sides thereof is laminated.

  The wiring board of the present invention is characterized in that a wiring laminated portion in which conductor layers and insulating layers are alternately laminated is formed on one side or both sides of a core substrate containing the wiring board material of the present invention.

  In the wiring board of the present invention, it is preferable that the wiring laminated portion has a terminal pad for connecting to a chip component on the surface side. By using a package substrate on which terminal pads for mounting chip parts such as IC chips and LSIs are formed, the solder melting temperature at the time of solder reflow when bonding silicon chips (thermal expansion coefficient 3 to 6 ppm / ° C.) Even if the temperature is lowered after heating up, the problem of peeling of the solder joint due to the difference in thermal expansion does not occur, and the connection reliability is improved.

  In the wiring board of the present invention, it is preferable that a probe for electronic component inspection is formed on the surface of the wiring laminated portion. By using an electronic component inspection apparatus such as a probe card, the evaluation position shift and contact failure due to the difference in thermal expansion between the wiring board and the silicon substrate to be inspected are reduced. As a result, accurate inspection with high connection reliability is possible.

  According to the wiring board material of the present invention and the prepreg of the present invention, a circuit board material that can realize a low thermal expansion coefficient that has not been achieved so far with a thermosetting resin system and that is excellent in high frequency characteristics and heat resistance characteristics. Can be obtained.

  According to the laminated board of the present invention and the multilayer board of the present invention, it is possible to provide a practical circuit board material excellent in high-frequency characteristics, heat resistance, etc. with a low thermal expansion coefficient with very little substrate warpage and chip peeling. I can do it.

  According to the wiring board of the present invention, a wiring board having a low coefficient of thermal expansion and high connection reliability can be obtained.

It is a schematic plan view which shows one Embodiment of the wiring board of this invention. It is a schematic back view of the wiring board of FIG. It is a fragmentary sectional view of the wiring board of FIG. It is a schematic explanatory drawing which shows the measuring method of the aperture ratio of a quartz cloth.

Embodiments of the present invention will be described below.
The wiring board material of the present invention is a wiring board material containing a thermosetting resin, an inorganic filler, and one or more quartz cloths, and the cloth weight of the quartz cloth is 100 g / m ² or less. A wiring board material containing 50 to 700 parts by mass of the inorganic filler with respect to 100 parts by mass of the thermosetting resin. A thermosetting resin-based laminate and circuit board molded using the wiring board material of the present invention can be obtained with a thermal expansion coefficient close to that of silicon.

  The method for producing the wiring board material of the present invention is not particularly limited, but components such as a thermosetting resin, an inorganic filler, and, if necessary, a solvent, a curing agent, a curing accelerator, a modifier, a flame retardant, and the like. After compounding and mixing uniformly with a kneader, mixer, blender, etc. to adjust the resin composition, one or more laminated quartz cloths are impregnated with the resin composition to produce the wiring board material of the present invention It is preferable to do. In the wiring board material of the present invention, it is preferable to mix 200 to 1200 parts by mass of the quartz cloth with respect to 100 parts by mass of the thermosetting resin.

The prepreg of the present invention is formed using the wiring board material of the present invention.
The production method of the prepreg of the present invention is not particularly limited, but a thermosetting resin, an inorganic filler, and, if necessary, a solvent, a curing agent, a curing accelerator, a modifier, a flame retardant, and the like are blended, After uniformly mixing with a kneader, a mixer, a blender, etc. to adjust the resin composition, impregnating the resin composition into one or more quartz cloths to obtain the wiring board material of the present invention, It is preferable to dry the wiring board material to produce the prepreg of the present invention.

  In the present invention, the thermosetting resin may be an epoxy resin, phenol resin, unsaturated polyester resin, silicone resin, bismaleimide triazine resin, polyimide amide resin, polyimide resin, urethane resin, etc. Although there is no limitation, epoxy resin, bismaleimide triazine resin, and polyimide resin are particularly preferable in terms of cost, moldability, and substrate characteristics.

  The inorganic filler may be fine powder such as alumina, aluminum hydroxide, talc, silica, calcium carbonate, iron oxide, mica, silicon nitride, aluminum nitride, and ceria, or a mixture thereof. It has a low coefficient of thermal expansion and can be used as a high fluidity wiring board material even when blended in large quantities. It is easier to mold into a laminated board than the spherical silica whose average particle size is 0.1 to 20 μm. The filler is optimal. When the average particle diameter is smaller than 0.1 μm, the viscosity of the resin composition increases and the fluidity is deteriorated, resulting in difficulty during the molding operation. On the other hand, if it is coarser than 20 μm, the smoothness of the surface of the laminate is deteriorated.

As the quartz cloth, natural or synthetic quartz quartz filaments can be used in either woven or non-woven form, but the cloth weight is 100 g / m ² or less, especially for forming wiring board materials into thin and precise laminates. Quartz cloth woven into the fabric is good, and is preferably 10 g / m ² or more and 100 g / m ² or less. When a quartz cloth exceeding 100 g / m ² is used, it becomes coarse and thick.

When a fiber bundle in which 15 to 200 quartz filaments having an average diameter of 20 μm or less, preferably 3 μm or more and 15 μm or less are bundled on a woven fabric, the weight of the quartz cloth is easily obtained as a product having the above-mentioned 100 g / m ² or less.
In the case of a fiber bundle outside this range, the cross strength becomes extremely weak or thick. If a quartz filament having an average diameter exceeding 20 μm is used, it is difficult to manufacture a precise thin laminate.

  When the opening ratio of the quartz cloth is 20 to 70%, the impregnation and adhesion of the resin composition can be suitably performed. Outside this range, for example, when the opening ratio of the quartz cloth is less than 20%, it is difficult to impregnate the resin composition, the amount of adhesion increases, and it tends to become spots. On the other hand, if it is higher than 70%, the resin composition will hardly stay on the quartz cloth, and the amount of adhesion will be significantly reduced. Furthermore, when the opening ratio of the quartz cloth is 20 to 70%, not only uniform impregnation and adhesion of the resin composition is easy, but the molded laminate has a low coefficient of thermal expansion, a smooth surface, and a thickness. There is very little variation. A multilayer substrate using such a laminated plate as a core material is suitable for a state-of-the-art circuit board material.

  FIG. 4 is a schematic explanatory view showing a method for measuring the aperture ratio of the quartz cloth. In FIG. 4, reference numeral 100 denotes a quartz cloth, and reference numeral 102 denotes a fiber bundle in which quartz filaments are bundled. In the present invention, as shown in FIG. 4, the aperture ratio of the quartz cloth refers to the area of the cross gap 104 (a × b) and the area between the gap centers C1, C2, C3, C4 of the adjacent cross gap (X × Y) is measured, and the ratio of the gap to the entire cross network is calculated by the following formula (1).

  In the formula (1), a is the length of the cross gap in the vertical direction, b is the length of the cross gap in the horizontal direction, X is the distance between the gap centers C1 and C2 of the cross gaps adjacent in the horizontal direction, and Y is This is the distance between the gap centers C2 and C3 of the cross gaps adjacent in the vertical direction.

In order to obtain the laminate of the present invention, the above-described wiring board material is used as it is or appropriately heated to form a prepreg, and then a required number of layers are laminated, and if necessary, a metal such as copper foil is laminated on one side or both sides. Molded with a roll or press heated and pressed.
In the laminated board of the present invention, the number of quartz cloths is not particularly limited as long as it is a plurality, but is preferably 5 sheets / mm to 75 sheets / mm. In the present invention, there is no limitation on the method of stacking the quartz cloth, and a single quartz cloth is impregnated with the resin composition described above to produce the wiring board material of the present invention. A plurality of wiring board materials or prepregs may be made by stacking, and the above-described resin composition is impregnated into a plurality of stacked quartz cloths to produce the wiring board material of the present invention. After forming a prepreg, the wiring board material or the prepreg may be formed by stacking one or more sheets.

  The multilayer board of the present invention is produced by laminating one or more printed boards having circuits formed on one side or both sides of the laminated board prepared as described above as a core material. Note that conduction between layers is usually performed by plating through holes or filling with conductive paste.

  An embodiment embodying a wiring board of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic plan view showing an embodiment of the wiring board of the present invention, and FIG. 2 is a schematic back view of the wiring board of FIG. FIG. 3 is a partial cross-sectional view of the wiring board of FIG.

  1-3, the code | symbol 10 is a wiring board of one Embodiment of this invention, and is a wiring board for chip component mounting. As shown in FIG. 3, the wiring substrate 10 includes a substantially rectangular plate-shaped core substrate 12, a first buildup layer (wiring laminated portion) 15 formed on the core main surface 13 of the core substrate 12, It consists of a second buildup layer (wiring laminated portion) 16 formed on the core back surface 14 of the core substrate 12.

  The core substrate 12 uses a laminated board formed using the wiring board material of the present invention. Through-hole conductors 17 are formed at a plurality of locations on the core substrate 12. The inside of the through-hole conductor 17 is filled with a filler 18 having an epoxy resin as a main component, for example. A conductor layer 19 made of copper is patterned on the core main surface 13 and the core back surface 14 of the core substrate 12, and each conductor layer 19 is electrically connected to the through-hole conductor 17.

  The first buildup layer 15 formed on the core main surface 13 of the core substrate 12 is made of two resin insulating layers 20 and 21 mainly composed of a thermosetting resin (for example, epoxy resin), and copper. The conductor layers 19, 22, and 23 are alternately stacked. In addition, terminal pads 230 constituting the conductor layer 23 are formed in an array at a plurality of locations on the surface of the second resin insulating layer 21. Further, the surface of the resin insulating layer 21 is almost entirely covered with a solder resist 29. An opening 30 for exposing the terminal pad 230 is formed at a predetermined location of the solder resist 29. A plurality of solder bumps are disposed on the surface of the terminal pad 230 and are electrically connected to surface connection terminals of a chip component (such as an IC chip mainly composed of silicon) having a rectangular flat plate shape. In addition, via conductors 26 and 28 are provided in the resin insulating layers 20 and 21, respectively. These via conductors 26 and 28 electrically connect the conductor layers 19, 22 and 23 to each other.

  Similar to the first buildup layer 15 described above, the second buildup layer 16 formed on the core back surface 14 of the core substrate 12 is a two-layer resin insulation layer made of a thermosetting resin (for example, epoxy resin). 31 and 32 and conductor layers 19, 33, and 34 are alternately stacked. BGA pads 340 that are electrically connected to the conductor layer 33 through the via conductors 28 are formed in an array at a plurality of locations on the lower surface of the second resin insulating layer 32. The lower surface of the resin insulating layer 32 is almost entirely covered with a solder resist 36. An opening 37 for exposing the BGA pad 340 is formed at a predetermined position of the solder resist 36. Solder bumps 38 are formed on the surface of the BGA pad 340.

  As shown in FIG. 1, on the surface 53 (surface of the buildup layer 15) side of the wiring board 10, terminal pads 230 for connecting to components are exposed in an array. As shown in FIG. 2, solder bumps 38 for connection to an external circuit board are formed in an array on the back surface 54 (the surface of the buildup layer 16) of the wiring board 10.

Next, a manufacturing procedure of the wiring board 10 having the above configuration will be described.
Double-sided copper-clad laminates obtained by adhering a copper foil to be a conductor layer 19 to the core main surface 13 and the core back surface 14 of a laminate (core substrate) formed using the wiring board material of the present invention described above ( A core substrate with metal foil) is prepared. A through hole penetrating the double-sided copper clad laminate is formed at a predetermined position. Then, after forming a plated through hole 17 by performing electroless copper plating and electrolytic copper plating according to a conventionally known method, the plated through hole 17 is filled with a filler 18 and thermally cured.

  Thereafter, the copper foil on both surfaces of the core substrate is etched to form the conductor layer 19 on the core substrate 12 by patterning. Specifically, after electroless copper plating, an exposure glass mask is placed for exposure, followed by development to form a predetermined pattern of plating resist. In this state, after electrolytic copper plating is performed using the electroless copper plating layer as a common electrode, first, the resist is dissolved and removed, and further unnecessary electroless copper plating layer is removed by etching. As a result, a conductor layer 19 having a predetermined pattern is formed on the surface of the core substrate 12.

  Next, the buildup layer 15 is formed on the core main surface 13 of the core substrate 12 and the buildup layer 16 is formed on the core back surface 14 of the core substrate 12 based on a conventionally known buildup method.

  More specifically, first, a film-like insulating resin material mainly composed of an epoxy resin is placed on the core main surface 13 and the core back surface 14 of the core substrate 12 so as to overlap each other. Then, the laminate is heated under pressure with a vacuum press-bonding hot press to cure the film-like insulating resin material, and the first resin insulating layer 20 on the core main surface 13 and the core back surface 14. 31 is formed.

  Via holes 25 are formed by irradiating laser at predetermined positions of the resin insulating layers 20 and 31. Then, by performing electroless copper plating, a via conductor 26 is formed in the via hole 25, and an electroless plating layer is formed on the entire top surface of the resin insulating layer 20. Thereafter, exposure and development are performed to form a resist having a predetermined pattern. Then, after the electrolytic copper plating is performed, the resist is first dissolved and removed, and an unnecessary electroless copper plating layer is removed by etching. As a result, conductor layers 22 and 33 having a predetermined pattern are formed on the resin insulating layers 20 and 31.

  As in the case of the first resin insulation layers 20 and 31, the second resin insulation layers 21 and 32 are formed. Furthermore, a via hole 27 is formed by irradiating a predetermined position on the resin insulating layers 21 and 32 with a laser. Then, by performing electroless copper plating, a via conductor 28 is formed in the via hole 27, and an electroless copper plating layer is formed on the entire upper surfaces of the resin insulating layers 21 and 32. Thereafter, exposure and development are performed to form a plating resist having a predetermined pattern, and electrolytic copper plating is performed. Then, the resist is dissolved and removed, and an unnecessary electroless copper plating layer is removed by etching. As a result, the conductor layer 23 constituting the plurality of terminal pads 230 is formed on the resin insulating layer 21, and the conductor layer 34 constituting the plurality of BGA pads 340 is formed on the resin insulating layer 32. Is done.

  Next, solder resists 29 and 36 are formed by applying and curing a photosensitive liquid resin material on the surfaces of the resin insulating layers 21 and 32. And it arrange | positions so that the glass mask for exposure may be piled up on the surface of the soldering resist 29. FIG. In this state, the exposure glass masks are arranged so as to overlap each other. In this state, the opening 30 is patterned in the solder resist by performing exposure through a glass mask for exposure and further developing. Similarly, with respect to the solder resist 36 on the lower surface side of the core substrate 12, an exposure glass mask is disposed on the surface of the solder resist 36, exposure and development are performed, and the opening 37 is patterned in the solder resist 36.

  The terminal pad 230 and the BGA pad 340 exposed from the openings 30 and 37 are subjected to nickel-gold plating. Thereafter, the solder bumps 38 are formed on the surface of the BGA pad 340 by a well-known method, whereby the wiring substrate 10 is completed.

  According to the present embodiment, since the thermal expansion coefficient of the core substrate 12 is small, when a silicon chip (thermal expansion coefficient 3 to 6 ppm / ° C.) is mounted, the temperature drops after heating to the solder melting temperature during solder reflow. Even if it performs, the problem of peeling of the solder joint part resulting from the difference in thermal expansion does not arise. Accordingly, it is possible to reliably suppress a connection failure with the chip component to be mounted.

  In the above embodiment, the wiring board for mounting chip components is shown, but it can also be a wiring board as an electronic component inspection apparatus. In this case, a conductive metal probe is formed on the terminal pad 230 exposed on the surface of the wiring laminated portion 15. The conductive metal probe can come into contact with the terminal group of the IC formed on the wafer. Since this wiring board also has a small coefficient of thermal expansion of the core substrate 12, there is little shift in the evaluation position due to the difference in thermal expansion between the wiring board and the silicon substrate to be inspected, and connection reliability is increased. As a result, an accurate inspection can be performed.

  In the manufacturing method of the above embodiment, the build-up layer 15 is formed on the core main surface 13 of the core substrate 12 and the build-up is performed on the core back surface 14 of the core substrate 12 based on a conventionally known build-up method. Although the up layer 16 is formed, it can be changed to the following process.

  In order to obtain the buildup layers 15 and 16, photosensitive resin insulating layers 20 and 31 made of a polyimide film having a copper foil attached to the outer surface are prepared. The resin insulating layers 21 and 32 are similarly prepared. Next, a predetermined number of positions in the copper foil and the resin insulating layers 20 and 31 are irradiated with laser from the copper foil side to form a plurality of substantially frustoconical via holes 25. Further, each via hole 25 was individually filled with a conductive paste containing Ag powder or Cu powder using a squeegee to form a truncated cone-shaped conductive paste filling body having a substantially flush surface. In this state, the resin insulating layers 20 and 31 are heated so that the conductive paste filler is temporarily cured to form the via conductors 26.

  Next, in a state in which a predetermined pattern of plating resist is formed on the pre-cured via conductor 26 and the copper foil, the portion not covered with the plating resist is removed by contact with an etching solution, and then the plating resist is peeled off. Peel off with liquid. As a result, conductor layers 22 and 33 having a predetermined pattern connected to the via conductor 26 are formed on the surfaces of the resin insulating layers 20 and 31. The resin insulating layers 21 and 32 are also subjected to the same process as above to form the via conductor 28, the terminal pad 230, and the BGA pad 340. On the other hand, as the solder resists 29 and 36, a thermosetting resin film prepared by drilling a predetermined position of the polyimide film is prepared.

  On the surface of the core substrate 12 (core material) on which the conductor layer 19 of the above-described embodiment is formed, the resin insulating layers 20 and 21 (printed substrate) and the solder resist 29 are laminated, pressure-bonded, and heated to build up the layer 15 In addition, the resin insulation layers 31 and 32 (printed circuit board) and the solder resist 36 are laminated, pressure-bonded and heated on the back surface of the core substrate 12 (core material) on which the conductor layer 19 is formed. Form. At this time, the via conductors 26 and 28, the conductor layers 22 and 33, the terminal pads 230, and the BGA pads 340 in the conductor layer 19 and the build-up layers 15 and 16 are electrically connected.

  In the above embodiment, since the solder bumps are formed on the back surface 54 of the wiring board, the BGA pad 340 is used. However, a PGA pad or an LGA pad may be used. When the PGA pad is formed, a pin is erected on the surface. Since the LGA pad is connected to a connection terminal such as a connector on the external circuit board, the LGA pad is exposed on the back surface 54 of the wiring board.

  Examples will be described below in more detail, but the present invention is not limited to these examples.

Example 1
100 parts by mass of an epoxy resin based on bisphenol A and F and using an acid anhydride as a curing agent, 1 part by mass of imidazole as a curing accelerator, and 570 parts by mass of spherical silica having an average particle size of 5.3 μm were mixed in a kneader. The resin composition was impregnated into a laminate of five quartz cloths having an aperture ratio of 35% and a basis weight of 15 g / m ² formed by a bundle of 40 quartz glass filaments having an average filament diameter of 6 μm. After obtaining the wiring board material, pressing is performed for 2 hours under the conditions of 150 ° C. and 100 kg / cm ² , and a laminate having a substantially rectangular plate shape in plan view of 25 mm length × 25 mm width × 1.0 mm thickness is obtained. Obtained.

  As a result of measuring the thermal expansion coefficient in the plane direction (XY direction) of this laminate by the compression method, it was 4.3 ppm / ° C. before the glass transition point (50 ° C. to 150 ° C.), which is extremely high in the thermal expansion coefficient of silicon. It was close. The glass transition point was measured by TMA (thermomechanical analysis) defined in JPCA-BU01, and the glass transition point of the laminate was 140 ° C. The bending elastic modulus of the laminate was 17 GPa and had sufficient strength.

A silicon chip was bonded to a multilayer board obtained by laminating 10 layers of a printed board in which a circuit was formed on a copper-clad polyimide board using the laminated board as a core material, but no peeling occurred.
In addition, the high-frequency characteristics were excellent, similar to a Teflon (registered trademark) substrate.
Further, using this laminate as a core base material, the wiring board shown in FIG. 1 was manufactured as described above. Even when the temperature was lowered after heating up to the solder melting temperature at the time of solder reflow, the solder joint part due to the difference in thermal expansion did not peel off, and the connection failure with the chip component to be mounted could be suppressed.

(Example 2)
A resin composition obtained by mixing 100 parts by mass of the epoxy resin shown in Example 1, 1 part by mass of imidazole as a curing accelerator, and 570 parts by mass of spherical silica having an average particle diameter of 5.3 μm with a kneader, has an average filament diameter of 7 μm. After impregnating one quartz cloth having an aperture ratio of 20% and a basis weight of 100 g / m ² formed of a bundle of 200 quartz glass filaments to obtain a wiring board material of the present invention, The mixture was temporarily dried for minutes to prepare a prepreg of the present invention. After cutting the prepreg, 15 sheets are stacked and pressed for 2 hours under the conditions of 150 ° C. and 100 kg / cm ² , and a laminated plate having a substantially rectangular plate shape in plan view of 25 mm length × 25 mm width × 1.5 mm thickness is obtained. Obtained. As a result of measuring the thermal expansion coefficient in the plane direction (XY direction) of this laminated board by the compression method, it was before the glass transition point (50 ° C. to 150 ° C.); 3.9 ppm / ° C.

(Comparative Example 1)
Quartz glass having an average filament diameter of 7 μm was prepared by mixing a resin composition obtained by mixing 100 parts by mass of the epoxy resin shown in Example 1, 1 part by mass of imidazole as a curing accelerator, and 5 parts by mass of spherical silica having an average particle diameter of 5 μm with a kneader. After impregnating a quartz cloth with a basis weight of 100 g / m ² formed by a bundle of 200 bundles of filaments, preliminarily dried at 120 ° C. for 1 minute, then cut 15 sheets, 150 ° C., 100 kg / cm ² A press was performed for 2 hours underneath to obtain a laminate having a substantially rectangular plate shape in plan view of 25 mm length × 25 mm width × 1.5 mm thickness. As a result of measuring the thermal expansion coefficient in the plane direction (XY direction) of this laminate by the compression method, it was 10.5 ppm / ° C. before the glass transition point (50 ° C. to 150 ° C.).

(Comparative Example 2)
A resin composition obtained by mixing 100 parts by mass of the epoxy resin shown in Example 1, 1 part by mass of imidazole as a curing accelerator, and 100 parts by mass of spherical silica having an average particle diameter of 30 μm is used as a quartz glass filament having an average filament diameter of 9 μm. After impregnating a quartz cloth having a basis weight of 130 g / m ² and an opening rate of 10% formed of 250 bundles of fibers, it is preliminarily dried at 120 ° C. for 5 minutes, and after cutting, 8 sheets are stacked, 150 ° C., 150 kg / cm ² The laminate was pressed for 4 hours under the above conditions to obtain a substantially rectangular plate-like laminate in plan view of 25 mm length × 25 mm width × 1.0 mm thickness. When the cross section of this laminated board was observed, spherical silica was present non-uniformly and was not preferable as a core material for a printed circuit board.

(Comparative Example 3)
As a result of conducting an experiment with the same formulation as in Example 1 except that an E glass cloth was used instead of the quartz cloth, the thermal expansion coefficient of the laminated plate was before the glass transition point (50 ° C. to 150 ° C.); 12 ppm / The multilayer board was partially peeled at the interface between the silicon chip and the substrate. The high-frequency characteristics are almost the same as those of conventional substrates and have not been improved so much.

  10: Wiring substrate, 12: Core substrate, 13: Core main surface, 14: Core back surface, 15: First buildup layer, wiring laminated portion, 16: Second buildup layer, wiring laminated portion, 17: Through-hole conductor , 18: filler, 19, 22, 23, 33, 34: conductor layer, 20, 21, 31, 32: resin insulation layer, 25, 27: via hole, 26, 28: via conductor, 29, 36: solder Resist, 30, 37: opening, 38: solder bump, 53: front surface of wiring board, 54: back surface of wiring board, 230: terminal pad, 340: pad for BGA, 100: quartz cloth, 102: fiber bundle, cloth Gap 104, C: Center of the gap.

Claims (7)

A wiring board material containing a thermosetting resin, an inorganic filler, and quartz cloth,
The cloth weight of the quartz cloth is 100 g / m ² or less,
Blending 50 to 700 parts by mass of the inorganic filler with respect to 100 parts by mass of the thermosetting resin;
The thermosetting resin is at least one selected from the group consisting of an epoxy resin, a bismaleimide triazine resin and a polyimide resin;
The inorganic filler is mainly composed of spherical silica having an average particle size of 0.1 to 20 μm,
The quartz cloth is formed using a fiber bundle in which 15 to 200 quartz filaments having an average diameter of 20 μm or less are bundled; and the opening ratio of the quartz cloth is 20 to 70%.
Including
Silicon chip (thermal expansion coefficient) with a low thermal expansion coefficient , excellent high frequency characteristics and heat resistance characteristics , and a low thermal expansion coefficient laminated board molded from the wiring board material due to the low thermal expansion coefficient. 3-6ppm / ° C), when solder reflow, after heating up to the solder melting temperature, even if the temperature dropped, the solder joint part was not peeled off due to the difference in thermal expansion. Characteristic wiring board material.   A prepreg formed using the wiring board material according to claim 1.   After the wiring board material according to claim 1 is used as it is or made into a prepreg, a required number of sheets are laminated, and if necessary, a metal foil is stacked on one side or both sides and heated and pressure-molded. Laminated board.   A multilayer board comprising the laminated board according to claim 3 as a core material, and a printed board having a circuit formed on one side or both sides thereof, if necessary.   A wiring board comprising a wiring laminated portion in which conductor layers and insulating layers are alternately laminated on one side or both sides of a core board containing the wiring board material according to claim 1.   6. The wiring board according to claim 5, wherein the wiring laminated portion is formed with terminal pads for connecting to chip components on the surface side.   6. The wiring board according to claim 5, wherein a probe for inspecting electronic components is formed on a surface of the wiring laminated portion.

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