JP5542504B2 - Signal processing apparatus and light detection apparatus - Google Patents

Description

  The present invention relates to a signal processing device that outputs an electric signal having a value corresponding to the amount of electric charge generated in the photodiode in accordance with the amount of light incident on the photodiode, and light including such a signal processing device and the photodiode. The present invention relates to a detection device.

  A light detection device that detects the amount of incident light includes a photodiode that generates a charge corresponding to the amount of incident light, and a signal processing device that outputs an electrical signal having a value corresponding to the amount of charge generated by the photodiode. In addition, the signal processing device includes an integration circuit including an amplifier and an integration capacitor unit, accumulates the charge generated by the photodiode in the integration capacitor unit of the integration circuit, and according to the capacitance value and the accumulated charge amount of the integration capacitor unit. The voltage value is output from the integration circuit. As such a light detection device, for example, one described in Patent Document 1 is known. The photodetector described in this document also has an AD conversion function, and can output a digital value corresponding to the amount of incident light.

  For example, the photodetection device may be used as a detection unit of an X-ray CT apparatus, and a large number of photodiodes may be arranged in an array and covered with a scintillator. When X-rays enter the scintillator, scintillation light is generated. When the scintillation light enters one of the photodiodes, electric charges are generated in the photodiodes, and the electric charges are converted into electric signals by the signal processing device.

Japanese Patent Laid-Open No. 5-215607

  The present inventor has found that the signal processing circuit as described above has the following problems.

The output current value of the photodiode is I, the charge storage time in the integration capacitor part of the integration circuit is T, the capacitance value of the integration capacitor part of the integration circuit is C _f, and the wiring capacitance between the photodiode and the integration capacitor part was a C _d, when the open loop gain of the amplifier of the integrating circuit is a, the voltage value V outputted from the integrating circuit is expressed by the following equation (1).

  In general, since the open loop gain A of the amplifier of the integration circuit may be infinite, the equation (1) can be approximated by the following equation (2). Conventionally, on the assumption that the approximate expression of the expression (2) is sufficiently accurate, the output current value I of the photodiode, that is, based on the output voltage value V of the integration circuit, based on the expression (2), that is, There has been a demand for the amount of light incident on the photodiode.

However, although the open loop gain A of the amplifier of the integration circuit is ideally treated as being infinite, it actually has a finite value. Depending on the ratio of 1 / A and C _f / (C _f + C _d ), 1 / A becomes a value that cannot be ignored compared to C _f / (C _f + C _d ). The approximate expression 2) does not hold.

As described above, even if an integration circuit including an integration capacitor unit having a highly accurate capacitance value C _f can be manufactured, the output value of the signal processing circuit is inversely proportional to the capacitance value C _f of the integration capacitor unit. The relationship (equation (2)) may be broken and the amount of light incident on the photodiode may not be obtained with high accuracy.

  The present invention has been made on the basis of the inventor's knowledge as described above, and an object of the present invention is to provide a signal processing device and a photodetection device capable of obtaining the amount of light incident on a photodiode with high accuracy. To do.

  A signal processing apparatus according to the present invention is a signal processing apparatus that outputs an electrical signal having a value corresponding to the amount of electric charge generated in a photodiode in accordance with the amount of light incident on the photodiode, and (1) a first amplifier , The first integration capacitor unit and the first switch, the first integration capacitor unit and the first switch are provided in parallel between the input terminal and the output terminal of the first amplifier, and the input terminal of the first amplifier is a photo Connected to the diode, discharged from the photodiode after the start of the charge accumulation operation in which the first integration capacitor unit is discharged during the initialization period in which the first switch is closed and the first switch changes from the closed state to the open state. A first integration circuit that accumulates the accumulated charge in the first integration capacitor unit and outputs a voltage value corresponding to the amount and capacitance value of the charge accumulated in the first integration capacitor unit, and (2) from the start of the charge accumulation operation After that, a constant voltage value is output And (3) a second amplifier, a second integration capacitor unit, a second switch and a resistor, and the second integration capacitor unit and the second switch are provided between the input terminal and the output terminal of the second amplifier. The second amplifier is provided in parallel, the input terminal of the second amplifier is connected to the output terminal of the voltage source through a resistor, the open loop gain of the second amplifier is equal to the open loop gain of the first amplifier, Is equal to the capacitance value of the first integration capacitor unit, and the second switch changes from the closed state to the open state when the charge accumulation operation starts, and the voltage value output from the voltage source after the charge accumulation operation starts A second integration circuit that outputs a voltage value representing the integrated value; and (4) a timing that represents a timing at which the voltage value reaches the reference value by comparing the voltage value output from the second integration circuit with the reference value. Timing instruction signal generation times for outputting instruction signals And (5) a holding circuit that samples and holds and outputs the voltage value output from the first integration circuit at a timing represented by the timing instruction signal output from the timing instruction signal generation circuit. To do.

  This signal processing device is used together with a photodiode. The first integration circuit of the signal processing device includes a first amplifier, a first integration capacitor unit, and a first switch. In the first integration circuit, a first integration capacitor unit and a first switch are provided in parallel between the input terminal and the output terminal of the first amplifier. In the first integration circuit, the input terminal of the first amplifier is connected to the photodiode. In the first integration circuit, the first integration capacitor unit is discharged during the initialization period in which the first switch is closed, and a reset level voltage value is output. Further, in the first integration circuit, the charge generated according to the amount of light incident on the photodiode is accumulated in the first integration capacitor unit from the start of the charge accumulation operation in which the first switch changes from the closed state to the open state, A voltage value corresponding to the amount of charge accumulated in the first integration capacitor and the capacitance value is output.

  The second integration circuit of this signal processing device includes a second amplifier, a second integration capacitor, a second switch, and a resistor. In the second integration circuit, a second integration capacitor unit and a second switch are provided in parallel between the input terminal and the output terminal of the second amplifier. In the second integration circuit, the input terminal of the second amplifier is connected to the output terminal of the voltage source via a resistor. The open loop gain of the second amplifier of the second integration circuit is equal to the open loop gain of the first amplifier of the first integration circuit. Further, the capacitance value of the second integration capacitor unit of the second integration circuit is equal to the capacitance value of the first integration capacitor unit of the first integration circuit. In the second integration circuit, the second switch changes from the closed state to the open state at the start of the charge accumulation operation, and a constant voltage value output from the voltage source after the start of the charge accumulation operation is input. A voltage value representing the integrated value is output.

  The timing instruction signal generation circuit compares the voltage value output from the second integration circuit with a reference value, and outputs a timing instruction signal indicating the timing at which the voltage value reaches the reference value. The holding circuit samples, holds, and outputs the voltage value output from the first integration circuit at the timing indicated by the timing instruction signal output from the timing instruction signal generation circuit. The voltage value output from the holding circuit represents the amount of light incident on the photodiode.

  Thus, the timing at which the voltage value output from the first integration circuit is sampled by the holding circuit is set by the voltage source, the second integration circuit, and the timing instruction signal generation circuit. Here, the open loop gain of the second amplifier of the second integration circuit is equal to the open loop gain of the first amplifier of the first integration circuit, and the capacitance value of the second integration capacitance unit of the second integration circuit is the first integration value. It is equal to the capacitance value of the first integration capacitor part of the circuit. Therefore, even if the open loop gain of these amplifiers has a finite value, the time from the start of the charge accumulation operation in the first integration circuit to the voltage value sampling operation in the holding circuit is appropriately adjusted, and the photodiode is Can be obtained with high accuracy.

In the signal processing apparatus according to the present invention, (1) the first integration capacitor unit is selectively set to have any one of _M capacitance values C _{1 to} C _M , and (2) the first M integrating circuits S _{1 to} S _M are provided as two integrating circuits, each integrating circuit S _m has the same configuration as the second integrating circuit, and the second integrating capacitor part of each integrating circuit S _m has a capacitance value C _m. the a, resistors of each integrating circuit _{S m} has a resistance value _{R m,} a product of the resistance value _{R m} and the capacitance value _{C m} among the M integrating circuits _S 1 to S _M are equal to each other, (3) M generation circuits T _{1 to} T _M are provided as timing instruction signal generation circuits, and each generation circuit T _m compares the voltage value output from the integration circuit S _m with the reference value to determine the voltage value. and it outputs a timing indication signal representative of the timing reaches the reference value, (4) holding circuit, to correspond to the set capacitance value C _m of the first integrating capacitor unit At the timing indicated by the output timing instruction signal from the generating circuit T _m, it is preferable to retain outputs by sampling the voltage value output from the first integrating circuit. However, M is an integer of 2 or more, and m is an integer of 1 or more and M or less.

In this case, the first integration capacitor unit of the first integration circuit is selectively set to have any one of _M capacitance values C _{1 to} C _M. Corresponding to the capacitance value C _m of the first integrating capacitor of the first integrating circuit, the integrating circuit S _m is provided as a second integrating circuit, also generation circuit the T _m of the timing instruction signal generating circuit Is provided. Second integration capacitance section of each integrating circuit S _m has a capacitance value C _m. Product of the resistance value and the capacitance value C _m of the resistor between the M integrating circuits S ₁ to S _M are equal to each other. Further, the open loop gain of the second amplifier of each of the _M integration circuits S _{1 to} S _M is equal to the open loop gain of the first amplifier of the first integration circuit. Therefore, even if the first integration capacitor portion of the first integration circuit is set to have any one of the _M capacitance values C _{1 to} C _M , when the charge accumulation operation starts in the first integration circuit The time from the voltage value to the voltage value sampling operation in the holding circuit is appropriately adjusted, and the amount of light incident on the photodiode can be obtained with high accuracy.

  The signal processing apparatus according to the present invention: (1) When the voltage value output from the first integration circuit is input, the voltage value is compared with a predetermined reference value, and the voltage value reaches the reference value And (2) the capacitance value of the first integration capacitor unit set to the minimum value at the start of the charge accumulation operation in the first integration circuit, When a saturation signal is output from the comparison circuit in the middle of the charge accumulation operation, the capacitance value of the first integration capacitor section is shorter as the time from the start of the charge accumulation operation in the first integration circuit to the output of the saturation signal in the comparison circuit is shorter. It is preferable to further include a capacitance value control unit that sets a large value.

  In this case, the voltage value output from the first integration circuit is input to the comparison circuit, the input voltage value and the predetermined reference value are compared in magnitude by the comparison circuit, and the input voltage value reaches the reference value. Sometimes, a saturation signal indicating that is output from the comparison circuit. The voltage value output from the first integration circuit is sampled and held and output by the holding circuit after a predetermined time has elapsed from the start of the charge accumulation operation in the integration circuit. The capacitance value of the first integration capacitor unit of the first integration circuit is set by the capacitance value control unit. The capacitance value control unit sets the capacitance value of the first integration capacitor unit of the first integration circuit to the minimum value at the start of the charge accumulation operation in the first integration circuit, and during the charge accumulation operation in the first integration circuit. When the saturation signal is output from the comparison circuit, the value is set to a larger value as the time from the start of the charge accumulation operation in the first integration circuit to the output of the saturation signal in the comparison circuit is shorter.

In the signal processing device according to the present invention, the capacitance value control unit is configured such that when the saturation signal is output from the comparison circuit during the charge accumulation operation in the first integration circuit, the saturation signal is output from the comparison circuit when the saturation signal is output. The capacitance value of the first integration capacitor unit is changed according to which partial period when the period from the start of the charge accumulation operation to the voltage value sampling operation in the holding circuit is divided into a plurality of partial periods. It is preferable to set. Further, the capacitance value control unit includes the capacitance values of the first integration capacitor unit, the saturation output voltage value of the first integration circuit, the reference value input to the comparison circuit, and the charge accumulation operation start time in the first integration circuit. Based on the time until the voltage value sampling operation in the holding circuit, the period from the start of the charge accumulation operation in the first integration circuit to the voltage value sampling operation in the holding circuit is divided into a plurality of partial periods, and the first integration When a saturation signal is output from the comparison circuit during the charge accumulation operation in the circuit, the first integration capacitor unit according to which partial period of the plurality of partial periods the saturation signal output time of the comparison circuit belongs to It is also preferable to change and set the capacitance value. In addition, the capacitance value control unit outputs a saturation signal from the comparison circuit during the charge accumulation operation in the first integration circuit, changes the capacitance value of the first integration capacitance unit, and then sets the saturation signal from the comparison circuit. It is also preferable to set the capacitance value of the first integration capacitor unit by changing it to a larger value.

  The signal processing apparatus according to the present invention includes (1) the first processing except that the capacitance value control unit changes and sets the capacitance value of the first integration capacitance unit based on the saturation signal output from the comparison circuit. A charge injection circuit for injecting a certain amount of charge of opposite polarity to the charge accumulated in the first integration capacitor of the integration circuit into the first integration capacitor, and (2) based on the saturation signal output from the comparison circuit, A counting circuit that counts the number of times that the voltage value output from the first integration circuit reaches the reference value, except when the capacitance value control unit changes and sets the capacitance value of the first integration capacitance unit; It is suitable to provide.

  In this case, the charge integration circuit uses the first integration circuit except for the case where the capacitance value control unit changes and sets the capacitance value of the first integration capacitor unit based on the saturation signal output from the comparison circuit. A certain amount of charge having a polarity opposite to that of the charge accumulated in the first integration capacitor is injected into the first integration capacitor. Also, based on the saturation signal output from the comparison circuit, the count value is output from the first integration circuit by the counting circuit except when the capacitance value control unit changes and sets the capacitance value of the first integration capacitance unit. The number of times the voltage value reaches the reference value is counted. An AD conversion function is realized by the first integration circuit, the comparison circuit, the charge injection circuit, and the counting circuit.

  The signal processing apparatus according to the present invention includes: (1) an amplifier circuit that inputs a voltage value held and output by the holding circuit, amplifies the input voltage value K times (where K> 1), and outputs the amplified voltage value; (2) It is preferable to further include an AD conversion circuit that sets a voltage value K times the reference value in the comparison circuit as a maximum input voltage value and outputs a digital value corresponding to the voltage value output from the amplifier circuit. is there. At this time, the signal processing apparatus according to the present invention inputs a reference value for setting the maximum input voltage value in the AD converter circuit, and compares the voltage value that is 1 / Kth of the reference value as a reference value. It is preferable to further include a reference value generation circuit to be given to the circuit.

  In this case, the voltage value held and output by the holding circuit is amplified K times by the amplifier circuit and output to the AD conversion circuit. In the AD conversion circuit, the voltage value K times the reference value in the comparison circuit is set as the maximum input voltage value, the voltage value output from the amplifier circuit is input, and a digital value corresponding to this voltage value is output. In this signal processing device, the amount of incident light is detected based on the value of the number of times counted by the counting circuit and the digital value output from the AD conversion circuit.

The signal processing apparatus according to the present invention further includes (1) an amplifier circuit that inputs a voltage value held and output by the holding circuit, amplifies the input voltage value, and outputs the amplified voltage value. (2) a capacitance value control unit However, when a saturation signal is output from the comparison circuit in the middle of the charge accumulation operation in the first integration circuit, the first integration capacitance is _set with the predetermined capacitance value _Cset as the upper limit in the variable range of the capacitance value of the first integration capacitance section. (3) The ratio of the capacitance value C _final of the first integral capacitance unit and the predetermined capacitance value C _set during the voltage value sampling operation in the holding circuit (C _final / C _set ) It is preferable that the input voltage value is amplified and output with a value that is a constant multiple of.

In this case, when the saturation signal is output from the comparison circuit during the charge accumulation operation in the first integration circuit by the capacitance value control unit, the capacitance value of the first integration capacitance unit is a predetermined capacitance value within the variable range. C _set is _set as the upper limit. The voltage value held and output by the holding circuit is converted into a ratio (C _final / C) between the capacitance value C _final of the first integration capacitor unit and the predetermined capacitance value C _set during the voltage value sampling operation in the holding circuit. The value is multiplied by a constant multiple of _set ).

The signal processing apparatus according to the present invention includes (1) an AD conversion circuit that outputs a digital value corresponding to a voltage value held and output by the holding circuit, and a digital value output from the AD conversion circuit. A digital value processing unit that processes and outputs an input digital value; and (2) when the capacitance value control unit outputs a saturation signal from the comparison circuit during the charge accumulation operation in the first integration circuit. The capacitance value of the first integration capacitor unit is _set with the predetermined capacitance value C _set as the upper limit in the variable range of the capacitance value of the first integration capacitor unit. (3) The digital value processing unit performs the voltage value sampling operation in the holding circuit. Multiplying the input digital value by a constant multiple of the ratio (C _final / C _set ) of the capacitance value C _final of the first integral capacitance part and the predetermined capacitance value C _set to the digital value obtained by the multiplication It is preferable to output.

In this case, when the saturation signal is output from the comparison circuit during the charge accumulation operation in the first integration circuit by the capacitance value control unit, the capacitance value of the first integration capacitance unit is a predetermined capacitance value within the variable range. C _set is _set as the upper limit. The voltage value held and output by the holding circuit is input to the AD conversion circuit and converted into a digital value corresponding to the input voltage value. The digital value output from the AD converter circuit is converted into a ratio (C _final / C) between the capacitance value C _final of the first integration capacitor unit and the predetermined capacitance value C _set during the voltage value sampling operation in the holding circuit by the digital value processing unit. _set ) is multiplied by a constant multiple, and a digital value obtained by the multiplication is output.

  The signal processing device according to the present invention includes a first holding circuit and a second holding circuit as holding circuits, and the amplifier circuit is a voltage corresponding to a difference in voltage value output from each of the first holding circuit and the second holding circuit. It is preferable to output a value, or it is preferable that the AD conversion circuit outputs a digital value corresponding to the difference between the voltage values output from the first holding circuit and the second holding circuit.

  In this case, the voltage value including the signal component and the noise component output from the first integration circuit is held by the first holding circuit, and the voltage value including only the noise component output from the first integration circuit is held second. Held by the circuit. A voltage value or a digital value corresponding to the difference between the voltage values output from the first holding circuit and the second holding circuit is output from the amplifier circuit or the AD conversion circuit.

  The signal processing apparatus according to the present invention includes a first holding circuit and a second holding circuit as holding circuits, and alternately holds the voltage value output from the first integrating circuit in the first holding circuit and the second holding circuit. The processing by the first integration circuit, the comparison circuit and the capacitance value control unit and the processing by the AD conversion circuit are preferably performed in parallel. By performing such a parallel operation, light detection can be performed at high speed.

  A photodetection device according to the present invention includes a photodiode that generates a charge according to the amount of incident light, and a signal processing device according to the present invention that outputs an electrical signal having a value according to the amount of charge generated by the photodiode. It is characterized by providing.

  The signal processing device and the light detection device according to the present invention can obtain the amount of light incident on the photodiode with high accuracy.

It is a figure which shows schematic structure of the photon detection apparatus 1 which concerns on this embodiment. It is a figure which shows the detailed structure of the photon detection apparatus 1 which concerns on this embodiment. It is a figure which shows the detailed structure of the photon detection apparatus 1 which concerns on this embodiment. It is a timing chart explaining operation | movement of the photon detection apparatus 1 which concerns on this embodiment. 1 is a circuit diagram of an integration circuit 10 included in a photodetecting device 1 according to the present embodiment. It is a graph showing a temporal change of the voltage value V ₁₀ outputted from the integrating circuit 10 included in the photodetector 1 according to the present embodiment. It is a timing chart explaining operation | movement of the photon detection apparatus 1 which concerns on this embodiment. It is a figure which shows the detailed structure of 1 A of photodetectors which concern on other embodiment. It is a figure which shows the detailed structure of the photodetector 1B which concerns on other embodiment. It is a figure which shows the detailed structure of 1 C of photodetectors which concern on other embodiment. It is a figure explaining the processing content of the digital value process part 130 contained in 1 C of photodetectors concerning other embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 is a diagram illustrating a schematic configuration of a photodetecting device 1 according to the present embodiment. The photodetection device 1 shown in this figure includes a photodiode array 2 and a signal processing device 3.

Photodiode array 2 includes N photodiodes _PD 1 -PD _N. N photodiodes _PD 1 -PD _N have a common configuration. The N photodiodes PD ₁ -PD _N it is preferable that are formed on a single semiconductor substrate. In addition, it is preferable that the light receiving regions of the _N photodiodes PD _{1 to} PDN are covered with a scintillator that generates scintillation light with the incidence of energy rays such as X-rays. The cathode terminals of the photodiodes PD _n reference potential _{V ref0} is inputted. Each photodiode PD _n is outputted from the generated charges corresponding to the amount of incident light anode terminal. N is an integer of 1 or more, and n is an integer of 1 or more and N or less. Further, N represents a 2 or more integer, N-number of photodiodes PD ₁ -PD _N may be arranged one-dimensionally or two-dimensionally.

The signal processing unit 3 outputs an electric signal (digital signal) having a value corresponding to the amount of charges generated in the photodiodes PD _n. The signal processing device 3 includes N reading units 4 ₁ to 4 _N , an amplifier circuit 70, an AD conversion circuit 80, a reference value generation circuit 90, a voltage source 100, an integration circuit (second integration circuit) 110, and a timing instruction signal generation Circuit 120 is included. The N reading units 4 ₁ to 4 _N have a common configuration. Each readout section 4 _n is provided corresponding to the photodiode PD _n . The signal processing device 3 is preferably formed on a semiconductor substrate different from the semiconductor substrate on which the photodiode array 2 is formed. Further, a scintillator is provided on the back surface of the semiconductor substrate on which the photodiode array 2 is formed, and the surface of the semiconductor substrate on which the photodiode array 2 is formed and the surface of the semiconductor substrate on which the signal processing device 3 is formed are connected to each other by bumps. It is preferred that

Each readout unit 4 _n includes an integration circuit (first integration circuit) 10, a comparison circuit 20, a charge injection circuit 30, a capacitance value control unit 40, a holding circuit 50, a counting circuit 60, and a switch SW. The integrating circuit 10 included in each reading unit 4 _n includes an amplifier, an integrating capacitor unit, and a switch, accumulates the charge output from the corresponding photodiode PD _n in the integrating capacitor unit, and stores the accumulated charge amount and the capacitance value. Is output to the comparison circuit 20 and the holding circuit 50. The capacitance value of the integration capacitor is set variably.

  The comparison circuit 20 receives the voltage value output from the integration circuit 10, compares the input voltage value with a predetermined reference value, and indicates when the input voltage value reaches the reference value. The saturation signal is output to the charge injection circuit 30, the capacitance value control unit 40 and the counting circuit 60. The holding circuit 50 samples and holds the voltage value output from the integrating circuit 10, and outputs the held voltage value to the amplifier circuit 70. The timing of sampling the voltage value is instructed by a timing instruction signal output from the timing instruction signal generation circuit 120.

The capacitance value control unit 40 controls the capacitance value of the integration capacitor unit of the integration circuit 10. Specifically, the capacitance value control section 40 is set to the minimum value the capacitance value of the integral capacitance part C ₁₀ during the charge accumulation operation starts in the integration circuit 10. When the saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10, the capacitance value control unit 40 starts from the charge accumulation operation start in the integration circuit 10 until the saturation signal is output in the comparison circuit 20. As the time is shorter, the capacitance value of the integration capacitor is set to a larger value.

The charge injection circuit 30 is connected to the integration capacitor unit of the integration circuit 10 except when the capacitance value control unit 40 changes and sets the capacitance value of the integration capacitor unit based on the saturation signal output from the comparison circuit 20. A certain amount of charge having a polarity opposite to that of the accumulated charge is injected into the integrating capacitor. The counting circuit 60 outputs the voltage value output from the integration circuit 10 except when the capacitance value control unit 40 changes and sets the capacitance value of the integration capacitance unit based on the saturation signal output from the comparison circuit 20. Count the number of times that reached the reference value. The counting circuit 60 included in each reading unit 4 _n is connected to a common wiring through the switch SW.

The input terminal of the amplifier circuit 70 is connected to the output terminal of the holding circuit 50 included in each reading unit 4 _n . Amplifier circuit 70 inputs the voltage values sequentially output is held by the holding circuit 50 included in each readout unit 4 _n, and a voltage value the input K times (where, K> 1) Voltage The value is output to the AD conversion circuit 80.

  The AD conversion circuit 80 sets the voltage value K times the reference value in the comparison circuit 20 as the maximum input voltage value, inputs the voltage value output from the amplifier circuit 70, and outputs a digital value corresponding to the input voltage value. To do. The reference value generation circuit 90 inputs a reference value for setting the maximum input voltage value in the AD conversion circuit 80, and a voltage value that is 1 / K of the input reference value is input to the comparison circuit 20. Use the reference value. The reference value generation circuit 90 can be configured by a resistance dividing circuit.

  The voltage source 100 outputs a constant voltage value to the integrating circuit 110 from the start of the charge accumulation operation in the integrating circuit 10 until the timing indicating signal is output from the timing indicating signal generation circuit 120. The voltage value output from the voltage source 100 is preferably set by a digital code input from the outside.

  The integration circuit 110 includes an amplifier, an integration capacitor unit, a switch, and a resistor, and a timing instruction is given for a voltage value representing a value obtained by integrating the voltage value output from the voltage source 100 after the charge storage operation in the integration circuit 10 is started. Output to the signal generation circuit 120. The open loop gain of the amplifier of the integration circuit 110 is equal to the open loop gain of the amplifier of the integration circuit 10. Further, the capacitance value of the integration capacitor unit of the integration circuit 110 is equal to the capacitance value of the integration capacitor unit of the integration circuit 10.

  The timing instruction signal generation circuit 120 compares the voltage value output from the integration circuit 110 with a reference value, and outputs a timing instruction signal indicating the timing at which the voltage value reaches the reference value to the holding circuit 50.

  2 and 3 are diagrams showing a detailed configuration of the photodetecting device 1 according to the present embodiment. FIG. 2 shows a set of photodiodes PD and a reading unit 4, and also shows an amplifier circuit 70, an AD conversion circuit 80, and a reference value generation circuit 90. Here, it is assumed that two holding circuits 51 and 52 are provided as the holding circuit 50. FIG. 3 shows a voltage source 100, an integration circuit 110, and a timing instruction signal generation circuit 120.

As shown in FIG. 2, the integration circuit 10 includes an amplifier A ₁₀ , an integration capacitor unit C _10, and a switch SW ₁₀ . Non inverting input terminal of the amplifier _{A 10} is connected to the reference potential _{V ref0.} Inverting input terminal of the amplifier A ₁₀ is connected to the photodiode PD. Integral capacitance part C ₁₀ and the switch SW ₁₀ between the inverting input terminal and the output terminal of the amplifier A ₁₀ is provided in parallel. The capacitance value of the integral capacitance part C ₁₀ is a variable and is set by the capacity value control unit 40. In the integration circuit 10, during the initialization period in which the switch SW ₁₀ is closed, the integration capacitor unit C ₁₀ is discharged, and a reset level voltage value is output. On the other hand, the integrating circuit 10, later than the charge accumulation start switch SW ₁₀ turns from the closed state to the open state, to accumulate charges output from the photodiode PD in the integrating capacitor unit C _10, the integral capacitance part A voltage value V ₁₀ corresponding to the amount of charge accumulated in C ₁₀ and the capacitance value is output. In the following, the capacitance value of the integral capacitance part _{C 10} shall be set to any one of _C 1, _{C 2} and _{C 3.}

Comparator circuit 20 inputs the voltage _{V 10} outputted from the integrating circuit 10, and the voltage value _{V 10} and a predetermined reference value _{V ref2} to magnitude comparison. When the voltage value V ₁₀ reaches the reference value V _ref2 , the comparison circuit 20 outputs a saturation signal φ ₁ indicating that fact.

The capacitance value control unit 40 controls the capacitance value of the integration capacitor unit C ₁₀ of the integration circuit 10. Specifically, the capacitance value control unit 40, at the start charge accumulation operation of the integrating circuit 10 (i.e., when the switch SW ₁₀ is turned from a closed state to an open state) the minimum capacitance value of the integral capacitance part C ₁₀ to Set to. When the saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10, the capacitance value control unit 40 starts from the charge accumulation operation start in the integration circuit 10 until the saturation signal is output in the comparison circuit 20. time is set to a large value the capacitance value of the shorter integral capacitance part C _10.

The charge injection circuit 30 includes switches SW _{31 to} SW ₃₄ and a capacitor unit C ₃₀ . The switch SW ₃₁ , the capacitor unit C ₃₀ and the switch SW ₃₂ are connected in order, the other end of the switch SW ₃₁ is connected to the inverting input terminal of the amplifier A ₁₀ of the integrating circuit 10, and the other end of the switch SW ₃₂ is The reference potential V _inj is connected. A connection point between the switch SW ₃₁ and the capacitor C ₃₀ is connected to the reference potential V _ref0 via the switch SW ₃₃ . A connection point between the switch SW ₃₂ and the capacitor C ₃₀ is connected to the reference potential V _ref0 through the switch SW ₃₄ .

Except where capacitance value control unit 40 sets by changing the capacitance value of the integral capacitance part C _10, the switches SW ₃₁ and SW ₃₄ are opened and closed and on the basis of the saturation signal phi ₁ that is output from the comparator circuit 20 The switches SW ₃₂ and SW ₃₃ open and close based on the logic inversion signal φ ₂ of the saturation signal φ ₁ output from the comparison circuit 20. That is, the charge injection circuit 30 is integrated based on the saturation signal φ ₁ output from the comparison circuit 20 except when the capacitance value control unit 40 changes and sets the capacitance value of the integration capacitance unit C _10. injecting a predetermined amount of charges of opposite polarity to be accumulated in the integrating capacitor unit C ₁₀ of the circuit 10 to the integrating capacitor unit C _10.

Counting circuit 60 based on the saturation signal phi ₁ that is output from the comparator circuit 20, unless the capacitance value control unit 40 sets by changing the capacitance value of the integral capacitance part C _10, output from the integrating circuit 10 The number of times that the voltage value V reached the reference value V _ref2 is counted, and this counted value is output as a digital value.

The integration circuit 10, the comparison circuit 20, the charge injection circuit 30, and the counting circuit 60 have an AD conversion function. That is, the absolute value of the amount of charge that is accumulated in the integrating capacitor unit C ₁₀ of the integrating circuit 10 is output from the photodiode PD within a certain period and Q _0, the saturation signal output from the comparison circuit 20 phi ₁ the absolute value of the integral capacitance part amount of injected charge on C ₁₀ of the integrating circuit 10 by the charge injection circuit 30 based on the Q _1. At this time, the count value by the counter circuit 60 (digital value) is an integer value by truncating the fractional part for the value obtained by dividing the Q ₀ in Q _1. Further, the voltage value output from the integration circuit 10 at the end of the predetermined period is a voltage corresponding to the residual value obtained by subtracting the integer value from the value obtained by dividing Q ₀ by Q _1. Value.

The holding circuit 51 and the holding circuit 52 have a common configuration. Each of the holding circuit 51 and the holding circuit 52 includes switches SW _{51 to} SW ₅₄ and a capacitor unit C ₅₀ . The switch SW ₅₁ , the capacitor unit C ₅₀ and the switch SW ₅₂ are connected in order, the other end of the switch SW ₅₁ is connected to the output terminal of the amplifier A ₁₀ of the integrating circuit 10, and the other end of the switch SW ₅₂ is amplified. The input terminal of the circuit 70 is connected. A connection point between the switch SW ₅₁ and the capacitor C ₅₀ is connected to the reference potential V _ref0 through the switch SW ₅₃ . A connection point between the switch SW ₅₂ and the capacitor C ₅₀ is connected to the reference potential V _ref0 via the switch SW ₅₄ .

In each of the holding circuit 51 and the holding circuit 52, the switches SW ₅₁ and SW ₅₄ open and close simultaneously. Switches SW ₅₂ and SW ₅₃ open and close simultaneously. When the switches SW ₅₁ and SW _{54 change} from the closed state to the open state, the output voltage value from the integrating circuit 10 is held in the capacitor unit C ₅₀ immediately before that. When the switches SW ₅₂ and SW ₅₃ are closed, the voltage value held in the capacitor unit C ₅₀ is output to the amplifier circuit 70.

The holding circuit 51 samples and holds the voltage value output from the integrating circuit 10 at the end of the operation after the charge accumulation operation is performed in the integrating circuit 10 for a fixed period, and the held voltage value V _51. Is output to the amplifier circuit 70. The timing of sampling the voltage value by the holding circuit 51 is instructed by a timing instruction signal output from the timing instruction signal generation circuit 120. On the other hand, the holding circuit 52 samples and holds the noise voltage value immediately after the reset output from the integrating circuit 10 at the moment when the switch SW ₁₀ of the integrating circuit 10 is opened from the closed state, and holds the held voltage value V. ₅₂ is output to the amplifier circuit 70.

Amplifier circuit 70 inputs the voltage value V ₅₁ output from the holding circuit 51 inputs the voltage value V ₅₂ output from the holding circuit 52, K times the difference between the inputted two voltage values The converted voltage value (K (V ₅₁ −V ₅₂ )) is output to the AD conversion circuit 80. The voltage value V ₅₁ output from the holding circuit 51 is an AD by the AD conversion function constituted by the integration circuit 10, the comparison circuit 20, the charge injection circuit 30, and the counting circuit 60 among the voltage values including the signal component and the noise component. This is the residual voltage value at the time of conversion. The voltage value V ₅₂ output from the holding circuit 52 does not include a signal component but includes only a noise component. Therefore, the voltage value output from the amplifier circuit 70 represents a value after the noise component is removed from the remaining voltage value.

As described above, the amplifier circuit 70 receives the voltage value held and output by the holding circuits 51 and 52, and converts the voltage value obtained by multiplying the difference between the two input voltage values by K times. Output to 80. Further, the AD conversion circuit 80 sets the voltage value K times the reference value in the comparison circuit 20 as the maximum input voltage value, inputs the voltage value output from the amplifier circuit 70, and outputs a digital value corresponding to the input voltage value. Is output. Therefore, the reference value generation circuit 90 inputs the reference value V _ref1 for setting the maximum input voltage value in the AD conversion circuit 80, and the voltage value of 1 / K of the reference value V _ref1 (V _ref1 / K). ) To the comparison circuit 20 as a reference value V _ref2 .

As shown in FIG. 3, the voltage source 100 includes a reference power source 101, a voltage value setting unit 102, an amplifier A ₁₀₀ , a capacitor unit C ₁₀₀ , a capacitor unit C _101, and switches SW _{100 to} SW ₁₀₄ . The voltage source 100 outputs a constant voltage value to the integration circuit 110 after the start of the charge accumulation operation in the integration circuit 10 (that is, when the switch SW ₁₀ changes from the closed state to the open state).

The reference power supply 101 is a power supply that outputs a constant voltage, and preferably comprises a band gap circuit that can output a constant voltage stably against power supply voltage fluctuations and temperature fluctuations. Between the reference power supply 101 and the inverting input terminal of the amplifier A ₁₀₀ , a switch SW ₁₀₁ , a capacitor unit C ₁₀₁ and a switch SW ₁₀₂ are provided in this order. A connection point between the switch SW ₁₀₁ and the capacitor C ₁₀₁ is connected to the reference potential V _ref0 through the switch SW ₁₀₃ . A connection point between the capacitor C ₁₀₁ and the switch SW ₁₀₂ is connected to the reference potential V _ref0 via the switch SW ₁₀₄ . The non-inverting input terminal of the amplifier _{A 100} is connected to the reference potential _{V ref0.} A capacitor C ₁₀₀ and a switch SW ₁₀₀ are provided in parallel between the inverting input terminal and the output terminal of the amplifier A ₁₀₀ . The voltage value setting unit 102 inputs a digital code indicating the voltage value to be output from the voltage source 100 from the outside, and performs the opening / closing operation of the switches SW _{101 to} SW ₁₀₄ as many times as the value represented by the digital code. .

In the voltage source 100, by the switch _{SW 100} is closed, capacitor portion _{C 100} is discharged, the output voltage value is initialized to _{V ref0.} While the switch SW ₁₀₀ is open, the switches SW ₁₀₁ and SW ₁₀₄ are closed and the switches SW ₁₀₂ and SW ₁₀₃ are open, and then the switches SW ₁₀₁ and SW ₁₀₄ are open and the switches SW ₁₀₂ and SW ₁₀₃ are open. By switching to the closed state, an amount of electric charge (hereinafter referred to as “unit amount electric charge”) corresponding to the product of the output voltage value of the reference power supply 101 and the capacitance value of the capacitor C ₁₀₁ is accumulated in the capacitor C ₁₀₀ . Is done.

During the period in which the switch SW ₁₀₀ is open, the unit amount charge is accumulated in the capacitor unit C _{100 as} many times as the value represented by the digital code input to the voltage value setting unit 102. Such accumulation of charge in the capacitor unit C ₁₀₀ is performed during an initialization period in which the switch SW ₁₀ of the integration circuit ₁₀ is closed. The voltage value output from the voltage source 100 after the start of the charge accumulation operation in the integration circuit 10 is a value corresponding to the product of the unit amount charge and the number of accumulations.

As the integration circuit (second integration circuit) 110, three integration circuits 110 _{1 to} 110 ₃ are provided. The integration circuit 110 ₁ includes an amplifier A ₁₁₁ , an integration capacitor unit C ₁₁₁ , a switch CW ₁₁₁ and a resistor R ₁₁₁ . A capacitor C ₁₁₁ and a switch SW ₁₁₁ are provided in parallel between the inverting input terminal and the output terminal of the amplifier A ₁₁₁ . The inverting input terminal of the amplifier A ₁₁₁ is connected to the output terminal of the voltage source 100 via the resistor R ₁₁₁ . The non-inverting input terminal of the amplifier A ₁₁₁ is connected to the reference potential V _ref0 .

The integrating circuit 110 _1, the switch _{SW 10} of the integrating circuit 10 to the charge accumulation operation starts to turn from a closed state to an open state, the switch _{SW 111} turns from the closed state to an open state. Then, the integrating circuit 110 ₁ outputs a voltage value that represents the integrated value of the voltage output from the voltage source 100 since from the start of charge accumulation operations.

Integrator circuit 110 ₂ includes an amplifier _{A 112,} the integrating capacitor unit _{C 112,} a switch _{CW 112} and resistor _{R 112.} Integrator circuit 110 ₃ includes an amplifier _{A 113,} the integrating capacitor unit _{C 113,} switches _{CW 113} and resistor _{R 113.} The configurations and operations of the integration circuits 110 ₂ and 110 ₃ are the same as those of the integration circuit 110 ₁ .

The open loop gains of the amplifiers A ₁₁₁ , A ₁₁₂ , and A ₁₁₃ are equal to the open loop gain of the amplifier A ₁₀ of the integration circuit 10. These amplifiers A ₁₁₁ , A ₁₁₂ , A ₁₁₃ and A ₁₀ preferably have a common configuration. The capacitance value of the integration capacitor unit C ₁₁₁ of the integration circuit 110 ₁ is C ₁ , the capacitance value of the integration capacitor unit C ₁₁₂ of the integration circuit 110 ₂ is C ₂ , and the capacitance value of the integration capacitor unit C ₁₁₃ of the integration circuit 110 _3. value is _{C 3.} These capacitance values C _{1 to} C ₃ are values that can be set as the capacitance value of the integration capacitor unit C ₁₀ of the integration circuit 10. The product of the resistance value of the resistor R ₁₁₁ of the integrating circuit 110 ₁ and the capacitance value C ₁ of the integrating capacitor unit C ₁₁₁ , the resistance value of the resistor R ₁₁₂ of the integrating circuit 110 ₂ and the capacitance value C ₂ of the integrating capacitor unit C _112. product of, and, the product of the resistance value and the capacitance value _{C 3} of the integral capacitance part _{C 113} of the integrator circuit 110 _third resistor _{R 113} are equal to each other.

As the timing instruction signal generation circuit 120, three generation circuits 120 _{1 to} 120 ₃ are provided. Generating circuit 120 _1, the voltage value and the reference value _{V ref3} output from the integrating circuit 110 ₁ and compares outputs a timing indication signal indicating the timing at which the voltage value has reached the reference value _{V ref3.} Generating circuit 120 _2, the voltage value and the reference value _{V ref3} output from the integrating circuit 110 ₂ and compares outputs a timing indication signal indicating the timing at which the voltage value has reached the reference value _{V ref3.} Also, generating circuit 120 _3, the voltage value and the reference value _{V ref3} output from the integrating circuit 110 ₃ and compares outputs a timing indication signal indicating the timing at which the voltage value has reached the reference value _{V ref3} .

The holding circuit 51 is a voltage value output from the integrating circuit 10 at a timing indicated by the timing instruction signal output from the generating circuit 120 _m corresponding to the set capacitance value C _m of the integrating capacitor unit C ₁₀ of the integrating circuit 10. Is sampled, held and output.

In addition, it is preferable that the light detection device 1 according to the present embodiment further includes a control unit. The control unit, opening and closing operations of the switches _{SW 10} in the integrating circuit 10, the counting operation of the counter circuit 60, opening and closing operations of the switches _SW 51 _{to SW 54} in the holding circuit 51 and 52, AD conversion operation in the AD converter circuit 80, a voltage source The opening / closing operation of the 100 switch SW _{100 and} the opening / closing operation of the switches SW _{111 to} SW ₁₁₃ of the generation circuits 120 _{1 to} 120 ₃ as the timing instruction signal generation circuit 120 are controlled at a predetermined timing.

Next, the operation of the photodetecting device 1 according to this embodiment will be described. FIG. 4 is a timing chart for explaining the operation of the photodetecting device 1 according to this embodiment. Here, the operations of the reading unit 4 _n , the amplifier circuit 70, and the AD conversion circuit 80 will be described, and the operations of the integrating circuit 110, the timing instruction signal generation circuit 120, and the digital value processing unit 130 will be described later. However, assuming that the control of the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 according to the capacitance value control section 40 is not performed, the capacitance value of the integral capacitance part C ₁₀ over a period of charge accumulation operations in the integrating circuit 10 Suppose that it is constant.

During the initialization period from time t ₀ to time t ₁ , the switch SW ₁₀ of the integration circuit 10 is closed, the integration capacitor C ₁₀ is discharged, and the voltage value V ₁₀ output from the integration circuit ₁₀ is at the reset level. . At this time, the saturation signal φ ₁ output from the comparison circuit 20 is at the logic level L, the switches SW ₃₁ and SW _{34 of} the charge injection circuit 30 are open, and the switches SW ₃₂ and SW _{33 of the} charge injection circuit 30 are open. Is closed, and the count value in the count circuit 60 is initialized to 0.

At time t ₁ , the switch SW ₁₀ of the integration circuit 10 is opened and the charge accumulation operation is started. Thereafter, the charge generated in the photodiode PD is accumulated in the integration capacitor unit C _10, and the accumulated charge A voltage value V ₁₀ corresponding to the amount is output from the integrating circuit 10. The voltage value V ₁₀ output from the integration circuit 10 is compared with the reference value V _ref2 by the comparison circuit 20.

To time t _2, the when the voltage value V ₁₀ outputted from the integrating circuit 10 reaches the reference value V _ref2, saturation signal phi ₁ that is output from the comparator circuit 20 is turned to the logic level H from the logic level L, With this The switches SW ₃₁ and SW ₃₄ of the charge injection circuit 30 are closed and the switches SW ₃₂ and SW ₃₃ are opened.

Then, the charge amount Q ₁₀ (= C ₁₀ · V _ref2 ) accumulated in the integration capacitor unit C ₁₀ when the voltage value V ₁₀ output from the integration circuit 10 reaches the reference value V _ref2 , and until that time charge amount _Q 30 that has been accumulated in the capacitance section _{C 30} of the charge injection circuit 30 into equal ₍₌ C 30 _{· V inj)} and to each other, the charges accumulated in the capacitor section _{C 30} of the charge injection circuit 30 is integrated It is injected into the integral capacitance part C ₁₀ of the circuit 10, the charge accumulation amount in the integrating capacitor unit C ₁₀ is reset.

Thereby, the voltage value V ₁₀ outputted from the integrating circuit 10 is once becomes the reset level, the voltage value V ₁₀ corresponding to the amount of the subsequently accumulated charge is output from the integrating circuit 10. Immediately, the saturation signal φ ₁ output from the comparison circuit 20 goes to the logic level L. Accordingly, the switches SW ₃₁ and SW _{34 of the} charge injection circuit 30 are opened, and the switches SW ₃₂ and SW ₃₃ are respectively switched. close up.

Time _{t 3,} time _{t 4,} even at time _{t 5} and time _{t 6,} respectively, the series of operations described above at time _{t 2} is performed. Here, time τ ₁₂ from time t ₁ to time t ₂ , time τ ₂₃ from time t ₂ to time t ₃ , time τ ₃₄ from time t ₃ to time t ₄ , time t ₄ to time t ₅ Time τ ₄₅ and time τ ₅₆ from time t ₅ to time t ₆ are equal to each other if the amount of light incident on the photodiode PD is constant.

Such a repetitive operation is performed from time t ₁ when the charge accumulation operation in the integration circuit 10 is started to time t ₇ (= t ₁ + T) when the integration period T elapses. Time from the time _{t 6} to time _{t 7} is shorter than such as the time τ _12. During the integration period T, the counting circuit 60 counts the number of times that the saturation signal φ ₁ output from the comparison circuit 20 changes from the logic level L to the logic level H. That is, the count value in the counter circuit 60 becomes a value 1 becomes the time _{t 2, the} next value 2 at time _{t 3,} time _{t 4} to the value 3, and the value becomes 4 at time _{t 5,} the value 5 to the time _{t 6} . That is, the AD conversion function is realized by the integration circuit 10, the comparison circuit 20, the charge injection circuit 30, and the counting circuit 60.

Prior to time t _7, the switches SW ₅₁ and SW ₅₄ of the holding circuit 51 are closed, and at time t ₇ , the switches SW ₅₁ and SW ₅₄ of the holding circuit 51 are opened. As a result, the signals are output from the integrating circuit 10 immediately before time t _7. The value V ₅₁ of the voltage value V ₁₀ that has been sampled is sampled and held by the holding circuit 51. Also, the switch _SW 51, _{SW 54} of the holding circuit 52 is closed at time _{t 1,} the time _{t 1} the switch _SW 51, _{SW 54} of the holding circuit 52 immediately opens, resulting, integrating circuit 10 at time _{t 1} the switch A value V ₅₂ of noise (kTC noise) generated by opening the SW ₁₀ and output from the integration circuit 10 is sampled and held by the holding circuit 52.

Then, between times _{t 7} after the time _t 8 ~t _9, the holding circuit 51 and the holding circuit 52 by the closing respective switches _SW 52, _{SW 53,} the voltage value _{V 51} that has been held by the holding circuit 51, The voltage value V ₅₂ held by the holding circuit 52 is input to the amplifier circuit 70, and a voltage value (K (V ₅₁ −V ₅₂ )) that is K times the difference between the two voltage values is supplied to the amplifier circuit. 70. The voltage value output from the amplifier circuit 70 is input to the AD conversion circuit 80, and a digital value corresponding to the input voltage value is output from the AD conversion circuit 80.

Further, after time t _7, the counting operation in the counting circuit 60 is stopped, and the count value at the time t ₇ is held by the counting circuit 60. Then, between times t ₈ ~t _9, closes the switch SW of the read unit 4 _n, the count value that has been held by the counter circuit 60 of the read section 4 _n is outputted via the switch SW.

Among the operations described above, the operations between times t _{0 to} t ₇ are simultaneously performed in parallel in the _N reading units 4 ₁ to 4 _N. On the other hand, the time _{t 7} after the operation is performed sequentially for the N reading unit ₄ 1 to 4 _N. As described above, for each of the N readout units 4 ₁ to 4 _N , the first digital value that is the count value by the count circuit 60 and the AD value as the output value with respect to the incident light amount to the photodiode PD, and AD A second digital value that is an AD conversion result by the conversion circuit 80 is obtained.

As can be seen from the above-described operation, the second digital value is positioned lower than the first digital value. If the first digital value is represented by M1 bits and the second digital value is represented by M2 bits, the digital value output from the photodetector 1 is (M1 + M2) bits of data D _{M1 + M2−.} It expressed as ₁ to D _0. Of these, the upper M1 bit data D _{M1 + M2-1 to} D _M2 correspond to the first digital value, and the lower M2 bit data D _{M2-1 to} D ₀ correspond to the second digital value.

Accordingly, in the light detection apparatus 1 according to the present embodiment, assuming that the control of the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 according to the capacitance value control section 40 is not performed, the period of charge accumulation operations in the integrating circuit 10 T When the capacitance value of the integral capacitance part _{C 10} over (time _t 1 ~t ₇₎ is constant, the incident light amount to the photodiode PD, the integrating circuit 10, comparator circuit 20, a charge injection circuit 30 and counting The AD conversion function realized by the circuit 60 converts the first digital value, and the AD converter circuit 80 converts the remaining value that cannot be AD converted into a second digital value. The Therefore, the light detection device 1 can detect the amount of incident light in a short time with a large dynamic range. In this photodetection device 1, when a plurality of photodiodes PD are arranged in a one-dimensional or two-dimensional manner, an incident light image can be taken with a large dynamic range.

In the optical detector 1 according to the present embodiment, the amplifier circuit 70 inputs the voltage value V ₅₁ output from the holding circuit 51 inputs the voltage value V ₅₂ output from the holding circuit 52, A voltage value (K (V ₅₁ −V ₅₂ )) obtained by multiplying the difference between the two input voltage values by K times (where K> 1) is output to the AD conversion circuit 80. The AD conversion circuit 80 sets the voltage value K times the reference value V _ref2 in the comparison circuit 20 as the maximum input voltage value, inputs the voltage value output from the amplifier circuit 70, and inputs the voltage value corresponding to this voltage value. 2 digital values (lower-order M2 bit data D _{M2-1 to} D ₀ ) are output. Thereby, noise generated during the AD conversion operation in the AD conversion circuit 80 is suppressed to 1 / K, so that the digital values (data D _{M1 + M2-1 to} D ₀ ) output from the light detection device 1 are highly accurate. Can be. Thus, the photodetector 1 according to the present embodiment can output a highly accurate digital value corresponding to the amount of incident light.

However, the operation of the capacitance value of the integral capacitance part C ₁₀ over a period T of the charge accumulation operation (time t ₁ ~t ₇₎ has been described so far above as being constant in the integration circuit 10, a saturation signal from the comparison circuit 20 Is output and the charge injection circuit 30 injects charges into the integration capacitor unit C ₁₀ of the integration circuit 10, so that the instantaneous response speed of the amplifier is required, and the power consumption increases in order to increase the bandwidth of the amplifier. . Therefore, the light detection apparatus 1 according to this embodiment, the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 with a variable, the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 by the capacitance value control section 40 by controlling, by reducing the number of charges to the integrating capacitor unit C ₁₀ of the integrating circuit 10 by the charge injection circuit 30 is injected, to reduce power consumption. Hereinafter, the integration circuit 10 and the capacitance value control unit 40 included in the photodetector 1 according to the present embodiment will be described in more detail.

FIG. 5 is a circuit diagram of the integrating circuit 10 included in the photodetector 1 according to the present embodiment. The integration circuit 10 includes an amplifier A ₁₀ , an integration capacitor unit C _10, and a switch SW ₁₀ . Non inverting input terminal of the amplifier _{A 10} is the reference potential _{V ref0} supplied. Inverting input terminal of the amplifier A ₁₀ is connected to the photodiode PD. Integral capacitance part C ₁₀ and the switch SW ₁₀ between the inverting input terminal and the output terminal of the amplifier A ₁₀ is provided in parallel.

Integral capacitance part _{C 10} of the integrating circuit 10 includes a switch _SW 12, _{SW 13} and the capacitor unit _C 11 _{-C 13.} A capacitor unit _{C 11,} a switch _{SW 12} and the capacitor section _{C 12} which are serially connected, the switch _{SW 13} and the capacitor section _{C 13} which are serially connected, an inverting input terminal of the amplifier _{A 10} and the output terminal Are provided in parallel. Capacitance of the capacitor section _{C 11} is _{C 1,} the sum of the capacitance section _{C 11} and the capacitor unit _{C 12} each capacitance value is _{C 2,} capacitor unit _C 11 _{-C 13} is the sum of the capacitance value _{C 3} It is. The magnitude relationship between the capacitance values C _{1 to} C ₃ is “C ₁ <C ₂ <C ₃ ”.

Capacity value control unit 40, by controlling the switch _SW 12, _{SW 13} of each opening and closing operation included in the integrating capacitor unit _{C 10,} the capacitance value of the integral capacitance part _{C 10} of the integrating circuit 10 of _C 1 -C ₃ Set to one of these values. Capacity value control unit 40, by both the switch _SW 12, _{SW 13} in the open state and sets the capacitance value of the integral capacitance part _{C 10} to _{C 1.} Capacity value control unit 40, the switch _{SW 12} by the switch _{SW 13} are closed to the open state and sets the capacitance value of the integral capacitance part _{C 10} to _{C 2.} The capacitance value control unit 40, both the switches _SW 12, _{SW 13} by a closed, sets the capacitance value of the integral capacitance part _{C 10} to _{C 3.}

The capacitance value control unit 40 opens both the switches SW ₁₂ and SW ₁₃ at the start of the charge accumulation operation in the integration circuit 10 (time t _{1 in} FIG. 4), so that the capacitance of the integration capacitance unit C ₁₀ is opened. setting the value to the minimum value C _1. The capacitance value control unit 40 starts the charge accumulation operation in the integration circuit 10 when a saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10 (time t _{2 in} FIG. 4). set to a large value the capacitance value of shorter integral capacitance part C ₁₀ (time tau ₁₂ from the time t ₁ in FIG. 4 to time t ₂₎ time until the saturation signal output at the comparator circuit 20 from.

Figure 6 is a diagram showing the time variation of the voltage value V ₁₀ outputted from the integrating circuit 10 included in the photodetector 1 according to the present embodiment. If the intensity of light incident on the photodiode PD is constant and the output current value of the photodiode PD is constant over the period of the charge accumulation operation, as shown in FIG. voltage V ₁₀ outputted from the gradually linearly approaching from the charge accumulation operation starts when the reset level to the reference value V _ref2 in the comparing circuit 20 with time. Each of the straight lines L ₂ and L ₃ shown in FIG. 6A is an integration circuit when the capacitance value of the integration capacitor unit C ₁₀ is set to the minimum value C ₁ over the period T of the charge accumulation operation in the integration circuit 10. It represents the temporal change of the output voltage value _{V 10} of 10.

Output current value I ₃ in the photodiode PD of the case shown by the straight line L _3, the charge accumulation capacitance value of the integral capacitance part C ₁₀ over a period T of the charge accumulation operation of the integrating circuit 10 in case of a C ₂ voltage value _{V 10} of the integration circuit 10 at the end of the period T is a value which is a saturation output voltage value _{V sat.} In the case of such an output current value I ₃ of the photodiode PD, when the capacitance value of the integration capacitor unit C ₁₀ is set to the minimum value C ₁ , the output voltage value of the integration circuit 10 from the start of the charge accumulation operation in the integration circuit 10. Let τ ₃ be the time required for V ₁₀ to reach the reference value V _ref2 .

The output current value I ₂ of the photodiode PD in the case indicated by the straight line L ₂ is the charge accumulation operation when the capacitance value of the integration capacitor unit C ₁₀ is C ₁ over the period T of the charge accumulation operation in the integration circuit 10. voltage value _{V 10} of the integration circuit 10 at the end of the period T is a value which is a saturation output voltage value _{V sat.} If the output current value I ₂ such photodiode PD, when the capacitance value of the integral capacitance part C ₁₀ and minimum value C _1, the output voltage value of the integrating circuit 10 from the time of the charge accumulation operation starts in the integration circuit 10 Let τ ₂ be the time until V ₁₀ reaches the reference value V _ref2 .

The output current values I ₂ and I ₃ of the photodiode PD are expressed by the following equation (3). Time tau ₂ from the start charge accumulation operation of the integrating circuit 10 to the output voltage value _{V 10} of the integration circuit 10 reaches the reference value _{V ref2,} tau ₃ is expressed by the following equation (4). Here, m is 2 or 3.

Note that the times τ ₂ and τ ₃ do not have to be values obtained from the above formula, and may be arbitrarily set from the outside, for example.

The capacitance value control unit 40 includes capacitance values C ₁ , C ₂ , and C ₃ of the integration capacitor unit C ₁₀ of the integration circuit 10, a saturated output voltage value V _{sat of} the integration circuit 10, and a reference value V input to the comparison circuit 20. _{Based on ref2} and the time T from the start of the charge accumulation operation in the integrating circuit 10 to the voltage value sampling operation in the holding circuit 50, the above-described times τ ₂ and τ ₃ are obtained, and the charge in the integrating circuit 10 is obtained. A period from the start of the accumulation operation to the voltage value sampling operation in the holding circuit 50 is divided into three partial periods.

When the saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10, the capacitance value control unit 40 outputs any of the three partial periods when the saturation signal is output from the comparison circuit 20. sought belongs to, by changing the capacitance value of the integral capacitance part C ₁₀ sets accordingly. Specifically, it is as follows.

As shown in FIG. 6B, when the saturation signal output time from the comparison circuit 20 belongs to the partial period from time 0 to time τ ₃ , the capacitance value control unit 40 includes the integration capacitance unit C ₁₀ . Change the capacitance value from C ₁ to C ₃ and set it. As shown in FIG. 4C, the capacitance value control unit 40, when the saturation signal output from the comparison circuit 20 belongs to a partial period from time τ ₃ to time τ ₂ , the integration capacitance unit C ₁₀ Is changed from C ₁ to C ₂ . Further, as shown in FIG. 2 (d), the capacitance value control unit 40, if it belongs to the sub-period at saturation signal output time tau ₂ later from the comparison circuit 20, the capacitance of the integrating capacitor unit C ₁₀ a value remains _{C 1.}

Thus, the capacitance value control unit 40, by setting by changing the capacitance value of the middle integral capacitance part C ₁₀ of the charge storage operation in the integrating circuit 10 to a large value from the initial minimum value C _1, the charge injection it is possible to reduce the number of times charge the integrating capacitor unit C ₁₀ of the integrating circuit 10 is injected by the circuit 30, since it does not require a fast response of the amplifier, it is possible to reduce the bandwidth of the amplifier, reducing power consumption can do.

The capacity value control unit 40, while the minimum value C ₁ of the capacitor value from the initial minimum value C ₁ if you change or the original to C ₂ in the middle of the integral capacitance part C ₁₀ of the charge storage operation in the integrating circuit 10 If set to, when the output is then the saturation signal from the comparator circuit 20 may be set by changing the capacitance value of the integral capacitance part C ₁₀ to further large value.

Further, when the capacitance value of the integration capacitor C ₁₀ is changed to C ₂ , C ₃ or is kept at the original C ₁ , when the saturation signal is output from the comparison circuit 20 thereafter, the capacitor value controller without changing the capacitance value of the integral capacitance part C ₁₀ to a large value by 40, injecting a quantity of charges of opposite polarity to be accumulated in the integrating capacitor unit C ₁₀ to integrating capacitor unit C ₁₀ by the charge injection circuit 30 and, the number of times that the voltage value V ₁₀ output from the integration circuit 10 reaches the reference value V _ref2 (i.e., the number of times the saturation signal is output from the comparator circuit 20) may be counted by a counter circuit 60 a.

The light detection apparatus 1 according to the present embodiment can detect the amount of incident light in a short time with a large dynamic range, and can reduce power consumption. However, in the optical detection apparatus 1 according to the present embodiment, even if the integral capacitance part C ₁₀ of the integrating circuit 10 is set with high accuracy in any of the capacitance C ₁ -C ₃ as designed, the amplifier A ₁₀ since the open loop gain is finite value not an ideal infinite, collapses the relationship approximate expression the output value of the integrating circuit 10 is inversely proportional to the capacitance value of the integral capacitance part C ₁₀ ((2) formula) In some cases, the amount of light incident on the photodiode PD cannot be obtained with high accuracy.

Therefore, the photodetection device 1 according to the present embodiment further includes a voltage source 100, an integration circuit 110, and a timing instruction signal generation circuit 120, and thereby, when the charge accumulation operation starts in the integration circuit 10 (time in FIG. 4). The length of the period T from the time t ₁ ) to the time of the voltage value sampling operation in the holding circuit 51 (time t _{7 in} FIG. 4) is adjusted.

FIG. 7 is a timing chart for explaining the operation of the photodetecting device 1 according to this embodiment. Here, operations of voltage source 100, integration circuit 110, timing instruction signal generation circuit 120, and holding circuit 51 will be described. The time _t 0, _{t 1} shown in FIG. 7 is the same as the time _t 0, _{t 1} shown in FIG. Further, any one of the times t ₇₁ , t ₇₂ , and t ₇₃ shown in FIG. ₇ corresponds to the time t ₇ shown in FIG.

As described above, in the voltage source 100, the initialization period t ₀ ~t ₁ switch SW ₁₀ of the integrating circuit 10 is closed, a number of times corresponding to a value represented by a digital code that is input to the voltage value setting portion 102 capacity accumulation unit quantity charges to parts C ₁₀₀ is performed. Then, the voltage value outputted from the voltage source 100 since from the charge accumulation operation starts t ₁ is a constant value corresponding to the product of and the accumulation times the unit weight charge.

Switch _SW 111 _{to SW 113} of the integration circuit _{1101 3,} similar to the switches _{SW 10} of the integrating circuit 10, an initialization period _t 0 ~t closed at _1, the charge accumulation operation starts _{t 1} later than Then it is open. The voltage value output from the integrating circuits 110 _{1 to} 110 ₃ during the initialization period t _{0 to} t ₁ is the reference potential V _ref0 . The voltage value output from the integration circuits 110 _{1 to} 110 ₃ after the charge accumulation operation start time t ₁ has changed from the reference potential V _ref0 and eventually reaches the reference potential V _ref3 .

The product of the resistance value of the resistor R ₁₁₁ of the integrating circuit 110 ₁ and the capacitance value C ₁ of the integrating capacitor unit C ₁₁₁ , the resistance value of the resistor R ₁₁₂ of the integrating circuit 110 ₂ and the capacitance value C ₂ of the integrating capacitor unit C _112. product of, and, the product of the resistance value and the capacitance value _{C 3} of the integral capacitance part _{C 113} of the integrator circuit 110 _third resistor _{R 113} are equal to each other. Thus, assuming the ideal case the open loop gain of the amplifier _A 111 _{to A 113} of the integration circuit _{1101 3} is assumed to be infinite, the integration circuit 110 after than the charge accumulation operation starts _{t 1 1} 110 voltage value output from the ₃ will change with each other as fast.

However, in practice, the open loop gain of the amplifier _A 111 _{to A 113} of the integration circuit _{1101 3} because it is a finite value not infinite, the charge accumulation start time _{t 1} integrator circuit 110 ₁ later than 110 voltage value output from the _3, will change at different speeds from each other. Accordingly, the times t ₇₁ , t ₇₂ , and t ₇₃ at which the voltage values output from the integrating circuits 110 _{1 to} 110 ₃ reach the reference potential V _ref3 after the charge accumulation operation start time t ₁ are different from each other.

When the capacitive element _{C 10} of the integrating circuit 10 is set to the capacitance value _{C 1,} the timing from the generating circuit 120 ₁ to the time _{t 71} to the voltage value output from the integrating circuit 110 ₁ reaches the reference voltage _{V ref3} instruction signal is outputted at the timing indicated by the timing indication signal output from the generating circuit 120 _1, the voltage value output from the integrating circuit 10 is sampled by a hold circuit 51. When the capacitive element _{C 10} of the integrating circuit 10 is set to the capacitance value _{C 2} is generating circuit 120 ₂ from the timing instruction signal to the time _{t 72} to the voltage value output from the integrating circuit 110 ₂ reaches the reference voltage _{V ref3} There is output at the timing indicated by the timing indication signal output from the generating circuit 120 _2, a voltage value output from the integrating circuit 10 is sampled by a hold circuit 51. Further, when the capacitive element _{C 10} of the integrating circuit 10 is set to the capacitance value _{C 3} is the timing from the generation circuit 120 ₃ to the time _{t 73} to the voltage value outputted from the integration circuit 110 ₃ reaches the reference voltage _{V ref3} instruction signal is outputted at the timing indicated by the timing indication signal output from the generating circuit 120 _3, the voltage value output from the integrating circuit 10 is sampled by a hold circuit 51.

Here, the open loop gains of the amplifiers A ₁₁₁ , A ₁₁₃ , and A ₁₁₃ of the integrating circuits 110 _{1 to} 110 ₃ are equal to the open loop gain of the amplifier A ₁₀ of the integrating circuit 10. Further, the capacitance value of the integration capacitor unit C ₁₁₁ of the integration circuit 110 ₁ is C ₁ , the capacitance value of the integration capacitor unit C ₁₁₂ of the integration circuit 110 ₂ is C ₂ , and the integration capacitor unit C ₁₁₃ of the integration circuit 110 _3. The capacitance value C ₃ is C ₃ , and these capacitance values C _{1 to} C ₃ are values that can be set as the capacitance value of the integration capacitor C ₁₀ of the integration circuit 10.

In other words, the integration circuit 110 ₁ is equivalent to a circuit in which a current corresponding to the resistance value of the resistor R ₁₁₁ flows in the integration circuit 10 when the capacitance value of the integration capacitor unit is set to C ₁ . Integrator circuit 110 _2, a current corresponding to the resistance value of the resistor R ₁₁₂ in the integrating circuit 10 when the capacitance value of the integral capacitance part is set to C ₂ is equal to that flowing. Integrator circuit 110 _3, a current corresponding to the resistance value of the resistor R ₁₁₃ in the integrating circuit 10 when the capacitance value of the integral capacitance part is set to C ₃ are equivalent to those flows.

Since such a relationship exists between the integrating circuits 110 _{1 to} 110 ₃ and the integrating circuit 10, the open loop gain of the amplifier A ₁₀ of the integrating circuit 10 is not ideal infinity but a finite value. Even if the relationship of the approximate expression (formula (2)) is broken, the timing of voltage value sampling by the holding circuit 51 is adjusted, so that the amount of light incident on the photodiode PD can be obtained with high accuracy.

  In the configuration described above, the two holding circuits 51 and 52 are provided, and the voltage value obtained by multiplying the difference between the voltage values output from the holding circuit 51 and the holding circuit 52 by K times is the amplification circuit 70. Is output from. Accordingly, the voltage value output from the amplifier circuit 70 represents a value after the switching noise generated in the holding circuit 50 or the like is suppressed. If such noise component removal is not necessary, the holding circuit 52 may not be provided.

Further, as shown in FIG. 8, four holding circuits ₅₁ 1 as the holding circuit _50, 52 _1, 51 2, 52 ₂ may be provided. FIG. 8 is a diagram showing a detailed configuration of a photodetecting device 1A according to another embodiment. Four holding circuits ₅₁ 1 in FIG. _8, 52 _1, 51 2, 52 _2, respectively, have already the configuration similar to the holding circuits 51 and 52 in FIG. 2 described.

Each of the holding circuits 51 ₁ and 51 ₂ holds and outputs a voltage value (including a signal component and a noise component) output from the integrating circuit 20, similarly to the holding circuit 51 in FIG. Each of the holding circuits 52 ₁ and 52 ₂ holds and outputs a voltage value (including only a noise component) output from the integrating circuit 20, similarly to the holding circuit 52 in FIG. 1 the first set of holding circuit _51, 52 ₁ and the holding circuit ₅₁ 2 of the second set, 52 _2, although the same operation, the operation timing are different.

That is, in the photodetector 1A, in each of a plurality of consecutive periods, with the control of the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 according to the capacitance value control unit 40, the integrating circuit 10, comparator circuit 20, a charge injection circuit 30 Further, it is assumed that the AD conversion operation by the counting circuit 60 is performed and the counting value (first digital value) is output from the counting circuit 60. In a certain first period among the plurality of consecutive periods, the voltage value sampling operation is performed by the _first set of holding circuits 51 ₁ and 52 ₁ , while the second set of holding circuits 51 ₂ and 52 is performed. ₂ is amplified by the amplifier circuit 70 and AD-converted by the AD converter circuit 80 to output a second digital value. In the first period to the subsequent second period, while the sampling operation of the second set of holding circuit 51 _2, 52 ₂ voltage value due takes place, held by the holding circuit 51 _1, 52 ₁ of the first set The amplified voltage value is amplified by the amplifier circuit 70 and AD-converted by the AD conversion circuit 80 to output a second digital value.

In this manner, in the photodetector 1A, integrated circuit voltage value output from 10 is 1 the first set of holding circuit _51, 52 ₁ and the second set of holding circuit ₅₁ 2, 52 ₂ and the sampling alternately Then, the processing by the integration circuit 10, the comparison circuit 20, the charge injection circuit 30, the capacitance value control unit 40 and the counting circuit 60 and the processing by the amplification circuit 70 and the AD conversion circuit 80 are performed in parallel. Accordingly, the photodetecting device 1A can perform photodetection or imaging at high speed in addition to the same effects as the photodetecting device 1 described above.

Incidentally, in the optical detection device 1A, when there is no need for removal of the noise component generated in the integration circuit 20, the holding circuit 52 _1, 52 ₂ may not be provided.

Photodetector 1,1A according to the present embodiment described so far above is the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 with a variable, the capacitance value of the integral capacitance part C ₁₀ by the capacitance value control section 40 as to control, keep the capacitance value of the integral capacitance part C ₁₀ during the charge accumulation operation starts in the integrating circuit 10 is set to the minimum value, a saturation signal from the comparator circuit 20 during the charge accumulation operation of the integrating circuit 10 is output when it is, set to a large value the capacitance value of about integral capacitance part C ₁₀ is short time until the saturation signal output at the comparator circuit from the time of the charge accumulation operation starts in the integration circuit 10. This makes it possible to charge the integrating capacitor unit C ₁₀ of the integrating circuit 10 by the charge injection circuit 30 can reduce the number of times to be injected, to reduce power consumption.

In the optical detecting device 1,1A according to the present embodiment, the amplifier circuit 70 inputs the voltage value V ₅₁ output from the holding circuit 51 inputs the voltage value V ₅₂ output from the holding circuit 52 Then, a voltage value (K (V ₅₁ −V ₅₂ )) obtained by multiplying the difference between these two input voltage values by K is output to the AD conversion circuit 80. The AD conversion circuit 80 sets the voltage value K times the reference value V _ref2 in the comparison circuit 20 as the maximum input voltage value, inputs the voltage value output from the amplifier circuit 70, and inputs the voltage value corresponding to this voltage value. 2 digital values (lower-order M2 bit data D _{M2-1 to} D ₀ ) are output. As a result, noise generated during the AD conversion operation in the AD conversion circuit 80 is suppressed to 1 / K, so the digital values (data D _{M1 + M2-1 to} D ₀ ) output from the photodetecting devices 1 and 1A are It can be highly accurate. As described above, the photodetectors 1 and 1A according to the present embodiment can output a highly accurate digital value according to the amount of incident light.

In addition, the photodetectors 1 and 1A according to the present embodiment can reduce the time required for resetting the integration circuit 10 despite the reduction in power consumption. Photodetector 1,1A according to the present embodiment, since it is possible to reduce the number of times charge the integrating capacitor unit C ₁₀ of the integrating circuit 10 is injected by the charge injection circuit 30, even if the power consumption of the integrating circuit 10 Even if it drops significantly, it is difficult for an error to occur in the output voltage value of the integrating circuit 10.

In addition, the photodetecting devices 1 and 1A according to the present embodiment arbitrarily set the values of the time τ ₂ and τ ₃ from the outside when it is desired to change the time of the charge accumulation operation in the integration circuit 10 according to the imaging target. If possible, a flexible response is possible.

In the configuration described above, when a plurality of reading units 4 ₁ to 4 _N are provided, the capacitance value of the integrating capacitor unit C ₁₀ of the integrating circuit 10 included in each reading unit 4 _n is set to other reading units. the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 included is set independently of the. Therefore, if the amplification factor of the amplifier circuit 70 remains constant, the value output from the light detection device 1 is the integration of the integration circuit 10 during the voltage value sampling operation by the holding circuit 50 in each reading unit 4 _n . The capacitance value C _final of the capacitance unit C ₁₀ has a value having a different gain with respect to the incident light amount. In the case of an application in which such a situation becomes a problem, a configuration as shown in FIG. 9 or FIG. 10 is preferable.

  FIG. 9 is a diagram illustrating a detailed configuration of a photodetecting device 1B according to another embodiment. In this figure, an integrating circuit 10, two holding circuits 51 and 52 as a holding circuit 50, an amplifier circuit 70, and an AD conversion circuit 80 are shown. Other components are the same as those shown in FIGS. 1 and 2. A detailed circuit configuration of the amplifier circuit 70 is shown.

The amplifier circuit 70 includes a two-input two-output full differential amplifier A ₇₀ , a capacitor unit C ₇₁ , a capacitor unit C ₇₂ , a switch SW _71, and a switch SW ₇₂ . The inverting input terminal of the amplifier A ₇₀ is connected to the output terminal of the holding circuit 51. Capacitance section C ₇₁ and the switch SW ₇₁ which are connected in parallel to each other between the inverting input terminal and the non-inverting output terminal of the amplifier A ₇₀ is provided. The non-inverting input terminal of the amplifier A ₇₀ is connected to the output terminal of the holding circuit 52. Between the non-inverting input terminal and the inverting output terminal of the amplifier A ₇₀ , a capacitor unit C ₇₂ and a switch SW ₇₂ connected in parallel with each other are provided. The AD conversion circuit 80 outputs a digital value corresponding to the difference between the voltage values output from the non-inverting input terminal and the inverting input terminal of the amplifier A ₇₀ of the amplifier circuit 70.

The capacitance values of the capacitive part C ₇₁ and the capacitive part C ₇₂ are equal to each other. The switch SW ₇₁ and the switch SW ₇₂ open and close at the same time. In the amplifier circuit 70, when the switch SW ₇₁ and the switch SW ₇₂ are closed, each of the capacitor unit C ₇₁ and the capacitor unit C ₇₂ is discharged, and the output differential voltage value is initialized. The amplifier circuit 70 outputs a differential voltage value corresponding to the input differential voltage value when the switch SW ₇₁ and the switch SW ₇₂ are open.

The capacitance value of the capacitance unit C ₅₀ included in each of the holding circuits 51 and 52 is C _H, and the capacitance value of each of the capacitance unit C ₇₁ and the capacitance unit C ₇₂ included in the amplifier circuit 70 is C _A. The capacitance value C _A is variable. If the capacitance value C _H and the capacitance value C _A are equal to each other, the output voltage value of the integration circuit 10 at the time of the voltage value sampling operation in the holding circuit 50 is output from the amplifier circuit 70 with a gain of 1. The gain can be varied by making the capacitance value C _A variable.

Therefore, when the saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10, the capacitance value control unit 40 _{sets the} predetermined capacitance value C _{set in} the variable range of the capacitance value of the integration capacitance unit C _10. setting the capacitance value of the integral capacitance part C ₁₀ as the upper limit. The predetermined capacitance value C _{The set} may be the upper limit of the variable range of the capacitance value of the integral capacitance part C _10. Then, the amplifier circuit 70 amplifies a value that is a constant multiple of the ratio (C _final / C _set ) of the capacitance value C _final and the predetermined capacitance value C _set of the integration capacitor C ₁₀ during the voltage value sampling operation in the holding circuit 50. The input voltage value is amplified and output as a rate. That is, the capacitance value C _{A of} each of the capacitance unit C ₇₁ and the capacitance unit C ₇₂ included in the amplifier circuit 70 is a value that is a constant multiple of the ratio (C _set / C _final ) (for example, (C _set / C _final ) C _H ). And

  In this way, when the voltage value output from the amplifier circuit 70 is input to the AD conversion circuit 80, the digital value output from the AD conversion circuit 80 becomes a value having a constant gain with respect to the amount of incident light. Further, transmission noise generated between the holding circuit 50 and the AD conversion circuit 80 is suppressed.

In addition, it is preferable that the photodetector 1B according to the present embodiment further includes a control unit. The control unit, opening and closing operations of the switches _{SW 10} in the integrating circuit 10, the counting operation of the counter circuit 60, opening and closing operations of the switches _SW 51 _{to SW 54} in the holding circuit 51 and 52, AD conversion operation in the AD converter circuit 80, the capacitance value The operation of the control unit 40 is controlled at a predetermined timing.

FIG. 10 is a diagram showing a detailed configuration of a photodetecting device 1C according to still another embodiment. In this figure, an integration circuit 10, two holding circuits 51 and 52 as a holding circuit 50, an amplifier circuit 70, an AD conversion circuit 80, and a digital value processing unit 130 are shown. Other components are the same as those shown in FIGS. 1 and 2. A detailed circuit configuration of the amplifier circuit 70 is shown. The amplifier circuit 70 has substantially the same configuration as that described with reference to FIG. 9, but the capacitance values C _{A of} the capacitance unit C ₇₁ and the capacitance unit C ₇₂ may be constant.

When the saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10, the capacitance value control unit 40 limits the predetermined capacitance value C _set within the variable range of the capacitance value of the integration capacitance unit C _10. to set the capacitance value of the integral capacitance part C ₁₀ as. The predetermined capacitance value C _{The set} may be the upper limit of the variable range of the capacitance value of the integral capacitance part C _10. Then, the digital value processor 130 provided on the subsequent stage of the AD conversion circuit 80 receives the digital value output from the AD conversion circuit 80, the capacitance of the voltage value sampling operation when the integral capacitance part C ₁₀ of the holding circuit 50 The input digital value is multiplied by a constant multiple of the ratio (C _final / C _set ) of the value C _final to the predetermined capacitance value C _set, and a digital value obtained by the multiplication is output.

If the ratio of any two capacitance value among settable capacitance value in the integrating capacitor unit C ₁₀ is the number of power of 2, the digital value processing unit 130, the required number of bits for the input digital value An output digital value can be generated with only a bit shift operation. For example, it is assumed that there is a relationship of “2 ⁴ C ₁ = 2 ² C ₂ = C ₃ ” between the capacitance values C ₁ , C ₂ , C _{3 that} can be set in the integration capacitor C ₁₀ , and the predetermined capacitance value C _set is _set to C ₁ and the digital value input to the digital value processing unit 130 as 8-bit [D ₇ D ₆ D ₅ D ₄ D ₃ D ₂ D ₁ D ₀ ], the output digital value from the digital value processing unit 130 Is 12 bits.

At this time, the digital value processing unit 130 performs the following processing. FIG. 11 is a diagram for explaining the processing contents of the digital value processing unit 130. FIG (a), the capacitance value C _final of the integral capacitance part C ₁₀ when a voltage value sampling operation in the holding circuit 50 represents the case where C _1, FIG. (B), the capacitive value C _final is C It indicates the case of _2, also, FIG (c) shows a case capacitive value C _final is C _3. Further, in each of FIGS. 9A to 9C, an 8-bit input digital value is shown on the left side and a 12-bit output digital value is shown on the right side.

When the capacitance value C _final of the integration capacitor unit C ₁₀ at the time of the voltage value sampling operation in the holding circuit 50 is C ₁ , as shown in FIG. without bit shift values, by inserting 0 in the upper four bits is output as _{[0 0 00 D 7 D 6} D 5 D 4 D 3 D 2 D 1 D 0]. When the capacitance value C _final voltage value integral capacitance part C ₁₀ of the sampling phase in the holding circuit 50 is C _2, as shown in FIG. (B), the output digital value of 12 bits, the input digital The value is shifted upward by 2 bits, 0 is inserted into the upper 2 bits and lower 2 bits, and output as [0 0 D ₇ D ₆ D ₅ D ₄ D ₃ D ₂ D ₁ D ₀ 0 0] The In addition, when the capacitance value C _final of the integration capacitor unit C ₁₀ at the time of the voltage value sampling operation in the holding circuit 50 is C ₃ , as shown in FIG. shifting the input digital value to the 4 bits only upper direction, by inserting 0 in the lower 4 bits are output as _{[D 7 D 6 D 5 D} 4 D 3 D 2 D 1 D 0 0 0 0 0].

  By processing the digital value in the digital value processing unit 130 in this way, the digital value output from the digital value processing unit 130 becomes a value having a constant gain with respect to the incident light amount. Further, transmission noise generated between the holding circuit 50 and the AD conversion circuit 80 is suppressed. Furthermore, the substantial number of bits of the digital value obtained by AD conversion increases.

Note that it is preferable that the photodetecting device 1C according to the present embodiment further includes a control unit. The control unit, opening and closing operations of the switches _{SW 10} in the integrating circuit 10, the counting operation of the counter circuit 60, opening and closing operations of the switches _SW 51 _{to SW 54} in the holding circuit 51 and 52, AD conversion operation in the AD converter circuit 80, the capacitance value The operation of the control unit 40 and the operation of the digital value processing unit 130 are controlled at a predetermined timing.

Light detection apparatus according to the present embodiment described so far, a capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 is variable, the capacitance value of the integral capacitance part C ₁₀ at the start charge accumulation operation of the integrating circuit 10 may be set to the minimum value, it was to change the capacitance value of the integral capacitance part C ₁₀ since from the time of the charge accumulation operation starts. However, the present invention also can be applied to a case that does not change the capacitance value of the integral capacitance part C ₁₀ since from the start of charge accumulation operation, also, the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 is variable However, the present invention can be applied to the case where it is fixed, and in any case, the amount of light incident on the photodiode PD can be obtained with high accuracy.

1, 1A, 1B, 1C ... photodetector, 2 ... photodiode array, 3 ... signal processing _{device, 4} 1 to 4 N _... reading unit, 10 ... integrating circuit (first integration circuit), 20 ... comparison circuit, 30 DESCRIPTION OF SYMBOLS ... Charge injection circuit, 40 ... Capacity value control part, 50-52 ... Holding circuit, 60 ... Count circuit, 70 ... Amplification circuit, 80 ... AD converter circuit, 90 ... Reference value generation circuit, 100 ... Voltage source, 110 ... Integration Circuit (second integration circuit), 120... Timing instruction signal generation circuit, 130... Digital value processing unit.

Claims (15)

A signal processing device that outputs an electrical signal having a value corresponding to the amount of charge generated in the photodiode according to the amount of light incident on the photodiode,
A first amplifier, a first integration capacitor unit, and a first switch, wherein the first integration capacitor unit and the first switch are provided in parallel between an input terminal and an output terminal of the first amplifier; Charge storage in which an input terminal of one amplifier is connected to the photodiode, discharges the first integration capacitor unit during an initialization period in which the first switch is closed, and the first switch changes from a closed state to an open state From the start of the operation, a charge output from the photodiode is accumulated in the first integration capacitor, and a voltage value corresponding to the amount of charge accumulated in the first integration capacitor and the capacitance value is output. One integration circuit,
A voltage source that outputs a constant voltage value after the start of the charge accumulation operation;
A second amplifier, a second integrating capacitor, a second switch, and a resistor, wherein the second integrating capacitor and the second switch are provided in parallel between an input terminal and an output terminal of the second amplifier; The input terminal of the second amplifier is connected to the output terminal of the voltage source via the resistor, the open loop gain of the second amplifier is equal to the open loop gain of the first amplifier, and the second integration capacitor And the second switch is changed from a closed state to an open state at the start of the charge storage operation, and from the voltage source after the charge storage operation starts. A second integration circuit that outputs a voltage value representing a value obtained by integrating the output voltage value;
A timing instruction signal generation circuit that compares a voltage value output from the second integration circuit with a reference value and outputs a timing instruction signal indicating a timing at which the voltage value reaches the reference value;
A holding circuit that samples and holds the voltage value output from the first integration circuit at a timing represented by the timing instruction signal output from the timing instruction signal generation circuit; and
A signal processing apparatus comprising: The first integration capacitor is selectively set to have any one of _M capacitance values C _{1 to} C _M ;
Comprises M integrating circuits S ₁ to S _M as said second integrator circuit, each integrating circuit S _m has the same configuration as the second integration circuit, said second integral capacitance part of each integrating circuit S _m has a capacity value _{C m,} the resistor has a resistance value _{R m} of each integrating circuit _{S m,} the resistance value _{R m} between the M integrating circuits _S 1 to S _M and the capacitance value _{C m} Are equal to each other,
As the timing instruction signal generation circuit, M generation circuits T _{1 to} T _M are provided, and each generation circuit T _m compares the voltage value output from the integration circuit S _m with a reference value to determine the voltage value. Output a timing instruction signal indicating the timing of reaching the reference value,
The holding circuit outputs a voltage value output from the first integration circuit at a timing indicated by a timing instruction signal output from the generation circuit T _m corresponding to the set capacitance value C _m of the first integration capacitance unit. Sampling, holding and outputting,
2. The signal processing apparatus according to claim 1, wherein M is an integer of 2 or more and m is an integer of 1 or more and M or less. The voltage value output from the first integration circuit is input, the voltage value is compared with a predetermined reference value, and when the voltage value reaches the reference value, a saturation signal indicating that is provided. A comparator circuit to output,
When the charge accumulation operation in the first integration circuit is started, the capacitance value of the first integration capacitor is set to a minimum value, and a saturation signal is output from the comparison circuit during the charge accumulation operation in the first integration circuit. A capacitance value control unit that sets the capacitance value of the first integration capacitor unit to a larger value as the time from the start of the charge accumulation operation in the first integration circuit to the output of the saturation signal in the comparison circuit is shorter. ,
The signal processing apparatus according to claim 2, further comprising: When the capacitance value control unit outputs a saturation signal from the comparison circuit during the charge accumulation operation in the first integration circuit, the charge accumulation operation in the first integration circuit is performed when the saturation signal is output in the comparison circuit. The capacitance value of the first integration capacitor unit is changed and set according to which partial period when the period from the start to the voltage value sampling operation in the holding circuit is divided into a plurality of partial periods. The signal processing apparatus according to claim 3. The capacitance value control unit is
Each capacitance value of the first integration capacitor unit, a saturated output voltage value of the first integration circuit, a reference value input to the comparison circuit, and a charge accumulation operation in the first integration circuit from the start of the charge accumulation operation in the holding circuit Based on the time until the voltage value sampling operation, the period from the start of the charge accumulation operation in the first integration circuit to the voltage value sampling operation in the holding circuit is divided into a plurality of partial periods,
When a saturation signal is output from the comparison circuit during the charge accumulation operation in the first integration circuit, which partial period of the plurality of partial periods the saturation signal output time of the comparison circuit belongs to And changing and setting the capacitance value of the first integral capacitance unit accordingly.
The signal processing apparatus according to claim 4. After the capacitance value control unit changes and sets the capacitance value of the first integration capacitor unit by outputting a saturation signal from the comparison circuit during the charge accumulation operation in the first integration circuit , the comparison circuit 6. The signal according to claim 3, wherein when a saturation signal is further output from the signal, the capacitance value of the first integration capacitor unit is changed to a larger value and set. Processing equipment. Except when the capacitance value control unit changes and sets the capacitance value of the first integration capacitor unit based on the saturation signal output from the comparison circuit, the first integration capacitor of the first integration circuit A charge injection circuit for injecting into the first integration capacitor part a certain amount of charge having a polarity opposite to that of the charge accumulated in the part;
The voltage value output from the first integration circuit, except when the capacitance value control unit changes and sets the capacitance value of the first integration capacitance unit based on the saturation signal output from the comparison circuit. A counting circuit that counts the number of times the reference value is reached;
The signal processing apparatus according to claim 3, further comprising: An amplifier circuit that inputs a voltage value held and output by the holding circuit, amplifies the input voltage value K times (where K> 1), and outputs the amplified voltage value;
An AD converter circuit that sets a voltage value K times the reference value in the comparison circuit as a maximum input voltage value and outputs a digital value corresponding to the voltage value output from the amplifier circuit;
The signal processing apparatus according to claim 3, further comprising:   A reference value generation circuit is further provided that inputs a reference value for setting the maximum input voltage value in the AD conversion circuit and supplies the voltage value of 1 / K of the reference value as the reference value to the comparison circuit. The signal processing apparatus according to claim 8. An input voltage value that is held and output by the holding circuit is input, and an amplification circuit that amplifies and outputs the input voltage value is further provided.
When the capacitance value control unit outputs a saturation signal from the comparison circuit during the charge accumulation operation in the first integration circuit, a predetermined capacitance value C of the variable range of the capacitance value of the first integration capacitance unit is obtained. _Set the capacitance value of the first integral capacitor with _set as the upper limit,
The amplifying circuit amplifies a value that is a constant multiple of a ratio (C _final / C _set ) between the capacitance value C _final of the first integration capacitor unit and the predetermined capacitance value C _set during the voltage value sampling operation in the holding circuit. Amplifies and outputs the input voltage value as a rate,
The signal processing device according to claim 3, wherein the signal processing device is a signal processing device. An AD conversion circuit that outputs a digital value corresponding to the voltage value held and output by the holding circuit, and a digital value that inputs the digital value output from the AD conversion circuit, processes the input digital value, and outputs the digital value A value processing unit,
When the capacitance value control unit outputs a saturation signal from the comparison circuit during the charge accumulation operation in the first integration circuit, a predetermined capacitance value C of the variable range of the capacitance value of the first integration capacitance unit is obtained. _Set the capacitance value of the first integral capacitor with _set as the upper limit,
The digital value processing unit is a constant multiple of a ratio (C _final / C _set ) of the capacitance value C _final of the first integration capacitor unit and the predetermined capacitance value C _set during the voltage value sampling operation in the holding circuit. Is multiplied by the input digital value, and the digital value obtained by the multiplication is output.
The signal processing device according to claim 3, wherein the signal processing device is a signal processing device. A first holding circuit and a second holding circuit as the holding circuit;
The amplifier circuit outputs a voltage value corresponding to a difference between the voltage values output from the first holding circuit and the second holding circuit;
The signal processing device according to claim 8, wherein the signal processing device is a signal processing device. A first holding circuit and a second holding circuit as the holding circuit;
The AD conversion circuit outputs a digital value corresponding to a difference in voltage value output from each of the first holding circuit and the second holding circuit;
The signal processing apparatus according to claim 11. A first holding circuit and a second holding circuit as the holding circuit;
The voltage value output from the first integration circuit is alternately held in the first holding circuit and the second holding circuit, and the processing by the first integration circuit, the comparison circuit, and the capacitance value control unit, In parallel with the processing by the AD conversion circuit,
The signal processing device according to claim 8, wherein the signal processing device is a signal processing device. A photodiode that generates charge according to the amount of incident light;
The signal processing device according to any one of claims 1 to 14, which outputs an electric signal having a value corresponding to an amount of electric charge generated in the photodiode.
An optical detection device comprising:

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