JP5275911B2 - Signal processing apparatus and light detection apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing apparatus and photodetector capable of reducing power consumption. <P>SOLUTION: A photodetector 1 includes a photodiode PD, an integration circuit 10, a comparator circuit 20, a charge injection circuit 30, a capacitance value control section 40, a holding circuit 50, a counting circuit 60 and the like. The integration circuit 10 includes an integration capacitor C<SB>10</SB>whose capacitance value is variable. The comparator circuit 20 compares an output voltage value V<SB>10</SB>of the integration circuit 10 with a reference value V<SB>ref2</SB>and outputs a saturation signal &phiv;<SB>1</SB>when the voltage value V<SB>10</SB>reaches the reference value V<SB>ref2</SB>. The capacitance value control section 40 sets the capacitance value of the integration capacitor C<SB>10</SB>to a minimum value when a charge accumulation operation in the integration circuit 10 is started, and sets the capacitance value of the integration capacitor C<SB>10</SB>to a larger value as the time from the start of the charge accumulation operation to the output of the saturation signal becomes shorter, when the saturation signal is output from the comparator circuit 20 in the middle of the charge accumulation operation. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a signal processing device that outputs an electric signal having a value corresponding to the amount of electric charge generated in the photodiode in accordance with the amount of light incident on the photodiode, and light including such a signal processing device and the photodiode. The present invention relates to a detection device.

  A light detection device that detects the amount of incident light includes a photodiode that generates a charge corresponding to the amount of incident light, and a signal processing device that outputs an electrical signal having a value corresponding to the amount of charge generated by the photodiode. As such a light detection device, for example, one described in Patent Document 1 is known. The photodetection device described in this document has an AD conversion function and can output a digital value corresponding to the amount of incident light.

  For example, the photodetection device may be used as a detection unit of an X-ray CT apparatus, and a large number of photodiodes may be arranged in an array and covered with a scintillator. When X-rays enter the scintillator, scintillation light is generated. When the scintillation light enters one of the photodiodes, electric charges are generated in the photodiodes, and the electric charges are converted into electric signals by the signal processing device.

Japanese Patent Laid-Open No. 5-215607

  Such a photodetection device is required to have a large number of pixels, high speed, and low power consumption. However, signal processing devices used in conventional photodetectors, including those described in Patent Document 1, increase power consumption due to the increase in the number of pixels or increase in speed, and it is difficult to reduce power consumption.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a signal processing device capable of reducing power consumption and a photodetection device including such a signal processing device. To do.

A signal processing device according to the present invention is a signal processing device that outputs an electric signal having a value corresponding to the amount of electric charge generated in the photodiode according to the amount of light incident on the photodiode, and (1) a capacitance value is An integration circuit that has an integration capacitor unit that accumulates the charge that is variably set and that is output from the photodiode, and that outputs a voltage value corresponding to the amount and capacitance of the charge stored in the integration capacitor unit; and (2) integration A comparison circuit that inputs a voltage value output from the circuit, compares the voltage value with a predetermined reference value, and outputs a saturation signal indicating that when the voltage value reaches the reference value; (3) A holding circuit that samples and holds and outputs the voltage value output from the integrating circuit after a certain time has elapsed from the start of the charge accumulating operation in the integrating circuit, and (4) integrating at the start of the charge accumulating operation in the integrating circuit. The capacity value of the capacity section When the saturation signal is output from the comparison circuit during the charge accumulation operation in the integration circuit, the time from the start of the charge accumulation operation in the integration circuit to the output of the saturation signal in the comparison circuit is short. (5) Based on the saturation signal output from the comparison circuit, the capacitance value control unit changes the capacitance value of the integration capacitance unit and sets it. A charge injection circuit that injects a certain amount of charge of opposite polarity to the charge accumulated in the integration capacitor part of the integration circuit into the integration capacitor part, and (6) based on the saturation signal output from the comparison circuit. And a counting circuit that counts the number of times that the voltage value output from the integration circuit reaches the reference value, except when the capacitance value control unit changes and sets the capacitance value of the integration capacitance unit. Features.

This signal processing device is used together with a photodiode. In this signal processing device, the charge generated according to the amount of light incident on the photodiode is stored in the integration capacitor of the integration circuit, and a voltage value corresponding to the amount of charge stored in the integration capacitor is output from the integration circuit. Is done. The voltage value output from the integration circuit is input to the comparison circuit, and the input voltage value and a predetermined reference value are compared in magnitude by the comparison circuit, and when the input voltage value reaches the reference value, this is indicated. A saturation signal is output from the comparison circuit. The voltage value output from the integration circuit is sampled and held and output by the holding circuit after a predetermined time has elapsed from the start of the charge accumulation operation in the integration circuit. The capacitance value of the integration capacitor unit of the integration circuit is set by the capacitance value control unit. When the capacitance value control unit sets the capacitance value of the integration capacitor unit to the minimum value at the start of the charge accumulation operation in the integration circuit, and when a saturation signal is output from the comparison circuit during the charge accumulation operation in the integration circuit, The shorter the time from the start of the charge accumulation operation in the integration circuit to the output of the saturation signal in the comparison circuit, the larger the value is set.
Charge accumulated in the integration capacitor unit of the integration circuit by the charge injection circuit, except when the capacitance value control unit changes and sets the capacitance value of the integration capacitor unit based on the saturation signal output from the comparison circuit A certain amount of charge having a reverse polarity is injected into the integrating capacitor. Also, based on the saturation signal output from the comparison circuit, the counting circuit outputs the signal from the integration circuit for a certain period of time, except when the capacitance value control unit changes and sets the capacitance value of the integration capacitor unit. The number of times the measured voltage value reaches the reference value is counted. The AD conversion function is realized by the integration circuit, the comparison circuit, the charge injection circuit, and the counting circuit.

  In the signal processing device according to the present invention, when the saturation signal is output from the comparison circuit during the charge accumulation operation in the integration circuit, the capacitance value control unit performs the charge accumulation operation in the integration circuit when the saturation signal is output in the comparison circuit. It is preferable to change and set the capacitance value of the integral capacitance unit according to which partial period of the period from the start to the voltage value sampling operation in the holding circuit. Further, the capacitance value control unit includes each capacitance value of the integration capacitor unit, a saturation output voltage value of the integration circuit, a reference value input to the comparison circuit, and a voltage value sampling in the holding circuit from the start of the charge accumulation operation in the integration circuit. Based on the time until the operation, the period from the start of the charge accumulation operation in the integration circuit to the voltage value sampling operation in the holding circuit is divided into a plurality of partial periods, and the comparison circuit is in the middle of the charge accumulation operation in the integration circuit It is also preferable to change and set the capacitance value of the integration capacitor unit according to which partial period of the plurality of partial periods the saturated signal output time in the comparison circuit belongs to when the saturated signal is output from It is. In addition, the capacitance value control unit sets the capacitance value of the integration capacitor unit when a saturation signal is further output from the comparison circuit after changing and setting the capacitance value of the integration capacitor unit during the charge accumulation operation in the integration circuit. It is also preferable to change and set a larger value.

  The signal processing apparatus according to the present invention includes: (1) an amplifier circuit that inputs a voltage value held and output by the holding circuit, amplifies the input voltage value K times (where K> 1), and outputs the amplified voltage value; (2) It is preferable to further include an AD conversion circuit that sets a voltage value K times the reference value in the comparison circuit as a maximum input voltage value and outputs a digital value corresponding to the voltage value output from the amplifier circuit. is there. At this time, the signal processing apparatus according to the present invention inputs a reference value for setting the maximum input voltage value in the AD converter circuit, and compares the voltage value that is 1 / Kth of the reference value as a reference value. It is preferable to further include a reference value generation circuit to be given to the circuit.

  In this case, the voltage value held and output by the holding circuit is amplified K times by the amplifier circuit and output to the AD conversion circuit. In the AD conversion circuit, the voltage value K times the reference value in the comparison circuit is set as the maximum input voltage value, the voltage value output from the amplifier circuit is input, and a digital value corresponding to this voltage value is output. In this signal processing device, the amount of incident light is detected based on the value of the number of times counted by the counting circuit and the digital value output from the AD conversion circuit.

The signal processing apparatus according to the present invention further includes (1) an amplifier circuit that inputs a voltage value held and output by the holding circuit, amplifies the input voltage value, and outputs the amplified voltage value. (2) a capacitance value control unit However, when a saturation signal is output from the comparison circuit in the middle of the charge accumulation operation in the integration circuit, the capacitance value of the integration capacitance unit is _set with the predetermined capacitance value C _set as the upper limit of the variable value range of the integration capacitance unit. (3) The amplification circuit obtains a value that is a constant multiple of the ratio (C _final / C _set ) of the capacitance value C _final of the integration capacitance unit and the predetermined capacitance value C _set during the voltage value sampling operation in the holding circuit. The input voltage value is preferably amplified and output.

In this case, the capacitance value control section, when the saturation signal from the comparison circuit during the charge accumulation operation of the integrating circuit is output, the maximum predetermined capacitance value C _{The set} of capacitance values variable range of the integral capacitance part Set as The voltage value held and output by the holding circuit is a ratio (C _final / C _set ) between the capacitance value C _final of the integration capacitor unit and the predetermined capacitance value C _set during the voltage value sampling operation in the holding circuit by the amplifier circuit. Amplified with a value that is a constant multiple of.

The signal processing apparatus according to the present invention includes (1) an AD conversion circuit that outputs a digital value corresponding to a voltage value held and output by the holding circuit, and a digital value output from the AD conversion circuit. A digital value processing unit that processes and outputs the input digital value. (2) The capacitance value control unit performs integration when a saturation signal is output from the comparison circuit during the charge accumulation operation in the integration circuit. The capacitance value of the integration capacitor unit is _set with a predetermined capacitance value C _set as the upper limit in the variable range of the capacitance value of the capacitor unit. (3) The digital value processing unit sets the integration capacitor unit during the voltage value sampling operation in the holding circuit. It is preferable to multiply the input digital value by a constant multiple of the ratio (C _final / C _set ) of the capacitance value C _final to the predetermined capacitance value C _set and output a digital value obtained by the multiplication. .

In this case, the capacitance value control section, when the saturation signal from the comparison circuit during the charge accumulation operation of the integrating circuit is output, the maximum predetermined capacitance value C _{The set} of capacitance values variable range of the integral capacitance part Set as The voltage value held and output by the holding circuit is input to the AD conversion circuit and converted into a digital value corresponding to the input voltage value. The digital value output from the AD conversion circuit is converted into a ratio (C _final / C _set ) between the capacitance value C _final and the predetermined capacitance value C _set of the integration capacitor during the voltage value sampling operation in the holding circuit. Is multiplied by a constant multiple, and a digital value obtained by the multiplication is output.

  The signal processing device according to the present invention includes a first holding circuit and a second holding circuit as holding circuits, and the amplifier circuit is a voltage corresponding to a difference in voltage value output from each of the first holding circuit and the second holding circuit. It is preferable to output a value, or it is preferable that the AD conversion circuit outputs a digital value corresponding to the difference between the voltage values output from the first holding circuit and the second holding circuit.

  In this case, the voltage value including the signal component and the noise component output from the integration circuit is held by the first holding circuit, and the voltage value including only the noise component output from the integration circuit is held by the second holding circuit. The A voltage value or a digital value corresponding to the difference between the voltage values output from the first holding circuit and the second holding circuit is output from the amplifier circuit or the AD conversion circuit.

  The signal processing device according to the present invention includes a first holding circuit and a second holding circuit as holding circuits, and alternately integrates the voltage values output from the integrating circuit by holding them in the first holding circuit and the second holding circuit. It is preferable that the processing by the circuit, the comparison circuit and the capacitance value control unit and the processing by the AD conversion circuit are performed in parallel. By performing such a parallel operation, light detection can be performed at high speed.

  In the signal processing device according to the present invention, one AD conversion circuit is provided for a plurality of sets of integration circuits, comparison circuits, holding circuits, and capacitance value control units, and the AD conversion circuit is configured by each set of holding circuits. It is preferable to output a digital value corresponding to the sequentially output voltage value. In this case, imaging can be performed by a photodetection device including a photodiode and a signal processing device, and the circuit scale of the signal processing device is reduced.

  A photodetection device according to the present invention includes a photodiode that generates a charge according to the amount of incident light, and a signal processing device according to the present invention that outputs an electrical signal having a value according to the amount of charge generated by the photodiode. It is characterized by providing.

  The signal processing device and the light detection device according to the present invention can reduce power consumption.

It is a figure which shows schematic structure of the photon detection apparatus 1 which concerns on this embodiment. It is a figure which shows the detailed structure of the photon detection apparatus 1 which concerns on this embodiment. It is a timing chart explaining operation | movement of the photon detection apparatus 1 which concerns on this embodiment. 1 is a circuit diagram of an integration circuit 10 included in a photodetecting device 1 according to the present embodiment. It is a graph showing a temporal change of the voltage value V ₁₀ outputted from the integrating circuit 10 included in the photodetector 1 according to the present embodiment. It is a figure which shows the detailed structure of 1 A of photodetectors which concern on other embodiment. It is a figure which shows the detailed structure of the photodetector 1B which concerns on other embodiment. It is a figure which shows the detailed structure of 1 C of photodetectors which concern on other embodiment. It is a figure explaining the processing content of the digital value process part 100 contained in 1 C of photodetectors concerning other embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 is a diagram illustrating a schematic configuration of a photodetecting device 1 according to the present embodiment. The photodetection device 1 shown in this figure includes a photodiode array 2 and a signal processing device 3.

Photodiode array 2 includes N photodiodes _PD 1 -PD _N. N photodiodes _PD 1 -PD _N have a common configuration. The N photodiodes PD ₁ -PD _N it is preferable that are formed on a single semiconductor substrate. In addition, it is preferable that the light receiving regions of the _N photodiodes PD _{1 to} PDN are covered with a scintillator that generates scintillation light with the incidence of energy rays such as X-rays. Each photodiode PD _n generates a charge according to the amount of incident light. N is an integer of 1 or more, and n is an integer of 1 or more and N or less. Further, N represents a 2 or more integer, N-number of photodiodes PD ₁ -PD _N may be arranged one-dimensionally or two-dimensionally.

The signal processing unit 3 outputs an electric signal (digital signal) having a value corresponding to the amount of charges generated in the photodiodes PD _n. The signal processing device 3 includes N reading units 4 ₁ to 4 _N , an amplification circuit 70, an AD conversion circuit 80, and a reference value generation unit 90. The N reading units 4 ₁ to 4 _N have a common configuration. Each readout section 4 _n is provided corresponding to the photodiode PD _n . The signal processing device 3 is preferably formed on a semiconductor substrate different from the semiconductor substrate on which the photodiode array 2 is formed. A scintillator is provided on the back surface of the semiconductor substrate on which the photodiode array 2 is formed, and the surface of the semiconductor substrate on which the photodiode array 2 is formed and the surface of the semiconductor substrate on which the signal processing device 3 is formed are connected to each other by bumps. It is preferred that

Each readout unit _4n includes an integration circuit 10, a comparison circuit 20, a charge injection circuit 30, a capacitance value control unit 40, a holding circuit 50, a counting circuit 60, and a switch SW. The integration circuit 10 included in each readout unit 4 _n includes an integration capacitor unit whose capacitance value is variably set, accumulates the charge output from the corresponding photodiode PD _n in the integration capacitor unit, and accumulates the accumulated capacitor unit. A voltage value corresponding to the charge amount and the capacitance value is output to the comparison circuit 20 and the holding circuit 50.

  The comparison circuit 20 receives the voltage value output from the integration circuit 10, compares the input voltage value with a predetermined reference value, and indicates when the input voltage value reaches the reference value. The saturation signal is output to the charge injection circuit 30, the capacitance value control unit 40 and the counting circuit 60. The holding circuit 50 samples and holds the voltage value output from the integrating circuit 10, and outputs the held voltage value to the amplifier circuit 70.

  The capacitance value control unit 40 controls the capacitance value of the integration capacitor unit of the integration circuit 10. Specifically, the capacitance value control unit 40 sets the capacitance value of the integration capacitor unit to the minimum value when the charge accumulation operation in the integration circuit 10 is started. When the saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10, the capacitance value control unit 40 starts from the charge accumulation operation start in the integration circuit 10 until the saturation signal is output in the comparison circuit 20. As the time is shorter, the capacitance value of the integration capacitor is set to a larger value.

The charge injection circuit 30 is connected to the integration capacitor unit of the integration circuit 10 except when the capacitance value control unit 40 changes and sets the capacitance value of the integration capacitor unit based on the saturation signal output from the comparison circuit 20. A certain amount of charge having a polarity opposite to that of the accumulated charge is injected into the integrating capacitor. The counting circuit 60 outputs the voltage value output from the integration circuit 10 except when the capacitance value control unit 40 changes and sets the capacitance value of the integration capacitance unit based on the saturation signal output from the comparison circuit 20. Count the number of times that reached the reference value. The counting circuit 60 included in each reading unit 4 _n is connected to a common wiring through the switch SW.

The input terminal of the amplifier circuit 70 is connected to the output terminal of the holding circuit 50 included in each reading unit 4 _n . Amplifier circuit 70 inputs the voltage values sequentially output is held by the holding circuit 50 included in each readout unit 4 _n, and a voltage value the input K times (where, K> 1) Voltage The value is output to the AD conversion circuit 80. The AD conversion circuit 80 sets the voltage value K times the reference value in the comparison circuit 20 as the maximum input voltage value, inputs the voltage value output from the amplifier circuit 70, and outputs a digital value corresponding to the input voltage value. To do. The reference value generation circuit 90 inputs a reference value for setting the maximum input voltage value in the AD conversion circuit 80, and a voltage value that is 1 / K of the input reference value is input to the comparison circuit 20. Use the reference value. The reference value generation circuit 90 can be configured by a resistance dividing circuit.

  FIG. 2 is a diagram showing a detailed configuration of the photodetecting device 1 according to the present embodiment. Here, a pair of photodiodes PD and a reading unit 4 are shown, and an amplifier circuit 70, an AD conversion circuit 80, and a reference value generation circuit 90 are shown. Here, it is assumed that two holding circuits 51 and 52 are provided as the holding circuit 50.

The integration circuit 10 includes an amplifier A ₁₀ , an integration capacitor unit C _10, and a switch SW ₁₀ . Non inverting input terminal of the amplifier A ₁₀ is grounded. Inverting input terminal of the amplifier A ₁₀ is connected to the photodiode PD. Integral capacitance part C ₁₀ and the switch SW ₁₀ between the inverting input terminal and the output terminal of the amplifier A ₁₀ is provided in parallel. The capacitance value of the integral capacitance part C ₁₀ is a variable and is set by the capacity value control unit 40. The integrating circuit 10, when the switch SW ₁₀ is closed, the integral capacitance part C ₁₀ is discharged, and outputs a voltage value of the reset level. On the other hand, the integrating circuit 10, when the switch SW ₁₀ is open, accumulates charges output from the photodiode PD in the integrating capacitor unit C _10, the amount and the capacitance value of the charge accumulated in the integrating capacitor unit C ₁₀ and outputs the voltage value _{V 10} corresponding to.

Comparator circuit 20 inputs the voltage _{V 10} outputted from the integrating circuit 10, and the voltage value _{V 10} and a predetermined reference value _{V ref2} to magnitude comparison. When the voltage value V ₁₀ reaches the reference value V _ref2 , the comparison circuit 20 outputs a saturation signal φ ₁ indicating that fact.

The capacitance value control unit 40 controls the capacitance value of the integration capacitor unit C ₁₀ of the integration circuit 10. Specifically, the capacitance value control unit 40, at the start charge accumulation operation of the integrating circuit 10 (i.e., when the switch SW ₁₀ is turned from a closed state to an open state) the minimum capacitance value of the integral capacitance part C ₁₀ to Set to. When the saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10, the capacitance value control unit 40 starts from the charge accumulation operation start in the integration circuit 10 until the saturation signal is output in the comparison circuit 20. time is set to a large value the capacitance value of the shorter integral capacitance part C _10.

The charge injection circuit 30 includes switches SW _{31 to} SW ₃₄ and a capacitive element C ₃₀ . The switch SW ₃₁ , the capacitive element C ₃₀ and the switch SW ₃₂ are connected in order, the other end of the switch SW ₃₁ is connected to the inverting input terminal of the amplifier A ₁₀ of the integrating circuit 10, and the other end of the switch SW ₃₂ is The reference potential V _inj is connected. A connection point between the switch SW ₃₁ and the capacitive element C ₃₀ is grounded via the switch SW ₃₃ . A connection point between the switch SW ₃₂ and the capacitive element C ₃₀ is grounded via the switch SW ₃₄ .

Except where capacitance value control unit 40 sets by changing the capacitance value of the integral capacitance part C _10, the switches SW ₃₁ and SW ₃₄ are opened and closed and on the basis of the saturation signal phi ₁ that is output from the comparator circuit 20 The switches SW ₃₂ and SW ₃₃ open and close based on the logic inversion signal φ ₂ of the saturation signal φ ₁ output from the comparison circuit 20. That is, the charge injection circuit 30 is integrated based on the saturation signal φ ₁ output from the comparison circuit 20 except when the capacitance value control unit 40 changes and sets the capacitance value of the integration capacitance unit C _10. injecting a predetermined amount of charges of opposite polarity to be accumulated in the integrating capacitor unit C ₁₀ of the circuit 10 to the integrating capacitor unit C _10.

Counting circuit 60 based on the saturation signal phi ₁ that is output from the comparator circuit 20, unless the capacitance value control unit 40 sets by changing the capacitance value of the integral capacitance part C _10, output from the integrating circuit 10 The number of times that the voltage value V reached the reference value V _ref2 is counted, and this counted value is output as a digital value.

The integration circuit 10, the comparison circuit 20, the charge injection circuit 30, and the counting circuit 60 have an AD conversion function. That is, the absolute value of the amount of charge that is accumulated in the integrating capacitor unit C ₁₀ of the integrating circuit 10 is output from the photodiode PD within a certain period and Q _0, the saturation signal output from the comparison circuit 20 phi ₁ the absolute value of the integral capacitance part amount of injected charge on C ₁₀ of the integrating circuit 10 by the charge injection circuit 30 based on the Q _1. At this time, the count value by the counter circuit 60 (digital value) is an integer value by truncating the fractional part for the value obtained by dividing the Q ₀ in Q _1. Further, the voltage value output from the integration circuit 10 at the end of the predetermined period is a voltage corresponding to the residual value obtained by subtracting the integer value from the value obtained by dividing Q ₀ by Q _1. Value.

The holding circuit 51 and the holding circuit 52 have a common configuration. Each of the holding circuit 51 and the holding circuit 52 includes switches SW _{51 to} SW ₅₄ and a capacitive element C ₅₀ . The switch SW ₅₁ , the capacitive element C ₅₀ and the switch SW ₅₂ are connected in order, the other end of the switch SW ₅₁ is connected to the output terminal of the amplifier A ₁₀ of the integrating circuit 10, and the other end of the switch SW ₅₂ is amplified. The input terminal of the circuit 70 is connected. A connection point between the switch SW ₅₁ and the capacitive element C ₅₀ is grounded via the switch SW ₅₃ . A connection point between the switch SW ₅₂ and the capacitive element C ₅₀ is grounded via the switch SW ₅₄ .

In each of the holding circuit 51 and the holding circuit 52, the switches SW ₅₁ and SW ₅₄ open and close simultaneously. Switches SW ₅₂ and SW ₅₃ open and close simultaneously. When the switches SW ₅₁ and SW _{54 change} from the closed state to the open state, the output voltage value from the integrating circuit 10 is held in the capacitive element C ₅₀ immediately before that. When the switches SW ₅₂ and SW ₅₃ are closed, the voltage value held in the capacitive element C ₅₀ is output to the amplifier circuit 70.

The holding circuit 51 samples and holds the voltage value output from the integrating circuit 10 at the end of the operation after the charge accumulation operation is performed in the integrating circuit 10 for a fixed period, and the held voltage value V _51. Is output to the amplifier circuit 70. On the other hand, the holding circuit 52 samples and holds the noise voltage value immediately after the reset output from the integrating circuit 10 at the moment when the switch SW ₁₀ of the integrating circuit 10 is opened from the closed state, and holds the held voltage value V. ₅₂ is output to the amplifier circuit 70.

Amplifier circuit 70 inputs the voltage value V ₅₁ output from the holding circuit 51 inputs the voltage value V ₅₂ output from the holding circuit 52, K times the difference between the inputted two voltage values The converted voltage value (K (V ₅₁ −V ₅₂ )) is output to the AD conversion circuit 80. The voltage value V ₅₁ output from the holding circuit 51 is an AD by the AD conversion function constituted by the integration circuit 10, the comparison circuit 20, the charge injection circuit 30, and the counting circuit 60 among the voltage values including the signal component and the noise component. This is the residual voltage value at the time of conversion. The voltage value V ₅₂ output from the holding circuit 52 does not include a signal component but includes only a noise component. Therefore, the voltage value output from the amplifier circuit 70 represents a value after the noise component is removed from the remaining voltage value.

As described above, the amplifier circuit 70 receives the voltage value held and output by the holding circuits 51 and 52, and converts the voltage value obtained by multiplying the difference between the two input voltage values by K times. Output to 80. Further, the AD conversion circuit 80 sets the voltage value K times the reference value in the comparison circuit 20 as the maximum input voltage value, inputs the voltage value output from the amplifier circuit 70, and outputs a digital value corresponding to the input voltage value. Is output. Therefore, the reference value generation circuit 90 inputs the reference value V _ref1 for setting the maximum input voltage value in the AD conversion circuit 80, and the voltage value of 1 / K of the reference value V _ref1 (V _ref1 / K). ) To the comparison circuit 20 as a reference value V _ref2 .

In addition, it is preferable that the light detection device 1 according to the present embodiment further includes a control unit. The control unit, opening and closing operations of the switches _{SW 10} in the integrating circuit 10, the counting operation of the counter circuit 60, opening and closing operations of the switches _SW 51 _{to SW 54} in the holding circuits 51 and 52, and, AD conversion operation in the AD converter circuit 80, Is controlled at a predetermined timing.

Next, the operation of the photodetecting device 1 according to this embodiment will be described. FIG. 3 is a timing chart for explaining the operation of the photodetecting device 1 according to this embodiment. However, here, as to the control of the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 according to the capacitance value control section 40 is not performed, the integral capacitance part C ₁₀ over a period of charge accumulation operations in the integrating circuit 10 Assume that the capacitance value is constant.

At time _{t 0,} is closed switch _{SW 10} of the integrating circuit 10, integrating capacitor unit _{C 10} is discharged, the voltage value _{V 10} outputted from the integrating circuit 10 is the reset level. At this time, the saturation signal φ ₁ output from the comparison circuit 20 is at the logic level L, the switches SW ₃₁ and SW _{34 of} the charge injection circuit 30 are open, and the switches SW ₃₂ and SW _{33 of the} charge injection circuit 30 are open. Is closed, and the count value in the count circuit 60 is initialized to 0.

At time t ₁ , the switch SW ₁₀ of the integration circuit 10 is opened and the charge accumulation operation is started, and the charge generated in the photodiode PD is accumulated in the integration capacitor unit C ₁₀ according to the amount of the accumulated charge. The voltage value V ₁₀ is output from the integrating circuit 10. The voltage value V ₁₀ output from the integration circuit 10 is compared with the reference value V _ref2 by the comparison circuit 20.

To time t _2, the when the voltage value V ₁₀ outputted from the integrating circuit 10 reaches the reference value V _ref2, saturation signal phi ₁ that is output from the comparator circuit 20 is turned to the logic level H from the logic level L, With this The switches SW ₃₁ and SW ₃₄ of the charge injection circuit 30 are closed and the switches SW ₃₂ and SW ₃₃ are opened.

Then, the charge amount Q ₁₀ (= C ₁₀ · V _ref2 ) accumulated in the integration capacitor unit C ₁₀ when the voltage value V ₁₀ output from the integration circuit 10 reaches the reference value V _ref2 , and until that time charge amount _Q 30 that has been accumulated in the capacitor _{C 30} of the charge injection circuit 30 into equal ₍₌ C 30 _{· V inj)} and to each other, the charges accumulated in the capacitor _{C 30} of the charge injection circuit 30 is integrated It is injected into the integral capacitance part C ₁₀ of the circuit 10, the charge accumulation amount in the integrating capacitor unit C ₁₀ is reset.

Thereby, the voltage value V ₁₀ outputted from the integrating circuit 10 is once becomes the reset level, the voltage value V ₁₀ corresponding to the amount of the subsequently accumulated charge is output from the integrating circuit 10. Immediately, the saturation signal φ ₁ output from the comparison circuit 20 goes to the logic level L. Accordingly, the switches SW ₃₁ and SW _{34 of the} charge injection circuit 30 are opened, and the switches SW ₃₂ and SW ₃₃ are respectively switched. close up.

Time _{t 3,} time _{t 4,} even at time _{t 5} and time _{t 6,} respectively, the series of operations described above at time _{t 2} is performed. Here, time τ ₁₂ from time t ₁ to time t ₂ , time τ ₂₃ from time t ₂ to time t ₃ , time τ ₃₄ from time t ₃ to time t ₄ , time t ₄ to time t ₅ Time τ ₄₅ and time τ ₅₆ from time t ₅ to time t ₆ are equal to each other if the amount of light incident on the photodiode PD is constant.

Such a repetitive operation is performed until time t ₇ (= t ₁ + T) when a certain time T elapses from time t ₁ when the charge accumulation operation in the integration circuit 10 is started. Time from the time _{t 6} to time _{t 7} is shorter than such as the time τ _12. The counting circuit 60 counts the number of times that the saturation signal φ ₁ output from the comparison circuit 20 changes from the logic level L to the logic level H during the fixed time T. That is, the count value in the counter circuit 60 becomes a value 1 becomes the time _{t 2, the} next value 2 at time _{t 3,} time _{t 4} to the value 3, and the value becomes 4 at time _{t 5,} the value 5 to the time _{t 6} . That is, the AD conversion function is realized by the integration circuit 10, the comparison circuit 20, the charge injection circuit 30, and the counting circuit 60.

Prior to time t _7, the switches SW ₅₁ and SW ₅₄ of the holding circuit 51 are closed, and at time t ₇ , the switches SW ₅₁ and SW ₅₄ of the holding circuit 51 are opened. As a result, the signals are output from the integrating circuit 10 immediately before time t _7. The value V ₅₁ of the voltage value V ₁₀ which has been sampled is held by the holding circuit 51. Also, the switch _SW 51, _{SW 54} of the holding circuit 52 is closed at time _{t 1,} the time _{t 1} the switch _SW 51, _{SW 54} of the holding circuit 52 immediately opens, resulting, integrating circuit 10 at time _{t 1} the switch A value V ₅₂ of noise (kTC noise) generated by opening the SW ₁₀ and output from the integration circuit 10 is sampled and held by the holding circuit 52.

Then, between times _{t 7} after the time _t 8 ~t _9, the holding circuit 51 and the holding circuit 52 by the closing respective switches _SW 52, _{SW 53,} the voltage value _{V 51} that has been held by the holding circuit 51, The voltage value V ₅₂ held by the holding circuit 52 is input to the amplifier circuit 70, and a voltage value (K (V ₅₁ −V ₅₂ )) that is K times the difference between the two voltage values is supplied to the amplifier circuit. 70. The voltage value output from the amplifier circuit 70 is input to the AD conversion circuit 80, and a digital value corresponding to the input voltage value is output from the AD conversion circuit 80.

Further, after time t _7, the counting operation in the counting circuit 60 is stopped, and the count value at the time t ₇ is held by the counting circuit 60. Then, between times t ₈ ~t _9, closes the switch SW of the read unit 4 _n, the count value that has been held by the counter circuit 60 of the read section 4 _n is outputted via the switch SW.

Among the operations described above, the operations between times t _{0 to} t ₇ are simultaneously performed in parallel in the _N reading units 4 ₁ to 4 _N. On the other hand, the time _{t 7} after the operation is performed sequentially for the N reading unit ₄ 1 to 4 _N. As described above, for each of the N readout units 4 ₁ to 4 _N , the first digital value that is the count value by the count circuit 60 and the AD value as the output value with respect to the incident light amount to the photodiode PD, and AD A second digital value that is an AD conversion result by the conversion circuit 80 is obtained.

As can be seen from the above-described operation, the second digital value is positioned lower than the first digital value. If the first digital value is represented by M1 bits and the second digital value is represented by M2 bits, the digital value output from the photodetector 1 is (M1 + M2) bits of data D _{M1 + M2−.} It expressed as ₁ to D _0. Of these, the upper M1 bit data D _{M1 + M2-1 to} D _M2 correspond to the first digital value, and the lower M2 bit data D _{M2-1 to} D ₀ correspond to the second digital value.

Accordingly, in the light detection apparatus 1 according to the present embodiment, assuming that the control of the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 according to the capacitance value control section 40 is not performed, the period of charge accumulation operations in the integrating circuit 10 T When the capacitance value of the integral capacitance part _{C 10} over (time _t 1 ~t ₇₎ is constant, the incident light amount to the photodiode PD, the integrating circuit 10, comparator circuit 20, a charge injection circuit 30 and counting The AD conversion function realized by the circuit 60 converts the first digital value, and the AD converter circuit 80 converts the remaining value that cannot be AD converted into a second digital value. The Therefore, the light detection device 1 can detect the amount of incident light in a short time with a large dynamic range. In this photodetection device 1, when a plurality of photodiodes PD are arranged in a one-dimensional or two-dimensional manner, an incident light image can be taken with a large dynamic range.

In the optical detector 1 according to the present embodiment, the amplifier circuit 70 inputs the voltage value V ₅₁ output from the holding circuit 51 inputs the voltage value V ₅₂ output from the holding circuit 52, A voltage value (K (V ₅₁ −V ₅₂ )) obtained by multiplying the difference between the two input voltage values by K times (where K> 1) is output to the AD conversion circuit 80. The AD conversion circuit 80 sets the voltage value K times the reference value V _ref2 in the comparison circuit 20 as the maximum input voltage value, inputs the voltage value output from the amplifier circuit 70, and inputs the voltage value corresponding to this voltage value. 2 digital values (lower-order M2 bit data D _{M2-1 to} D ₀ ) are output. Thereby, noise generated during the AD conversion operation in the AD conversion circuit 80 is suppressed to 1 / K, so that the digital values (data D _{M1 + M2-1 to} D ₀ ) output from the light detection device 1 are highly accurate. Can be. Thus, the photodetector 1 according to the present embodiment can output a highly accurate digital value corresponding to the amount of incident light.

However, the operation of the capacitance value of the integral capacitance part C ₁₀ over a period T of the charge accumulation operation (time t ₁ ~t ₇₎ has been described so far above as being constant in the integration circuit 10, a saturation signal from the comparison circuit 20 Is output and the charge injection circuit 30 injects charges into the integration capacitor unit C ₁₀ of the integration circuit 10, so that the instantaneous response speed of the amplifier is required, and the power consumption increases in order to increase the bandwidth of the amplifier. . Therefore, the light detection apparatus 1 according to this embodiment, the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 with a variable, the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 by the capacitance value control section 40 by controlling, by reducing the number of charges to the integrating capacitor unit C ₁₀ of the integrating circuit 10 by the charge injection circuit 30 is injected, to reduce power consumption. Hereinafter, the integration circuit 10 and the capacitance value control unit 40 included in the photodetector 1 according to the present embodiment will be described in more detail.

FIG. 4 is a circuit diagram of the integrating circuit 10 included in the photodetector 1 according to the present embodiment. The integration circuit 10 includes an amplifier A ₁₀ , an integration capacitor unit C _10, and a switch SW ₁₀ . Non inverting input terminal of the amplifier A ₁₀ is grounded. Inverting input terminal of the amplifier A ₁₀ is connected to the photodiode PD. Integral capacitance part C ₁₀ and the switch SW ₁₀ between the inverting input terminal and the output terminal of the amplifier A ₁₀ is provided in parallel.

Integral capacitance part _{C 10} of the integrating circuit 10 includes a switch _SW 11 _{to SW 13} and the capacitor _C 11 _{-C 13.} The switch SW ₁₁ and the capacitive element C ₁₁ connected in series, the switch SW ₁₂ and the capacitive element C ₁₂ connected in series, and the switch SW ₁₃ and the capacitive element C ₁₃ connected in series are connected to the amplifier A. ₁₀ are provided in parallel between the inverting input terminal and the output terminal. Each capacitance value capacitor element _C 11 _{-C 13} are different from each other. In the following, the capacitance value _{C 1} of the capacitor _{C 11,} the magnitude relationship between the capacitance value _{C 3} of the capacitance value _{C 2} and the capacitor _{C 13} of the capacitor _{C 12} and _"C 1 _<C 2 _{<C 3} ' .

Capacity value control unit 40, by controlling the switch _SW 11 _{to SW 13} of each opening and closing operation included in the integrating capacitor unit _{C 10,} sets the capacitance value of the integral capacitance part _{C 10} of the integrating circuit 10. Capacity value control unit 40, only the switch _{SW 11} of the switch _SW 11 _{to SW 13} by a closed, sets the capacitance value of the integral capacitance part _{C 10} to _{C 1.} Capacity value control unit 40, only the switch _{SW 12} of the switch _SW 11 _{to SW 13} by a closed, sets the capacitance value of the integral capacitance part _{C 10} to _{C 2.} The capacitance value control unit 40, only the switch _{SW 13} of the switch _SW 11 _{to SW 13} by a closed, sets the capacitance value of the integral capacitance part _{C 10} to _{C 3.}

Capacity value control unit 40, at the start charge accumulation operation of the integrating circuit 10 (time _{t 1} in FIG. 3), only by closed switch _{SW 11} of the switch _SW 11 _{to SW 13,} the integral capacitance part It is set to the minimum value _{C 1} and the capacitance value of C _10. The capacitance value control unit 40 starts the charge accumulation operation in the integration circuit 10 when a saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10 (time t _{2 in} FIG. 3). set to a large value the capacitance value of the shorter integral capacitance part C ₁₀ (time tau ₁₂ from the time t ₁ in FIG. 3 to time t ₂₎ time until the saturation signal output at the comparator circuit 20 from.

Figure 5 is a diagram showing the time variation of the voltage value V ₁₀ outputted from the integrating circuit 10 included in the photodetector 1 according to the present embodiment. If the intensity of light incident on the photodiode PD is constant and the output current value of the photodiode PD is constant over the period of the charge accumulation operation, as shown in FIG. voltage V ₁₀ outputted from the gradually linearly approaching from the charge accumulation operation starts when the reset level to the reference value V _ref2 in the comparing circuit 20 with time. Each of the straight lines L ₂ and L ₃ shown in FIG. 6A is an integration circuit when the capacitance value of the integration capacitor unit C ₁₀ is set to the minimum value C ₁ over the period T of the charge accumulation operation in the integration circuit 10. It represents the temporal change of the output voltage value _{V 10} of 10.

Output current value I ₃ in the photodiode PD of the case shown by the straight line L _3, the charge accumulation capacitance value of the integral capacitance part C ₁₀ over a period T of the charge accumulation operation of the integrating circuit 10 in case of a C ₂ voltage value _{V 10} of the integration circuit 10 at the end of the period T is a value which is a saturation output voltage value _{V sat.} In the case of such an output current value I ₃ of the photodiode PD, when the capacitance value of the integration capacitor unit C ₁₀ is set to the minimum value C ₁ , the output voltage value of the integration circuit 10 from the start of the charge accumulation operation in the integration circuit 10. Let τ ₃ be the time required for V ₁₀ to reach the reference value V _ref2 .

The output current value I ₂ of the photodiode PD in the case indicated by the straight line L ₂ is the charge accumulation operation when the capacitance value of the integration capacitor unit C ₁₀ is C ₁ over the period T of the charge accumulation operation in the integration circuit 10. voltage value _{V 10} of the integration circuit 10 at the end of the period T is a value which is a saturation output voltage value _{V sat.} If the output current value I ₂ such photodiode PD, when the capacitance value of the integral capacitance part C ₁₀ and minimum value C _1, the output voltage value of the integrating circuit 10 from the time of the charge accumulation operation starts in the integration circuit 10 Let τ ₂ be the time until V ₁₀ reaches the reference value V _ref2 .

The output current values I ₂ and I ₃ of the photodiode PD are expressed by the following equation (1). Time tau ₂ from the start charge accumulation operation of the integrating circuit 10 to the output voltage value _{V 10} of the integration circuit 10 reaches the reference value _{V ref2,} tau ₃ is expressed by the following equation (2). Here, n is 2 or 3.

Note that the times τ ₂ and τ ₃ do not have to be values obtained from the above formula, and may be arbitrarily set from the outside, for example.

The capacitance value control unit 40 includes capacitance values C ₁ , C ₂ , and C ₃ of the integration capacitor unit C ₁₀ of the integration circuit 10, a saturated output voltage value V _{sat of} the integration circuit 10, and a reference value V input to the comparison circuit 20. _{Based on ref2} and the time T from the start of the charge accumulation operation in the integrating circuit 10 to the voltage value sampling operation in the holding circuit 50, the above-described times τ ₂ and τ ₃ are obtained, and the charge in the integrating circuit 10 is obtained. A period from the start of the accumulation operation to the voltage value sampling operation in the holding circuit 50 is divided into three partial periods.

When the saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10, the capacitance value control unit 40 outputs any of the three partial periods when the saturation signal is output from the comparison circuit 20. sought belongs to, by changing the capacitance value of the integral capacitance part C ₁₀ sets accordingly. Specifically, it is as follows.

As shown in FIG. 5B, when the saturation signal output time from the comparison circuit 20 belongs to the partial period from time 0 to time τ ₃ , the capacitance value control unit 40 includes the integration capacitance unit C ₁₀ . Change the capacitance value from C ₁ to C ₃ and set it. As shown in FIG. 5C, the capacitance value control unit 40, when the output of the saturation signal from the comparison circuit 20 belongs to a partial period from time τ ₃ to time τ ₂ , the integration capacitance unit C ₁₀ Is changed from C ₁ to C ₂ . Further, as shown in FIG. 5 (d), the capacitance value control unit 40, if it belongs to the sub-period at saturation signal output time tau ₂ later from the comparison circuit 20, the capacitance of the integrating capacitor unit C ₁₀ a value remains _{C 1.}

Thus, the capacitance value control unit 40, by setting by changing the capacitance value of the middle integral capacitance part C ₁₀ of the charge storage operation in the integrating circuit 10 to a large value from the initial minimum value C _1, the charge injection it is possible to reduce the number of times charge the integrating capacitor unit C ₁₀ of the integrating circuit 10 is injected by the circuit 30, since it does not require a fast response of the amplifier, it is possible to reduce the bandwidth of the amplifier, reducing power consumption can do.

The capacity value control unit 40, while the minimum value C ₁ of the capacitor value from the initial minimum value C ₁ if you change or the original to C ₂ in the middle of the integral capacitance part C ₁₀ of the charge storage operation in the integrating circuit 10 If set to, when the output is then the saturation signal from the comparator circuit 20 may be set by changing the capacitance value of the integral capacitance part C ₁₀ to further large value.

Further, when the capacitance value of the integration capacitor C ₁₀ is changed to C ₂ , C ₃ or is kept at the original C ₁ , when the saturation signal is output from the comparison circuit 20 thereafter, the capacitor value controller without changing the capacitance value of the integral capacitance part C ₁₀ to a large value by 40, injecting a quantity of charges of opposite polarity to be accumulated in the integrating capacitor unit C ₁₀ to integrating capacitor unit C ₁₀ by the charge injection circuit 30 and, the number of times that the voltage value V ₁₀ output from the integration circuit 10 reaches the reference value V _ref2 (i.e., the number of times the saturation signal is output from the comparator circuit 20) may be counted by a counter circuit 60 a.

  In the configuration described above, the two holding circuits 51 and 52 are provided, and the voltage value obtained by multiplying the difference between the voltage values output from the holding circuit 51 and the holding circuit 52 by K times is the amplification circuit 70. Is output from. Thus, the voltage value output from the amplifier circuit 70 represents a value after the noise component generated in the integrating circuit 20 is removed. If such noise component removal is not necessary, the holding circuit 52 may not be provided.

Further, as shown in FIG. 6, four holding circuits ₅₁ 1 as the holding circuit _50, 52 _1, 51 2, 52 ₂ may be provided. FIG. 6 is a diagram showing a detailed configuration of a photodetecting device 1A according to another embodiment. Four holding circuits ₅₁ 1 in FIG. _6, 52 _1, 51 2, 52 _2, respectively, have already the configuration similar to the holding circuits 51 and 52 in FIG. 2 described.

Each of the holding circuits 51 ₁ and 51 ₂ holds and outputs a voltage value (including a signal component and a noise component) output from the integrating circuit 20, similarly to the holding circuit 51 in FIG. Each of the holding circuits 52 ₁ and 52 ₂ holds and outputs a voltage value (including only a noise component) output from the integrating circuit 20, similarly to the holding circuit 52 in FIG. 1 the first set of holding circuit _51, 52 ₁ and the holding circuit ₅₁ 2 of the second set, 52 _2, although the same operation, the operation timing are different.

That is, in the photodetector 1A, in each of a plurality of consecutive periods, with the control of the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 according to the capacitance value control unit 40, the integrating circuit 10, comparator circuit 20, a charge injection circuit 30 Further, it is assumed that the AD conversion operation by the counting circuit 60 is performed and the counting value (first digital value) is output from the counting circuit 60. In a certain first period among the plurality of consecutive periods, the voltage value sampling operation is performed by the _first set of holding circuits 51 ₁ and 52 ₁ , while the second set of holding circuits 51 ₂ and 52 is performed. ₂ is amplified by the amplifier circuit 70 and AD-converted by the AD converter circuit 80 to output a second digital value. In the first period to the subsequent second period, while the sampling operation of the second set of holding circuit 51 _2, 52 ₂ voltage value due takes place, held by the holding circuit 51 _1, 52 ₁ of the first set The amplified voltage value is amplified by the amplifier circuit 70 and AD-converted by the AD conversion circuit 80 to output a second digital value.

In this manner, in the photodetector 1A, integrated circuit voltage value output from 10 is 1 the first set of holding circuit _51, 52 ₁ and the second set of holding circuit ₅₁ 2, 52 ₂ and the sampling alternately Then, the processing by the integration circuit 10, the comparison circuit 20, the charge injection circuit 30, the capacitance value control unit 40 and the counting circuit 60 and the processing by the amplification circuit 70 and the AD conversion circuit 80 are performed in parallel. Accordingly, the photodetecting device 1A can perform photodetection or imaging at high speed in addition to the same effects as the photodetecting device 1 described above.

Incidentally, in the optical detection device 1A, when there is no need for removal of the noise component generated in the integration circuit 20, the holding circuit 52 _1, 52 ₂ may not be provided.

Photodetector 1,1A according to the present embodiment described so far above is the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 with a variable, the capacitance value of the integral capacitance part C ₁₀ by the capacitance value control section 40 as to control, keep the capacitance value of the integral capacitance part C ₁₀ during the charge accumulation operation starts in the integrating circuit 10 is set to the minimum value, a saturation signal from the comparator circuit 20 during the charge accumulation operation of the integrating circuit 10 is output when it is, set to a large value the capacitance value of about integral capacitance part C ₁₀ is short time until the saturation signal output at the comparator circuit from the time of the charge accumulation operation starts in the integration circuit 10. This makes it possible to charge the integrating capacitor unit C ₁₀ of the integrating circuit 10 by the charge injection circuit 30 can reduce the number of times to be injected, to reduce power consumption.

In the optical detecting device 1,1A according to the present embodiment, the amplifier circuit 70 inputs the voltage value V ₅₁ output from the holding circuit 51 inputs the voltage value V ₅₂ output from the holding circuit 52 Then, a voltage value (K (V ₅₁ −V ₅₂ )) obtained by multiplying the difference between these two input voltage values by K is output to the AD conversion circuit 80. The AD conversion circuit 80 sets the voltage value K times the reference value V _ref2 in the comparison circuit 20 as the maximum input voltage value, inputs the voltage value output from the amplifier circuit 70, and inputs the voltage value corresponding to this voltage value. 2 digital values (lower-order M2 bit data D _{M2-1 to} D ₀ ) are output. As a result, noise generated during the AD conversion operation in the AD conversion circuit 80 is suppressed to 1 / K, so the digital values (data D _{M1 + M2-1 to} D ₀ ) output from the photodetecting devices 1 and 1A are It can be highly accurate. As described above, the photodetectors 1 and 1A according to the present embodiment can output a highly accurate digital value according to the amount of incident light.

In addition, the photodetectors 1 and 1A according to the present embodiment can reduce the time required for resetting the integration circuit 10 despite the reduction in power consumption. Photodetector 1,1A according to the present embodiment, since it is possible to reduce the number of times charge the integrating capacitor unit C ₁₀ of the integrating circuit 10 is injected by the charge injection circuit 30, even if the power consumption of the integrating circuit 10 Even if it drops significantly, it is difficult for an error to occur in the output voltage value of the integrating circuit 10.

In addition, the photodetecting devices 1 and 1A according to the present embodiment arbitrarily set the values of the time τ ₂ and τ ₃ from the outside when it is desired to change the time of the charge accumulation operation in the integration circuit 10 according to the imaging target. If possible, a flexible response is possible.

In the configuration described above, when a plurality of reading units 4 ₁ to 4 _N are provided, the capacitance value of the integrating capacitor unit C ₁₀ of the integrating circuit 10 included in each reading unit 4 _n is set to other reading units. the capacitance value of the integral capacitance part C ₁₀ of the integrating circuit 10 included is set independently of the. Therefore, if the amplification factor of the amplifier circuit 70 remains constant, the value output from the light detection device 1 is the integration of the integration circuit 10 during the voltage value sampling operation by the holding circuit 50 in each reading unit 4 _n . The capacitance value C _final of the capacitance unit C ₁₀ has a value having a different gain with respect to the incident light amount. In the case of an application in which such a situation becomes a problem, a configuration as shown in FIG. 7 or FIG. 8 is preferable.

  FIG. 7 is a diagram illustrating a detailed configuration of a photodetecting device 1B according to another embodiment. In this figure, an integrating circuit 10, two holding circuits 51 and 52 as a holding circuit 50, an amplifier circuit 70, and an AD conversion circuit 80 are shown. Other components are the same as those shown in FIGS. 1 and 2. A detailed circuit configuration of the amplifier circuit 70 is shown.

The amplifier circuit 70 includes a full differential amplifier A _{70 with} two inputs and two outputs, a capacitive element C ₇₁ , a capacitive element C ₇₂ , a switch SW ₇₁ and a switch SW ₇₂ . The inverting input terminal of the amplifier A ₇₀ is connected to the output terminal of the holding circuit 51. A capacitive element C ₇₁ and a switch SW ₇₁ connected in parallel with each other are provided between the inverting input terminal and the non-inverting output terminal of the amplifier A ₇₀ . The non-inverting input terminal of the amplifier A ₇₀ is connected to the output terminal of the holding circuit 52. A capacitive element C ₇₂ and a switch SW ₇₂ connected in parallel to each other are provided between the non-inverting input terminal and the inverting output terminal of the amplifier A ₇₀ . The AD conversion circuit 80 outputs a digital value corresponding to the difference between the voltage values output from the non-inverting input terminal and the inverting input terminal of the amplifier A ₇₀ of the amplifier circuit 70.

The capacitance values of the capacitive element C ₇₁ and the capacitive element C ₇₂ are equal to each other. The switch SW ₇₁ and the switch SW ₇₂ open and close at the same time. In the amplifier circuit 70, when the switch SW ₇₁ and the switch SW ₇₂ are closed, each of the capacitive element C ₇₁ and the capacitive element C ₇₂ is discharged, and the output differential voltage value is initialized. The amplifier circuit 70 outputs a differential voltage value corresponding to the input differential voltage value when the switch SW ₇₁ and the switch SW ₇₂ are open.

The capacitance value of the capacitive element C ₅₀ included in each of the holding circuits 51 and 52 is C _H, and the capacitance value of each of the capacitive element C ₇₁ and the capacitive element C ₇₂ included in the amplifier circuit 70 is C _A. The capacitance value C _A is variable. If the capacitance value C _H and the capacitance value C _A are equal to each other, the output voltage value of the integration circuit 10 at the time of the voltage value sampling operation in the holding circuit 50 is output from the amplifier circuit 70 with a gain of 1. The gain can be varied by making the capacitance value C _A variable.

Therefore, when the saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10, the capacitance value control unit 40 _{sets the} predetermined capacitance value C _{set in} the variable range of the capacitance value of the integration capacitance unit C _10. setting the capacitance value of the integral capacitance part C ₁₀ as the upper limit. The predetermined capacitance value C _{The set} may be the upper limit of the variable range of the capacitance value of the integral capacitance part C _10. Then, the amplifier circuit 70 amplifies a value that is a constant multiple of the ratio (C _final / C _set ) of the capacitance value C _final and the predetermined capacitance value C _set of the integration capacitor C ₁₀ during the voltage value sampling operation in the holding circuit 50. The input voltage value is amplified and output as a rate. That is, the capacitance value C _{A of} each of the capacitive element C ₇₁ and the capacitive element C ₇₂ included in the amplifier circuit 70 is a value that is a constant multiple of the ratio (C _set / C _final ) (for example, (C _set / C _final ) C _H ). And

  In this way, when the voltage value output from the amplifier circuit 70 is input to the AD conversion circuit 80, the digital value output from the AD conversion circuit 80 becomes a value having a constant gain with respect to the amount of incident light. Further, transmission noise generated between the holding circuit 50 and the AD conversion circuit 80 is suppressed.

In addition, it is preferable that the photodetector 1B according to the present embodiment further includes a control unit. The control unit, opening and closing operations of the switches _{SW 10} in the integrating circuit 10, the counting operation of the counter circuit 60, opening and closing operations of the switches _SW 51 _{to SW 54} in the holding circuits 51 and 52, and, AD conversion operation in the AD converter circuit 80, The operation of the capacitance value control unit 40 is controlled at a predetermined timing.

FIG. 8 is a diagram showing a detailed configuration of a photodetecting device 1C according to still another embodiment. In this figure, an integration circuit 10, two holding circuits 51 and 52 as a holding circuit 50, an amplification circuit 70, an AD conversion circuit 80, and a digital value processing unit 100 are shown. Other components are the same as those shown in FIGS. 1 and 2. A detailed circuit configuration of the amplifier circuit 70 is shown. The amplifier circuit 70 has a configuration substantially similar to the configuration described in FIG. 7, but the capacitance values C _{A of} the capacitive element C ₇₁ and the capacitive element C ₇₂ may be constant.

When the saturation signal is output from the comparison circuit 20 during the charge accumulation operation in the integration circuit 10, the capacitance value control unit 40 limits the predetermined capacitance value C _set within the variable range of the capacitance value of the integration capacitance unit C _10. to set the capacitance value of the integral capacitance part C ₁₀ as. The predetermined capacitance value C _{The set} may be the upper limit of the variable range of the capacitance value of the integral capacitance part C _10. Then, the digital value processor 100 provided on the subsequent stage of the AD conversion circuit 80 receives the digital value output from the AD conversion circuit 80, the capacitance of the voltage value sampling operation when the integral capacitance part C ₁₀ of the holding circuit 50 The input digital value is multiplied by a constant multiple of the ratio (C _final / C _set ) of the value C _final to the predetermined capacitance value C _set, and a digital value obtained by the multiplication is output.

If the ratio of any two capacitance value among settable capacitance value in the integrating capacitor unit C ₁₀ is the number of powers of 2 squared, the digital value processing unit 100, the required number of bits for the input digital value An output digital value can be generated with only a bit shift operation. For example, it is assumed that there is a relationship of “2 ⁴ C ₁ = 2 ² C ₂ = C ₃ ” between the capacitance values C ₁ , C ₂ , C _{3 that} can be set in the integration capacitor C ₁₀ , and the predetermined capacitance value C _set is _set to C _3, and the input digital value to the digital value processing unit 100 is 8 bits [D ₇ D ₆ D ₅ D ₄ D ₃ D ₂ D ₁ D ₀ ], and the output digital value from the digital value processing unit 100 Is 12 bits.

At this time, the digital value processing unit 100 performs the following processing. FIG. 9 is a diagram for explaining the processing contents of the digital value processing unit 100. FIG (a), the capacitance value C _final of the integral capacitance part C ₁₀ when a voltage value sampling operation in the holding circuit 50 represents the case where C _1, FIG. (B), the capacitive value C _final is C It shows the case where _2, also FIG. (c) shows a case capacitive value C _final is C _3. Further, in each of FIGS. 9A to 9C, an 8-bit input digital value is shown on the left side and a 12-bit output digital value is shown on the right side.

When the capacitance value C _final of the integration capacitor unit C ₁₀ at the time of the voltage value sampling operation in the holding circuit 50 is C ₁ , as shown in FIG. without bit shift values, by inserting 0 in the upper four bits is output as _{[0 0 00 D 7 D 6} D 5 D 4 D 3 D 2 D 1 D 0]. When the capacitance value C _final voltage value integral capacitance part C ₁₀ of the sampling phase in the holding circuit 50 is C _2, as shown in FIG. (B), the output digital value of 12 bits, the input digital The value is shifted upward by 2 bits, 0 is inserted into the upper 2 bits and lower 2 bits, and output as [0 0 D ₇ D ₆ D ₅ D ₄ D ₃ D ₂ D ₁ D ₀ 0 0] The In addition, when the capacitance value C _final of the integration capacitor unit C ₁₀ at the time of the voltage value sampling operation in the holding circuit 50 is C ₃ , as shown in FIG. shifting the input digital value to the 4 bits only upper direction, by inserting 0 in the lower 4 bits are output as _{[D 7 D 6 D 5 D} 4 D 3 D 2 D 1 D 0 0 0 0 0].

  By processing the digital value in the digital value processing unit 100 in this way, the digital value output from the digital value processing unit 100 becomes a value having a constant gain with respect to the incident light amount. Further, transmission noise generated between the holding circuit 50 and the AD conversion circuit 80 is suppressed. Furthermore, the substantial number of bits of the digital value obtained by AD conversion increases.

Note that it is preferable that the photodetecting device 1C according to the present embodiment further includes a control unit. The control unit, opening and closing operations of the switches _{SW 10} in the integrating circuit 10, the counting operation of the counter circuit 60, opening and closing operations of the switches _SW 51 _{to SW 54} in the holding circuits 51 and 52, and, AD conversion operation in the AD converter circuit 80, The operation of the capacitance value control unit 40 and the operation of the digital value processing unit 100 are controlled at a predetermined timing.

1, 1A, 1B, 1C ... photodetector, 2 ... photodiode array, 3 ... signal processing _{device, 4} 1 to 4 N _... reading unit, 10 ... integrating circuit 20 ... comparison circuit, 30 ... charge injection circuit, 40 DESCRIPTION OF SYMBOLS ... Capacity value control part, 50-52 ... Holding circuit, 60 ... Count circuit, 70 ... Amplifier circuit, 80 ... AD converter circuit, 90 ... Reference value generation circuit, 100 ... Digital value processing part.

Claims (13)

A signal processing device that outputs an electrical signal having a value corresponding to the amount of charge generated in the photodiode according to the amount of light incident on the photodiode,
An integration circuit that has an integration capacitance unit that variably sets a capacitance value and accumulates charges output from the photodiode, and outputs an amount of charge accumulated in the integration capacitance unit and a voltage value corresponding to the capacitance value;
The voltage value output from the integration circuit is input, the voltage value is compared with a predetermined reference value, and when the voltage value reaches the reference value, a saturation signal indicating that fact is output. A comparison circuit;
A holding circuit that samples and holds and outputs the voltage value output from the integrating circuit after a predetermined time has elapsed from the start of charge accumulation operation in the integrating circuit;
When the charge accumulation operation in the integration circuit is started, the capacitance value of the integration capacitor unit is set to a minimum value, and when the saturation signal is output from the comparison circuit during the charge accumulation operation in the integration circuit, the integration circuit A capacitance value control unit that sets the capacitance value of the integral capacitance unit to a larger value as the time from the start of charge accumulation operation in the circuit to the time of saturation signal output in the comparison circuit is shorter;
Except when the capacitance value control unit changes and sets the capacitance value of the integration capacitor unit based on the saturation signal output from the comparison circuit, the charge accumulated in the integration capacitor unit of the integration circuit And a charge injection circuit for injecting a certain amount of charge of opposite polarity into the integration capacitor unit,
Based on the saturation signal output from the comparison circuit, the voltage value output from the integration circuit is the reference value except when the capacitance value control unit changes and sets the capacitance value of the integration capacitance unit. A counting circuit for counting the number of times reached,
A signal processing apparatus comprising:   When the saturation value is output from the comparison circuit during the charge accumulation operation in the integration circuit, the capacitance value control unit outputs the saturation signal in the comparison circuit from the start of the charge accumulation operation in the integration circuit. 2. The signal processing according to claim 1, wherein the capacitance value of the integration capacitor unit is changed and set in accordance with which partial period of the period until the voltage value sampling operation in the holding circuit belongs. apparatus. The capacitance value control unit is
Each capacitance value of the integration capacitor unit, the saturation output voltage value of the integration circuit, the reference value input to the comparison circuit, and from the start of charge accumulation operation in the integration circuit to the time of voltage value sampling operation in the holding circuit Based on the time, the period from the start of charge accumulation operation in the integration circuit until the voltage value sampling operation in the holding circuit is divided into a plurality of partial periods,
When a saturation signal is output from the comparison circuit during the charge accumulation operation in the integration circuit, depending on which partial period of the plurality of partial periods the saturation signal output time in the comparison circuit belongs to Changing and setting the capacitance value of the integral capacitance section,
The signal processing apparatus according to claim 2.   When the saturation value is further output from the comparison circuit after the capacitance value control unit changes and sets the capacitance value of the integration capacitance unit during the charge accumulation operation in the integration circuit, The signal processing apparatus according to claim 1, wherein the capacitance value is changed and set to a larger value. An amplifier circuit that inputs a voltage value held and output by the holding circuit, amplifies the input voltage value K times (where K> 1), and outputs the amplified voltage value;
An AD converter circuit that sets a voltage value K times the reference value in the comparison circuit as a maximum input voltage value and outputs a digital value corresponding to the voltage value output from the amplifier circuit;
The signal processing apparatus according to any one of claim 1 to 4, further comprising a. A reference value generation circuit is further provided that inputs a reference value for setting the maximum input voltage value in the AD conversion circuit and supplies the voltage value of 1 / K of the reference value as the reference value to the comparison circuit. The signal processing apparatus according to claim 5 . An input voltage value that is held and output by the holding circuit is input, and an amplification circuit that amplifies and outputs the input voltage value is further provided.
When the saturation value is output from the comparison circuit during the charge accumulation operation in the integration circuit, the capacitance value control unit _{sets a} predetermined capacitance value _Cset as an upper limit in the variable range of the capacitance value of the integration capacitance unit. Set the capacitance value of the integral capacitance section,
The amplification circuit uses a value that is a constant multiple of the ratio (C _final / C _set ) of the capacitance value C _final of the integration capacitor unit and the predetermined capacitance value C _set during the voltage value sampling operation in the holding circuit as an amplification factor. Amplifies and outputs the input voltage value,
The signal processing apparatus according to any one of claim 1 to 4, characterized in that. An AD conversion circuit that outputs a digital value corresponding to the voltage value held and output by the holding circuit, and a digital value that inputs the digital value output from the AD conversion circuit, processes the input digital value, and outputs the digital value A value processing unit,
When the saturation value is output from the comparison circuit during the charge accumulation operation in the integration circuit, the capacitance value control unit _{sets a} predetermined capacitance value _Cset as an upper limit in the variable range of the capacitance value of the integration capacitance unit. Set the capacitance value of the integral capacitance section,
The digital value processing unit inputs a value that is a constant multiple of the ratio (C _final / C _set ) of the capacitance value C _final of the integration capacitance unit and the predetermined capacitance value C _set during the voltage value sampling operation in the holding circuit. Multiply the digital value and output the digital value obtained by the multiplication,
The signal processing apparatus according to any one of claim 1 to 4, characterized in that. A first holding circuit and a second holding circuit as the holding circuit;
The amplifier circuit outputs a voltage value corresponding to a difference between the voltage values output from the first holding circuit and the second holding circuit;
The signal processing device according to claim 5 , wherein the signal processing device is a signal processing device. A first holding circuit and a second holding circuit as the holding circuit;
The AD conversion circuit outputs a digital value corresponding to a difference in voltage value output from each of the first holding circuit and the second holding circuit;
The signal processing apparatus according to claim 8 . A first holding circuit and a second holding circuit as the holding circuit;
The voltage value output from the integration circuit is alternately held in the first holding circuit and the second holding circuit, the processing by the integration circuit, the comparison circuit and the capacitance value control unit, and the AD conversion circuit Process in parallel,
The signal processing apparatus according to claim 5 , wherein the signal processing apparatus is any one of claims 5, 6, and 8 . One AD conversion circuit is provided for a plurality of sets of the integration circuit, the comparison circuit, the holding circuit, and the capacitance value control unit,
The AD converter circuit outputs a digital value corresponding to a voltage value sequentially output by each holding circuit;
The signal processing apparatus according to claim 5 , wherein the signal processing apparatus is any one of the following. A photodiode that generates charge according to the amount of incident light;
The signal processing apparatus according to any one of claims 1 to 12 , which outputs an electric signal having a value corresponding to an amount of electric charge generated in the photodiode.
An optical detection device comprising:

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