JP5537525B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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JP5537525B2
JP5537525B2 JP2011208851A JP2011208851A JP5537525B2 JP 5537525 B2 JP5537525 B2 JP 5537525B2 JP 2011208851 A JP2011208851 A JP 2011208851A JP 2011208851 A JP2011208851 A JP 2011208851A JP 5537525 B2 JP5537525 B2 JP 5537525B2
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真理子 鈴木
忠司 酒井
尚志 佐久間
雅之 片桐
雄一 山崎
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    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
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    • H01ELECTRIC ELEMENTS
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66143Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01ELECTRIC ELEMENTS
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes

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Description

本発明の実施の形態は半導体装置および半導体装置の製造方法に関する。   Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the semiconductor device.

ダイヤモンドはその機械的、化学的および熱的特性に加え、優れた潜在的な半導体特性を持つことから、半導体デバイス材料として注目されている。特に、室温で約5.5eVのバンドギャップを持つため、紫外線発光デバイスや負性電子親和力を利用した電子放出デバイスとして期待される。また、絶縁破壊耐性が高いため、ハイパワーデバイスとして期待される。さらに、堅牢な結晶性から、特に高温や放射線などの過酷な環境下で用いられる耐環境性デバイスとして期待される。   In addition to its mechanical, chemical and thermal properties, diamond has attracted attention as a semiconductor device material because of its excellent potential semiconductor properties. In particular, since it has a band gap of about 5.5 eV at room temperature, it is expected as an ultraviolet light emitting device or an electron emitting device utilizing negative electron affinity. In addition, since it has high dielectric breakdown resistance, it is expected as a high-power device. Furthermore, it is expected as an environment-resistant device that is used under severe environments such as high temperature and radiation due to its robust crystallinity.

ダイヤモンドのパワーデバイスは近年盛んに開発が行われ、ショットキー接合を有するショットキーバリアダイオード、ショットキー接合にpn接合を組み合わせたデバイス、pin構造のデバイス等に関する報告がなされている。もっとも、特に、n型ダイヤモンド半導体層の形成において、均一な不純物濃度や高い結晶性を安定して制御することは困難である。したがって、n型ダイヤモンド半導体層を安定して形成する方法が求められている。   Diamond power devices have been actively developed in recent years, and reports have been made on Schottky barrier diodes having a Schottky junction, devices combining a pn junction with a Schottky junction, devices having a pin structure, and the like. However, it is difficult to stably control the uniform impurity concentration and high crystallinity particularly in the formation of the n-type diamond semiconductor layer. Therefore, a method for stably forming an n-type diamond semiconductor layer is required.

特開2006−240983号公報JP 2006-240983 A 特開平5−24989号公報JP-A-5-24989

本発明は、上記事情を考慮してなされたものであり、その目的とするところは、不純物濃度の均一性および結晶性に優れたn型ダイヤモンド半導体層を有する半導体装置および半導体装置の製造方法を提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having an n-type diamond semiconductor layer excellent in uniformity of impurity concentration and crystallinity, and a method of manufacturing the semiconductor device. It is to provide.

実施の形態の半導体装置は、(100)面から<011>±10度方向に10度以上40度以下の範囲で傾斜する面を備えるダイヤモンド基板と、面上に形成され、リン(P)を含有するn型ダイヤモンド半導体層と、を備え、ダイヤモンド基板と、n型ダイヤモンド基板との間に、さらに、p型ダイヤモンド半導体層を有する。 The semiconductor device according to the embodiment includes a diamond substrate having a surface inclined in a range of 10 degrees or more and 40 degrees or less in the <011> ± 10 degrees direction from the (100) plane; An n-type diamond semiconductor layer, and a p-type diamond semiconductor layer is further provided between the diamond substrate and the n-type diamond substrate.

実施の形態の半導体装置の作用を説明する図である。It is a figure explaining the effect | action of the semiconductor device of embodiment. 実施の形態の半導体装置の模式断面図である。It is a schematic cross section of the semiconductor device of an embodiment. 実施の形態の半導体装置の製造方法を示す模式工程断面図である。It is a schematic process sectional view showing a manufacturing method of a semiconductor device of an embodiment.

ダイヤモンド半導体において、n型層の制御は一般に困難である。これまでに(111)基板上、(100)基板上でリン(P)をドープすることによりn型伝導が得られている。(111)基板は固いために加工が困難であり、大面積化や平坦化が難しい。このため、産業応用上はより安価で加工のしやすい(100)基板あるいはその近傍の面方位を持つ基板を用いての半導体装置の製造が望ましい。   In a diamond semiconductor, it is generally difficult to control the n-type layer. So far, n-type conduction has been obtained by doping phosphorus (P) on the (111) substrate and the (100) substrate. Since the (111) substrate is hard, it is difficult to process, and it is difficult to increase the area and flatten it. For this reason, for industrial applications, it is desirable to manufacture a semiconductor device using a (100) substrate that is cheaper and easier to process or a substrate having a plane orientation in the vicinity thereof.

しかしながら、特に、(100)面上でのダイヤモンドの成長は、異常成長粒子やヒロックなどが発生しやすい。またリン(P)ドープのn型層において平坦な膜を得ることが困難である。さらに、ドーピング濃度や成長方向の濃度プロファイルの制御などが困難である。このため、(100)面上のn型ダイヤモンド半導体層を備える半導体デバイスでは、所望のデバイス特性を得ることが困難であった。   However, in particular, the growth of diamond on the (100) plane tends to generate abnormally grown particles, hillocks, and the like. Moreover, it is difficult to obtain a flat film in the phosphorus (P) -doped n-type layer. Furthermore, it is difficult to control the doping concentration and the concentration profile in the growth direction. For this reason, it has been difficult to obtain desired device characteristics in a semiconductor device including an n-type diamond semiconductor layer on the (100) plane.

以下、図面を参照しつつ本発明の実施の形態を説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

なお、本明細書中、(100)面との記載は、(100)面と結晶構造上等価な面方位を備える面、例えば、(001)、(010)等、を包含するものとする。また、[100]と結晶構造上等価な方位は、<100>と記載するものとする。   In the present specification, the description of (100) plane includes a plane having a plane orientation equivalent to the (100) plane, for example, (001), (010), and the like. In addition, an orientation equivalent to [100] in terms of crystal structure is described as <100>.

本実施の形態の半導体装置は、(100)面から<011>±10度方向に10度以上40度以下の範囲で傾斜する面を備えるダイヤモンド基板と、上記面上に形成され、リン(P)を含有するn型ダイヤモンド半導体層と、を備える。   The semiconductor device according to the present embodiment is formed on a diamond substrate having a surface inclined in a range of 10 degrees or more and 40 degrees or less in the <011> ± 10 degrees direction from the (100) plane; And an n-type diamond semiconductor layer.

本実施の形態の半導体装置は、上記構成を備えることにより、不純物濃度の均一性および結晶性に優れたn型ダイヤモンド半導体層を実現できる。また、加工が容易であり、安価に製造することが可能となる。   By providing the semiconductor device of the present embodiment with the above structure, an n-type diamond semiconductor layer having excellent impurity concentration uniformity and crystallinity can be realized. Further, it is easy to process and can be manufactured at low cost.

図1は、本実施の形態の半導体装置の模式断面図である。本実施の形態の半導体装置は、pnダイオードである。   FIG. 1 is a schematic cross-sectional view of the semiconductor device of the present embodiment. The semiconductor device of the present embodiment is a pn diode.

図1に示すように、本実施の形態のpnダイオード100は、単結晶のダイヤモンド基板10と、ダイヤモンド基板10上に形成されるp型ダイヤモンド半導体層12、p型ダイヤモンド半導体層12上に形成され、p型ダイヤモンド半導体層12よりも低不純物濃度のp型ダイヤモンド半導体層14を備えている。さらに、p型ダイヤモンド半導体層14上に、リン(P)を不純物として含有するn型ダイヤモンド半導体層16が形成されている。 As shown in FIG. 1, pn diodes 100 of the present embodiment, the diamond substrate 10 of single crystal, on the p + -type diamond semiconductor layer 12, p + -type diamond semiconductor layer 12 formed on the diamond substrate 10 A p-type diamond semiconductor layer 14 that is formed and has a lower impurity concentration than the p + -type diamond semiconductor layer 12 is provided. Further, an n-type diamond semiconductor layer 16 containing phosphorus (P) as an impurity is formed on the p-type diamond semiconductor layer 14.

型ダイヤモンド半導体層12、p型ダイヤモンド半導体層14およびn型ダイヤモンド半導体層16でリッジが形成されている。n型ダイヤモンド半導体層16上には、ショットキー電極18が形成されている。また、リッジ外のp型ダイヤモンド半導体層12上には、オーミック電極20が形成されている。 A ridge is formed by the p + type diamond semiconductor layer 12, the p type diamond semiconductor layer 14, and the n type diamond semiconductor layer 16. A Schottky electrode 18 is formed on the n-type diamond semiconductor layer 16. An ohmic electrode 20 is formed on the p + type diamond semiconductor layer 12 outside the ridge.

ショットキー電極18はn型ダイヤモンド半導体層16とショットキー接合を形成する金属、例えば、ニッケル(Ni)を用いて形成される。また、オーミック電極20はp型ダイヤモンド半導体層12とできるだけ接触抵抗が小さくなるような金属、例えば、チタン(Ti)などにより形成する。   The Schottky electrode 18 is formed using a metal that forms a Schottky junction with the n-type diamond semiconductor layer 16, for example, nickel (Ni). The ohmic electrode 20 is formed of a metal having a contact resistance as small as possible with the p-type diamond semiconductor layer 12, such as titanium (Ti).

ここで、ダイヤモンド基板10は、(100)面から<011>±10度方向に10度以上40度以下の範囲で傾斜する面を備える。そして、p型ダイヤモンド半導体層12、p型ダイヤモンド半導体層14およびn型ダイヤモンド半導体層16はこの面上に同一の面方位で形成されている。 Here, the diamond substrate 10 includes a surface that is inclined in the range of 10 degrees or more and 40 degrees or less in the <011> ± 10 degrees direction from the (100) plane. The p + type diamond semiconductor layer 12, the p type diamond semiconductor layer 14, and the n type diamond semiconductor layer 16 are formed on this plane with the same plane orientation.

本実施の形態のpnダイオード100は、ショットキー電極18とp型ダイヤモンド半導体層14との間に、比較的低濃度のn型ダイヤモンド半導体層16を挟むことで、整流作用を維持しつつ、高い順方向電流を流すことが可能である。特に、本実施の形態によれば、(100)面から<011>±10度方向に10度以上40度以下の範囲で傾斜する面上に、リン(P)を不純物として含有するn型ダイヤモンド半導体層16を形成することで、n型ダイヤモンド半導体層16のリン(P)の濃度の均一性が向上する。また、n型ダイヤモンド半導体層16に結晶欠陥の少ない高い結晶性が実現される。したがって、高性能なpnダイオードが実現される。   The pn diode 100 according to the present embodiment has a relatively low concentration n-type diamond semiconductor layer 16 sandwiched between the Schottky electrode 18 and the p-type diamond semiconductor layer 14, thereby maintaining a rectifying action and high. It is possible to pass a forward current. In particular, according to the present embodiment, n-type diamond containing phosphorus (P) as an impurity on a surface inclined in a range of 10 degrees to 40 degrees in the <011> ± 10 degrees direction from the (100) plane. By forming the semiconductor layer 16, the uniformity of phosphorus (P) concentration in the n-type diamond semiconductor layer 16 is improved. Further, high crystallinity with few crystal defects is realized in the n-type diamond semiconductor layer 16. Therefore, a high-performance pn diode is realized.

次に、本実施の形態の半導体装置の製造方法について説明する。本実施の形態の半導体装置の製造方法は、(100)面から<011>±10度方向に10度以上40度以下の範囲で傾斜する面を備えるダイヤモンド基板を準備し、上記面上に、エピタキシャル成長法により、リン(P)を含有するn型ダイヤモンド半導体層を形成する。図3は、本実施の半導体装置の製造方法を示す模式工程断面図である。   Next, a method for manufacturing the semiconductor device of the present embodiment will be described. The method for manufacturing a semiconductor device according to the present embodiment prepares a diamond substrate having a surface inclined in a range of 10 degrees or more and 40 degrees or less in the <011> ± 10 degrees direction from the (100) plane. An n-type diamond semiconductor layer containing phosphorus (P) is formed by an epitaxial growth method. FIG. 3 is a schematic process cross-sectional view illustrating the manufacturing method of the semiconductor device of the present embodiment.

まず、(100)面から<011>±10度方向に10度以上40度以下の範囲で傾斜する面を備える単結晶のダイヤモンド基板12を準備する。そして、ダイヤモンド基板12上に、マイクロ波プラズマCVD(Chemical Vapor Deposition)法により、p型ダイヤモンド半導体層12、p型ダイヤモンド半導体層14およびn型ダイヤモンド半導体層16をエピタキシャル成長させる(図3(a))。n型ダイヤモンド半導体層のリン(P)濃度は、例えば、1×1015cm−3以上である。 First, a single crystal diamond substrate 12 having a surface inclined in a range of 10 degrees to 40 degrees in the <011> ± 10 degrees direction from the (100) plane is prepared. Then, the p + type diamond semiconductor layer 12, the p type diamond semiconductor layer 14 and the n type diamond semiconductor layer 16 are epitaxially grown on the diamond substrate 12 by microwave plasma CVD (Chemical Vapor Deposition) (FIG. 3A). ). The phosphorus (P) concentration of the n-type diamond semiconductor layer is, for example, 1 × 10 15 cm −3 or more.

次に、n型ダイヤモンド半導体層16、p型ダイヤモンド半導体層14、およびp型ダイヤモンド半導体層12を一部リッジ状に残してRIE(Reactive Ion Etching)法などによりエッチングし、p型ダイヤモンド半導体層12を露出させる(図3(b))。 Next, the n-type diamond semiconductor layer 16, the p-type diamond semiconductor layer 14, and the p + -type diamond semiconductor layer 12 are partly left in a ridge shape and are etched by a RIE (Reactive Ion Etching) method or the like to obtain a p + -type diamond semiconductor. The layer 12 is exposed (FIG. 3B).

次に、p型ダイヤモンド半導体層12上に、例えば、チタン(Ti)/白金(Pt)/金(Au)を電子ビーム蒸着により堆積する。続いて、500℃〜600℃でアニールを行い、オーミック電極20を形成する(図3(c))。 Next, for example, titanium (Ti) / platinum (Pt) / gold (Au) is deposited on the p + type diamond semiconductor layer 12 by electron beam evaporation. Subsequently, annealing is performed at 500 ° C. to 600 ° C. to form the ohmic electrode 20 (FIG. 3C).

次に、n型ダイヤモンド半導体層16上に、例えば、ニッケル(Ni)を電子ビーム蒸着により堆積し、ショットキー電極18を形成する(図3(d))。   Next, for example, nickel (Ni) is deposited on the n-type diamond semiconductor layer 16 by electron beam evaporation to form the Schottky electrode 18 (FIG. 3D).

以上の製造方法により、図2に示すpnダイオード100が実現される。本実施の形態の製造方法によれば、(100)面から<011>±10度方向に10度以上40度以下の範囲で傾斜する面を備える単結晶のダイヤモンド基板12上に、n型ダイヤモンド半導体層16をエピタキシャル成長させることで、不純物濃度の均一性が高く、結晶欠陥の少ない高品質なn型ダイヤモンド半導体層16が形成可能となる。したがって、高性能なpnダイオードを製造することが可能となる。   The pn diode 100 shown in FIG. 2 is realized by the above manufacturing method. According to the manufacturing method of the present embodiment, n-type diamond is formed on a single-crystal diamond substrate 12 having a surface inclined in a range of 10 degrees or more and 40 degrees or less in the <011> ± 10 degrees direction from the (100) plane. By epitaxially growing the semiconductor layer 16, it is possible to form a high-quality n-type diamond semiconductor layer 16 with high uniformity of impurity concentration and few crystal defects. Therefore, a high-performance pn diode can be manufactured.

図1は、本実施の形態の半導体装置の作用を説明する図である。図1は、単結晶のダイヤモンド基板の結晶構造を、[100]方向および[011]方向に平行な断面で示した図である。黒丸は炭素原子を示す。また、点線は各傾斜における表面構造を示す。   FIG. 1 is a diagram for explaining the operation of the semiconductor device of this embodiment. FIG. 1 is a diagram showing the crystal structure of a single crystal diamond substrate in a cross section parallel to the [100] direction and the [011] direction. Black circles indicate carbon atoms. A dotted line indicates a surface structure at each inclination.

図1に示すように、(100)面から<011>方向に傾斜する面では、(111)面のステップが表面上に現れることになる。このステップの密度、いいかえればステップ数の密度は、傾斜が25度の時に最大になる。このようなステップが表面に現れることにより、ステップに安定に付着するリン(P)原子が、エピタキシャル成長するダイヤモンド膜中へ安定して取り込まれる。したがって、n型ダイヤモンド半導体層の高いn型不純物濃度と、高いn型不純物濃度の均一性が実現される。   As shown in FIG. 1, on the surface inclined in the <011> direction from the (100) plane, the step of the (111) plane appears on the surface. The density of this step, in other words, the density of the number of steps, becomes maximum when the inclination is 25 degrees. When such a step appears on the surface, phosphorus (P) atoms that stably adhere to the step are stably taken into the epitaxially grown diamond film. Therefore, high n-type impurity concentration of the n-type diamond semiconductor layer and high n-type impurity concentration uniformity are realized.

また、<100>方向に延びやすいヒロックや異常成長粒子の大きさを低減することが可能となり平坦性が向上する。また、ステップフロー成長が優勢となることでも、ヒッロクや異常成長粒子の密度を低減することが可能となる。このため、n型ダイヤモンド半導体層中の結晶欠陥の低減も可能となる。   In addition, it is possible to reduce the size of hillocks and abnormally grown particles that tend to extend in the <100> direction, and the flatness is improved. Moreover, the density of hillocks and abnormally grown particles can be reduced even when step flow growth becomes dominant. For this reason, it is possible to reduce crystal defects in the n-type diamond semiconductor layer.

そして、成膜時のn型不純物の濃度および分布(プロファイル)の制御が容易になり、低濃度でのドーピング遅れや、厚膜成長による平坦性の劣化も抑制することが可能となる。   Further, it becomes easy to control the concentration and distribution (profile) of the n-type impurity during film formation, and it is possible to suppress doping delay at a low concentration and deterioration of flatness due to thick film growth.

以上のように、本実施の形態によれば、特性および生産性に優れたn型ダイヤモンド半導体層の形成が可能となる。したがって、n型ダイヤモンド半導体層を用いるデバイスの特性および生産性が向上する。   As described above, according to the present embodiment, it is possible to form an n-type diamond semiconductor layer having excellent characteristics and productivity. Therefore, the characteristics and productivity of the device using the n-type diamond semiconductor layer are improved.

なお、(100)面からの傾斜が<011>に対し±10度方向の範囲にあれば、<011>方向への傾斜とほぼ同等な効果が得られる。   If the inclination from the (100) plane is in the range of ± 10 degrees relative to <011>, an effect substantially equivalent to that in the <011> direction can be obtained.

また、ステップの密度は、傾斜が25度で最大になることから、(100)面から<011>±10度方向への傾斜角度(オフ角)は、10度以上40度以下であり、15度以上35度以下であることが望ましく、21度以上29度以下であることがより望ましい。   In addition, since the density of the step becomes maximum when the inclination is 25 degrees, the inclination angle (off angle) from the (100) plane to the <011> ± 10 degrees direction is 10 degrees or more and 40 degrees or less, 15 It is desirable that the angle is not less than 35 degrees and not more than 35 degrees, and more desirably not less than 21 degrees and not more than 29 degrees.

以上、具体例を参照しつつ本発明の実施の形態について説明した。上記、実施の形態はあくまで、例として挙げられているだけであり、本発明を限定するものではない。また、実施の形態の説明においては、半導体装置、半導体装置の製造方法等で、本発明の説明に直接必要としない部分等については記載を省略したが、必要とされる半導体装置、半導体装置の製造方法等に関わる要素を適宜選択して用いることができる。   The embodiments of the present invention have been described above with reference to specific examples. The above embodiment is merely given as an example, and does not limit the present invention. In the description of the embodiment, the description of the semiconductor device, the method for manufacturing the semiconductor device, etc., which is not directly necessary for the description of the present invention is omitted. Elements relating to the manufacturing method and the like can be appropriately selected and used.

例えば、実施の形態では、n型ダイヤモンド半導体層をp型ダイヤモンド半導体層の上に形成し、pn接合を形成したが、p型ダイヤモンド半導体層とn型ダイヤモンド半導体層の間に高純度i層(intrinsicダイヤモンド層)を設けてもよい。また、n型ダイヤモンド半導体層上にショットキー電極を形成したが、n型ダイヤモンド半導体層を高濃度n型ダイヤモンド半導体層とし、p型ダイヤモンド半導体層との間に高純度i層を設け、高濃度n型ダイヤモンド半導体層上にオーミック電極を形成するpinダイオード構造でもよい。また、基板にp型導電性基板を用い、基板裏面にオーミック電極を形成する縦型のデバイス構造であっても良い。   For example, in the embodiment, an n-type diamond semiconductor layer is formed on a p-type diamond semiconductor layer and a pn junction is formed. However, a high-purity i layer (between the p-type diamond semiconductor layer and the n-type diamond semiconductor layer ( An intrinsic diamond layer) may be provided. Further, the Schottky electrode is formed on the n-type diamond semiconductor layer. The n-type diamond semiconductor layer is a high-concentration n-type diamond semiconductor layer, and a high-purity i layer is provided between the p-type diamond semiconductor layer and a high concentration. A pin diode structure in which an ohmic electrode is formed on the n-type diamond semiconductor layer may be used. Alternatively, a vertical device structure may be used in which a p-type conductive substrate is used as the substrate and an ohmic electrode is formed on the back surface of the substrate.

その他、本発明の要素を具備し、当業者が適宜設計変更しうる全ての半導体装置および半導体装置の製造方法が、本発明の範囲に包含される。本発明の範囲は、特許請求の範囲およびその均等物の範囲によって定義されるものである。   In addition, the scope of the present invention includes all semiconductor devices that include the elements of the present invention and that can be appropriately modified by those skilled in the art and methods for manufacturing the semiconductor devices. The scope of the present invention is defined by the appended claims and equivalents thereof.

実施の形態の製造方法で、実施の形態のpnダイオードを製造する。(100)面から<011>度方向に15度傾斜する面を備える単結晶のダイヤモンド基板を用い、マイクロ波プラズマCVD法により、p型ダイヤモンド半導体層12、p型ダイヤモンド半導体層14およびn型ダイヤモンド半導体層16をエピタキシャル成長させる。 The pn diode of the embodiment is manufactured by the manufacturing method of the embodiment. Using a single crystal diamond substrate having a plane inclined by 15 degrees in the <011> degree direction from the (100) plane, the p + type diamond semiconductor layer 12, the p type diamond semiconductor layer 14 and the n type are formed by microwave plasma CVD. The diamond semiconductor layer 16 is epitaxially grown.

型ダイヤモンド半導体層12はホウ素(B)濃度を5×1020cm−3、p型ダイヤモンド半導体層14はホウ素(B)濃度を5×1019cm−3とし、n型ダイヤモンド半導体層12のリン(P)濃度は1×1015cm−3である。 The p + type diamond semiconductor layer 12 has a boron (B) concentration of 5 × 10 20 cm −3 , the p type diamond semiconductor layer 14 has a boron (B) concentration of 5 × 10 19 cm −3 , and the n type diamond semiconductor layer 12. The phosphorus (P) concentration of is 1 × 10 15 cm −3 .

RIE法により、リッジを形成し、p型ダイヤモンド半導体層12上にオーミック電極20を、Ti/Pt/Auを電子ビーム蒸着により堆積し、500℃で15分アニールすることで形成する。次に、n型ダイヤモンド半導体層16上にショットキー電極18を、ニッケル(Ni)を電子ビーム蒸着により堆積し形成する。 A ridge is formed by RIE, and an ohmic electrode 20 is deposited on the p + type diamond semiconductor layer 12 by depositing Ti / Pt / Au by electron beam evaporation and annealing at 500 ° C. for 15 minutes. Next, a Schottky electrode 18 is formed on the n-type diamond semiconductor layer 16 by depositing nickel (Ni) by electron beam evaporation.

ここでn型ダイヤモンド半導体層16はドナー濃度が低いため、ショットキー電極18を形成することにより熱平衡状態では完全に空乏化している。   Here, since the n-type diamond semiconductor layer 16 has a low donor concentration, the Schottky electrode 18 is formed so that it is completely depleted in the thermal equilibrium state.

作製されるpnダイオードI−V特性を測定すると、±10Vにおける整流比10桁以上、10Vにおける順方向電流密度が10000A/cmという値が得られる。また、逆方向のリーク電流は100Vで1pA以下であり、500Vまで電圧をかけてもブレークダウンは起こらない。 When the pn diode IV characteristic to be manufactured is measured, a rectification ratio of 10 digits or more at ± 10 V is obtained, and a forward current density at 10 V is 10000 A / cm 2 . Further, the reverse leakage current is 1 pA or less at 100 V, and no breakdown occurs even when a voltage up to 500 V is applied.

10 ダイヤモンド基板
12 p型ダイヤモンド半導体層
14 p型ダイヤモンド半導体層
16 n型ダイヤモンド半導体層
18 ショットキー電極
20 オーミック電極
100 pnダイオード
10 diamond substrate 12 p + type diamond semiconductor layer 14 p type diamond semiconductor layer 16 n type diamond semiconductor layer 18 Schottky electrode 20 ohmic electrode 100 pn diode

Claims (7)

(100)面から<011>±10度方向に10度以上40度以下の範囲で傾斜する面
を備えるダイヤモンド基板と、
前記面上に形成され、リン(P)を含有するn型ダイヤモンド半導体層と、
を備え
前記ダイヤモンド基板と、前記n型ダイヤモンド半導体層との間に、さらに、p型ダイヤモンド半導体層を有すること特徴とする半導体装置。
A diamond substrate comprising a surface inclined in a range of 10 degrees to 40 degrees in the <011> ± 10 degrees direction from the (100) plane;
An n-type diamond semiconductor layer formed on the surface and containing phosphorus (P);
Equipped with a,
Wherein the diamond substrate, between the n-type diamond semiconductor layer, further, a semiconductor device characterized by having a p-type diamond semiconductor layer.
前記n型ダイヤモンド半導体層のリン(P)濃度が、1×1015cm−3以上である
ことを特徴とする請求項1記載の半導体装置。
The semiconductor device according to claim 1, wherein the n-type diamond semiconductor layer has a phosphorus (P) concentration of 1 × 10 15 cm −3 or more.
(100)面から<011>±10度方向に15度以上35度以下の範囲で傾斜する面を備えるダイヤモンド基板と、 前記面上に形成され、リン(P)を含有するn型ダイヤモンド半導体層と、を備えることを特徴とする半導体装置。  A diamond substrate having a surface inclined in a range of 15 degrees to 35 degrees in the <011> ± 10 degrees direction from the (100) plane; and an n-type diamond semiconductor layer containing phosphorus (P) formed on the surface A semiconductor device comprising: 前記n型ダイヤモンド半導体層のリン(P)濃度が、1×10The phosphorus (P) concentration of the n-type diamond semiconductor layer is 1 × 10 1515 cmcm −3-3 以上であることを特徴とする請求項3記載の半導体装置。4. The semiconductor device according to claim 3, wherein the semiconductor device is as described above. 前記ダイヤモンド基板と、前記n型ダイヤモンド半導体層との間に、さらに、p型ダイヤモンド半導体層を有することを特徴とする請求項3または請求項4記載の半導体装置。5. The semiconductor device according to claim 3, further comprising a p-type diamond semiconductor layer between the diamond substrate and the n-type diamond semiconductor layer. (100)面から<011>±10度方向に10度以上40度以下の範囲で傾斜する面
を備えるダイヤモンド基板を準備し、
前記面上にp型ダイヤモンド半導体層を形成し、
前記p型ダイヤモンド半導体層上に、エピタキシャル成長により、リン(P)を含有するn型ダイヤモンド半導体層を形成することを特徴とする半導体装置の製造方法。
Preparing a diamond substrate having a surface inclined in a range of 10 degrees or more and 40 degrees or less in a <011> ± 10 degrees direction from the (100) plane;
Forming a p-type diamond semiconductor layer on the surface;
An n-type diamond semiconductor layer containing phosphorus (P) is formed on the p-type diamond semiconductor layer by epitaxial growth.
前記n型ダイヤモンド半導体層のリン(P)濃度が、1×1015cm−3以上である
ことを特徴とする請求項6記載の半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 6, wherein a phosphorus (P) concentration of the n-type diamond semiconductor layer is 1 × 10 15 cm −3 or more.
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