JP5536349B2 - Image display device - Google Patents

Description

  The present invention relates to an image display device such as an organic EL display device.

  Conventionally, an organic EL (Electro Luminescence) element that emits light by recombination of holes and electrons injected into the light emitting layer, and a thin film transistor (Thin Film Transistor) formed of, for example, amorphous silicon or polycrystalline silicon, for example. An image display device including a pixel circuit including “TFT”) has been proposed.

  An image display device using an organic EL element has a bottom emission structure that emits light downward through the substrate from the organic EL element formed on the light-transmitting substrate, and an upper side from the organic EL element formed on the substrate. It can be classified as a top emission structure that emits light. As an image display device having a bottom emission structure, there is Patent Document 1 or the like. In addition to the organic EL element, Patent Document 2 exists as an image display apparatus using a liquid crystal element.

JP 2007-081094 A JP-A-9-101543

  However, the bottom emission structure has a problem that the aperture ratio (the ratio of the light emission area of each pixel) is small because the organic EL element and the pixel circuit are formed side by side in the pixel in plan view.

  The present invention has been made in view of the above, and an object thereof is to provide an image display device capable of increasing the aperture ratio.

  An image display device according to an embodiment of the present invention includes: a light emitting element that emits light when current flows; a driver element that adjusts an amount of current flowing through the light emitting element by applying a voltage; and the driver element. And a capacitive element in which charges corresponding to the voltage applied are accumulated, and the capacitive element is formed by laminating a plurality of dielectric layers through electrode layers.

  The image display device according to an embodiment of the present invention is the image display device according to claim 1, wherein the capacitor element includes a first electrode layer and a first dielectric formed on the first electrode layer. A body layer, a second electrode layer formed on the first dielectric layer, a second dielectric layer formed on the second electrode layer, and a second layer formed on the second dielectric layer. The driver element and the capacitive element are provided so as to be separated from each other in plan view, and one of the first electrode layer and the second electrode layer is The gate electrode layer of the driver element is made of the same material, and the other of the first electrode layer and the second electrode layer is made of the same material as the source / drain layer of the driver element.

  An image display device according to an embodiment of the present invention is the image display device according to claim 2, wherein the light emitting element is provided so as to be separated from the driver element and the capacitor element in a plan view. The third electrode layer is made of the same material as the light transmissive electrode of the light emitting element.

  An image display device according to an embodiment of the present invention is the image display device according to claim 1, wherein the capacitor element includes a first capacitor element that accumulates charges according to a threshold voltage of the driver element. And a second capacitor element connected to the first capacitor element and storing a charge corresponding to the amount of current flowing through the light emitting element.

  An image display device according to an embodiment of the present invention is the image display device according to claim 4, wherein the first capacitor element and the second capacitor element are separated from each other in plan view. It is characterized by that.

  An image display apparatus according to an embodiment of the present invention is the image display apparatus according to claim 4, wherein charges accumulated in the first capacitor element and the second capacitor element are emitted during a light emission period of the light emitting element. Accordingly, the driver element is turned on, and the light emitting element emits light.

  ADVANTAGE OF THE INVENTION According to this invention, the image display apparatus which can raise an aperture ratio can be provided.

FIG. 1 is a circuit diagram showing a pixel circuit and a light emitting element constituting one pixel of the image display apparatus according to the first embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the pixel circuit of FIG. FIG. 3 is a diagram illustrating a current flow in the pixel circuit in the period T1 in which the charge accumulated in the capacitor element is initialized. FIG. 4 is a diagram illustrating a current flow in the pixel circuit in the period T2 in which the threshold voltage of the driving transistor _Td is detected. FIG. 5 is a diagram illustrating a current flow in the pixel circuit in the period T3 in which image data is written from the image signal line to the second capacitor element C _data . FIG. 6 is a diagram illustrating a current flow in the pixel circuit in the period T4 in which the light emitting element emits light. FIG. 7 is a top view when one pixel of the image display device configured by the pixel circuit and the light emitting element of FIG. 1 is actually realized. FIG. 8 is a cross-sectional view for explaining the structure of one pixel of the image display device of FIG. FIGS. 9-1 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIG. 9B is a process sectional view of the image display apparatus according to the present embodiment. FIGS. 9-3 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIGS. 9-4 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIG. 9-5 is a process sectional view of the image display apparatus according to the present embodiment. FIGS. 9-6 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIG. 9-7 is a process sectional view of the image display apparatus according to the present embodiment. FIGS. 9-8 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIGS. 9-9 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIGS. 9-10 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIGS. 9-11 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIGS. 9-12 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIGS. 9-13 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIGS. 9-14 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIGS. 9-15 is process sectional drawing of the image display apparatus concerning this Embodiment. FIGS. FIG. 10 is a circuit diagram showing the pixel circuit and the light emitting element 1 constituting one pixel of the image display device according to the first modification. FIG. 11 is a top view when actually realizing one pixel of an image display device according to a modified example including the pixel circuit and the light emitting element of FIG. FIG. 12 is a cross-sectional view for explaining the structure of one pixel of the image display device of FIG. FIG. 13 is a cross-sectional view for explaining the structure of the portion of the capacitance region R3 '. FIG. 14 is a circuit diagram showing a pixel circuit and the light emitting element 1 constituting one pixel of the image display device according to the second modification.

  Embodiments of an image display apparatus according to the present invention will be described below in detail with reference to the accompanying drawings. In addition, this invention shall not be limited to the following embodiment.

<< First Embodiment >>
FIG. 1 is a circuit diagram showing a pixel circuit and a light emitting element constituting one pixel of the image display apparatus according to the first embodiment of the present invention. A plurality of pixels are arranged in a matrix to form a screen for displaying an image. In FIG. 1, the capacity of the light emitting element is clearly shown.

This pixel circuit is a 5-TFT pixel circuit relating to a bottom emission structure of a common cathode using n-type TFTs. The pixel includes a light emitting element 1, five TFTs, various wirings for controlling each TFT, and two capacitor elements. Here, five TFT and the threshold voltage detection transistor T used when detecting the driving transistor T _d, the threshold voltage of the driving transistor T _d which current begins to flow between the drain and source of the driving transistor T _d of the driver element _th , a first reset transistor T _r used when resetting the charge accumulated in the light emitting element 1, a second reset transistor T _f used when resetting the charge accumulated in the two capacitance elements, and supplying an image signal a switching transistor T _s used when.

FIG. 2 is a timing chart showing the operation of the pixel circuit of FIG. As shown in FIG. 2, the unit frame period for displaying one image data includes a period T1 for initializing the light emitting element 1 and a period for detecting the threshold voltage _Vth of the driving transistor _Td. It consists of T2, a period T3 for writing image data, and a period T4 for the light emitting element 1 to emit light. Note that, since the potential of the image signal line 2 in the period T3 is an arbitrary value determined by the light emission luminance of each light emitting element 1, in FIG. 2, hatching is added for convenience in a range where the potential can exist. . In addition, the cathode electrode of the light emitting element 1 is connected to the ground line GND3 which is a reference potential. In the present embodiment, the potential of the ground line GND3 is always 0 V from the period T1 to the period T4.

  Hereinafter, the periods T1 to T4 in FIG. 2 will be described with reference to FIGS. Note that at the start of the period T1, charges are accumulated in the two capacitor elements in the period T4 of the previous frame.

  FIG. 3 shows the flow of current in the pixel circuit in the period T1 for initializing the charge accumulated in the capacitor.

As shown in FIG. 3, a first capacitor element C _th charge corresponding to the threshold voltage applied to the driving transistor T _d is accumulated, it is connected to the first capacitive element C _th, flowing through the light emitting element 1 Charges are released from the second capacitor element C _data in which charges corresponding to the amount of current are accumulated.

Here, potentials of various wirings for controlling each TFT in the period T1 are described. First, one end of the drive transistor _{T d,} and the potential of the power supply line VDD4 connected to one end of the first reset transistor _{T r} to 0V. Is connected to the gate of the first reset transistor T _r, the potential of the reset line 5 for switching the ON or OFF state of the first reset transistor T _r, a high potential (VgH). The potential of the _Tth control line 6 that switches the threshold voltage detection transistor _Tth on or off is set to a high potential (VgH). The potential of the scanning line 7 be switched on or off of the switching transistor T _s and a low potential (VgL). In the period T1, by controlling the potentials of the various wirings in this way, the first reset transistor T _r , the second reset transistor T _f and the threshold voltage detection transistor T _th are turned on, and the first capacitor element C _th The charge accumulated in the second capacitor element C _data flows to the power supply line VDD4 through these TFTs.

FIG. 4 shows a current flow in the pixel circuit in the period T2 in which the threshold voltage of the driving transistor _Td is detected.

As shown in FIG. 4, the threshold voltage of the drive transistor _Td where current starts to flow through the drive transistor _Td is detected. That is, as the potential between the gate and source of the driving transistor T _d is the threshold voltage of the driving transistor T _d, accumulate charge for giving a predetermined potential to the gate of the driving transistor T _d in the first capacitance element C _th .

Here, potentials of various wirings for controlling each TFT in the period T2 are described. First, the potential of the reset line 5 is set to a low potential (VgL). The potential of the power supply line VDD4 is set to a low potential (−Vp). The potential of the _Tth control line 6 is maintained at a high potential (VgH). The potential of the scanning line 7 is maintained at a low potential (VgL). In the period T2, by controlling the potentials of the various wirings in this way, the driving transistor T _d , the threshold voltage detection transistor T _th and the second reset transistor T _f are turned on in the first half of the period T2. Then, in the late period T2, the potential between the gate and source of the driving transistor T _d is, when a threshold voltage of the driving transistor T _d, a state where no current flows through the driving transistor T _d. As a result, in the period T2, the charge corresponding to the threshold voltage of the driving transistor T _d is accumulated in the first capacitor element C _th, variations in the threshold voltage V _th of the driving transistor T _d different for each pixel is compensated.

FIG. 5 shows a current flow in the pixel circuit in a period T3 in which image data is written from the image signal line 2 to the second capacitor element C _data .

Here, the potential of the _Tth control line 6 is switched from the high potential (VgH) to the low potential (VgL), and the second reset transistor _Tf and the threshold voltage detection transistor _Tth are switched from the on state to the off state. Then, the potential of the power supply line VDD4 is returned to 0V.

As shown in FIG. 5, charges corresponding to the luminance emitted from the light emitting element 1 are accumulated in the second capacitor element C _data . That is, set in accordance with the potential supplied from the image signal line 2 to the second capacitive element C _data to the luminance of the light emitting element 1, the switching transistor T second capacitor via the _s device C _data to the image signal line 2 potential The electric charge according to is supplied.

Here, potentials of various wirings for controlling each TFT in the period T3 are described. First, the potentials of the reset line 5 and the scanning line 7 are set to a high potential (VgH). Next, the potential of the image signal line 2 is set to an appropriate potential between 0 V and a high potential (VgH) according to the image data. Then, charges corresponding to the potential of the image signal line 2 are supplied to C _data via the switching transistor T _s . Thereafter, the potential of the scanning line 7 is set to a low potential (VgL), and then the potential of the reset line 5 is set to a low potential (VgL).

  FIG. 6 shows a current flow in the pixel circuit in the period T4 during which the light emitting element 1 emits light.

As shown in FIG. 6, a potential corresponding to the charge accumulated in the first capacitor element C _th and the second capacitive element C _data is given to the gate potential of the driving transistor T _d, turn on the driving transistor T _d And Then, a current flows from the power supply line VDD4 toward the ground line GND3, and the light emitting element 1 emits light.

Here, potentials of various wirings for controlling each TFT in the period T4 are described. The potentials of the reset line 5, the scanning line 7, and the _Tth control line 6 are maintained at a low potential (VgL). By controlling the potentials of the various wirings in this manner in the period T4, the switching transistor T _s , the threshold voltage detection transistor T _th , the first reset transistor T _r, and the second reset transistor T _f are turned off in the period T4. To do. Then, the potential of the power supply line VDD4 is switched from 0 V to a high potential (Vdd). Here, the charge accumulated in the first capacitor element _Cth is accumulated according to the threshold voltage of the drive transistor _Td , and the potential according to the charge is given to the gate potential of the drive transistor _Td. . Further, the charge accumulated in the second capacitor element C _data is accumulated according to the light emission luminance of the light emitting element 1, and the potential corresponding to the charge is further given to the gate potential of the drive transistor _Td . As a result, the drive transistor _Td enters a state in which a current according to the light emission luminance of the light emitting element 1 flows, and a current flows from the power supply line VDD4 having a high potential to the ground line GND3. The light emitting element 1 emits light with a light emission luminance corresponding to the amount of current flowing between the source and drain of the drive transistor _Td .

  Next, the light emitting element 1 included in the pixel will be described.

The light emitting element 1 includes at least a first conductive layer 18, a second conductive layer 20, and an organic light emitting layer 19 that is interposed between the first conductive layer 18 and the second conductive layer 20 and made of an organic light emitting material. It has a structure. In this pixel circuit, the first conductive layer is connected to one end of the drive transistor _Td , and the second conductive layer 20 is connected to the ground layer GND3 that serves as a reference potential.

  The first conductive layer 18 is made of a material that can transmit light emitted from the organic light emitting layer 19. For example, the first conductive layer 18 uses a light-transmitting conductive material such as an indium tin oxide film (ITO) or a tin oxide film. Formed. The second conductive layer 20 can be made of, for example, a material such as magnesium, silver, aluminum, or calcium, or an alloy thereof. The thickness of the second conductive layer 20 is set to 30 nm or less to form a light transmissive electrode. Can do. As a result, the light emitted from the organic light emitting layer 19 passes through the first conductive layer 18 and is emitted to the outside.

  The second conductive layer 20 is made of a material having a high light reflectivity such as a metal such as aluminum or silver, or an alloy thereof. In this way, by configuring the second conductive layer 20 from a material having a high light reflectance, the light extraction efficiency can be improved in the bottom emission structure.

  As a material of the organic light emitting layer 19, for example, a light emitting material such as Alq3 (tris (8-quinolinolato) aluminum complex) is used. In order to increase luminous efficiency, an organic metal compound such as tris [pyridinyl-kN-phenyl-kC] iridium or a dye such as coumarin is used as a dopant material and doped into a host material having a hole transport property or an electron transport property. The light emitting layer 19 may be configured. The density | concentration of the dopant material which comprises the organic light emitting layer 19 shall be 0.5 mass% or more and 20 mass% or less, for example. Examples of the host material having a hole transporting property include α-NPD and TPD. Examples of a host material having an electron transporting property include bis (2-methyl-8-quinolinolato) -4- (phenylphenolato) aluminum, 1,4-phenylenebis (triphenylsilane), 1,3-bis ( Triphenylsilyl) benzene, 1,3,5-tri (9H-carbazol-9-yl) benzene, CBP, Alq3, or SDPVBi. In addition, the material which comprises each layer of the organic light emitting layer 19 is selected according to the color of the emitted light. Examples of a dopant material that emits red light include tris (1-phenylisoquinolinato-C2, N) iridium or DCJTB. Examples of dopant materials that emit green light include tris [pyridinyl-kN-phenyl-kC] iridium or bis [2- (2-benzoxazolyl) phenolato] zinc (II). Examples of the dopant material that emits blue light include a distyrylarylene derivative, a perylene derivative, or an azomethine zinc complex. The organic light emitting layer 19 is not limited to a single layer structure, and may have a multiple layer structure. Such an organic EL element has a function of generating light by recombination of holes and electrons injected into the organic light emitting layer 19.

FIG. 7 is a top view when one pixel of the image display device configured by the pixel circuit and the light emitting element 1 of FIG. 1 is actually realized, and FIG. 8 is a structure of one pixel of the image display device of FIG. It is sectional drawing for demonstrating. In FIG. 8, for ease of explanation, in each part of FIG. 1, a portion representing the structure of the light emitting element 1 is an opening region R <b> 1, and a portion including the TFT structure is a TFT region R <b> 2. It depicts a portion representing a C _th and structure of the second capacitive element _{C data} as a capacitor region R3.

  A plurality of pixels of the image display device are formed on the substrate 11 due to its structure. Each pixel includes a first electrode layer 12, a first dielectric layer 13, a second electrode layer 14, a second dielectric layer 15, a third electrode layer 16, a planarizing film 17, and the light emitting element 1. .

  First, the opening region R1 will be described. The substrate 11 is made of, for example, glass or plastic, and is used in common by a plurality of pixels. On the substrate 11, a plurality of pixels arranged in a matrix in a plan view are formed. The substrate 11 is made of a material that transmits light, and the light emitted from the light emitting element 1 can be taken out to the outside. Note that a driver IC capable of setting potentials of various wirings can be mounted on the end portion of the substrate 11 in order to control the on state or the off state of each TFT.

  As shown in FIG. 8, the light emitting element 1 is formed on the flat surface of the substrate 11. That is, the first conductive layer 18 is formed on the substrate 11. A second conductive layer 20 is formed on the first conductive layer 18 via an organic light emitting layer 19. Thus, if the light emitting element 1 is not formed on a flat surface, the first conductive layer 18 and the second conductive layer 20 may be short-circuited, and the organic light emitting layer 19 may not emit light. In addition, even if the first conductive layer 18 and the second conductive layer 20 are not short-circuited, if the first conductive layer 18 is formed on an uneven surface, the organic light emitting layer formed on the first conductive layer 18 The thickness of 19 is not substantially uniform, the current is concentrated at a specific portion where the thickness of the organic light emitting layer 19 is thin, and the organic light emitting layer 19 may be deteriorated. Therefore, the first conductive layer 18 is formed on a flat surface so that the thickness of the organic light emitting layer 19 and the second conductive layer 20 is substantially uniform.

  The second conductive layer 20 is formed over the planarizing film 17 on the TFT region R2 and the capacitor region R3. A planarizing film 17 is formed on the TFT region R2 and the capacitor region R3 in order to reduce surface irregularities caused by various layers. As a result, the second conductive layer 20 is continuously formed in adjacent pixels. For the planarizing film 17, an organic material having an insulating property such as a novolac resin, an acrylic resin, an epoxy resin, or a silicon resin can be used.

  Further, a contact hole 21 penetrating the planarizing film 17 is formed in the planarizing film 17. The contact hole 21 is formed so that the lower part is narrower than the upper part. The contact hole 21 is formed in each pixel, and the organic light emitting layer 19 is exposed at the bottom of the contact hole 21. The second conductive layer 20 and the organic light emitting layer 19 are connected.

Next, the TFT region R2 will be described. As shown in FIG. 8, each pixel is provided with various TFTs including a gate layer 22, a gate insulating film 23, a channel layer 24, and a source / drain layer 25 on the substrate 11. Here, the TFT shown in FIG. 8 is a threshold voltage detection transistor _Tth . Then, the threshold voltage detection transistor T _th on the second dielectric layer 15 except for a part of the source-drain layer 25 of the threshold voltage detection transistor T _th is formed. The second dielectric layer 15 formed directly above the threshold voltage detection transistor T _th, the source-drain layer 25 of the threshold voltage detection transistor T _th is, for example, a short circuit between the conductive members, such as the third electrode layer 16 It is preventing.

  A gate layer 22 is formed on the substrate 11 in the TFT region R2. The gate layer 22 is made of, for example, a conductor material such as aluminum or molybdenum, or an alloy thereof.

  On the gate layer 22, for example, a gate insulating film 23 is formed to prevent the source / drain layer 25 and the gate layer 22 from being short-circuited. The gate insulating film 23 is made of a material that insulates between the channel layer 24 and the gate layer 22, and is made of an insulating material such as silicon nitride or silicon oxide.

  A channel layer 24 is formed on the gate insulating film 23 in a region overlapping the gate layer 22 in plan view. The channel layer 24 is made of amorphous silicon (amorphous silicon).

  A source / drain layer 25 is formed from the end of the channel layer 24 to the gate insulating film 23. The source / drain layer 25 is not formed on the center of the channel layer 24, and the source / drain layer 25 is divided into two so as to expose the center of the channel layer 14. The source / drain layer 25 is made of a conductive material such as aluminum or molybdenum. One end of the divided source / drain layer 25 is electrically connected to the first electrode layer 12 formed on the substrate 11.

  A second dielectric layer 15 is formed from the center of the exposed channel layer 24 to the source / drain layer 25. The second dielectric layer 15 is not formed on the source / drain layer 25 but is exposed. A part of the first conductive layer 18 extends from the substrate 11 on the exposed source / drain layer 25. A part of the source / drain layer 25 and the first conductive layer 18 are electrically connected.

Next, the capacity region R3 will be described. As shown in FIG. 8, the first capacitor layer C _data is constituted by the first electrode layer 12 formed on the substrate 11, the first dielectric layer 13, and the second electrode layer 14. The second capacitor layer _Cth is composed of the second electrode layer 14, the second dielectric layer 15, and the third electrode layer 16. The second electrode layer 14 functions as an electrode layer of the first capacitor element _Cth and the second capacitor element _Cdata . Then, the second electrode layer 14 is formed on the first electrode layer 12 via the first dielectric layer 13, and the third electrode layer 16 is formed on the second electrode layer 14 via the second dielectric layer 15. As a result, the first capacitor element _Cth and the second capacitor element _Cdata can be stacked one above the other. As a result, it is possible to provide a multilayer capacitor structure including the first capacitor element _Cth and the second capacitor element _Cdata .

Here, each layer constituting the first capacitor element C _th and the second capacitor element C _data will be described.

  The first electrode layer 12 is formed on the substrate 11 so as to be separated from the gate layer 22 and is electrically insulated from the gate layer 22. The first electrode layer 12 is made of the same material as the gate layer 22 and is made of, for example, a conductor material such as aluminum or molybdenum, an alloy thereof, or the like.

  The first dielectric layer 13 is formed from the first electrode layer 12 to the substrate 11 with a part of the first electrode layer 12 exposed. The exposed part of the first electrode layer 12 and the part of the source / drain layer 25 are electrically connected. The first dielectric layer 13 is made of the same material as the gate insulating film 23 and is made of an insulating material such as silicon nitride or silicon oxide.

  The second electrode layer 14 is formed on the first dielectric layer 13 in a region overlapping the first electrode layer 12 in plan view. The second electrode layer 14 is formed to be separated from the source / drain layer 25 and insulated from the source / drain layer 25. The second electrode layer 14 is made of the same material as the source / drain layer 25 and is made of a conductive material such as aluminum or molybdenum.

  The second dielectric layer 15 is formed from the second electrode layer 14 to the first dielectric layer 13. A part of the second dielectric layer 15 is formed to extend to the TFT region R2 adjacent to the capacitor region R3. The second dielectric layer 15 is made of an insulating material such as silicon nitride or silicon oxide, for example.

  The third electrode layer 16 is formed on the second dielectric layer 15 in a region overlapping the second electrode layer 14 in plan view. The third electrode layer 16 is made of the same material as that of the first conductive layer. For example, a material such as an indium tin oxide film (ITO), a tin oxide film, magnesium, silver, aluminum, or calcium, or an alloy thereof is used. Can be used.

In this way, by forming each layer of the first capacitor element C _th and the second capacitor element C _data , the second electrode layer 14 and the third electrode layer are provided between the first electrode layer 12 and the second electrode layer 14. The charge can be accumulated between the two.

As a result, the capacitor region R3 can be reduced by stacking the first capacitor element _Cth and the second capacitor element _Cdata in the vertical direction. Then, the opening region R1 can be increased by the amount that the capacitance region R3 is reduced. As a result, in each pixel, by increasing the region where the light emitting element 1 is formed in the opening region R1, the aperture ratio can be increased, and the light emission luminance of each pixel can be improved. Further, by increasing the aperture ratio, a desired light emission luminance can be obtained even if the amount of current flowing through each pixel is reduced. Therefore, by reducing the amount of current flowing through each pixel, deterioration of the organic light emitting material can be suppressed and the product life of the light emitting element 1 can be extended.

For example, when the specification of the image display device is a pixel size of 123 μm × 369 μm and a duty (ratio of the light emission period in the frame) of 80%, the first capacitor element C _th and the second capacitor element C _data overlap in plan view. When there is no area and both are provided side by side, the aperture ratio is 34.9%, whereas in the image display device according to the present embodiment, the aperture ratio can be improved to 39.9%. .

Then, from the viewpoint of the product life of the light emitting element 1, the image display device according to the present embodiment improves the aperture ratio by 15% compared to the case where the first capacitor element _Cth and the second capacitor element _Cdata are provided together. Therefore, the current density can be reduced by 12.6%. Here, assuming that the lifetime of the light-emitting element 1 is inversely proportional to the current density of about 1.7, the lifetime of the light-emitting element 1 of the image display device according to the present embodiment is 1.26 times longer due to the reduction of the current density. can do. That is, when the half life of the image display device provided with the first capacitor element C _th and the second capacitor element C _data is 15000 hours, the half life of the image display device according to the present embodiment is improved to about 19000 hours. Will do.

(Method for manufacturing image display device)
Next, a method for manufacturing an image display device having the configuration shown in FIGS. 1, 7, and 8 will be described. 9-1 to 9-15 are process cross-sectional views of the image display apparatus according to the present embodiment.

  First, as shown in FIG. 9A, the first metal layer 31 is formed on the substrate 11 by using, for example, a sputtering method. Here, as the material of the substrate 11, for example, glass is used, and the thickness thereof is 0.7 mm. Moreover, as a material of the 1st metal layer 31, aluminum is used, for example, The thickness is 0.3 micrometer. Thereafter, in order to pattern the first metal layer 31 into a predetermined shape, a resist is applied on the first metal layer 31, and the resist is exposed and developed to expose a part of the first metal layer 31 from the resist. . Furthermore, the first metal layer 31 is patterned into a predetermined shape by sequentially etching the first metal layer 31 exposed from the resist and removing the remaining resist. 9B, the first metal layer 31 is patterned into a predetermined shape, and the first electrode layer 12 is formed in the capacitor region R3. Further, the gate layer 22 is formed in the TFT region R2. As described above, the first electrode layer 12 and the gate layer 22 can be formed at the same time, and the manufacturing process can be simplified as compared with the case where they are formed separately.

  Next, the first insulating layer 32 is continuously formed on the first electrode layer 12, the gate layer 22, and the exposed substrate 11 by using, for example, a CVD method. Further, as shown in FIG. 9C, the semiconductor layer 33 is formed on the first insulating layer 32. Here, as the material of the first insulating layer 32, for example, silicon nitride is used, and the thickness thereof is 0.3 μm. Moreover, as a material of the semiconductor layer 33, for example, amorphous silicon (amorphous silicon) is used, and the thickness thereof is 0.1 μm. Next, a resist is applied onto the semiconductor layer 33, and the resist is exposed and developed to expose a part of the semiconductor layer 33 from the resist. Further, etching of the semiconductor layer 33 exposed from the resist and peeling of the remaining resist are sequentially performed. Then, the semiconductor layer 33 exposed from the resist is etched and the remaining resist is peeled in order to pattern the semiconductor layer 33 into a predetermined shape. As a result, the channel layer 24 can be formed directly on the gate layer 22 as shown in FIG. 9-4.

  Next, a resist is applied onto the channel layer 24 and the exposed gate layer 22, and the resist is exposed and developed to expose a part of the first insulating layer 32 from the resist. Further, the first insulating layer 32 is patterned into a predetermined shape by sequentially etching the first insulating layer 32 exposed from the resist and peeling off the remaining resist. As a result, as shown in FIG. 9-5, a through hole 34 penetrating the first insulating layer 32 can be formed immediately above the capacitor region R3 so that a part of the first electrode layer 12 is exposed. . Furthermore, the surface of the substrate 11 can be exposed by etching the first insulating layer 32 immediately above the opening region R1. Since the first insulating layer 32 is etched, the gate insulating film 23 can be formed so as to cover the gate layer 22 in the TFT region R2. Furthermore, the first dielectric layer 13 can be formed in the capacitive region R3. In this way, the first dielectric layer 13 and the gate insulating film 23 can be formed at the same time, and the manufacturing process can be simplified as compared with the case where they are formed separately.

  Next, as shown in FIG. 9-6, the second metal layer 35 is formed using, for example, a sputtering method so as to cover the opening region R1, the TFT region R2, and the capacitor region R3. A part of the second metal layer 35 is connected to the first electrode layer 12 through a through hole. Here, as the material of the second metal layer 35, for example, aluminum is used, and the thickness thereof is 0.3 μm. Thereafter, a resist is applied onto the second metal layer 35, and the resist is exposed and developed to expose a part of the second metal layer 35 from the resist. Further, the second metal layer 35 is patterned into a predetermined shape by sequentially etching the second metal layer 35 exposed from the resist and peeling off the remaining resist. As a result, as shown in FIG. 9-7, the second electrode layer 14 can be formed immediately above the first dielectric layer 13. Furthermore, the source / drain layer 25 can be formed from the first electrode layer 12 to the gate insulating film 23 through a through hole. The source / drain layer 25 is divided into two parts so that a part of the channel layer 24 is exposed.

  Next, as illustrated in FIG. 9-8, the second insulating layer 36 is formed by using, for example, a CVD method so as to cover the opening region R1, the TFT region R2, and the capacitor region R3. Here, as a material of the second insulating layer 36, for example, silicon nitride is used, and the thickness thereof is 0.2 μm. Thereafter, a resist is applied onto the second insulating layer 36, and the resist is exposed and developed to expose a part of the second insulating layer 36 from the resist. Further, the second insulating layer 36 is patterned into a predetermined shape by sequentially etching the second insulating layer 36 exposed from the resist and peeling off the remaining resist. As a result, as shown in FIG. 9-9, the surface of the substrate 11 can be exposed in the opening region R1. Furthermore, the second dielectric layer 15 can be formed on the TFT region R2 and the capacitor region R3. The second dielectric layer 15 has a through hole 37 so as to expose a part of the source / drain layer of the TFT region R2.

  Next, as shown in FIG. 9-10, the third metal layer 38 is formed by using, for example, a sputtering method so as to cover the opening region R1, the TFT region R2, and the capacitor region R3. Here, as a material of the third metal layer 38, for example, an indium tin oxide film (ITO) is used, and the thickness thereof is smaller than 0.04 μm. Thereafter, a resist is applied onto the third metal layer 38, and the resist is exposed and developed to expose a part of the third metal layer 38 from the resist. Further, the third metal layer 38 is patterned into a predetermined shape by sequentially etching the third metal layer 38 and removing the remaining resist. 9-11, the third electrode layer 16 can be formed so as to overlap the second electrode layer 14 in plan view in the capacitance region R3. Furthermore, the first conductive layer 18 can be formed from the opening region R1 to the exposed source / drain layer 25 in the TFT region R2. As described above, the third electrode layer 16 and the first conductive layer 18 can be formed at the same time, and the manufacturing process can be simplified as compared with the case where they are formed separately.

  Next, as illustrated in FIG. 9-12, the resin layer 39 is formed by using, for example, a spin coat method so as to cover the opening region R1, the TFT region R2, and the capacitor region R3. Here, as a material of the resin layer 39, for example, an acrylic resin is used, and the thickness thereof is 2.0 μm. Thereafter, as shown in FIGS. 9 to 13, the planarization film 17 is formed by patterning the resin layer 39 into a predetermined shape using a conventionally known thin film processing technique, for example, a photoetching technique. Here, in the planarizing film 17, a through hole (contact hole) 21 having a lower width than the upper portion is formed in the opening region R 1, and the first conductive layer 18 is exposed at the bottom of the through hole 21.

Next, as shown in FIGS. 9-14, the organic light emitting layer 19 is vapor-deposited using a conventionally known vapor deposition method so as to cover the exposed first conductive layer 18 in the opening region R1. Then, as shown in FIG. 9-15, the second conductive layer 20 is deposited on the organic light emitting layer 19. Here, as the material of the second conductive layer 20, for example, aluminum is used, and the thickness thereof is 300 nm. Through this process, as shown in FIGS. 1, 7, and 8, the first capacitor element _Cth and the second capacitor element C _data that are electrically connected in series are stacked in the vertical direction. An image display device according to the above can be manufactured.

<Modification 1>
In the image display device according to the first embodiment, the first capacitor element C _th and the second capacitor element C _data that are electrically connected in series are stacked in the vertical direction. In contrast, the image display apparatus according to the first modification of the present invention is provided such that the first capacitor element C _th and the second capacitor element C _data are separated from each other in plan view, and the first capacitor element This is a stacked capacitor structure in which C _th and second capacitor element C _data are stacked one above the other.

The image display device according to the first modification has substantially the same overall configuration as the image display device according to the first embodiment, but the first capacitor element C _th includes the third capacitor element C _th1 and the fourth capacitor element C _th1 . The change is that the second capacitive element C _data is divided into two capacitive elements C _th2 and the second capacitive element C _data is divided into five capacitive elements C _data1 and sixth capacitive element C _data2 . Hereinafter, regarding the image display device according to the first modification, the same parts as those of the image display device according to the first embodiment will be denoted by the same reference numerals, and description thereof will be omitted.

  FIG. 10 is a circuit diagram showing the pixel circuit and the light emitting element 1 constituting one pixel of the image display device according to the first modification.

In the present pixel circuit, the third capacitor element C _th1 and the fourth capacitor element C _th2 are electrically connected in parallel. Further, the fifth capacitive element C _data1 and the sixth capacitive element C _data2 are electrically connected in parallel.

FIG. 11 is a top view when one pixel of an image display device according to a modified example configured by the pixel circuit and the light emitting element 1 of FIG. 1 is actually realized, and FIG. 12 is a diagram of the image display device of FIG. It is sectional drawing for demonstrating the structure of 1 pixel. In FIG. 12, for ease of explanation, in each part of FIG. 1, a portion representing the structure of the light emitting element 1 is an opening region R <b> 1, and a portion including the TFT structure is a TFT region R <b> 2. A portion representing the structures of C _data1 and the sixth capacitive element C _data2 is depicted as a capacitive region R3 ′.

Here, the capacity region R3 ′ will be described. As shown in FIG. 12, on the substrate 11, a first electrode layer 41, a first dielectric layer 42 formed on the first electrode layer 41, and a first dielectric layer 42 formed on the first dielectric layer 42. A stacked capacitor structure is formed which includes a two-electrode layer 43, a second dielectric layer 44 formed on the second electrode layer 43, and a third electrode layer 45 formed on the second dielectric layer 44. Yes. Then, the first capacitor layer 41 formed on the substrate 11, the first dielectric layer 42, and the second electrode layer 43 constitute the fifth capacitor element C _data1 . The sixth capacitor element C _data2 is configured by the second electrode layer 43, the second dielectric layer 44, and the third electrode layer 45. The second electrode layer 43 functions as an electrode layer for the fifth capacitor element C _data1 and the sixth capacitor element C _data2 .

Further, as shown in FIG. 13, the first electrode layer 41 and the third electrode layer 45 are electrically connected. Specifically, the first electrode layer 41 and the source / drain layer 25 are connected through a through hole penetrating the first dielectric layer 42. The source / drain layer 25 and the third electrode layer 45 are connected through a through hole penetrating the second dielectric layer 44. The first electrode layer 41 and the third electrode layer 45 are electrically connected, and the fifth capacitor element C _data1 and the sixth capacitor element C _data2 are electrically connected in parallel.

Similarly, the third capacitor element C _th1 and the fourth capacitor element C _th2 are electrically connected in parallel, and the third capacitor element C _th1 or a part of the fourth capacitor element C _th2 and the fifth capacitor element C _th2 The capacitive element C _data1 or the sixth capacitive element C _data2 is connected in a plan view. In this manner, an image display apparatus according to a modification example including the pixel circuit and the light emitting element 1 illustrated in FIG. 10 can be realized.

<Modification 2>
In the image display apparatus according to the modified example 1, it was laminated a first capacitive element C _th and the second capacitor element C _data which is electrically connected in series in the vertical direction. On the other hand, the image display device according to the second modification of the present invention has a multilayer capacitive structure in which a capacitive element having the functions of both the first capacitive element _Cth and the second capacitive element _Cdata is formed.

  Compared with the image display device according to the first embodiment and the image display device according to modification example 1, the 5 TFT pixel circuit in the image display device according to modification example 2 is changed to a 2 TFT pixel circuit. Hereinafter, with respect to the image display device according to Modification Example 2, the same parts as those of the image display device according to the first embodiment and the image display device according to Modification Example 1 are denoted by the same reference numerals, and description thereof is omitted while being different. The part will be described.

  FIG. 14 is a circuit diagram showing a pixel circuit and the light emitting element 1 constituting one pixel of the image display device according to the second modification.

In the present pixel circuit, both the seventh capacitor element C _s1 and the eighth capacitor element C _s2 have the functions of both the first capacitor element C _th and the second capacitor element C _data . In other words, the seventh capacitor element C _s1 is the eighth capacitor element C _s2, charge corresponding to the threshold voltage or more of the driving transistor T _d to be applied to the driving transistor T _d is accumulated.

In the light emitting element 1, when the driving transistor _Td is in an on state, the power supply line VDD4 is set to a high potential and the power supply line VSS40 is set to a lower potential than the power supply line VDD4. Then, a potential difference is generated between the power supply line VDD4 and the power supply line VSS40. Then, a current is passed through the light emitting element 1 and the driving transistor _Td to cause the light emitting element 1 to emit light. At this time, both the seventh capacitor element C _s1 and the eighth capacitor element C _s2 have a charge corresponding to the threshold voltage potential of the drive transistor T _d and the light emission luminance of the light emitting element 1 supplied from the image signal line 2. A corresponding charge is accumulated.

The aperture ratio can be improved by stacking the seventh capacitor element C _s1 and the eighth capacitor element C _s2 of the 2-TFT pixel circuit vertically and connecting them in parallel electrically.

1 Light Emitting Element 2 Image Signal Line 3 Ground Line GND
4 Power line VDD
5 Reset line 6 T _th control line 7 Scan line 11 Substrate 12, 41 First electrode layer 13, 42 First dielectric layer 14, 43 Second electrode layer 15, 44 Second dielectric layer 16, 45 Third electrode layer 17 planarization film 18 first conductive layer 19 organic light emitting layer 20 second conductive layer 21 contact hole 22 gate layer 23 gate insulating film 24 channel layer 25 source / drain layer 31 first metal layer 32 first insulating layer 33 semiconductor layer 34 37 through hole 35 second metal layer 36 second insulating layer 38 third metal layer 39 resin layer 40 power line VSS

Claims (4)

A light emitting element that emits light when a current flows;
A driver element that adjusts an amount of current flowing through the light emitting element by applying a voltage; and
A capacitor element that accumulates charges according to the voltage applied to the driver element,
The capacitive element, Ri greens are laminated via the electrode layers a plurality of dielectric layers, a first electrode layer, a first dielectric layer formed on the first electrode layer, the first dielectric A second electrode layer formed on the layer; a second dielectric layer formed on the second electrode layer; and a third electrode layer formed on the second dielectric layer. And
The driver element and the capacitive element are provided so as to be separated in a plan view,
One of the first electrode layer and the second electrode layer is made of the same material as the gate layer of the driver element, and the other of the first electrode layer and the second electrode layer is a source / drain layer of the driver element. Made of the same material as
The light emitting element is provided so as to be separated from the driver element and the capacitive element in plan view.
The third electrode layer is made of the same material as the light transmissive electrode of the light emitting element . The image display device according to claim 1,
The capacitor element is connected to the first capacitor element for storing charges according to the threshold voltage of the driver element, and is stored in the capacitor element according to the amount of current flowing through the light emitting element. An image display device comprising a two-capacitance element. The image display device according to claim 2 ,
The image display device, wherein the first capacitor element and the second capacitor element are provided so as to be separated from each other in plan view. The image display device according to claim 3 ,
An image display device, wherein the driver element is turned on based on charges accumulated in the first capacitor element and the second capacitor element during a light emission period of the light emitting element, and the light emitting element emits light.

Images