JP5525962B2 - Output buffer circuit and control method thereof - Google Patents

Description

  The present invention relates to an output buffer circuit and a control method thereof. In particular, when different power supply voltages are supplied between the input system and the output system, an output buffer circuit capable of converting a signal having a small amplitude in the input system into a signal having a large amplitude in the output system and outputting the signal, and It relates to the control method.

  Recent advances in semiconductor integrated circuit technology are remarkable. As the technology of microfabrication advances, systems that were not conceived in the past can be integrated on one chip. In addition, high-speed systems that have never been considered for operating frequencies have also appeared. On the other hand, as the miniaturization technology progresses, the withstand voltage of the transistors incorporated in the semiconductor integrated circuit is decreasing, and the power supply voltage supplied to the semiconductor integrated circuit is changed from 5 V to 3.3 V, from 3.3 V to 1.8 V. Or it is changing to a lower power supply voltage.

  That is, the semiconductor integrated circuit is required to operate at a higher speed, and the transistor has a lower withstand voltage, so that the power supply voltage tends to decrease accordingly. However, some semiconductor integrated circuits are required to operate at higher speed while maintaining compatibility with conventional products to which a high power supply voltage is supplied. For example, in a semiconductor integrated circuit having an SD card interface, there is a demand for a semiconductor integrated circuit that operates in both the conventional 3.3 V specification 50 MHZ operation mode and the 1.8 V specification 208 MHZ operation mode. That is, a higher speed operation is required when a lower voltage of 1.8V is supplied than when a power supply voltage of 3.3V is supplied.

  Patent Document 1 describes an output circuit and a level shift circuit that output a high-amplitude signal using a low breakdown voltage transistor. FIG. 5 shows a circuit block diagram of the output buffer circuit described in Patent Document 1. In FIG. According to the output buffer circuit shown in FIG. 5, the first intermediate voltage Vref1 applied to the gate terminals of the N-channel transistors N21 and N23 is set to a threshold voltage that is half the power supply voltage VDD (VDD / 2). The voltage Vref1 = VDD / 2 + Vtn which is higher by the value voltage Vtn is set, and the second intermediate voltage Vref2 applied to the gate terminals of the P-channel transistors P21 and P23 is set to a voltage half of the power supply voltage VDD (VDD / 2). By setting the voltage Vref2 = VDD / 2− | Vtp | lower by the threshold voltage Vtp, the amplitude of the signal output to the connection points A to D can be suppressed to VDD / 2 or less, which is half the power supply voltage. it can. Therefore, even if the breakdown voltage between the source and drain of each transistor is about half of the power supply voltage, Patent Document 1 discloses that a high-amplitude signal can be output without deterioration or destruction of the transistor. Have been described. If the conventional output buffer circuit shown in FIG. 5 is used, it is considered that a 3.3 V high amplitude signal can be output using a 1.8 V low voltage transistor.

JP 2005-39560 A US Pat. No. 5,821,800

  The following analysis is given by the present invention. When the conventional output buffer circuit shown in FIG. 5 is used at a low power supply voltage VDD, there is no potential difference between the second intermediate voltage Vref2 and the power supply voltage VDD, so that the PMOS transistor P23 does not conduct, Level cannot be output. Therefore, this conventional output buffer circuit is good when used in an environment where a high power supply voltage such as 3.3V is supplied, but performs a switching operation at a high speed when a low power supply voltage such as 1.8V is supplied. I can't.

An output buffer circuit according to one aspect of the present invention is supplied with first and second power supplies, and converts an output logic signal of the first power supply system into an output logic signal of the second power supply system for output. A buffer circuit that outputs the first power supply voltage as a first control voltage signal when an absolute value of the second power supply voltage exceeds a predetermined voltage value; and an absolute value of the second power supply voltage. A first control voltage generation circuit that outputs a ground voltage as the first control voltage signal when the voltage is equal to or lower than the predetermined voltage value, and a second power supply voltage value is set to a second value when the input logic signal is at the ground level. A second control voltage generation circuit that outputs a second control voltage signal that is output as a control voltage signal and that has a voltage value substantially equal to the first control voltage when the input logic signal is at a first power supply voltage level. And between the second power source and ground. The source and drain of the first to fourth transistors, in which the second transistor is a first conductivity type transistor and the third and fourth transistors are second conductivity type transistors, are connected in series in that order. The second control voltage signal, the first control voltage signal, the reference voltage signal, and the inverted signal of the input logic signal are connected to the gates of the first to fourth transistors, respectively. The output logic signal is output from the connection point of the drain of the transistor and the third transistor, and the first control voltage generation circuit has a drain connected to the second power supply and a gate connected to the second power supply. A thirteenth transistor which is a depletion transistor of the second conductivity type connected to one power source, and a drain connected to the source of the thirteenth transistor via a resistor. A depletion transistor of the second conductivity type whose gate and source are grounded, a gate connected to the source of the thirteenth transistor, a source grounded via a resistor, and a drain connected to the first transistor A fifteenth transistor which is a second conductivity type transistor connected to one power source, a first inverter circuit to which a first power source is supplied and a source of the fifteenth transistor is connected to an input terminal; And a second inverter circuit that is supplied with a first power source, an output terminal of the first inverter circuit is connected to an input terminal, and the first control voltage signal is output from the output terminal .

  According to the output buffer circuit of the present invention, an output buffer circuit that can be used regardless of the voltage level of the second power supply voltage serving as an output system can be obtained. In particular, when the second power supply voltage is high, an output signal having an amplitude exceeding the breakdown voltage of the transistor is output. When the second power supply voltage is low, the same circuit as that when the second power supply voltage is high is used. Thus, an output buffer circuit that switches at high speed can be obtained.

  According to the output buffer circuit control method of the present invention, when the second power supply voltage is high, an output signal having an amplitude exceeding the withstand voltage of the transistor used in the output buffer circuit is output. Is low, a method for controlling the output buffer circuit that performs high-speed switching can be obtained.

FIG. 3 is a block diagram of an output buffer circuit according to an embodiment of the present invention. FIG. 2 is a more detailed circuit diagram of FIG. 1. It is a characteristic view of the input voltage versus output voltage of the 1st control voltage generation circuit in one example. It is a wave form diagram of each part of the output buffer circuit by one Example. 10 is a circuit diagram of a conventional output buffer circuit described in Patent Document 1. FIG.

  First, an outline of an embodiment of the present invention will be described. In addition, the drawings of the examples and the reference numerals in the drawings cited in the description of the outline are shown as examples of the embodiments, and the variations of the embodiments according to the present invention are not limited thereby.

  As shown in FIG. 1, an output buffer circuit according to an embodiment is supplied with first and second power supplies (VDD1 and VDD2), and receives an input logic signal IN of a first power supply system as a second power supply system. The output buffer circuit 100 outputs the first power supply voltage VDD1 as the first control voltage signal when the absolute value of the second power supply voltage VDD2 exceeds a predetermined voltage value. A first control voltage generation circuit 10 that outputs as VCT1 and outputs the ground voltage GND as the first control voltage signal VCT1 when the absolute value of the second power supply voltage VDD2 is equal to or lower than a predetermined voltage value, and an input logic signal IN The voltage value VDD2 of the second power supply is output as the second control voltage signal VCT2 when at the ground GND level, and the first control voltage signal VCT is output when the input logic signal IN is at the first power supply voltage VDD1 level. The first and second transistors are of the first conductivity type between the second control voltage generation circuit 20 that outputs the second control voltage signal VCT2 having substantially the same voltage value and the second power supply and the ground. The source and drain of the first to fourth transistors P1, P2, N3, and N4 in which the third and fourth transistors are transistors of the second conductivity type are arranged in that order (the order of P1, P2, N3, and N4). ) Connected in series, and the gates of the first to fourth transistors, respectively, the second control voltage signal VCT2, the first control voltage signal VCT1, the reference voltage signal VREF, and the inverted signal INB of the input logic signal, And the output logic signal OUT is output from the connection point of the drains of the second transistor P2 and the third transistor N3.

  Preferably, the reference voltage signal VREF connected to the gate of the third transistor N3 is a constant voltage signal at the first power supply voltage VDD1 level.

  Preferably, as shown in FIG. 2, the first control voltage generation circuit 10 is supplied with a voltage dividing circuit 11 that divides the voltage value of the second power supply VDD2 and the first power supply VDD1, and the divided voltage is supplied. Voltage value determination circuits 12, 13, and 14 for determining the value Q11.

  As shown in FIG. 2, the second control voltage generation circuit 20 includes fifth and sixth transistors P5 each having a source connected to the second power supply VDD2 and a gate connected to the other drain. , P6 and the sources are connected to the drains of the fifth and sixth transistors P5 and P6, respectively, and the seventh and eighth transistors P7 and P8 have the gates supplied with the first control voltage signal VCT1, and the sources are A ninth transistor N9, which is grounded, receives an inverted signal INB of the input logic signal at the gate, and controls conduction and non-conduction of the current flowing between the drain and the drain of the seventh transistor P7, and the source is grounded The tenth transistor in which the input logic signal IN is connected to the gate and the conduction and non-conduction of the current flowing between the drain and the drain of the eighth transistor P8 is controlled. And the second control voltage signal VCT2 is output from the drain of the sixth transistor P6, the fifth to eighth transistors P5 to P8 are transistors of the first conductivity type, and the ninth to tenth transistors When the transistors N9 and N10 are of the second conductivity type and the input logic signal IN is at the first power supply voltage VDD1 level, the voltage level of the second control voltage signal VCT2 is the threshold value of the eighth transistor P8. The voltage level may be shifted from the voltage level of the first control voltage signal VCT1 by that amount.

  Preferably, as shown in FIG. 2, the second control voltage generation circuit 20 has a source connected to the drain of the ninth transistor N9, a drain connected to the drain of the seventh transistor P7, and a reference to the gate. An eleventh transistor N11 of the second conductivity type to which the voltage signal VREF is input, a source connected to the drain of the tenth transistor N10, a drain connected to the drain of the eighth transistor, and a reference voltage signal to the gate And a twelfth conductivity type twelfth transistor N12 to which VREF is input.

  Preferably, as shown in FIG. 2, the first control voltage generation circuit 10 includes a first resistance element N13 having one end connected to the second power supply VDD2, and one end other than the first resistance element N13. A voltage dividing circuit including a second resistance element (series connection of R2 and N14) connected to one end and the other end connected to the ground GND, the other end of the first resistance element N13, and a second resistance A source follower circuit 12 having one end of an element (series connection of R2 and N14) connected to a gate and a drain connected to a second power source, and a waveform shaping of an output signal of the source follower circuit, and the first control voltage Waveform shaping circuits (13 and 14) for generating signals.

  More preferably, as shown in FIG. 2, the first control voltage generation circuit 10 includes a second conductivity type depletion having a drain connected to the second power supply VDD2 and a gate connected to the first power supply VDD1. A thirteenth transistor N13 which is a transistor; a fourteenth transistor N14 which is a depletion transistor of the second conductivity type whose drain is connected to the source of the thirteenth transistor N13 via a resistor R2, and whose gate and source are grounded; A fifteenth transistor N15 which is a second conductivity type transistor having a gate connected to the source of the thirteenth transistor N13, a source grounded through the resistor R3, and a drain connected to the first power supply VDD1; The first power supply VDD1 is supplied, and the source of the fifteenth transistor N15 is connected to the input terminal Q15. The first inverter circuit 13 and the first power supply VDD1 are supplied, the output terminal Q12 of the first inverter circuit 13 is connected to the input terminal, and the first control voltage signal VCT1 is output from the output terminal Q13. 2 inverter circuits 14. In the example of FIG. 2, the depletion transistors N13 and N14 are used in the voltage dividing circuit 11 of the first control voltage generation circuit 10, but the voltage dividing circuit 11 does not use a depletion transistor but is a normal enhancement type transistor. Needless to say, it can be configured using only.

  Preferably, as shown in FIG. 2, each of the first conductivity type transistors P1, P2, P5 to P8 is a PMOS transistor, and each of the second conductivity type transistors N3, N4, and N9 to N15 is an NMOS transistor. Both the first power supply VDD1 and the second power supply VDD2 are power supplies to which a positive power supply voltage is supplied with respect to the ground.

  Alternatively, each of the first conductivity type transistors P1, P2, and P5 to P8 is an NMOS transistor, and each of the second conductivity type transistors N3, N4, and N9 to N15 is a PMOS transistor, and the first power supply VDD1 and the second power supply. Both VDD2 may be power supplies to which a negative power supply voltage is supplied with respect to the ground.

  In addition, as shown in FIG. 1, the output buffer circuit control method according to the embodiment includes a first conductivity type first source drain connected in series between the second power supply VDD2 and the output terminal OUT. First and second transistors P1, P2, and second and third conductivity type third and fourth transistors N3, N4 having source and drain connected in series between the output terminal OUT and ground GND, Control of the output buffer circuit 100 that is supplied with the first power supply VDD1 and the second power supply VDD2, converts the input logic signal IN of the first power supply system into the output logic signal OUT of the second power supply system, and outputs it from the output terminal OUT. In the method, when the absolute value of the second power supply voltage VDD2 exceeds a predetermined voltage value, the first power supply voltage VDD1 is applied to the gate of the second transistor P2, and the second power supply voltage VDD2 Absolute When the value is equal to or lower than a predetermined voltage value, the ground voltage GND is applied, and when the input logic signal IN is at the ground GND level, the voltage value VDD2 of the second power supply is applied to the gate of the first transistor P1. When the signal IN is at the first power supply voltage VDD1 level, a voltage value VCT2 substantially equal to the gate voltage VCT1 of the second transistor P2 is applied, and the first power supply voltage VDD1 level is applied to the gate of the third transistor N3. The inverted voltage of the input logic signal IN is applied to the gate of the fourth transistor N4.

  The description of the outline is finished above, and more specific embodiments of the present invention will be described in more detail with reference to the drawings.

  FIG. 1 is a block diagram of an output buffer circuit according to the first embodiment. The output buffer circuit 100 shown in FIG. 1 is an output buffer circuit 100 that converts a VDD1-related input logic signal IN inputted from a logic signal input terminal IN into a VDD2-related output signal and outputs it from an output terminal OUT. In the output buffer circuit according to the first embodiment, when the voltage value of the second power supply voltage VDD2 is supplied with a voltage equivalent to the voltage value of the first power supply voltage VDD1, the power supply voltage higher than the first power supply voltage VDD1. Consideration has been given so that it can be used in both cases.

  For example, when the output buffer circuit is an output buffer circuit of a device used by being attached to and detached from various systems such as an SD card, when a high voltage power supply (for example, 3.3 V) is supplied from the system However, it is preferable that the low voltage power supply (for example, 1.8 V) can be used in both cases. When a high voltage power supply is supplied from the system, if a regulator circuit is provided inside the apparatus, the internal circuit of the apparatus can be operated by stepping down to a low voltage power supply. However, the power supply of the output circuit in the interface portion with the system needs to have a high power supply voltage in accordance with the power supply voltage of the system. In order to cope with such a case, the output buffer circuit of FIG. 1 has the second power supply voltage VDD2 even if the second power supply voltage VDD2 is equal to or lower than the first power supply voltage VDD1. Is configured to operate regardless of whether the voltage is higher than the first power supply voltage VDD1.

  In the output buffer circuit according to the first embodiment, the PMOS transistor and the NMOS transistor that constitute the output buffer circuit are both low breakdown voltage transistors, and the voltage value of the second power supply voltage VDD2 is the source-drain breakdown voltage, the gate Even when the breakdown voltage between the sources and the breakdown voltage between the gate and drain are exceeded, only a voltage equivalent to VDD1 is applied at most between the source and drain, between the gate and source, and between the gate and drain of each transistor. Therefore, the output buffer circuit may be a low breakdown voltage transistor that can be used for a microfabrication process of a semiconductor device. That is, the withstand voltage of each transistor is sufficient if it has a withstand voltage of VDD1, and the voltage value of the second power supply VDD2 is sufficient if it does not exceed twice the maximum value of the voltage value of the first power supply VDD1. It may be a high voltage exceeding the withstand voltage.

  In FIG. 1, the source and drain of the first transistor P1 and the second transistor P2 are connected in series between the second power supply VDD2 and the output terminal OUT. Both the first transistor P1 and the second transistor P2 are low breakdown voltage PMOS transistors. A second control voltage signal VCT2 output from the second control voltage generation circuit 20 is connected to the gate of the first transistor P1, and the first control voltage generation circuit 10 outputs to the gate of the second transistor P2. A first control voltage signal VCT1 is connected.

  Further, the source and drain of the third transistor N3 and the fourth transistor N4 are connected in series between the output terminal OUT and the ground GND. The third transistor N3 and the fourth transistor N4 are both low breakdown voltage NMOS transistors. The reference voltage signal VREF is connected to the gate of the third transistor N3, and the inverted input logic signal INB is connected to the gate of the fourth transistor N4.

  The reference voltage signal VREF is preferably supplied with the voltage value VDD1 itself of the first power supply VDD1. The voltage applied to the reference voltage signal VREF is a voltage other than VDD1 as long as the voltage applied between the drain and source of the NMOS transistors N3 and N4, between the gate and source, and between the gate and drain can be relaxed. Also good.

  Further, the VDD1 system input logic signal IN inputted from the logic signal input terminal IN is logically inverted by the VDD1 system inverter circuit 30 to become an inverted input logic signal INB, which is connected to the gate of the fourth transistor N4. Note that the input logic signal IN and the inverted input logic signal INB, which is an inverted signal thereof, are VDD1-related logic (digital) signals in which the low level is the GND level and the high level is the VDD1 level.

  The first control voltage generation circuit 10 is supplied with the first power supply VDD1 as a power supply, inputs the voltage value of the second power supply VDD2, determines the voltage value of the second power supply VDD2, and based on the determination result, The first control voltage signal VCT1 is output. When the voltage value of the second power supply VDD2 exceeds a predetermined voltage value, the first control voltage generation circuit 10 outputs the voltage value of the first power supply VDD1 as the first control voltage signal VCT1. On the other hand, when the voltage value of the second power supply VDD2 is equal to or lower than the predetermined voltage value, the ground voltage GND is output as the first control voltage signal VCT1. The predetermined voltage value used as a reference for determination by the first control voltage generation circuit 10 can be arbitrarily set. For example, the voltage value of the second power supply VDD2 is set based on the power supply voltage value of the first power supply VDD1. The determination can be made based on whether or not the voltage value of the first power supply VDD1 exceeds a certain level. For example, when the first power supply VDD1 is 1.8V, the determination can be made based on whether the voltage value of the second power supply VDD2 is 3.3V or 1.8V.

  The second control voltage generation circuit 20 is a circuit to which the second power supply VDD2 is supplied as a power supply, and receives the input logic signal IN and the first control voltage signal VCT1, and outputs the second control voltage signal VCT2. . When the input logic signal IN is at a low level (GND level), the second control voltage generation circuit 20 outputs the second power supply voltage VDD2 as the second control voltage signal VCT2. When the input logic signal IN is at a high level (VDD1 level), a signal having a voltage level substantially equal to that of the first control voltage signal VCT1 is output as the second control voltage signal VCT2.

  According to the above configuration, since the transistors P1 and P2 are connected in series between the output terminal OUT and the second power supply VDD2, the voltage from the output terminal OUT is high when the voltage value of the second power supply VDD2 is high. When outputting an output signal of the ground GND level, the gate voltages of the transistors P1 and P2 are controlled so that the source-drain voltage higher than VDD1 is not applied to the transistors P1 and P2 connected in series. In addition, the voltage between the gate source and the gate drain is controlled so that a voltage of VDD1 or more is not applied.

  Similarly, when the transistors N3 and N4 are connected in series between the output terminal OUT and the ground GND, and the voltage value of the second power supply VDD2 is high, an output signal of VDD2 level is output from the output terminal OUT. In addition, the source-drain voltage of VDD1 or higher is not applied to the transistors N3 and N4 connected in series, and the voltage of VDD1 or higher is not applied to the voltage between the gate source and the gate drain.

  On the other hand, when the power supply voltage of the second power supply VDD2 is low, the first control voltage signal VCT1 is fixed at the ground level, so that the transistor P2 is always in a conductive state. When the transistor P1 outputs a low level from the output terminal OUT, a voltage of VDD2 level is applied to the gate and the transistor P1 is controlled to be completely non-conductive. When a high level is output from the output terminal OUT, a voltage level close to ground is applied to the gate of the transistor P1, so that the voltage level of the output terminal OUT can be raised to the VDD2 level at high speed.

  FIG. 2 is a circuit diagram illustrating the internal circuit configuration of the first control voltage generation circuit 10 and the second control voltage generation circuit 20 of the output buffer circuit 100 in FIG. The internal circuit configurations of the first control voltage generation circuit 10 and the second control voltage generation circuit 20 will be further described with reference to FIG. The circuit of FIG. 2 is the same as the output buffer circuit of FIG. 1 except that the internal circuit configuration of the first control voltage generation circuit 10 and the second control voltage generation circuit 20 is described. Therefore, description of the parts already described in FIG. 1 is omitted.

  In FIG. 2, the first control voltage generation circuit 10 includes a voltage dividing circuit 11 that divides the voltage value of the second power supply VDD <b> 2 and a voltage value determination circuit that determines the voltage value divided by the voltage dividing circuit 11. The voltage value determination circuit includes a source follower circuit 12 that shifts the voltage value that has been voltageized by the voltage divider circuit 11 and cascaded inverter circuits 13 and 14 that determine the voltage level of the output signal of the source follower circuit 12 and shape the waveform. Consists of.

  The voltage dividing circuit 11 includes a thirteenth transistor N13, which is an NMOS low breakdown voltage depletion transistor having a drain connected to the second power supply VDD2 and a gate connected to the first power supply VDD1 via a resistor R1, and a thirteenth transistor. A fourteenth transistor N14, which is an NMOS low breakdown voltage depletion transistor having a drain connected to the source of N13 via a resistor R2, is provided. The gate and source of the fourteenth transistor N14 are connected to the ground GND. With the above configuration, a current flows from the second power supply VDD2 to the ground GND through the drain and source of the thirteenth transistor N13 and between the resistor R2 and the drain and source of the fourteenth transistor N14. When a current flows, a constant voltage is generated at the node Q11 that is the source of the transistor N13, depending on the on-resistances of the transistors N13 and N14 and the value of the resistor R2. The voltage generated at node Q11 is determined by voltage value determination circuits 12-14. The resistor R1 is provided for protecting the gate of the transistor N13. For circuit operation, the resistor R1 is not necessarily provided. In addition, although the NMOS depletion transistors N13 and N14 are used in the voltage dividing circuit here, it is needless to say that the voltage dividing circuit can be configured by using only a normal enhancement type MOS transistor without using the depletion transistor. . It is also possible to form a voltage dividing circuit with a resistor without using a transistor.

  The source follower circuit 12 includes a fifteenth transistor N15 that is an NMOS transistor having a drain grounded to the first power supply VDD1 and a gate connected to the node Q11, and a resistor R3 that connects the source of the transistor N15 and the ground GND. I have. In the source follower circuit 12, when the current flows, the voltage at the output node Q15 is lower than the input node Q11 by the gate-source voltage of the NMOS transistor N15. The voltage at the output node Q15 of the source follower circuit 12 is determined by the cascaded inverter circuits 13 and 14, and is output as a logic signal having the voltage value VDD1 level or GND level. The voltage output from the inverter circuit 14 (the voltage level of the first control voltage signal VCT1) is the VDD1 level when the voltage value of the second power supply VDD2 exceeds a predetermined voltage value, and the voltage of the second power supply VDD2 When the value is equal to or lower than a predetermined voltage value, the GND level is obtained.

  The voltage value that serves as a determination criterion for the voltage value of the second power supply VDD2 can be arbitrarily determined depending on the ratio of the values of the transistors N13 and N14 and the resistor R2, the size ratio of the inverter circuit 13 in the first stage, and the like. In order to determine whether the value of the power supply VDD2 is 1.8V or 3.3V, it is preferable that the voltage value serving as a determination reference is an intermediate voltage value between 1.8V and 3.3V.

  Next, the configuration of the second control voltage generation circuit 20 will be described. The sources of the fifth and sixth transistors P5 and P6, which are PMOS low breakdown voltage transistors, are both connected to the second power supply VDD2. The gate of the transistor P5 is connected to the drain of the transistor P6, and the gate of the transistor P6 is connected to the drain of the transistor P5. The drains of the transistors P5 and P6 are connected to the sources of seventh and eighth transistors P7 and P8, respectively, which are PMOS low breakdown voltage transistors. The gates of the transistors P7 and P8 are both connected to the first control voltage signal VCT1. The drains of the transistors P7 and P8 are connected to the drains of the eleventh and twelfth transistors N11 and N12, which are NMOS low breakdown voltage transistors, respectively. A reference voltage signal VREF is connected to the gates of the transistors N11 and N12. The sources of the transistors N11 and N12 are connected to the drains of the ninth and tenth transistors N9 and N10, which are NMOS low breakdown voltage transistors, respectively. The inverted input logic signal INB is connected to the gate of the transistor N9, and the input logic signal IN is connected to the gate of the transistor N10. The sources of the transistors N9 and N10 are connected to the ground GND.

  With the above configuration, the second control voltage generation circuit 20 basically functions as a level shifter that level-shifts the VDD1 system input logic signal IN to the VDD2 system logic signal. However, since the second control voltage signal VCT2 output from the second control voltage generation circuit 20 is connected to the gate of the PMOS transistor P1 whose source is connected to the second power supply VDD2, the power supply voltage VDD2 is a high voltage. In this case, the low-level voltage value of the second control voltage signal VCT2 is controlled so as not to drop below the voltage value of the first power supply VDD1.

  When the low level voltage value of the second control voltage signal VCT2 falls below the voltage value of the first power supply VDD1, an excessive voltage is applied between the gate and source of the low breakdown voltage PMOS transistor P1, and the PMOS transistor P1 is destroyed. Fear arises. In addition, when the voltage value of the second power supply VDD2 is a low voltage corresponding to the first power supply VDD1, the PMOS transistor P1 is sufficient if the low level voltage value of the second control voltage signal VCT2 does not fall to the ground level GND. It cannot be conducted at high speed. Therefore, by applying the first control voltage signal VCT1 to the gates of the transistors P7 and P8, the low level potential of the second control voltage signal VCT2 is controlled.

  In addition, the low-voltage transistor groups (P5, P7, N11, N9 and P6, P8, P9, N10) connected in series that constitute the second control voltage generation circuit 20 itself by the transistors P7, P8, N11, and N12. An excessive voltage is prevented from being applied.

  Next, the result of confirming the operation of the output buffer circuit of Example 1 by simulation will be described. FIG. 3 is a graph showing a simulation result of input / output voltage characteristics of the first control voltage generation circuit. In FIG. 3, the horizontal axis represents the voltage value of VDD2, and the vertical axis represents the voltage value of the first control voltage signal VCT1. The voltage values of VDD1 and VREF are fixed at 1.8V. In FIG. 3, for reference, the voltage value of VDD2 and the voltage value of VREF are also plotted in addition to the voltage value of the first control voltage signal VCT1. The first control voltage signal VCT1 is 0V when the voltage value of the second power supply VDD2 is 1.8V or less (below the voltage value of VDD1), and the voltage value of the second power supply VDD2 is 1.8V (VDD1 When the voltage value is exceeded, the voltage value 1.8V of the first power supply is output.

  Next, FIG. 4 is a simulation waveform diagram when the output buffer circuit 100 of the first embodiment is actually operated at the voltage values 3.3 V and 1.8 V of the second power supply VDD2. The horizontal axis indicates time. In FIG. 4, the voltage values of the first power supply VDD1 and the reference voltage signal VREF are fixed at 1.8V. In the upper part of FIG. 4, the input logic signal IN, the voltage level of the output terminal OUT, and the voltage level of the second power supply VDD2 are plotted. As an input logic signal IN, a square wave that repeats from 0 ns to high level (1.8 V) 5 ns and low level (0 V) 5 ns is input. The voltage value of the second power supply VDD2 is 3.3 V until about 18 ns, and then 1.8 V after about 19 ns. A signal output from the output terminal OUT is in phase with the input logic signal IN, and when the voltage value of the second power supply VDD2 is 3.3V, a high level 3.3V is output, and the voltage of the second power supply VDD2 is output. When the value is 1.8V, a high level 1.8V is output. The low level is 0 V regardless of the voltage value of the second power supply VDD2.

  Next, the inverting input signal INB, the first control voltage signal VCT1, and the second control voltage signal VCT2 are plotted in the lower part of FIG. The inverted input signal INB is a square wave having a low level of 0 V and a high level of 1.8 V, and a phase inverted from that of the input logic signal IN, regardless of the voltage value of the second power supply voltage VDD2. The first control voltage signal VCT1 outputs 1.8V (from 0 ns to about 19 ns) when the voltage value of the second power supply VDD2 exceeds 1.8V, and the voltage value of VDD2 becomes 1.8V. After decreasing, 0V is output (after 19 ns).

  The second control voltage signal VCT2 basically outputs a logic signal in phase with the inverted input logic signal INB (opposite phase with the input logic signal IN), but the voltage value of the power supply voltage VDD2 is 3.3V ( The operation differs between 1.8V (or 1.8V or less) and 1.8V (or 1.8V or less). When the voltage value of the power supply voltage VDD2 is 3.3V, a control voltage signal having the same phase as the inverted input logic signal INB, a high level of 3.3V (the same potential as VDD2), and a low level of about 2V (substantially the same as VDD1) Output. Note that the low level does not become the same voltage as VDD1 as can be understood with reference to FIG. 2. The source potential (VCT2) of the transistor P8, which is a PMOS transistor, is changed to the gate potential (VCT1) of the transistor P8. This is because the voltage does not fall below the voltage obtained by adding the threshold value of P8.

  When the voltage value of the second power supply VDD2 is 1.8V, the second control voltage signal VCT2 is in phase with the inverting input logic signal INB and has a high level of 1.8V (the same potential as VDD2) and a low level of about 0.3V. A control voltage signal (substantially the same as GND) is output.

  In the above embodiment, the first power supply VDD1 and the second power supply VDD2 are both power supplies that output a positive voltage with respect to the ground GND. In the case of a power source that outputs a negative voltage with respect to the ground GND, it can be applied as it is if all the PMOS and NMOS of the transistor conductivity type are replaced. That is, even when the absolute value of the voltage value of the second power supply is higher than a certain voltage value, a high output amplitude can be obtained using only the low breakdown voltage transistor. Further, even when the absolute value of the voltage value of the second power supply is lower than a certain voltage value, the output can be driven at high speed using the same circuit as in the case of the high voltage.

  It should be noted that the embodiments and examples can be changed and adjusted within the scope of the entire disclosure (including claims) of the present invention and based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

10: first control voltage generation circuit 11: voltage dividing circuit 12: source follower circuit 13, 14, 30: inverter circuit 20: second control voltage generation circuit 100: output buffer circuit IN: logic signal input terminal, input logic signal ( VDD1 system)
OUT: Output terminal (VDD2 system)
P1-P2, P5-P8: PMOS transistors N3-N4, N9-N12, N15: NMOS transistors N13, N14: NMOS depletion transistors VDD1: first power supply VDD2: second power supply GND: ground R1-R3: resistor INB : Inverted input logic signal (VDD1 system)
VCT1: first control voltage signal VCT2: second control voltage signal VREF: reference voltage signal

Claims (8)

An output buffer circuit that is supplied with first and second power supplies, converts an input logic signal of the first power supply system into an output logic signal of the second power supply system, and outputs the output logic signal;
When the absolute value of the second power supply voltage exceeds a predetermined voltage value, the first power supply voltage is output as a first control voltage signal, and the absolute value of the second power supply voltage is the predetermined voltage value. A first control voltage generation circuit that outputs a ground voltage as the first control voltage signal when:
When the input logic signal is at the ground level, the voltage value of the second power supply is output as the second control voltage signal. When the input logic signal is at the first power supply voltage level, it is substantially the same as the first control voltage signal. A second control voltage generation circuit for outputting the second control voltage signal having a level voltage value;
The first to fourth transistors are first conductivity type transistors between the second power source and the ground, and the third and fourth transistors are second conductivity type transistors. Connect the source and drain of the transistor in series in that order,
The second control voltage signal, the first control voltage signal, the reference voltage signal, and the inverted signal of the input logic signal are connected to the gates of the first to fourth transistors, respectively. The output logic signal is output from the connection point of the drains of the transistor and the third transistor ,
The first control voltage generation circuit includes:
A thirteenth transistor which is a second conductivity type depletion transistor having a drain connected to the second power supply and a gate connected to the first power supply;
A fourteenth transistor which is a second conductivity type depletion transistor having a drain connected to the source of the thirteenth transistor via a resistor and a gate and a source grounded;
A fifteenth transistor that is a second conductivity type transistor having a gate connected to the source of the thirteenth transistor, a source grounded through a resistor, and a drain connected to the first power supply;
A first inverter circuit to which a first power is supplied and a source of the fifteenth transistor is connected to an input terminal;
A second inverter circuit that is supplied with a first power supply, an output terminal of the first inverter circuit is connected to an input terminal, and outputs the first control voltage signal from an output terminal;
Output buffer circuit, which comprises a.   2. The output buffer circuit according to claim 1, wherein the reference voltage signal is a constant voltage signal at the first power supply voltage level.   The first control voltage generation circuit includes a voltage dividing circuit that divides the voltage value of the second power supply, and a voltage value determination circuit that is supplied with the first power supply and determines the divided voltage value. The output buffer circuit according to claim 1 or 2. The second control voltage generation circuit includes:
Fifth and sixth transistors having both sources connected to the second power source and both gates connected to the other drain;
Seventh and eighth transistors having sources connected to the drains of the fifth and sixth transistors, respectively, and the first control voltage signal being input to the gates;
A ninth transistor in which a source is grounded, an inverted signal of the input logic signal is input to a gate, and conduction and non-conduction of a current flowing between the drain and the drain of the seventh transistor are controlled;
A tenth transistor having a source grounded and a gate connected to the input logic signal, the conduction and non-conduction of a current flowing between the drain and the drain of the eighth transistor are controlled;
With
The second control voltage signal is output from the drain of the sixth transistor, the fifth to eighth transistors are transistors of the first conductivity type, and the ninth to tenth transistors are transistors of the second conductivity type. Because
The voltage level of the second control voltage signal when the input logic signal is the first power supply voltage level is a voltage level shifted from the voltage level of the first control voltage signal by the threshold value of the eighth transistor. The output buffer circuit according to claim 1, wherein the output buffer circuit is an output buffer circuit. The second control voltage generation circuit includes:
An eleventh transistor of the second conductivity type having a source connected to the drain of the ninth transistor, a drain connected to the drain of the seventh transistor, and a reference voltage signal input to the gate;
A twelfth conductivity type twelfth transistor having a source connected to a drain of the tenth transistor, a drain connected to a drain of the eighth transistor, and a reference voltage signal input to a gate;
The output buffer circuit according to claim 4, further comprising: The first control voltage generation circuit includes:
A first resistance element having one end connected to the second power source;
A voltage dividing circuit including: a second resistance element having one end connected to the other end of the first resistance element and the other end connected to the ground;
A source follower circuit in which the other end of the first resistance element and one end of the second resistance element are connected to a gate, and a drain is connected to the second power source;
A waveform shaping circuit for shaping the output signal of the source follower circuit and generating the first control voltage signal;
6. The output buffer circuit according to claim 1, further comprising: Each of the first conductivity type transistors is a PMOS transistor, and each of the second conductivity type transistors is an NMOS transistor. Both the first power supply and the second power supply are supplied with a positive power supply voltage with respect to the ground. the output buffer circuit according to claim 1 to 6 any one of claims, characterized in that a power supply. Each of the first conductivity type transistors is an NMOS transistor, and each of the second conductivity type transistors is a PMOS transistor. Both the first power source and the second power source are supplied with a negative power source voltage with respect to the ground. the output buffer circuit according to claim 1 to 7 any one of claims, characterized in that a power supply.

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