JP5501196B2 - Output circuit - Google Patents

Description

  The present invention relates to an output circuit. In particular, the present invention relates to an output circuit capable of outputting a signal having a voltage higher than the breakdown voltage of a transistor.

  In recent years, with the miniaturization of the manufacturing process, it has become difficult to manufacture a high voltage transistor. For example, deterioration due to hot carriers, NBTI (Negative Bias Temperature Instability), etc. is remarkable, and even if a high voltage transistor can be manufactured, it is difficult to guarantee the same reliability as before.

  On the other hand, in a process in which transistors having different breakdown voltages such as 1.8 V and 3.3 V cannot be mixed, both a 1.8 V interface and a 3.3 V interface may be required on the same chip. In this case, the 1.8V interface must be realized with a 3.3V withstand voltage transistor, or the 3.3V interface must be realized with a 1.8V withstand voltage transistor.

  As described above, when high voltage transistors are difficult to manufacture, when interfaces with different voltage levels are mounted on the same chip, a high voltage signal is output even though low voltage transistors are used. A circuit that can be used is required. As a method for realizing a high voltage output circuit using such a low withstand voltage transistor, overdriving beyond the rating of the transistor can be considered, but it may not be appropriate from the viewpoint of ensuring reliability.

  Therefore, a technique related to a circuit that outputs a signal having a voltage higher than the breakdown voltage without exceeding the breakdown voltage of the transistor has been developed. FIG. 2 is FIG. In FIG. 2, the intermediate voltage Vref1 applied to the gate terminals of the N-channel transistors N11 and N13 is set higher than the half of the power supply voltage by the threshold voltage of the transistor, and is applied to the gate terminals of the P-channel transistors P11 and P13. An output circuit is disclosed that sets the applied intermediate voltage Vref2 to a voltage lower than half of the power supply voltage by a threshold voltage of the transistor. By adopting such a configuration, the voltage applied to the terminal of each transistor can be suppressed to about half of the power supply voltage. As a result, it is possible to output a high voltage signal corresponding to the power supply voltage by using a transistor having a breakdown voltage of about half of the power supply voltage. Note that Embodiments 5 to 7 of Patent Document 1 describe examples in which the output circuit is used for a level shift circuit (see FIGS. 6 and 7 of Patent Document 1). Although not shown in Patent Document 1, a logic signal Vin2 having a low level of 1/2 Vdd and a high level of Vdd is applied to a low-voltage signal Vin1 ( A circuit that shifts the level from a low level of 0 V and a high level of 1/2 Vdd is required.

  Further, Patent Document 2 discloses a circuit capable of outputting a signal having an amplitude of 5V by using the level shifter 2 while using a 3V withstand voltage transistor. FIG. 3 shows FIG.

JP 2005-0395560 A US Pat. No. 5,559,464

  The following analysis has been made from the viewpoint of the present invention.

  However, the output circuit described in Patent Document 1 is based on the premise that the amplitude of the input signal is the same magnitude as the power supply voltage. Therefore, when the amplitude of the input signal is lower than the power supply voltage, specifically, when the amplitude is about half the power supply voltage, the current between the source and drain of the transistor P12 is cut off at the gate terminal of the transistor P12. A low voltage cannot be obtained, and an output amplitude of GND at a low level cannot be obtained.

  In addition, the output circuits disclosed in Embodiments 5 to 7 of Patent Document 1 and Patent Document 2 require the level shifter 2 and are necessary compared to the output circuit described in Patent Document 1 shown in FIG. There is a problem that there are many elements and the layout area increases.

  As described above, there are problems to be solved in the prior art.

  In one aspect of the present invention, when the amplitude of an input signal is about half of the power supply voltage, an output circuit capable of outputting a signal having a voltage amplitude corresponding to the power supply voltage using a low withstand voltage transistor is provided on a small scale. Realization with a simple circuit configuration is desired.

  According to the first aspect of the present invention, a first first conductivity type transistor in which an input signal having a voltage lower than the power supply voltage is input to the drain terminal and a first intermediate voltage is applied to the gate terminal. The power supply voltage is connected to the source terminal, the source terminal of the first first conductivity type transistor is connected to the gate terminal, and the power supply voltage is connected to the source terminal. A third first conductivity type transistor in which a drain terminal of the second first conductivity type transistor is connected to a gate terminal, and a source terminal of the first first conductivity type transistor is connected to a drain terminal; A fourth first conductivity type transistor in which a first intermediate voltage is connected to a gate terminal, and a drain terminal of the second first conductivity type transistor is connected to a source terminal; And a drain terminal of the first second conductivity type transistor connected to the source terminal, and a second intermediate terminal connected to the gate terminal. A second second conductivity type transistor to which a voltage is applied and whose drain terminal is connected to the drain terminal of the fourth first conductivity type transistor, the drain terminal of the fourth first conductivity type transistor, and An output circuit using the drain terminal of the second second conductivity type transistor as an output terminal is provided.

  According to each aspect of the present invention, there is provided an output circuit capable of outputting a signal having a voltage amplitude corresponding to a power supply voltage using a low-breakdown-voltage transistor when the amplitude of the input signal is about half of the power supply voltage. It can be realized with a small circuit configuration.

It is a figure for explaining the outline of the present invention. It is an example of the circuit diagram of the conventional output circuit using a low voltage | pressure-resistant transistor. It is an example of a conventional level shift circuit using a low breakdown voltage transistor. It is a figure which shows the circuit structure of the output circuit which concerns on the 1st Embodiment of this invention. FIG. 5 is a diagram illustrating the voltage of each node and the state of each transistor when the input signal Vi changes from 0 V to 1.8 V in the output circuit of FIG. 4. FIG. 5 is a diagram illustrating the voltage of each node and the state of each transistor when an input signal Vi changes from 1.8 V to 0 V in the output circuit of FIG. 4. It is an example of the simulation result of the output circuit which concerns on 1st Embodiment. It is an example of the simulation result of the output circuit which concerns on 1st Embodiment. It is an example of the simulation result of the output circuit which concerns on 1st Embodiment. It is an example of a simulation result when a signal having an amplitude of about half the power supply voltage is input to the output circuit described in Patent Document 1. It is a figure which shows the circuit structure of the output circuit which concerns on the 2nd Embodiment of this invention. It is an example of the simulation result of the output circuit which concerns on 2nd Embodiment. It is an example of the simulation result of the output circuit which concerns on 2nd Embodiment. It is an example of the simulation result of the output circuit which concerns on 2nd Embodiment. It is a figure which shows the circuit structure of the output circuit which concerns on the 3rd Embodiment of this invention.

  First, the outline of the present invention will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment. As described above, the output circuit described in Patent Document 1 is based on the premise that the amplitude of the input signal is the same amplitude as the power supply voltage. Therefore, if the input signal has an amplitude that is about half of the power supply voltage, a signal having a voltage higher than half of the power supply voltage cannot be generated, and half the power supply voltage is set as the input signal and is equal to the power supply voltage. When voltage is used as an output signal, the circuit described in Patent Document 1 cannot be adopted. In other words, the circuit described in Patent Document 1 cannot convert a low-voltage signal into a high-voltage signal and output it.

  Therefore, consider an output circuit including a third first conductivity type transistor as shown in FIG. For example, the first intermediate voltage is set to a voltage obtained by subtracting the absolute value of the voltage corresponding to the threshold voltage of the first conductivity type transistor from the voltage corresponding to half of the power supply voltage. For example, the second intermediate voltage is set to a voltage corresponding to half of the power supply voltage. In the output circuit shown in FIG. 1, when the input signal rises to about half of the power supply voltage, the first and second second conductivity type transistors are turned on. Then, the output signal starts to decrease toward 0V. At this time, if there is no third first conductivity type transistor, it is impossible to apply a voltage that turns off the second first conductivity type transistor to the gate terminal of the second first conductivity type transistor. As a result, even if the input signal is at a high level, a current flows from the power supply voltage to the output signal through the second first conductivity type transistor and the fourth first conductivity type transistor, and the output signal is affected by the power supply voltage. The signal of 0V cannot be completely output.

  However, if the third first conductivity type transistor is provided, the third first conductivity type transistor is turned on as the output signal decreases, and the second first conductivity type transistor is turned off. it can. As a result, the influence of the power supply voltage on the output signal can be eliminated, and the output signal can output 0V.

  Each of the first to fourth first conductivity type transistors and the first to second second conductivity type transistors is a low voltage transistor that operates in a low voltage system that is a voltage system of an input signal. May be a voltage having an absolute value larger than the voltage of the low voltage system.

  The input signal may be supplied to the drain terminal of the first first conductivity type transistor and the gate terminal of the first second conductivity type transistor via an inverting circuit.

  The first intermediate voltage is equal to a voltage obtained by subtracting a voltage corresponding to the absolute value of the threshold voltage of the first conductivity type transistor from the absolute value of substantially half of the power supply voltage, and the second intermediate voltage. May be equal to substantially half the power supply voltage.

  Further, the first intermediate voltage and the second intermediate voltage may be substantially equal.

  Further, an intermediate voltage generation circuit that generates the first intermediate voltage and the second intermediate voltage from the power supply voltage may be provided.

  Further, the power supply voltage may have a positive voltage value with respect to the ground, and the first conductivity type transistor may be a P channel type MOS transistor and the second conductivity type transistor may be an N channel type MOS transistor.

  The power supply voltage may have a negative voltage value with respect to the ground, and the first conductivity type transistor may be an N channel type MOS transistor and the second conductivity type transistor may be a P channel type MOS transistor.

[First Embodiment]
Next, the first embodiment of the present invention will be described in more detail with reference to FIG. FIG. 4 is a diagram showing a circuit configuration of the output circuit according to the present embodiment.

  The output circuit according to the first embodiment shown in FIG. 4 converts an input signal having an amplitude of 1.8V into an output signal having an amplitude of 3.3V. The output circuit according to this embodiment includes P-channel transistors PMOS11 to PMOS14, N-channel transistors NMOS11 and NMOS12, and an inverter INV1. The P-channel transistors PMOS11 to PMOS14 and the N-channel transistors NMOS11 and NMOS12 are MOS transistors, and the withstand voltage between the source and the drain is 1.8V. The power supply voltage VDD18 is 1.8V, and the power supply voltage VDD33 is 3.3V. The intermediate voltage Vm1 is set to Vm1 = VDD33 / 2− | Vtp |. The intermediate voltage Vm2 is set to Vm2 = VDD33 / 2. Here, Vtp is a threshold voltage of the P-channel transistor, and Vm1 is a voltage obtained by subtracting a voltage corresponding to the absolute value of Vtp from a voltage corresponding to half of the power supply voltage VDD33.

  The gate terminal of the transistor PMOS11 is connected to the intermediate voltage Vm1, and the drain terminal is connected to the output terminal of the inverter INV1. Furthermore, the source terminal of the transistor PMOS11 is connected to the gate terminal of the transistor PMOS12 and the drain terminal of the transistor PMOS13. The source terminal of the transistor PMOS12 is connected to the power supply voltage VDD33, and the drain terminal is connected to the source terminal of the transistor PMOS14 and the gate terminal of the transistor PMOS13. The gate terminal of the transistor PMOS14 is connected to the intermediate voltage Vm1, the drain terminal is connected in common with the drain terminal of the transistor NMOS12, and is used as a terminal for outputting the output signal Vo. The source terminal of the transistor PMOS13 is connected to the power supply voltage VDD33. The output terminal of the inverter INV1 is connected to the drain terminal of the transistor PMOS11 and to the gate terminal of the transistor NMOS11. The drain terminal of the transistor NMOS11 is connected to the source terminal of the transistor NMOS12, and the source terminal is connected to the ground (GND). The gate terminal of the transistor NMOS12 is connected to the intermediate voltage Vm2.

  Although a detailed description of the operation of the output circuit according to the present embodiment will be described later, the voltage at the terminals of each transistor is used at that time, so that connection points necessary for the description are defined as nodes. A connection point between the output terminal of the inverter INV1, the drain terminal of the transistor PMOS11, and the gate terminal of the transistor NMOS11 is a node S1. A connection point between the gate terminal of the transistor PMOS12 and the drain terminal of the transistor PMOS13 is a node S2. A connection point of the drain terminal of the transistor PMOS12, the source terminal of the transistor PMOS14, and the gate terminal of the transistor PMOS13 is a node S3. A connection point between the drain terminal of the transistor NMOS11 and the source terminal of the transistor NMOS12 is a node S4.

  Next, the operation of the output circuit shown in FIG. 4 will be described. First, a case where the voltage of the input signal Vi changes from 0V to 1.8V will be described. FIG. 5 is a diagram illustrating the voltage of each node and the state of the transistors when the input signal Vi changes from 0V to 1.8V in the output circuit illustrated in FIG. The vertical axis represents the input signal Vi, nodes S1 to S4, transistors PMOS12 and PMOS13, and transistor NMOS11.

  When the input signal Vi changes from 0V to 1.8V, the output voltage of the inverter INV1 starts changing from 1.8V to 0V. Here, consider the source voltage (voltage of the node S2) of the transistor PMOS11 at the time when the voltage starts to decrease. The state of the transistor PMOS13 will be described later. In this case, the transistor PMOS13 is in the on state. Then, although the voltage of the node S2 should be equal to the voltage of the power supply voltage VDD33, in reality, a current flows through the transistor PMOS11 and a slight voltage drop occurs. Nevertheless, the voltage is higher than the intermediate voltage Vm1 (VDD33 / 2- | Vtp |), which is the gate voltage of the transistor PMOS11, and the voltage between the gate and the source of the transistor PMOS11 exceeds the threshold voltage of the transistor PMOS11. The PMOS 11 is turned on.

  Since the transistor PMOS11 is in the on state, the voltage at the node S2 gradually decreases as the voltage at the node S1 decreases. Since the voltage at the node S2 is also the gate voltage of the transistor PMOS12, the transistor PMOS12 is turned on when the gate-source voltage of the transistor PMOS12 exceeds the threshold voltage of the transistor PMOS12 (time t1).

  When the transistor PMOS12 is turned on, the voltage of the node S3 increases toward the power supply voltage VDD33. Since the voltage at the node S3 is the gate voltage of the transistor PMOS13, the transistor PMOS13 is turned off when the gate-source voltage of the transistor PMOS13 falls below the threshold voltage of the transistor PMOS13 (time t2).

  Further, as the voltage at the node S1 decreases, the voltage at the node S2 gradually decreases due to the current flowing between the source and drain of the transistor PMOS11. However, when the voltage of the node S2 decreases until the difference between the node S2 that is the source voltage of the transistor PMOS11 and the intermediate voltage Vm1 that is the gate voltage of the transistor PMOS11 becomes equal to the absolute value (| Vtp |) of the threshold voltage of the transistor PMOS11. No more current flows between the source and drain of the transistor PMOS11. Therefore, since Vm1 = VDD33 / 2− | Vtp |, the voltage of the node S2 decreases to approximately VDD33 / 2, but does not fall below the intermediate voltage Vm1. Therefore, it is possible to prevent an excessive voltage from being applied between the gate and the source of the transistor PMOS12 when outputting a high level to the output signal Vo.

  Further, since the transistor PMOS12 is on, the voltage at the node S3 is equal to the power supply voltage VDD33. Further, since the gate voltage of the transistor PMOS14 is Vm1 and the source voltage of the transistor PMOS14 is equal to the voltage of the node S3, the gate-source voltage of the transistor PMOS14 can be expressed as VDD33−Vm1 = VDD33 / 2 + | Vtp |. Since the threshold voltage of the transistor PMOS14 is exceeded, the transistor PMOS14 is turned on.

  Next, the operation of the transistor NMOS11 will be described. Since the output terminal of the inverter INV1 is connected to the gate terminal of the transistor NMOS11, the transistor NMOS11 is turned off when the voltage at the node S1 falls below the threshold voltage of the transistor NMOS11 (time t3). When the transistor NMOS11 is turned off, the voltage at the node S4 increases. However, as the voltage at the node S4 increases, the gate-source voltage of the transistor NMOS12 decreases. When the gate-source voltage of the transistor NMOS12 decreases to the threshold voltage of the transistor NMOS12, the transistor NMOS12 is turned off, and the voltage increase at the node S4 stops. Therefore, even if the voltage of the output signal Vo rises, the voltage between the drain and source of the transistors NMOS11 and NMOS12 can be suppressed to about half of the power supply voltage.

  Therefore, the output signal Vo rises to 3.3V. The absolute values of the gate-source voltage, the gate-drain voltage, and the drain-source voltage of each of the transistors PMOS11, PMOS12, PMOS13, PMOS14, NMOS11, NMOS12 when the output signal Vo becomes high level and increases to 3.3V. All of the values can be suppressed to at most about half of the power supply voltage.

  Next, a case where the voltage of the input signal Vi changes from 1.8V to 0V will be described. FIG. 6 is a diagram illustrating the voltage of each node and the state of the transistors when the input signal Vi changes from 1.8 V to 0 V in the output circuit illustrated in FIG. The items on the vertical axis are the same as those in FIG.

  When the input signal Vi changes from 1.8V to 0V, the output voltage of the inverter INV1 starts to change from 0V to 1.8V. Since the output voltage of the inverter INV1 and the voltage of the node S1 are equal, the voltage of the node S1 starts to rise from 0V. Since the voltage at the node S1 is equal to the gate voltage of the transistor NMOS11, the transistor NMOS11 is turned on when the voltage at the node S1 exceeds the threshold voltage of the transistor NMOS11 (time t4).

  When the transistor NMOS11 is turned on, the voltage of the node S4 starts to decrease toward 0V. When the gate-source voltage of the transistor NMOS12 exceeds the threshold voltage of the transistor NMOS12 as the voltage of the node S4 decreases, the transistor NMOS12 is turned on, and the transistor PMOS14 is kept on, so that the node S3 The voltage begins to drop.

  Although the voltage of the node S3 starts to decrease from 3.3V, the voltage of the node S3 and the gate voltage of the transistor PMOS13 are equal. Therefore, when the voltage of the node S3 decreases to VDD33− | Vtp | Since the inter-voltage exceeds the threshold voltage, the transistor PMOS13 is turned on (time t5).

  When the transistor PMOS13 is turned on, the voltage at the node S2 starts to increase toward the power supply voltage VDD33. When the gate-source voltage of the transistor PMOS11 exceeds the threshold voltage of the transistor PMOS11 as the voltage of the node S2 increases, the transistor PMOS11 is turned on. Further, when the voltage at the node S2 rises and the gate-source voltage of the transistor PMOS12 falls below the threshold voltage of the transistor PMOS12, the transistor PMOS12 is turned off (time t6).

  As a result, the output signal Vo decreases to 0V. At this time, the voltage at the node S3 decreases as the output signal Vo decreases because the transistor PMOS12 is turned off. However, as the voltage at the node S3 decreases, the gate-source voltage of the transistor PMOS14 decreases. . When the voltage at the node S3 drops to about half of the power supply voltage VDD33, the transistor PMOS14 is turned off, so that the voltage at the node S3 does not drop any further. Therefore, even if the output signal Vo decreases to 0V, the drain-source voltages of the transistors PMOS12 and PMOS14 can be suppressed to about half of the power supply voltage VDD33, respectively. In addition, the absolute values of the gate-source voltage, the gate-drain voltage, and the drain-source voltage of any transistor included in the output circuit can be suppressed to about half of the power supply voltage.

  7 to 9 show simulation results when a signal having an amplitude of 1.8 V is input to the output circuit according to the present embodiment. FIG. 7 shows an input signal Vi, an output signal Vo, an intermediate voltage Vm1, and an intermediate voltage Vm2. FIG. 8 shows the voltage at the node S1, the voltage at the node S2, the intermediate voltage Vm1, and the intermediate voltage Vm2. FIG. 9 shows the voltage at the node S3, the voltage at the node S4, the intermediate voltage Vm1, and the intermediate voltage Vm2. 7 to 9, it can be seen that a signal having an amplitude of 1.8V can be input as an input signal and an output signal having an amplitude of 3.3V can be output.

  Here, when the output circuit according to the present embodiment does not have the transistor PMOS 13 as in the output circuit described in Patent Document 1 described with reference to FIG. Verify the output signal. FIG. 10 shows a simulation result when a signal having an amplitude about half the power supply voltage Vdd is input to the output circuit described in Patent Document 1 described with reference to FIG. In this case, when the input signal Vin is 0 V, the voltage of the node D (corresponding to the node S2 in FIG. 4) cannot rise to around 3.3 V, and the transistor P12 cannot be turned off. Therefore, the power supply voltage Vdd is affected via the transistors P12 and P13, and the low level of the output signal Vout cannot be reduced to 0 V, and the output circuit does not operate correctly. From the simulation result of FIG. 10, it can be seen that the low level of the output signal Vout increases by about 0.5V.

  On the other hand, by making the configuration of the output circuit as shown in FIG. 4, when the input signal Vi is 0V, the transistor PMOS13 can be turned on, and the voltage of the node S2 is pulled up to 3.3V. As a result, the transistor PMOS12 is turned off, and the voltage of the output signal Vo can be reduced to 0V (see FIG. 7).

  As described above, the output circuit according to the present embodiment can output a high voltage using a low breakdown voltage transistor. At the same time, a transistor corresponding to the transistor N11 in FIG. Further, as compared with the output circuit disclosed in Patent Document 2 (FIG. 3), a small amplitude signal is input using a small number of components and low breakdown voltage transistors, and the signal has an amplitude corresponding to the power supply voltage. Can be output.

[Second Embodiment]
Next, a second embodiment will be described in detail with reference to the drawings. FIG. 11 is a diagram showing a circuit configuration of the output circuit according to the present embodiment. In FIG. 11, the same components as those in FIG. The difference between the output circuit shown in FIG. 11 and the output circuit shown in FIG. 4 is that the intermediate voltages Vm2 and Vm1 of FIG. 4 are integrated into one intermediate voltage Vm. Here, the intermediate voltage Vm is set to a voltage corresponding to VDD33 / 2.

  In the output circuit of FIG. 4, two kinds of intermediate voltages are supplied with Vm1 = VDD33 / 2− | Vtp | and Vm2 = VDD33 / 2. However, the influence of the threshold voltage Vtp of the P-channel transistor on the circuit operation. If V is sufficiently small, Vm2≈Vm1 can be satisfied. Here, the influence of Vtp on circuit operation is when Vtp is sufficiently small and the operation of the output circuit and the reliability of the transistor are not affected even if the voltage of the node S2 is increased by a voltage corresponding to Vtp. It is. In this case, the intermediate voltages Vm1 and Vm2 can be combined into one, and the intermediate voltage generation circuit can be simplified.

  Therefore, when the intermediate voltage is set to Vm = VDD33 / 2, the gate voltages of the transistors PMOS11 and PMOS14 are compared with the voltage of the node S2 in the first embodiment, and a voltage corresponding to the threshold voltage (Vtp) of the P-channel transistor. Only get higher. If the gate voltages of the transistors PMOS11 and PMOS14 are increased by a voltage corresponding to the threshold voltage (Vtp) of the P-channel transistor, the following problem may occur. First, when the input signal Vi is at a low level and the output signal Vo is at a low level, the voltage at the node S3 rises by | Vtp | from the first embodiment. However, a withstand voltage of VDD33 / 2 or higher is required. Second, when the input signal Vi is at a high level and the output signal Vo is at a high level, the gate voltage of the transistor PMOS11 is higher by | Vtp | than in the first embodiment, so that the gate voltage is increased. Accordingly, the voltage at the node S2, which is the source voltage of the transistor PMOS11, also increases. When the voltage at the node S2 increases, the gate-source voltage of the transistor P12 decreases, and the on-resistance of the transistor PMOS12 increases. At this time, since the voltage at the node S1 is 0 V, a voltage higher than VDD33 / 2 is applied between the source and drain of the transistor PMOS11 as the voltage at the node S2 increases. Therefore, if there is a margin in the driving capability of the transistor PMOS12 and the breakdown voltage between the source and drain of the transistors PMOS11 and PMOS14, the overall operation is not affected. Therefore, the operation of the entire output circuit is related to the first embodiment. Similar to the output circuit.

  12 to 14 show simulation results when a signal having an amplitude of 1.8 V is input to the output circuit according to the present embodiment. FIG. 12 shows an input signal Vi, an output signal Vo, and an intermediate voltage Vm. FIG. 13 shows the voltage at the node S1, the voltage at the node S2, and the intermediate voltage Vm. FIG. 14 shows the voltage at the node S3, the voltage at the node S4, and the intermediate voltage Vm. From FIG. 12 to FIG. 14, it can be seen that even in the output circuit according to the present embodiment, it is possible to output a high-amplitude signal using a low breakdown voltage transistor. Further, it can be seen from FIG. 13 that the low level of the node S2 in this embodiment is higher than the low level of the node S2 in the first embodiment.

  As described above, by combining the intermediate voltages into one, the scale of the entire output circuit can be reduced, which can contribute to cost reduction.

[Third Embodiment]
Next, a third embodiment will be described in detail with reference to the drawings. FIG. 15 is a diagram showing a circuit configuration of the output circuit according to the present embodiment. In FIG. 15, the same components as those of FIG. A difference between the output circuit shown in FIG. 15 and the output circuit shown in FIG. 11 is that an intermediate voltage generation circuit 10 is provided.

  The output circuit according to the second embodiment needs to control the timing of applying the intermediate voltage Vm so that the voltage applied to each transistor does not exceed the breakdown voltage of the transistor. More specifically, it is necessary to apply the intermediate voltage Vm simultaneously with the power supply voltage VDD33 or before the rise of the power supply voltage VDD33. On the contrary, when the supply of the intermediate voltage Vm is stopped, it is necessary to perform the supply at the same time as the supply of the power supply voltage VDD33 or after the supply of the power supply voltage VDD33 is stopped. Therefore, it is necessary to control the intermediate voltage Vm at an appropriate timing.

  Therefore, the output circuit according to the present embodiment includes the intermediate voltage generation circuit 10 that generates the intermediate voltage Vm using the power supply voltage VDD33. The intermediate voltage generation circuit 10 synchronizes the supply / stop of the intermediate voltage Vm with the supply / stop of the power supply voltage VDD33. The operation of the output circuit according to the present embodiment is the same as that of the output circuit described in the second embodiment. Therefore, description of the operation is omitted. In particular, by generating the intermediate voltage generation circuit 10 from the relatively high power supply voltage VDD33 without using the low voltage power supply VDD18, only the power supply voltage VDD33 is supplied. Even if it is not supplied, it is possible to prevent an excessive voltage from being applied to each transistor constituting the output circuit.

  As described above, by using the intermediate voltage generation circuit 10, the intermediate voltage Vm can be generated from the power supply voltage VDD33, and complicated control for generating the intermediate voltage Vm becomes unnecessary.

  In the first to third embodiments, the case where the power supply is a positive voltage with respect to the ground has been described as a preferred embodiment. However, the present invention is not limited to the case where the power supply is a positive voltage, and can also be used for an output circuit in which the power supply voltage is a negative voltage. In such a case, in the first to third embodiments, all the PMOS transistors and NMOS transistors may be used interchangeably.

  It should be noted that the disclosures of the above patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

10 Intermediate voltage generation circuit INV1 Inverter NMOS11, NMOS12 N-channel transistor PMOS11-PMOS14 P-channel transistor

Claims (8)

A first first conductivity type transistor in which an input signal having a voltage lower than the power supply voltage is input to the drain terminal, and a first intermediate voltage is applied to the gate terminal;
A second first conductivity type transistor in which the power supply voltage is connected to a source terminal, and a source terminal of the first first conductivity type transistor is connected to a gate terminal;
The power supply voltage is connected to the source terminal, the drain terminal of the second first conductivity type transistor is connected to the gate terminal, and the source terminal of the first first conductivity type transistor is connected to the drain terminal. A first conductivity type transistor of
A fourth first conductivity type transistor in which the first intermediate voltage is connected to a gate terminal, and a drain terminal of the second first conductivity type transistor is connected to a source terminal;
A first second conductivity type transistor in which the input signal is input to a gate terminal and a source terminal is grounded;
The drain terminal of the first second conductivity type transistor is connected to the source terminal, the second intermediate voltage is applied to the gate terminal, and the drain terminal is connected to the drain terminal of the fourth first conductivity type transistor. A second second conductivity type transistor;
With
An output circuit comprising a drain terminal of the fourth first conductivity type transistor and a drain terminal of the second second conductivity type transistor as output terminals.   The first to fourth first conductivity type transistors and the first to second second conductivity type transistors are all low voltage transistors that operate in a low voltage system that is a voltage system of the input signal, and 2. The output circuit according to claim 1, wherein the power supply voltage is a voltage having an absolute value larger than that of the low voltage system voltage.   3. The output circuit according to claim 1, wherein the input signal is supplied to a drain terminal of the first first conductivity type transistor and a gate terminal of the first second conductivity type transistor via an inverting circuit.   The first intermediate voltage is equal to a voltage obtained by subtracting a voltage corresponding to an absolute value of a threshold voltage of the first conductivity type transistor from an absolute value of a substantially half voltage of the power supply voltage. The output circuit according to any one of claims 1 to 3, wherein the intermediate voltage is equal to substantially half of the power supply voltage.   4. The output circuit according to claim 1, wherein the first intermediate voltage and the second intermediate voltage are substantially equal. 5.   The output circuit according to claim 5, further comprising an intermediate voltage generation circuit that generates the first intermediate voltage and the second intermediate voltage from the power supply voltage.   7. The power supply voltage has a positive voltage value with respect to the ground, the first conductivity type transistor is a P-channel type MOS transistor, and the second conductivity type transistor is an N-channel type MOS transistor. The output circuit according to any one of the above.   7. The power supply voltage has a negative voltage value with respect to the ground, the first conductivity type transistor is an N channel type MOS transistor, and the second conductivity type transistor is a P channel type MOS transistor. The output circuit according to any one of the above.

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